@inproceedings{52744, author = {{Jafarzadeh, Hanieh and Klemme, Florian and Amrouch, Hussam and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{European Test Symposium, The Hague, Netherlands, May 20-24, 2024}}, location = {{The Hague, NL}}, pages = {{6}}, publisher = {{IEEE}}, title = {{{Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations}}}, year = {{2024}}, } @inproceedings{52742, author = {{Jafarzadeh, Hanieh and Klemme, Florian and Amrouch, Hussam and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024}}, location = {{Maceió}}, pages = {{6}}, publisher = {{IEEE}}, title = {{{Vmin Testing under Variations: Defect vs. Fault Coverage}}}, year = {{2024}}, } @inproceedings{52743, author = {{Hellebrand, Sybille and Sadeghi-Kohan, Somayeh and Wunderlich, Hans-Joachim}}, booktitle = {{International Symposium of EDA (ISEDA), Xi'an, China, May 10-13, 2024}}, location = {{Xi'an, China}}, pages = {{1}}, title = {{{Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle}}}, year = {{2024}}, } @inproceedings{52745, author = {{Wunderlich, Hans-Joachim and Jafarzadeh, Hanieh and Hellebrand, Sybille}}, booktitle = {{International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024}}, location = {{Xi’an, China}}, pages = {{1}}, title = {{{Robust Test of Small Delay Faults under PVT-Variations}}}, year = {{2024}}, } @misc{50284, author = {{Stiballe, Alisa and Reimer, Jan Dennis and Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}}, publisher = {{37. ITG / GMM / GI -Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'24), Feb. 2024}}, title = {{{Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression}}}, year = {{2024}}, } @misc{35204, author = {{Ghazal, Abdulkarim and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille}}, keywords = {{WORKSHOP}}, pages = {{2}}, publisher = {{35. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'23), Feb. 2023}}, title = {{{On Cryptography Effects on Interconnect Reliability}}}, year = {{2023}}, } @phdthesis{46482, abstract = {{Ever increasing demands on the performance of microchips are leading to ever more complex semiconductor technologies with ever shrinking feature sizes. Complex applications with high demands on safety and reliability, such as autonomous driving, are simultaneously driving the requirements for test and diagnosis of VLSI circuits. Throughout the life cycle of a microchip, uncertainties occur that affect its timing behavior. For example, weak circuit structures, aging effects, or process variations can lead to a change in the timing behavior of the circuit. While these uncertainties do not necessarily lead to a change of the functional behavior, they can lead to a reliability problem. With modular and hybrid compaction two test instruments are presented in this work that can be used for X-tolerant test response compaction in the built-in Faster-than-At-Speed Test (FAST) which is used to detect uncertainties in VLSI circuits. One challenge for test response compaction during FAST is the high and varying X-rate at the outputs of the circuit under test. By dividing the circuit outputs into test groups and separately compacting these test groups using stochastic compactors, the modular compaction is able to handle these high and varying X-rates. To deal with uncertainties on logic interconnects, a method for distinguishing crosstalk and process variation is presented. In current semiconductor technologies, the number of parasitic coupling capacitances between logic interconnects is growing. These coupling capacitances can lead to crosstalk, which causes increased current flow in the logic interconnects, which in turn can lead to increased electromigration. In the presented method, delay maps describing the timing behavior of the circuit outputs at different operating points are used to train artificial neural networks which classify the tested circuits into fault-free and faulty.}}, author = {{Sprenger, Alexander}}, keywords = {{Testantwortkompaktierung, Prozessvariation, Silicon Lifecycle Management}}, pages = {{xi, 160}}, publisher = {{Universität Paderborn}}, title = {{{Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen}}}, doi = {{10.17619/UNIPB/1-1787}}, year = {{2023}}, } @inproceedings{46739, author = {{Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)}}, publisher = {{IEEE}}, title = {{{Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication}}}, doi = {{10.1109/dsn-w58399.2023.00056}}, year = {{2023}}, } @inproceedings{46738, author = {{Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{IEEE Asian Test Symposium (ATS'23), October 2023}}, title = {{{Optimizing the Streaming of Sensor Data with Approximate Communication}}}, year = {{2023}}, } @article{46264, abstract = {{System-level interconnects provide the backbone for increasingly complex systems on a chip. Their vulnerability to electromigration and crosstalk can lead to serious reliability and safety issues during the system lifetime. This article presents an approach for periodic in-system testing which maintains a reliability profile to detect potential problems before they actually cause a failure. Relying on a common infrastructure for EM-aware system workload management and test, it minimizes the stress induced by the test itself and contributes to the self-healing of system-induced electromigration degradations. }}, author = {{Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, issn = {{2168-2356}}, journal = {{IEEE Design &Test}}, keywords = {{Electrical and Electronic Engineering, Hardware and Architecture, Software}}, pages = {{1--1}}, publisher = {{Institute of Electrical and Electronics Engineers (IEEE)}}, title = {{{Workload-Aware Periodic Interconnect BIST}}}, doi = {{10.1109/mdat.2023.3298849}}, year = {{2023}}, } @inproceedings{45830, author = {{Jafarzadeh, Hanieh and Klemme, Florian and Reimer, Jan Dennis and Najafi Haghi, Zahra Paria and Amrouch, Hussam and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{IEEE International Test Conference (ITC'23), Anaheim, USA, October 2023}}, location = {{Anaheim, USA}}, publisher = {{IEEE}}, title = {{{Robust Pattern Generation for Small Delay Faults under Process Variations}}}, year = {{2023}}, } @article{29351, abstract = {{Safety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. The required high fault coverage at runtime is usually obtained by a combination of concurrent error detection or correction and periodic tests within rather short time intervals. The concurrent scheme ensures the integrity of computed results while the periodic test has to identify potential aging problems and to prevent any fault accumulation which may invalidate the concurrent error detection mechanism. Such periodic built-in self-test (BIST) schemes are already commercialized for memories and for random logic. The paper at hand extends this approach to interconnect structures. A BIST scheme is presented which targets interconnect defects before they will actually affect the system functionality at nominal speed. A BIST schedule is developed which significantly reduces aging caused by electromigration during the lifetime application of the periodic test.}}, author = {{Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, issn = {{0923-8174}}, journal = {{Journal of Electronic Testing}}, keywords = {{Electrical and Electronic Engineering}}, publisher = {{Springer Science and Business Media LLC}}, title = {{{Stress-Aware Periodic Test of Interconnects}}}, doi = {{10.1007/s10836-021-05979-5}}, year = {{2022}}, } @misc{29890, author = {{Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, keywords = {{WORKSHOP}}, pages = {{2}}, publisher = {{European Workshop on Silicon Lifecycle Management, March 18, 2022}}, title = {{{EM-Aware Interconnect BIST}}}, year = {{2022}}, } @inproceedings{19422, author = {{Sprenger, Alexander and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille}}, booktitle = {{IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020}}, title = {{{Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study}}}, year = {{2020}}, } @misc{15419, author = {{Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}}, keywords = {{WORKSHOP}}, pages = {{4}}, publisher = {{32. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'20), 16. - 18. Februar 2020}}, title = {{{Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects}}}, year = {{2020}}, } @inproceedings{29200, author = {{Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}}, booktitle = {{38th IEEE VLSI Test Symposium (VTS)}}, publisher = {{IEEE}}, title = {{{Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects}}}, doi = {{10.1109/vts48691.2020.9107591}}, year = {{2020}}, } @inproceedings{19421, author = {{Holst, Stefan and Kampmann, Matthias and Sprenger, Alexander and Reimer, Jan Dennis and Hellebrand, Sybille and Wunderlich, Hans-Joachim and Weng, Xiaoqing}}, booktitle = {{IEEE International Test Conference (ITC'20), November 2020}}, title = {{{Logic Fault Diagnosis of Hidden Delay Defects}}}, year = {{2020}}, } @misc{8112, author = {{Maaz, Mohammad Urf and Sprenger, Alexander and Hellebrand, Sybille}}, keywords = {{WORKSHOP}}, publisher = {{31. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'19)}}, title = {{{A Hybrid Space Compactor for Varying X-Rates}}}, year = {{2019}}, } @article{8667, author = {{Sprenger, Alexander and Hellebrand, Sybille}}, issn = {{0218-1266}}, journal = {{Journal of Circuits, Systems and Computers}}, number = {{1}}, pages = {{1--23}}, publisher = {{World Scientific Publishing Company}}, title = {{{Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test}}}, doi = {{10.1142/s0218126619400012}}, volume = {{28}}, year = {{2019}}, } @article{13048, abstract = {{Marginal hardware introduces severe reliability threats throughout the life cycle of a system. Although marginalities may not affect the functionality of a circuit immediately after manufacturing, they can degrade into hard failures and must be screened out during manufacturing test to prevent early life failures. Furthermore, their evolution in the field must be proactively monitored by periodic tests before actual failures occur. In recent years small delay faults have gained increasing attention as possible indicators of marginal hardware. However, small delay faults on short paths may be undetectable even with advanced timing aware ATPG. Faster-than-at-speed test (FAST) can detect such hidden delay faults, but so far FAST has mainly been restricted to manufacturing test.}}, author = {{Kampmann, Matthias and A. Kochte, Michael and Liu, Chang and Schneider, Eric and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, issn = {{1937-4151}}, journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}}, number = {{10}}, pages = {{1956 -- 1968}}, publisher = {{IEEE}}, title = {{{Built-in Test for Hidden Delay Faults}}}, volume = {{38}}, year = {{2019}}, } @inproceedings{12918, abstract = {{The test for small delay faults is of major importance for predicting potential early life failures or wearout problems. Typically, a faster-than-at-speed test (FAST) with sev¬eral different frequencies is used to detect also hidden small delays, which can only be propagated over short paths. But then the outputs at the end of long paths may no longer reach their stable values at the nominal observation time and must be considered as unknown (X-values). Thus, test response compaction for FAST must be extremely flexible to cope with high X-rates, which also vary with the test frequencies. Stochastic compaction introduced by Mitra et al. is controlled by weighted pseudo-random signals allowing for easy adaptation to varying conditions. As demonstrated in previous work, the pseudo-random control can be optimized for high fault efficiency or X-reduction, but a given target in fault efficiency cannot be guaranteed. To close this gap, a hybrid space compactor is introduced in this paper. It is based on the observation that many faults are lost in the compaction of relatively few critical test patterns. For these critical patterns a deterministic compaction phase is added to the test, where the existing compactor structure is re-used, but controlled by specifically determined control vectors. }}, author = {{Maaz, Mohammad Urf and Sprenger, Alexander and Hellebrand, Sybille}}, booktitle = {{50th IEEE International Test Conference (ITC)}}, keywords = {{Faster-than-at-speed test, BIST, DFT, Test response compaction, Stochastic compactor, X-handling}}, location = {{Washington, DC, USA}}, pages = {{1--8}}, publisher = {{IEEE}}, title = {{{A Hybrid Space Compactor for Adaptive X-Handling}}}, year = {{2019}}, } @misc{4576, author = {{Sprenger, Alexander and Hellebrand, Sybille}}, keywords = {{WORKSHOP}}, publisher = {{30. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'18)}}, title = {{{Stochastische Kompaktierung für den Hochgeschwindigkeitstest}}}, year = {{2018}}, } @article{12974, author = {{Hellebrand, Sybille and Henkel, Joerg and Raghunathan, Anand and Wunderlich, Hans-Joachim}}, journal = {{IEEE Embedded Systems Letters}}, number = {{1}}, pages = {{1--1}}, publisher = {{IEEE}}, title = {{{Guest Editors' Introduction - Special Issue on Approximate Computing}}}, doi = {{10.1109/les.2018.2789942}}, volume = {{10}}, year = {{2018}}, } @article{13057, author = {{Kampmann, Matthias and Hellebrand, Sybille}}, journal = {{Microelectronics Reliability}}, pages = {{124--133}}, title = {{{Design For Small Delay Test - A Simulation Study}}}, volume = {{80}}, year = {{2018}}, } @misc{13072, author = {{Kampmann, Matthias and Hellebrand, Sybille}}, keywords = {{WORKSHOP}}, title = {{{Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test}}}, year = {{2018}}, } @inproceedings{29460, abstract = {{STT-RAM cells can be considered as an alternative or a hybrid addition to today's SRAM-based cache memories. This is mostly because of their scalability and low leakage power. Moreover, their data storing mechanism (storing the value as resistance) makes them very suitable and applicable for multivalue cache architectures. This feature results in system performance enhancement without any area overhead. On the other hand, the required two-step read/write procedure in multilevel cells results in a non-uniform time access and energy and power overhead on the system. In this paper, we propose a new architecture to dynamically swap data between soft (fast read access) and hard (slow read access) bits in ML cell. Moreover, by reconfiguring cache block size, the proposed architecture can switch between ML and SL modes at runtime. In other words, the swapping method places the hot part of each cache block into soft-bits and the less accessed part into the hard-bits. The SL/ML switching method benefits from the low latency and energy of SL mode and the high storing capacity of ML mode at the same time. Although experimental results show that our proposed method slightly increases the miss rate compared with the conventional ML caches, the performance and energy are improved by 4.9% and 6.5%, respectively. Also, the storage overhead of our method is about 1% that is negligible.}}, author = {{Rezaeizadeh Rookerd, Ramin and Sadeghi-Kohan, Somayeh and Navabi, Zainalabedin}}, booktitle = {{Proceedings of the 2018 on Great Lakes Symposium on VLSI}}, publisher = {{ACM}}, title = {{{Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture}}}, doi = {{10.1145/3194554.3194599}}, year = {{2018}}, } @inproceedings{4575, author = {{Sprenger, Alexander and Hellebrand, Sybille}}, booktitle = {{2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)}}, isbn = {{9781538657546}}, publisher = {{IEEE}}, title = {{{Tuning Stochastic Space Compaction to Faster-than-at-Speed Test}}}, doi = {{10.1109/ddecs.2018.00020}}, year = {{2018}}, } @inproceedings{10575, author = {{Liu, Chang and Schneider, Eric and Kampmann, Matthias and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{27th IEEE Asian Test Symposium (ATS'18)}}, isbn = {{9781538694664}}, title = {{{Extending Aging Monitors for Early Life and Wear-Out Failure Prevention}}}, doi = {{10.1109/ats.2018.00028}}, year = {{2018}}, } @inproceedings{29459, abstract = {{Transistor and interconnect wearout is accelerated with transistor scaling resulting in timing variations and consequently reliability challenges in digital circuits. With the emergence of new issues like Electro-migration these problems are getting more crucial. Age monitoring methods can be used to predict and deal with the aging problem. Selecting appropriate locations for placement of aging monitors is an important issue. In this work we propose a procedure for selection of appropriate internal nodes that expose smaller overheads to the circuit, using correlation between nodes and the shareability amongst them. To select internal nodes, we first prune some nodes based on some attributes and thus provide a near-optimal solution that can effectively get a number of internal nodes and consider the effects of electro-migration as well. We have applied our proposed scheme to several processors and ITC benchmarks and have looked at its effectiveness for these circuits.}}, author = {{Sadeghi-Kohan, Somayeh and Vafaei, Arash and Navabi, Zainalabedin}}, booktitle = {{2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)}}, publisher = {{IEEE}}, title = {{{Near-Optimal Node Selection Procedure for Aging Monitor Placement}}}, doi = {{10.1109/iolts.2018.8474120}}, year = {{2018}}, } @inproceedings{12973, author = {{Deshmukh, Jyotirmoy and Kunz, Wolfgang and Wunderlich, Hans-Joachim and Hellebrand, Sybille}}, booktitle = {{35th IEEE VLSI Test Symposium (VTS'17)}}, publisher = {{IEEE}}, title = {{{Special Session on Early Life Failures}}}, doi = {{10.1109/vts.2017.7928933}}, year = {{2017}}, } @misc{13078, author = {{Kampmann, Matthias and Hellebrand, Sybille}}, keywords = {{WORKSHOP}}, title = {{{X-tolerante Prüfzellengruppierung für den Test mit erhöhter Betriebsfrequenz}}}, year = {{2017}}, } @inproceedings{10576, author = {{Kampmann, Matthias and Hellebrand, Sybille}}, booktitle = {{20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS'17)}}, isbn = {{9781538604724}}, publisher = {{IEEE}}, title = {{{Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test}}}, doi = {{10.1109/ddecs.2017.7934564}}, year = {{2017}}, } @article{29462, abstract = {{Time-variant age information of different parts of a system can be used for system-level performance improvement through high-level task scheduling, thus extending the life-time of the system. Progressive age information should provide the age state that the system is in, and the rate that it is being aged at. In this paper, we propose a structure that monitors certain paths of a circuit and detects its gradual age growth, and provides the aging rate and aging state of the circuit. The proposed monitors are placed on a selected set of nodes that represent a timing bottleneck of the system. These monitors sample expected data on these nodes, and compare them with the expected values. The timing of sampling changes as the circuit ages and its delay increases. The timing of sampling will provide a measure of aging advancement of a circuit. To assess the efficacy of the proposed method and compare it with other state-of-the-art aging monitors, we use them on selected nodes of the execution unit of different processors, as well as some circuits from ITC99 benchmarks. The results reveal that the precision of our proposed method is between 0.12 (ns) to 0.401 (ns). Its Area and power overhead are negligible and are about 2.13 and 0.69 percent respectively.}}, author = {{Sadeghi-Kohan, Somayeh and Kamal, Mehdi and Navabi, Zainalabedin}}, issn = {{2168-6750}}, journal = {{IEEE Transactions on Emerging Topics in Computing}}, keywords = {{Age advancement, age monitoring clock, aging rate, self-adjusting monitors}}, number = {{3}}, pages = {{627--641}}, publisher = {{Institute of Electrical and Electronics Engineers (IEEE)}}, title = {{{Self-Adjusting Monitor for Measuring Aging Rate and Advancement}}}, doi = {{10.1109/tetc.2017.2771441}}, volume = {{8}}, year = {{2017}}, } @inproceedings{29463, abstract = {{In this paper we propose to think out of the box and discuss an approach for universal mitigation of Negative Bias Temperature Instability (NBTI) induced aging untied from the limitations of its modelling. The cost-effective approach exploits a simple property of a randomized design, i.e., the equalized signal probability and switching activity at gate inputs. The techniques considered for structural design randomization involve both the hardware architecture and embedded software layers. Ultimately, the proposed approach aims at extending the reliable lifetime of nanoelectronic systems.}}, author = {{Jenihhin, Maksim and Kamkin, Alexander and Navabi, Zainalabedin and Sadeghi-Kohan, Somayeh}}, booktitle = {{2016 IEEE East-West Design & Test Symposium (EWDTS)}}, publisher = {{IEEE}}, title = {{{Universal mitigation of NBTI-induced aging by design randomization}}}, doi = {{10.1109/ewdts.2016.7807635}}, year = {{2017}}, } @inproceedings{12975, author = {{Kampmann, Matthias and Hellebrand, Sybille}}, booktitle = {{25th IEEE Asian Test Symposium (ATS'16)}}, pages = {{1--6}}, publisher = {{IEEE}}, title = {{{X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test}}}, doi = {{10.1109/ats.2016.20}}, year = {{2016}}, } @inproceedings{12976, author = {{Kampmann, Matthias and A. Kochte, Michael and Schneider, Eric and Indlekofer, Thomas and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{24th IEEE Asian Test Symposium (ATS'15)}}, pages = {{109--114}}, publisher = {{IEEE}}, title = {{{Optimized Selection of Frequencies for Faster-Than-at-Speed Test}}}, doi = {{10.1109/ats.2015.26}}, year = {{2015}}, } @article{13056, author = {{Huang, Zhengfeng and Liang, Huaguo and Hellebrand, Sybille}}, journal = {{Journal of Electronic Testing - Theory and Applications (JETTA)}}, number = {{4}}, pages = {{349--359}}, publisher = {{Springer}}, title = {{{A High Performance SEU Tolerant Latch}}}, volume = {{31}}, year = {{2015}}, } @misc{13077, author = {{Hellebrand, Sybille and Indlekofer, Thomas and Kampmann, Matthias and Kochte, Michael and Liu, Chang and Wunderlich, Hans-Joachim}}, keywords = {{Workshop}}, title = {{{Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler}}}, year = {{2015}}, } @inproceedings{29465, abstract = {{Transistor and interconnect wearout is accelerated with transistor scaling resulting in timing variations and consequently reliability challenges in digital circuits. Age monitoring methods can be used to predict and deal with the aging problem. Selecting appropriate locations for placement of hardware aging monitors is an important issue. In this work we propose a procedure for selection of appropriate internal nodes in combinational clouds between pipeline stages or combinational parts of a sequential circuit to place hardware monitors that can effectively provide aging information of various components of a modern digital system. In order to implement the node selection procedure, we propose an object-oriented model. Object-oriented model of a circuit along with a probabilistic and logical simulation engine that we have developed can effectively be used for implementation and also fast evaluation of the proposed node selection mechanism. The proposed object-oriented C+ + models can be integrated into a SystemC RTL model making it possible to perform mixed-level simulation, and integrated evaluation of a complete system. We have applied our proposed scheme to several processors including MIPS, ARM, ALPHA and MiniRISC and have looked at its effectiveness for these processors.}}, author = {{Sadeghi-Kohan, Somayeh and Kamran, Arezoo and Forooghifar, Farnaz and Navabi, Zainalabedin}}, booktitle = {{2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)}}, publisher = {{IEEE}}, title = {{{Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation}}}, doi = {{10.1109/dtis.2015.7127373}}, year = {{2015}}, } @inproceedings{29466, abstract = {{Transistor and interconnect wearout is accelerated with transistor scaling that results in timing variations. Progressive age measurement of a circuit can help a better prevention mechanism for reducing more aging. This requires age monitors that collect progressive age information of the circuit. This paper focuses on monitor structures for implementation of progressive age detection. The monitors are self-adjusting that they adjust themselves to detect progressive changes in the timing of a circuit. Furthermore, the monitors are designed for low hardware overhead, and certainty in reported timing changes.}}, author = {{Sadeghi-Kohan, Somayeh and Kamal, Mehdi and McNeil, John and Prinetto, Paolo and Navabi, Zain}}, booktitle = {{2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)}}, publisher = {{IEEE}}, title = {{{Online self adjusting progressive age monitoring of timing variations}}}, doi = {{10.1109/dtis.2015.7127368}}, year = {{2015}}, } @inproceedings{12977, author = {{Hellebrand, Sybille and Indlekofer, Thomas and Kampmann, Matthias and A. Kochte, Michael and Liu, Chang and Wunderlich, Hans-Joachim}}, booktitle = {{IEEE International Test Conference (ITC'14)}}, publisher = {{IEEE}}, title = {{{FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects}}}, doi = {{10.1109/test.2014.7035360}}, year = {{2014}}, } @article{13054, author = {{Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, journal = {{DeGruyter Journal on Information Technology (it)}}, number = {{4}}, pages = {{165--172}}, publisher = {{DeGruyter}}, title = {{{SAT-Based ATPG beyond Stuck-at Fault Testing}}}, volume = {{56}}, year = {{2014}}, } @article{13055, author = {{Rodriguez Gomez, Laura and Cook, Alejandro and Indlekofer, Thomas and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, journal = {{Journal of Electronic Testing - Theory and Applications (JETTA)}}, number = {{5}}, pages = {{527--540}}, publisher = {{Springer}}, title = {{{Adaptive Bayesian Diagnosis of Intermittent Faults}}}, volume = {{30}}, year = {{2014}}, } @article{46266, author = {{Alizadeh, Bijan and Behnam, Payman and Sadeghi-Kohan, Somayeh}}, issn = {{0018-9340}}, journal = {{IEEE Transactions on Computers}}, keywords = {{Computational Theory and Mathematics, Hardware and Architecture, Theoretical Computer Science, Software}}, pages = {{1--1}}, publisher = {{Institute of Electrical and Electronics Engineers (IEEE)}}, title = {{{A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs}}}, doi = {{10.1109/tc.2014.2329687}}, year = {{2014}}, } @inproceedings{46268, author = {{Mohammadi, Marzieh and Sadeghi-Kohan, Somayeh and Masoumi, Nasser and Navabi, Zainalabedin}}, booktitle = {{2014 19th IEEE European Test Symposium (ETS)}}, publisher = {{IEEE}}, title = {{{An off-line MDSI interconnect BIST incorporated in BS 1149.1}}}, doi = {{10.1109/ets.2014.6847847}}, year = {{2014}}, } @inproceedings{46267, author = {{Sadeghi-Kohan, Somayeh and Behnam, Payman and Alizadeh, Bijan and Fujita, Masahiro and Navabi, Zainalabedin}}, booktitle = {{2014 19th IEEE European Test Symposium (ETS)}}, publisher = {{IEEE}}, title = {{{Improving polynomial datapath debugging with HEDs}}}, doi = {{10.1109/ets.2014.6847797}}, year = {{2014}}, } @inproceedings{12979, author = {{Hellebrand, Sybille}}, booktitle = {{14th IEEE Latin American Test Workshop - (LATW'13)}}, publisher = {{IEEE}}, title = {{{Analyzing and Quantifying Fault Tolerance Properties}}}, doi = {{10.1109/latw.2013.6562662}}, year = {{2013}}, } @misc{13075, author = {{Cook, Alejandro and Rodriguez Gomez, Laura and Hellebrand, Sybille and Indlekofer, Thomas and Wunderlich, Hans-Joachim}}, keywords = {{WORKSHOP}}, title = {{{Adaptive Test and Diagnosis of Intermittent Faults}}}, year = {{2013}}, } @inproceedings{46271, author = {{Sadeghi-Kohan, Somayeh and Namaki-Shoushtari, Majid and Javaheri, Fatemeh and Navabi, Zainalabedin}}, booktitle = {{2012 IEEE International Test Conference}}, publisher = {{IEEE}}, title = {{{BS 1149.1 extensions for an online interconnect fault detection and recovery}}}, doi = {{10.1109/test.2012.6401583}}, year = {{2013}}, } @inproceedings{46270, author = {{Sadeghi-Kohan, Somayeh and Keshavarz, Shahrzad and Zokaee, Farzaneh and Farahmandi, Farimah and Navabi, Zainalabedin}}, booktitle = {{East-West Design & Test Symposium (EWDTS 2013)}}, publisher = {{IEEE}}, title = {{{A new structure for interconnect offline testing}}}, doi = {{10.1109/ewdts.2013.6673207}}, year = {{2013}}, } @inproceedings{12980, author = {{Cook, Alejandro and Hellebrand, Sybille and E. Imhof, Michael and Mumtaz, Abdullah and Wunderlich, Hans-Joachim}}, booktitle = {{13th IEEE Latin American Test Workshop (LATW'12)}}, pages = {{1--4}}, publisher = {{IEEE}}, title = {{{Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test}}}, doi = {{10.1109/latw.2012.6261229}}, year = {{2012}}, } @inproceedings{12981, author = {{Cook, Alejandro and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{17th IEEE European Test Symposium (ETS'12)}}, pages = {{1--6}}, publisher = {{IEEE}}, title = {{{Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test}}}, doi = {{10.1109/ets.2012.6233025}}, year = {{2012}}, } @misc{13074, author = {{Cook, Alejandro and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, keywords = {{WORKSHOP}}, title = {{{Eingebaute Selbstdiagnose mit zufälligen und deterministischen Mustern}}}, year = {{2012}}, } @inproceedings{12982, author = {{Cook, Alejandro and Hellebrand, Sybille and Indlekofer, Thomas and Wunderlich, Hans-Joachim}}, booktitle = {{20th IEEE Asian Test Symposium (ATS'11)}}, pages = {{285--290}}, publisher = {{IEEE}}, title = {{{Diagnostic Test of Robust Circuits}}}, doi = {{10.1109/ats.2011.55}}, year = {{2011}}, } @inproceedings{12984, author = {{Polian, Ilia and Becker, Bernd and Hellebrand, Sybille and Wunderlich, Hans-Joachim and Maxwell, Peter}}, booktitle = {{16th IEEE European Test Symposium Trondheim (ETS'11)}}, publisher = {{IEEE}}, title = {{{Towards Variation-Aware Test Methods}}}, doi = {{10.1109/ets.2011.51}}, year = {{2011}}, } @inproceedings{13053, author = {{Cook, Alejandro and Hellebrand, Sybille and Indlekofer, Thomas and Wunderlich, Hans-Joachim}}, booktitle = {{5. GMM/GI/ITG Fachtagung "Zuverlässigkeit und Entwurf"}}, pages = {{48--53}}, title = {{{Robuster Selbsttest mit Diagnose}}}, year = {{2011}}, } @article{13052, author = {{Hopsch, Fabian and Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans-Joachim}}, journal = {{SCIENCE CHINA Information Sciences, Science China Press, co-published with Springer}}, number = {{4}}, pages = {{1813--1826}}, title = {{{Variation-Aware Fault Modeling}}}, volume = {{54}}, year = {{2011}}, } @inproceedings{46272, author = {{Kamran, Arezoo and Nemati, Nastaran and Sadeghi-Kohan, Somayeh and Navabi, Zainalabedin}}, booktitle = {{2010 East-West Design & Test Symposium (EWDTS)}}, publisher = {{IEEE}}, title = {{{Virtual tester development using HDL/PLI}}}, doi = {{10.1109/ewdts.2010.5742156}}, year = {{2011}}, } @misc{10670, author = {{Fröse, Viktor and Ibers, Rüdiger and Hellebrand, Sybille}}, keywords = {{WORKSHOP}}, title = {{{Testdatenkompression mit Hilfe der Netzwerkinfrastruktur}}}, year = {{2010}}, } @inproceedings{12987, author = {{Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans-Joachim}}, booktitle = {{40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W'10)}}, publisher = {{IEEE}}, title = {{{Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits}}}, doi = {{10.1109/dsnw.2010.5542612}}, year = {{2010}}, } @inproceedings{13051, author = {{Hunger, Marc and Hellebrand, Sybille}}, booktitle = {{4. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf"}}, pages = {{81--88}}, title = {{{Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz}}}, year = {{2010}}, } @misc{13073, author = {{Hellebrand, Sybille}}, title = {{{Nano-Electronic Systems}}}, year = {{2010}}, } @inproceedings{12983, author = {{Hopsch, Fabian and Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans-Joachim}}, booktitle = {{19th IEEE Asian Test Symposium (ATS'10)}}, pages = {{87--93}}, publisher = {{IEEE}}, title = {{{Variation-Aware Fault Modeling}}}, doi = {{10.1109/ats.2010.24}}, year = {{2010}}, } @inproceedings{12985, author = {{Indlekofer, Thomas and Schnittger, Michael and Hellebrand, Sybille}}, booktitle = {{28th IEEE International Conference on Computer Design (ICCD'10)}}, pages = {{480--485}}, publisher = {{IEEE}}, title = {{{Efficient Test Response Compaction for Robust BIST Using Parity Sequences}}}, doi = {{10.1109/iccd.2010.5647648}}, year = {{2010}}, } @inproceedings{12986, author = {{Hunger, Marc and Hellebrand, Sybille}}, booktitle = {{25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'10)}}, pages = {{101--108}}, publisher = {{IEEE}}, title = {{{The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems}}}, doi = {{10.1109/dft.2010.19}}, year = {{2010}}, } @inproceedings{12988, author = {{Froese, Viktor and Ibers, Rüdiger and Hellebrand, Sybille}}, booktitle = {{28th IEEE VLSI Test Symposium (VTS'10)}}, pages = {{227--231}}, publisher = {{IEEE}}, title = {{{Reusing NoC-Infrastructure for Test Data Compression}}}, doi = {{10.1109/vts.2010.5469570}}, year = {{2010}}, } @inproceedings{13049, author = {{Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans-Joachim}}, booktitle = {{4th Workshop on Dependable and Secure Nanocomputing (WDSN'10), (Invited Paper)}}, title = {{{Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits}}}, year = {{2010}}, } @inproceedings{13050, author = {{Indlekofer, Thomas and Schnittger, Michael and Hellebrand, Sybille}}, booktitle = {{4. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf"}}, pages = {{17--24}}, title = {{{Robuster Selbsttest mit extremer Kompaktierung}}}, year = {{2010}}, } @inproceedings{12991, author = {{Hunger, Marc and Hellebrand, Sybille and Czutro, Alejandro and Polian, Ilia and Becker, Bernd}}, booktitle = {{15th IEEE International On-Line Testing Symposium (IOLTS'09}}, publisher = {{IEEE}}, title = {{{ATPG-Based Grading of Strong Fault-Secureness}}}, doi = {{10.1109/iolts.2009.5196027}}, year = {{2009}}, } @inproceedings{12990, author = {{Hellebrand, Sybille and Hunger, Marc}}, booktitle = {{24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'09), (Invited Talk)}}, pages = {{77}}, publisher = {{IEEE}}, title = {{{Are Robust Circuits Really Robust?}}}, doi = {{10.1109/dft.2009.28}}, year = {{2009}}, } @inproceedings{13030, author = {{Hunger, Marc and Hellebrand, Sybille and Czutro, Alexander and Polian, Ilia and Becker, Bernd}}, booktitle = {{3. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf"}}, title = {{{Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung}}}, year = {{2009}}, } @misc{13033, author = {{Coym, Torsten and Hellebrand, Sybille and Ludwig, Stefan and Straube, Bernd and Wunderlich, Hans-Joachim and G. Zoellin, Christian}}, keywords = {{WORKSHOP}}, title = {{{Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit}}}, year = {{2008}}, } @misc{13035, author = {{Amgalan, Uranmandakh and Hachmann, Christian and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, keywords = {{WORKSHOP}}, title = {{{Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen}}}, year = {{2008}}, } @inproceedings{12992, author = {{Oehler, Philipp and Bosio, Alberto and di Natale, Giorgio and Hellebrand, Sybille}}, booktitle = {{14th IEEE International On-Line Testing Symposium (IOLTS'08), (Poster)}}, publisher = {{IEEE}}, title = {{{A Modular Memory BIST for Optimized Memory Repair}}}, doi = {{10.1109/iolts.2008.30}}, year = {{2008}}, } @inproceedings{12994, author = {{Amgalan, Uranmandakh and Hachmann, Christian and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{26th IEEE VLSI Test Symposium (VTS'08)}}, pages = {{125--130}}, publisher = {{IEEE}}, title = {{{Signature Rollback - A Technique for Testing Robust Circuits}}}, doi = {{10.1109/vts.2008.34}}, year = {{2008}}, } @inproceedings{12993, author = {{Hunger, Marc and Hellebrand, Sybille}}, booktitle = {{14th IEEE International On-Line Testing Symposium (IOLTS'08)}}, publisher = {{IEEE}}, title = {{{Verification and Analysis of Self-Checking Properties through ATPG}}}, doi = {{10.1109/iolts.2008.32}}, year = {{2008}}, } @inproceedings{13031, author = {{Hunger, Marc and Hellebrand, Sybille}}, booktitle = {{2. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf"}}, title = {{{Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG}}}, year = {{2008}}, } @inproceedings{13032, author = {{Oehler, Philipp and Bosio, Alberto and Di Natale, Giorgio and Hellebrand, Sybille}}, booktitle = {{2. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf"}}, title = {{{Modularer Selbsttest und optimierte Reparaturanalyse}}}, year = {{2008}}, } @misc{13038, author = {{Hellebrand, Sybille}}, keywords = {{WORKSHOP}}, title = {{{Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing}}}, year = {{2007}}, } @misc{13039, author = {{Ali, Muhammad and Welzl, Michael and Hessler, Sven and Hellebrand, Sybille}}, keywords = {{WORKSHOP}}, title = {{{An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips}}}, year = {{2007}}, } @misc{13042, author = {{Oehler, Philipp and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, keywords = {{WORKSHOP}}, title = {{{An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy}}}, year = {{2007}}, } @misc{13043, author = {{Hellebrand, Sybille}}, title = {{{Qualitätssicherung für Nanochips - Wie IT-Produkte zuverlässig werden}}}, year = {{2007}}, } @inproceedings{12995, author = {{Hellebrand, Sybille and G. Zoellin, Christian and Wunderlich, Hans-Joachim and Ludwig, Stefan and Coym, Torsten and Straube, Bernd}}, booktitle = {{22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'07)}}, pages = {{50--58}}, publisher = {{IEEE}}, title = {{{A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction}}}, doi = {{10.1109/dft.2007.43}}, year = {{2007}}, } @inproceedings{12996, author = {{Oehler, Philipp and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'07)}}, pages = {{185--190}}, publisher = {{IEEE}}, title = {{{Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair}}}, doi = {{10.1109/ddecs.2007.4295278}}, year = {{2007}}, } @inproceedings{12997, author = {{Oehler, Philipp and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{12th IEEE European Test Symposium (ETS'07)}}, pages = {{91--96}}, publisher = {{IEEE}}, title = {{{An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy}}}, doi = {{10.1109/ets.2007.10}}, year = {{2007}}, } @inproceedings{13037, author = {{Hellebrand, Sybille and G. Zoellin, Christian and Wunderlich, Hans-Joachim and Ludwig, Stefan and Coym, Torsten and Straube, Bernd}}, booktitle = {{43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM'07), (Invited Paper)}}, title = {{{Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance}}}, year = {{2007}}, } @article{13036, author = {{Hellebrand, Sybille and G. Zoellin, Christian and Wunderlich, Hans-Joachim and Ludwig, Stefan and Coym, Torsten and Straube, Bernd}}, journal = {{Informacije MIDEM, Ljubljana (Invited Paper)}}, number = {{4 (124)}}, pages = {{212--219}}, title = {{{Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance}}}, volume = {{37}}, year = {{2007}}, } @article{13044, author = {{Ali, Muhammad and Hessler, Sven and Welzl, Michael and Hellebrand, Sybille}}, journal = {{International Journal on High Performance Systems Architecture}}, number = {{2}}, pages = {{113--123}}, title = {{{An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip}}}, volume = {{1}}, year = {{2007}}, } @inproceedings{13040, author = {{Ali, Muhammad and Welzl, Michael and Hessler, Sven and Hellebrand, Sybille}}, booktitle = {{4th International Conference on Information Technology: New Generations (ITNG'07)}}, pages = {{1027--1032}}, title = {{{A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip}}}, year = {{2007}}, } @inproceedings{13041, author = {{Becker, Bernd and Polian, Ilia and Hellebrand, Sybille and Straube, Bernd and Wunderlich, Hans-Joachim}}, booktitle = {{1. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf"}}, title = {{{Test und Zuverlässigkeit nanoelektronischer Systeme}}}, year = {{2007}}, } @article{13045, author = {{Becker, Bernd and Polian, Ilia and Hellebrand, Sybille and Straube, Bernd and Wunderlich, Hans-Joachim}}, journal = {{it - Information Technology}}, number = {{5}}, pages = {{305--311}}, title = {{{DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme}}}, volume = {{48}}, year = {{2006}}, } @misc{13046, author = {{Oehler, Philipp and Hellebrand, Sybille}}, keywords = {{WORKSHOP}}, title = {{{A Low Power Design for Embedded DRAMs with Online Consistency Checking}}}, year = {{2005}}, } @misc{13101, author = {{Ali, Muhammad and Welzl, Michael and Hellebrand, Sybille}}, keywords = {{WORKSHOP}}, title = {{{Dynamic Routing: A Prerequisite for Reliable NoCs}}}, year = {{2005}}, } @misc{13102, author = {{Oehler, Philipp and Hellebrand, Sybille}}, keywords = {{WORKSHOP}}, title = {{{Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study}}}, year = {{2005}}, } @inproceedings{12999, author = {{Ali, Muhammad and Welzl, Michael and Zwicknagl, Martin and Hellebrand, Sybille}}, booktitle = {{IEEE International Conference on Microelectronics (ICM'05)}}, publisher = {{IEEE}}, title = {{{Considerations for Fault-Tolerant Networks on Chips}}}, doi = {{10.1109/icm.2005.1590063}}, year = {{2005}}, } @inproceedings{13000, author = {{Oehler, Philipp and Hellebrand, Sybille}}, booktitle = {{10th IEEE European Test Symposium (ETS'05)}}, pages = {{148--153}}, publisher = {{IEEE}}, title = {{{Low Power Embedded DRAMs with High Quality Error Correcting Capabilities}}}, doi = {{10.1109/ets.2005.28}}, year = {{2005}}, } @inproceedings{12998, author = {{Ali, Muhammad and Welzl, Michael and Hellebrand, Sybille}}, booktitle = {{23rd IEEE NORCHIP Conference}}, pages = {{70--73}}, publisher = {{IEEE}}, title = {{{A Dynamic Routing Mechanism for Network on Chip}}}, doi = {{10.1109/norchp.2005.1596991}}, year = {{2005}}, } @inproceedings{13071, author = {{Liu Jing, Michelle and Ruehrup, Stefan and Schindelhauer, Christian and Volbert, Klaus and Dierkes, Martin and Bellgardt, Andreas and Ibers, Rüdiger and Hilleringmann, Ulrich}}, booktitle = {{{GOR/NGB Conference Tilburg 2004}}}, title = {{{Sensor Networks with More Features Using Less Hardware}}}, year = {{2004}}, } @misc{13099, author = {{Breu, Ruth and Fahringer, Thomas and Fensel, Dieter and Hellebrand, Sybille and Middeldorp, Aart and Scherzer, Otmar}}, title = {{{Im Westen viel Neues - Informatik an der Universität Innsbruck}}}, year = {{2004}}, } @misc{13100, author = {{Hellebrand, Sybille and Wuertenberger, Armin and S. Tautermann, Christofer}}, keywords = {{WORKSHOP}}, title = {{{Data Compression for Multiple Scan Chains Using Dictionaries with Corrections}}}, year = {{2004}}, }