@inproceedings{4575, author = {{Sprenger, Alexander and Hellebrand, Sybille}}, booktitle = {{2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)}}, isbn = {{9781538657546}}, publisher = {{IEEE}}, title = {{{Tuning Stochastic Space Compaction to Faster-than-at-Speed Test}}}, doi = {{10.1109/ddecs.2018.00020}}, year = {{2018}}, } @inproceedings{10575, author = {{Liu, Chang and Schneider, Eric and Kampmann, Matthias and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{27th IEEE Asian Test Symposium (ATS'18)}}, isbn = {{9781538694664}}, title = {{{Extending Aging Monitors for Early Life and Wear-Out Failure Prevention}}}, doi = {{10.1109/ats.2018.00028}}, year = {{2018}}, } @inproceedings{29459, abstract = {{Transistor and interconnect wearout is accelerated with transistor scaling resulting in timing variations and consequently reliability challenges in digital circuits. With the emergence of new issues like Electro-migration these problems are getting more crucial. Age monitoring methods can be used to predict and deal with the aging problem. Selecting appropriate locations for placement of aging monitors is an important issue. In this work we propose a procedure for selection of appropriate internal nodes that expose smaller overheads to the circuit, using correlation between nodes and the shareability amongst them. To select internal nodes, we first prune some nodes based on some attributes and thus provide a near-optimal solution that can effectively get a number of internal nodes and consider the effects of electro-migration as well. We have applied our proposed scheme to several processors and ITC benchmarks and have looked at its effectiveness for these circuits.}}, author = {{Sadeghi-Kohan, Somayeh and Vafaei, Arash and Navabi, Zainalabedin}}, booktitle = {{2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)}}, publisher = {{IEEE}}, title = {{{Near-Optimal Node Selection Procedure for Aging Monitor Placement}}}, doi = {{10.1109/iolts.2018.8474120}}, year = {{2018}}, } @inproceedings{12973, author = {{Deshmukh, Jyotirmoy and Kunz, Wolfgang and Wunderlich, Hans-Joachim and Hellebrand, Sybille}}, booktitle = {{35th IEEE VLSI Test Symposium (VTS'17)}}, publisher = {{IEEE}}, title = {{{Special Session on Early Life Failures}}}, doi = {{10.1109/vts.2017.7928933}}, year = {{2017}}, } @misc{13078, author = {{Kampmann, Matthias and Hellebrand, Sybille}}, keywords = {{WORKSHOP}}, title = {{{X-tolerante Prüfzellengruppierung für den Test mit erhöhter Betriebsfrequenz}}}, year = {{2017}}, } @inproceedings{10576, author = {{Kampmann, Matthias and Hellebrand, Sybille}}, booktitle = {{20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS'17)}}, isbn = {{9781538604724}}, publisher = {{IEEE}}, title = {{{Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test}}}, doi = {{10.1109/ddecs.2017.7934564}}, year = {{2017}}, } @article{29462, abstract = {{Time-variant age information of different parts of a system can be used for system-level performance improvement through high-level task scheduling, thus extending the life-time of the system. Progressive age information should provide the age state that the system is in, and the rate that it is being aged at. In this paper, we propose a structure that monitors certain paths of a circuit and detects its gradual age growth, and provides the aging rate and aging state of the circuit. The proposed monitors are placed on a selected set of nodes that represent a timing bottleneck of the system. These monitors sample expected data on these nodes, and compare them with the expected values. The timing of sampling changes as the circuit ages and its delay increases. The timing of sampling will provide a measure of aging advancement of a circuit. To assess the efficacy of the proposed method and compare it with other state-of-the-art aging monitors, we use them on selected nodes of the execution unit of different processors, as well as some circuits from ITC99 benchmarks. The results reveal that the precision of our proposed method is between 0.12 (ns) to 0.401 (ns). Its Area and power overhead are negligible and are about 2.13 and 0.69 percent respectively.}}, author = {{Sadeghi-Kohan, Somayeh and Kamal, Mehdi and Navabi, Zainalabedin}}, issn = {{2168-6750}}, journal = {{IEEE Transactions on Emerging Topics in Computing}}, keywords = {{Age advancement, age monitoring clock, aging rate, self-adjusting monitors}}, number = {{3}}, pages = {{627--641}}, publisher = {{Institute of Electrical and Electronics Engineers (IEEE)}}, title = {{{Self-Adjusting Monitor for Measuring Aging Rate and Advancement}}}, doi = {{10.1109/tetc.2017.2771441}}, volume = {{8}}, year = {{2017}}, } @inproceedings{29463, abstract = {{In this paper we propose to think out of the box and discuss an approach for universal mitigation of Negative Bias Temperature Instability (NBTI) induced aging untied from the limitations of its modelling. The cost-effective approach exploits a simple property of a randomized design, i.e., the equalized signal probability and switching activity at gate inputs. The techniques considered for structural design randomization involve both the hardware architecture and embedded software layers. Ultimately, the proposed approach aims at extending the reliable lifetime of nanoelectronic systems.}}, author = {{Jenihhin, Maksim and Kamkin, Alexander and Navabi, Zainalabedin and Sadeghi-Kohan, Somayeh}}, booktitle = {{2016 IEEE East-West Design & Test Symposium (EWDTS)}}, publisher = {{IEEE}}, title = {{{Universal mitigation of NBTI-induced aging by design randomization}}}, doi = {{10.1109/ewdts.2016.7807635}}, year = {{2017}}, } @inproceedings{12975, author = {{Kampmann, Matthias and Hellebrand, Sybille}}, booktitle = {{25th IEEE Asian Test Symposium (ATS'16)}}, pages = {{1--6}}, publisher = {{IEEE}}, title = {{{X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test}}}, doi = {{10.1109/ats.2016.20}}, year = {{2016}}, } @inproceedings{12976, author = {{Kampmann, Matthias and A. Kochte, Michael and Schneider, Eric and Indlekofer, Thomas and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{24th IEEE Asian Test Symposium (ATS'15)}}, pages = {{109--114}}, publisher = {{IEEE}}, title = {{{Optimized Selection of Frequencies for Faster-Than-at-Speed Test}}}, doi = {{10.1109/ats.2015.26}}, year = {{2015}}, } @article{13056, author = {{Huang, Zhengfeng and Liang, Huaguo and Hellebrand, Sybille}}, journal = {{Journal of Electronic Testing - Theory and Applications (JETTA)}}, number = {{4}}, pages = {{349--359}}, publisher = {{Springer}}, title = {{{A High Performance SEU Tolerant Latch}}}, volume = {{31}}, year = {{2015}}, } @misc{13077, author = {{Hellebrand, Sybille and Indlekofer, Thomas and Kampmann, Matthias and Kochte, Michael and Liu, Chang and Wunderlich, Hans-Joachim}}, keywords = {{Workshop}}, title = {{{Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler}}}, year = {{2015}}, } @inproceedings{29465, abstract = {{Transistor and interconnect wearout is accelerated with transistor scaling resulting in timing variations and consequently reliability challenges in digital circuits. Age monitoring methods can be used to predict and deal with the aging problem. Selecting appropriate locations for placement of hardware aging monitors is an important issue. In this work we propose a procedure for selection of appropriate internal nodes in combinational clouds between pipeline stages or combinational parts of a sequential circuit to place hardware monitors that can effectively provide aging information of various components of a modern digital system. In order to implement the node selection procedure, we propose an object-oriented model. Object-oriented model of a circuit along with a probabilistic and logical simulation engine that we have developed can effectively be used for implementation and also fast evaluation of the proposed node selection mechanism. The proposed object-oriented C+ + models can be integrated into a SystemC RTL model making it possible to perform mixed-level simulation, and integrated evaluation of a complete system. We have applied our proposed scheme to several processors including MIPS, ARM, ALPHA and MiniRISC and have looked at its effectiveness for these processors.}}, author = {{Sadeghi-Kohan, Somayeh and Kamran, Arezoo and Forooghifar, Farnaz and Navabi, Zainalabedin}}, booktitle = {{2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)}}, publisher = {{IEEE}}, title = {{{Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation}}}, doi = {{10.1109/dtis.2015.7127373}}, year = {{2015}}, } @inproceedings{29466, abstract = {{Transistor and interconnect wearout is accelerated with transistor scaling that results in timing variations. Progressive age measurement of a circuit can help a better prevention mechanism for reducing more aging. This requires age monitors that collect progressive age information of the circuit. This paper focuses on monitor structures for implementation of progressive age detection. The monitors are self-adjusting that they adjust themselves to detect progressive changes in the timing of a circuit. Furthermore, the monitors are designed for low hardware overhead, and certainty in reported timing changes.}}, author = {{Sadeghi-Kohan, Somayeh and Kamal, Mehdi and McNeil, John and Prinetto, Paolo and Navabi, Zain}}, booktitle = {{2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)}}, publisher = {{IEEE}}, title = {{{Online self adjusting progressive age monitoring of timing variations}}}, doi = {{10.1109/dtis.2015.7127368}}, year = {{2015}}, } @inproceedings{12977, author = {{Hellebrand, Sybille and Indlekofer, Thomas and Kampmann, Matthias and A. Kochte, Michael and Liu, Chang and Wunderlich, Hans-Joachim}}, booktitle = {{IEEE International Test Conference (ITC'14)}}, publisher = {{IEEE}}, title = {{{FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects}}}, doi = {{10.1109/test.2014.7035360}}, year = {{2014}}, } @article{13054, author = {{Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, journal = {{DeGruyter Journal on Information Technology (it)}}, number = {{4}}, pages = {{165--172}}, publisher = {{DeGruyter}}, title = {{{SAT-Based ATPG beyond Stuck-at Fault Testing}}}, volume = {{56}}, year = {{2014}}, } @article{13055, author = {{Rodriguez Gomez, Laura and Cook, Alejandro and Indlekofer, Thomas and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, journal = {{Journal of Electronic Testing - Theory and Applications (JETTA)}}, number = {{5}}, pages = {{527--540}}, publisher = {{Springer}}, title = {{{Adaptive Bayesian Diagnosis of Intermittent Faults}}}, volume = {{30}}, year = {{2014}}, } @article{46266, author = {{Alizadeh, Bijan and Behnam, Payman and Sadeghi-Kohan, Somayeh}}, issn = {{0018-9340}}, journal = {{IEEE Transactions on Computers}}, keywords = {{Computational Theory and Mathematics, Hardware and Architecture, Theoretical Computer Science, Software}}, pages = {{1--1}}, publisher = {{Institute of Electrical and Electronics Engineers (IEEE)}}, title = {{{A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs}}}, doi = {{10.1109/tc.2014.2329687}}, year = {{2014}}, } @inproceedings{46268, author = {{Mohammadi, Marzieh and Sadeghi-Kohan, Somayeh and Masoumi, Nasser and Navabi, Zainalabedin}}, booktitle = {{2014 19th IEEE European Test Symposium (ETS)}}, publisher = {{IEEE}}, title = {{{An off-line MDSI interconnect BIST incorporated in BS 1149.1}}}, doi = {{10.1109/ets.2014.6847847}}, year = {{2014}}, } @inproceedings{46267, author = {{Sadeghi-Kohan, Somayeh and Behnam, Payman and Alizadeh, Bijan and Fujita, Masahiro and Navabi, Zainalabedin}}, booktitle = {{2014 19th IEEE European Test Symposium (ETS)}}, publisher = {{IEEE}}, title = {{{Improving polynomial datapath debugging with HEDs}}}, doi = {{10.1109/ets.2014.6847797}}, year = {{2014}}, }