[{"page":"6","type":"conference","citation":{"mla":"Jafarzadeh, Hanieh, et al. “Time and Space Optimized Storage-Based BIST under Multiple Voltages and Variations.” European Test Symposium, The Hague, Netherlands, May 20-24, 2024, IEEE, p. 6.","bibtex":"@inproceedings{Jafarzadeh_Klemme_Amrouch_Hellebrand_Wunderlich, title={Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations}, booktitle={European Test Symposium, The Hague, Netherlands, May 20-24, 2024}, publisher={IEEE}, author={Jafarzadeh, Hanieh and Klemme, Florian and Amrouch, Hussam and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, pages={6} }","apa":"Jafarzadeh, H., Klemme, F., Amrouch, H., Hellebrand, S., & Wunderlich, H.-J. (n.d.). Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations. European Test Symposium, The Hague, Netherlands, May 20-24, 2024, 6.","ama":"Jafarzadeh H, Klemme F, Amrouch H, Hellebrand S, Wunderlich H-J. Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations. In: European Test Symposium, The Hague, Netherlands, May 20-24, 2024. IEEE; :6.","chicago":"Jafarzadeh, Hanieh, Florian Klemme, Hussam Amrouch, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Time and Space Optimized Storage-Based BIST under Multiple Voltages and Variations.” In European Test Symposium, The Hague, Netherlands, May 20-24, 2024, 6. IEEE, n.d.","ieee":"H. Jafarzadeh, F. Klemme, H. Amrouch, S. Hellebrand, and H.-J. Wunderlich, “Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations,” in European Test Symposium, The Hague, Netherlands, May 20-24, 2024, The Hague, NL, p. 6.","short":"H. Jafarzadeh, F. Klemme, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, in: European Test Symposium, The Hague, Netherlands, May 20-24, 2024, IEEE, n.d., p. 6."},"year":"2024","language":[{"iso":"eng"}],"conference":{"end_date":"2024-05-24","location":"The Hague, NL","name":"IEEE European Test Symposium","start_date":"2024-05-20"},"date_updated":"2024-03-22T17:05:29Z","_id":"52744","publication":"European Test Symposium, The Hague, Netherlands, May 20-24, 2024","department":[{"_id":"48"}],"quality_controlled":"1","publisher":"IEEE","author":[{"full_name":"Jafarzadeh, Hanieh","first_name":"Hanieh","last_name":"Jafarzadeh"},{"last_name":"Klemme","first_name":"Florian","full_name":"Klemme, Florian"},{"full_name":"Amrouch, Hussam","first_name":"Hussam","last_name":"Amrouch"},{"full_name":"Hellebrand, Sybille","orcid":"0000-0002-3717-3939","first_name":"Sybille","id":"209","last_name":"Hellebrand"},{"last_name":"Wunderlich","first_name":"Hans-Joachim","full_name":"Wunderlich, Hans-Joachim"}],"publication_status":"accepted","date_created":"2024-03-22T17:04:25Z","status":"public","title":"Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations","user_id":"209"},{"title":"Vmin Testing under Variations: Defect vs. Fault Coverage","user_id":"209","department":[{"_id":"48"}],"publication":"IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024","publisher":"IEEE","quality_controlled":"1","author":[{"full_name":"Jafarzadeh, Hanieh","first_name":"Hanieh","last_name":"Jafarzadeh"},{"first_name":"Florian","full_name":"Klemme, Florian","last_name":"Klemme"},{"first_name":"Hussam","full_name":"Amrouch, Hussam","last_name":"Amrouch"},{"id":"209","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","first_name":"Sybille"},{"first_name":"Hans-Joachim","full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich"}],"publication_status":"accepted","date_created":"2024-03-22T16:49:22Z","status":"public","conference":{"end_date":"2024-04-12","location":"Maceió","start_date":"2024-04-09","name":"IEEE Latin American Test Symposium (LATS)"},"_id":"52742","date_updated":"2024-03-22T17:06:40Z","page":"6","citation":{"apa":"Jafarzadeh, H., Klemme, F., Amrouch, H., Hellebrand, S., & Wunderlich, H.-J. (n.d.). Vmin Testing under Variations: Defect vs. Fault Coverage. IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, 6.","ama":"Jafarzadeh H, Klemme F, Amrouch H, Hellebrand S, Wunderlich H-J. Vmin Testing under Variations: Defect vs. Fault Coverage. In: IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024. IEEE; :6.","short":"H. Jafarzadeh, F. Klemme, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, in: IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, IEEE, n.d., p. 6.","chicago":"Jafarzadeh, Hanieh, Florian Klemme, Hussam Amrouch, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Vmin Testing under Variations: Defect vs. Fault Coverage.” In IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, 6. IEEE, n.d.","ieee":"H. Jafarzadeh, F. Klemme, H. Amrouch, S. Hellebrand, and H.-J. Wunderlich, “Vmin Testing under Variations: Defect vs. Fault Coverage,” in IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, Maceió, p. 6.","mla":"Jafarzadeh, Hanieh, et al. “Vmin Testing under Variations: Defect vs. Fault Coverage.” IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, IEEE, p. 6.","bibtex":"@inproceedings{Jafarzadeh_Klemme_Amrouch_Hellebrand_Wunderlich, title={Vmin Testing under Variations: Defect vs. Fault Coverage}, booktitle={IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024}, publisher={IEEE}, author={Jafarzadeh, Hanieh and Klemme, Florian and Amrouch, Hussam and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, pages={6} }"},"year":"2024","type":"conference","language":[{"iso":"eng"}]},{"type":"conference","citation":{"chicago":"Hellebrand, Sybille, Somayeh Sadeghi-Kohan, and Hans-Joachim Wunderlich. “Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle.” In International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, 1, n.d.","ama":"Hellebrand S, Sadeghi-Kohan S, Wunderlich H-J. Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle. In: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024. ; :1.","apa":"Hellebrand, S., Sadeghi-Kohan, S., & Wunderlich, H.-J. (n.d.). Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle. International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, 1.","bibtex":"@inproceedings{Hellebrand_Sadeghi-Kohan_Wunderlich, title={Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle}, booktitle={International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024}, author={Hellebrand, Sybille and Sadeghi-Kohan, Somayeh and Wunderlich, Hans-Joachim}, pages={1} }","mla":"Hellebrand, Sybille, et al. “Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle.” International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, p. 1.","short":"S. Hellebrand, S. Sadeghi-Kohan, H.-J. Wunderlich, in: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, n.d., p. 1.","ieee":"S. Hellebrand, S. Sadeghi-Kohan, and H.-J. Wunderlich, “Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle,” in International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, Xi’an, China, p. 1."},"year":"2024","page":"1","language":[{"iso":"eng"}],"_id":"52743","date_updated":"2024-03-22T17:06:02Z","conference":{"end_date":"2024-05-13","start_date":"2024-05-10","name":"International Symposium of EDA (ISEDA)","location":"Xi'an, China"},"author":[{"orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","first_name":"Sybille","id":"209","last_name":"Hellebrand"},{"last_name":"Sadeghi-Kohan","id":"78614","first_name":"Somayeh","full_name":"Sadeghi-Kohan, Somayeh","orcid":"https://orcid.org/0000-0001-7246-0610"},{"full_name":"Wunderlich, Hans-Joachim","first_name":"Hans-Joachim","last_name":"Wunderlich"}],"publication":"International Symposium of EDA (ISEDA), Xi'an, China, May 10-13, 2024","department":[{"_id":"48"}],"publication_status":"accepted","status":"public","date_created":"2024-03-22T16:57:53Z","title":"Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle","user_id":"209"},{"conference":{"end_date":"2024-05-13","start_date":"2024-05-10","name":"International Symposium of EDA (ISEDA)","location":"Xi’an, China"},"_id":"52745","date_updated":"2024-03-22T17:11:16Z","language":[{"iso":"eng"}],"page":"1","year":"2024","citation":{"chicago":"Wunderlich, Hans-Joachim, Hanieh Jafarzadeh, and Sybille Hellebrand. “Robust Test of Small Delay Faults under PVT-Variations.” In International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, 1, n.d.","ama":"Wunderlich H-J, Jafarzadeh H, Hellebrand S. Robust Test of Small Delay Faults under PVT-Variations. In: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024. ; :1.","apa":"Wunderlich, H.-J., Jafarzadeh, H., & Hellebrand, S. (n.d.). Robust Test of Small Delay Faults under PVT-Variations. International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, 1.","bibtex":"@inproceedings{Wunderlich_Jafarzadeh_Hellebrand, title={Robust Test of Small Delay Faults under PVT-Variations}, booktitle={International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024}, author={Wunderlich, Hans-Joachim and Jafarzadeh, Hanieh and Hellebrand, Sybille}, pages={1} }","mla":"Wunderlich, Hans-Joachim, et al. “Robust Test of Small Delay Faults under PVT-Variations.” International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, p. 1.","short":"H.-J. Wunderlich, H. Jafarzadeh, S. Hellebrand, in: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, n.d., p. 1.","ieee":"H.-J. Wunderlich, H. Jafarzadeh, and S. Hellebrand, “Robust Test of Small Delay Faults under PVT-Variations,” in International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, Xi’an, China, p. 1."},"type":"conference","user_id":"209","title":"Robust Test of Small Delay Faults under PVT-Variations","publication":"International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024","department":[{"_id":"48"}],"author":[{"last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim","first_name":"Hans-Joachim"},{"last_name":"Jafarzadeh","full_name":"Jafarzadeh, Hanieh","first_name":"Hanieh"},{"last_name":"Hellebrand","id":"209","first_name":"Sybille","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille"}],"date_created":"2024-03-22T17:11:03Z","status":"public","publication_status":"accepted"},{"date_created":"2024-01-08T08:47:32Z","status":"public","publication_status":"published","department":[{"_id":"48"}],"publisher":"37. ITG / GMM / GI -Workshop \"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen\" (TuZ'24), Feb. 2024","author":[{"first_name":"Alisa","full_name":"Stiballe, Alisa","last_name":"Stiballe"},{"first_name":"Jan Dennis","full_name":"Reimer, Jan Dennis","last_name":"Reimer","id":"36703"},{"first_name":"Somayeh","orcid":"https://orcid.org/0000-0001-7246-0610","full_name":"Sadeghi-Kohan, Somayeh","last_name":"Sadeghi-Kohan","id":"78614"},{"id":"209","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","first_name":"Sybille"}],"user_id":"209","title":"Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression","place":"Darmstadt, Germany","language":[{"iso":"eng"}],"year":"2024","type":"misc","citation":{"mla":"Stiballe, Alisa, et al. Modeling Crosstalk-Induced Interconnect Delay with Polynomial Regression. 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’24), Feb. 2024, 2024.","bibtex":"@book{Stiballe_Reimer_Sadeghi-Kohan_Hellebrand_2024, place={Darmstadt, Germany}, title={Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression}, publisher={37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’24), Feb. 2024}, author={Stiballe, Alisa and Reimer, Jan Dennis and Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}, year={2024} }","apa":"Stiballe, A., Reimer, J. D., Sadeghi-Kohan, S., & Hellebrand, S. (2024). Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression. 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’24), Feb. 2024.","ama":"Stiballe A, Reimer JD, Sadeghi-Kohan S, Hellebrand S. Modeling Crosstalk-Induced Interconnect Delay with Polynomial Regression. 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’24), Feb. 2024; 2024.","chicago":"Stiballe, Alisa, Jan Dennis Reimer, Somayeh Sadeghi-Kohan, and Sybille Hellebrand. Modeling Crosstalk-Induced Interconnect Delay with Polynomial Regression. Darmstadt, Germany: 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’24), Feb. 2024, 2024.","ieee":"A. Stiballe, J. D. Reimer, S. Sadeghi-Kohan, and S. Hellebrand, Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression. Darmstadt, Germany: 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’24), Feb. 2024, 2024.","short":"A. Stiballe, J.D. Reimer, S. Sadeghi-Kohan, S. Hellebrand, Modeling Crosstalk-Induced Interconnect Delay with Polynomial Regression, 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’24), Feb. 2024, Darmstadt, Germany, 2024."},"_id":"50284","date_updated":"2024-03-22T17:12:39Z"},{"date_updated":"2023-04-06T21:06:37Z","_id":"35204","language":[{"iso":"eng"}],"page":"2","year":"2023","type":"misc","citation":{"mla":"Ghazal, Abdulkarim, et al. On Cryptography Effects on Interconnect Reliability. 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, 2023.","bibtex":"@book{Ghazal_Sadeghi-Kohan_Reimer_Hellebrand_2023, place={Erfurt, Germany}, title={On Cryptography Effects on Interconnect Reliability}, publisher={35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023}, author={Ghazal, Abdulkarim and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille}, year={2023} }","chicago":"Ghazal, Abdulkarim, Somayeh Sadeghi-Kohan, Jan Dennis Reimer, and Sybille Hellebrand. On Cryptography Effects on Interconnect Reliability. Erfurt, Germany: 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, 2023.","apa":"Ghazal, A., Sadeghi-Kohan, S., Reimer, J. D., & Hellebrand, S. (2023). On Cryptography Effects on Interconnect Reliability. 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023.","ama":"Ghazal A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. On Cryptography Effects on Interconnect Reliability. 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023; 2023.","ieee":"A. Ghazal, S. Sadeghi-Kohan, J. D. Reimer, and S. Hellebrand, On Cryptography Effects on Interconnect Reliability. Erfurt, Germany: 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, 2023.","short":"A. Ghazal, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, On Cryptography Effects on Interconnect Reliability, 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, Erfurt, Germany, 2023."},"place":"Erfurt, Germany","user_id":"36703","title":"On Cryptography Effects on Interconnect Reliability","keyword":["WORKSHOP"],"department":[{"_id":"48"}],"author":[{"last_name":"Ghazal","first_name":"Abdulkarim","full_name":"Ghazal, Abdulkarim"},{"full_name":"Sadeghi-Kohan, Somayeh","first_name":"Somayeh","id":"78614","last_name":"Sadeghi-Kohan"},{"full_name":"Reimer, Jan Dennis","first_name":"Jan Dennis","id":"36703","last_name":"Reimer"},{"id":"209","last_name":"Hellebrand","full_name":"Hellebrand, Sybille","orcid":"0000-0002-3717-3939","first_name":"Sybille"}],"publisher":"35. Workshop \"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen\" (TuZ'23), Feb. 2023","date_created":"2023-01-04T10:20:41Z","status":"public"},{"place":"Paderborn","title":"Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen","department":[{"_id":"48"}],"publication_status":"published","date_updated":"2023-08-12T09:13:18Z","doi":"10.17619/UNIPB/1-1787","oa":"1","language":[{"iso":"ger"}],"extern":"1","abstract":[{"text":"Ever increasing demands on the performance of microchips are leading to ever more complex semiconductor technologies with ever shrinking feature sizes. Complex applications with high demands on safety and reliability, such as autonomous driving, are simultaneously driving the requirements for test and diagnosis of VLSI circuits. Throughout the life cycle of a microchip, uncertainties occur that affect its timing behavior. For example, weak circuit structures, aging effects, or process variations can lead to a change in the timing behavior of the circuit. While these uncertainties do not necessarily lead to a change of the functional behavior, they can lead to a reliability problem.\r\nWith modular and hybrid compaction two test instruments are presented in this work that can be used for X-tolerant test response compaction in the built-in Faster-than-At-Speed Test (FAST) which is used to detect uncertainties in VLSI circuits. One challenge for test response compaction during FAST is the high and varying X-rate at the outputs of the circuit under test. By dividing the circuit outputs into test groups and separately compacting these test groups using stochastic compactors, the modular compaction is able to handle these high and varying X-rates.\r\nTo deal with uncertainties on logic interconnects, a method for distinguishing crosstalk and process variation is presented. In current semiconductor technologies, the number of parasitic coupling capacitances between logic interconnects is growing. These coupling capacitances can lead to crosstalk, which causes increased current flow in the logic interconnects, which in turn can lead to increased electromigration. In the presented method, delay maps describing the timing behavior of the circuit outputs at different operating points are used to train artificial neural networks which classify the tested circuits into fault-free and faulty.","lang":"eng"},{"lang":"ger","text":"Immer größere Anforderungen an die Leistungsfähigkeit von Mikrochips führen zu Halbleitertechnologien mit immer kleiner werdenden Strukturgrößen. Anwendungen mit hohen Ansprüchen an Sicherheit und Zuverlässigkeit, wie z.B. das autonome Fahren, treiben gleichzeitig die Anforderungen an den Test hochintegrierter Schaltungen an. Während des gesamten Lebenszyklus eines Mikrochips kommt es zu Unsicherheiten im Zeitverhalten. So können z.B. schwache Schaltungsstrukturen, Alterungseffekte oder Prozessvariationen zu einer Veränderung des Zeitverhaltens führen. Während diese Unsicherheiten nicht zu einer Veränderung des funktionalen Verhaltens führen müssen, können sie jedoch zu einem Zuverlässigkeitsproblem führen.\r\nMit der modularen und der hybriden Kompaktierung werden in dieser Arbeit zwei Testinstrumente vorgestellt, die für die X-tolerante Testantwortkompaktierung im eingebauten Hochgeschwindigkeitstest verwendet werden können. Eine Herausforderung für die Testantwortkompaktierung während des Hochgeschwindigkeitstests ist die hohe und variierende X-Rate an den Ausgängen der zu testenden Schaltung. Durch die Einteilung der Schaltungsausgänge in Prüfgruppen und die separierte Kompaktierung der Prüfgruppen mithilfe von stochastischen Kompaktierern, können die vorgestellten Verfahren diese hohen und variierenden X-Raten verarbeiten.\r\nFür den Umgang mit Unsicherheiten auf Verbindungsleitungen der Logik-Schaltung wird ein Verfahren zur Unterscheidung von Übersprechen und Prozessvariation vorgestellt. In aktuellen Halbleitertechnologien kommt es vermehrt zu parasitären Koppelkapazitäten zwischen den Verbindungsleitungen. In dem vorgestellten Verfahren werden künstliche neuronale Netze trainiert, um die Schaltungen in fehlerfrei und fehlerhaft zu klassifizieren."}],"user_id":"22707","publisher":"Universität Paderborn","author":[{"first_name":"Alexander","orcid":"0000-0002-0775-7677","full_name":"Sprenger, Alexander","last_name":"Sprenger","id":"22707"}],"keyword":["Testantwortkompaktierung","Prozessvariation","Silicon Lifecycle Management"],"status":"public","date_created":"2023-08-12T09:10:38Z","_id":"46482","main_file_link":[{"url":"https://nbn-resolving.org/urn:nbn:de:hbz:466:2-45493","open_access":"1"}],"type":"dissertation","citation":{"ieee":"A. Sprenger, Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen. Paderborn: Universität Paderborn, 2023.","short":"A. Sprenger, Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen, Universität Paderborn, Paderborn, 2023.","bibtex":"@book{Sprenger_2023, place={Paderborn}, title={Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen}, DOI={10.17619/UNIPB/1-1787}, publisher={Universität Paderborn}, author={Sprenger, Alexander}, year={2023} }","mla":"Sprenger, Alexander. Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen. Universität Paderborn, 2023, doi:10.17619/UNIPB/1-1787.","chicago":"Sprenger, Alexander. Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen. Paderborn: Universität Paderborn, 2023. https://doi.org/10.17619/UNIPB/1-1787.","ama":"Sprenger A. Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen. Universität Paderborn; 2023. doi:10.17619/UNIPB/1-1787","apa":"Sprenger, A. (2023). Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen. Universität Paderborn. https://doi.org/10.17619/UNIPB/1-1787"},"year":"2023","page":"xi, 160","supervisor":[{"orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","first_name":"Sybille","id":"209","last_name":"Hellebrand"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}]},{"doi":"10.1109/dsn-w58399.2023.00056","_id":"46739","date_updated":"2023-08-26T10:49:07Z","language":[{"iso":"eng"}],"type":"conference","year":"2023","citation":{"ieee":"S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication,” 2023, doi: 10.1109/dsn-w58399.2023.00056.","short":"S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, in: 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), IEEE, 2023.","mla":"Sadeghi-Kohan, Somayeh, et al. “Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication.” 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), IEEE, 2023, doi:10.1109/dsn-w58399.2023.00056.","bibtex":"@inproceedings{Sadeghi-Kohan_Hellebrand_Wunderlich_2023, title={Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication}, DOI={10.1109/dsn-w58399.2023.00056}, booktitle={2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2023} }","ama":"Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. In: 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W). IEEE; 2023. doi:10.1109/dsn-w58399.2023.00056","apa":"Sadeghi-Kohan, S., Hellebrand, S., & Wunderlich, H.-J. (2023). Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W). https://doi.org/10.1109/dsn-w58399.2023.00056","chicago":"Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication.” In 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W). IEEE, 2023. https://doi.org/10.1109/dsn-w58399.2023.00056."},"user_id":"78614","title":"Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication","date_created":"2023-08-26T10:48:31Z","status":"public","publication_status":"published","department":[{"_id":"48"}],"publication":"2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)","author":[{"full_name":"Sadeghi-Kohan, Somayeh","orcid":"https://orcid.org/0000-0001-7246-0610","first_name":"Somayeh","id":"78614","last_name":"Sadeghi-Kohan"},{"first_name":"Sybille","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","last_name":"Hellebrand","id":"209"},{"last_name":"Wunderlich","first_name":"Hans-Joachim","full_name":"Wunderlich, Hans-Joachim"}],"publisher":"IEEE"},{"conference":{"start_date":"2023-10-14","name":"IEEE Asian Test Symposium (ATS'23)","end_date":"2023-10-17"},"_id":"46738","date_updated":"2024-01-08T08:49:08Z","citation":{"ieee":"S. Sadeghi-Kohan, J. D. Reimer, S. Hellebrand, and H.-J. Wunderlich, “Optimizing the Streaming of Sensor Data with Approximate Communication,” presented at the IEEE Asian Test Symposium (ATS’23), 2023.","short":"S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich, in: IEEE Asian Test Symposium (ATS’23), October 2023, Beijing, China, 2023.","bibtex":"@inproceedings{Sadeghi-Kohan_Reimer_Hellebrand_Wunderlich_2023, place={Beijing, China}, title={Optimizing the Streaming of Sensor Data with Approximate Communication}, booktitle={IEEE Asian Test Symposium (ATS’23), October 2023}, author={Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2023} }","mla":"Sadeghi-Kohan, Somayeh, et al. “Optimizing the Streaming of Sensor Data with Approximate Communication.” IEEE Asian Test Symposium (ATS’23), October 2023, 2023.","ama":"Sadeghi-Kohan S, Reimer JD, Hellebrand S, Wunderlich H-J. Optimizing the Streaming of Sensor Data with Approximate Communication. In: IEEE Asian Test Symposium (ATS’23), October 2023. ; 2023.","apa":"Sadeghi-Kohan, S., Reimer, J. D., Hellebrand, S., & Wunderlich, H.-J. (2023). Optimizing the Streaming of Sensor Data with Approximate Communication. IEEE Asian Test Symposium (ATS’23), October 2023. IEEE Asian Test Symposium (ATS’23).","chicago":"Sadeghi-Kohan, Somayeh, Jan Dennis Reimer, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Optimizing the Streaming of Sensor Data with Approximate Communication.” In IEEE Asian Test Symposium (ATS’23), October 2023. Beijing, China, 2023."},"year":"2023","type":"conference","language":[{"iso":"eng"}],"title":"Optimizing the Streaming of Sensor Data with Approximate Communication","user_id":"36703","place":"Beijing, China","date_created":"2023-08-26T08:47:52Z","status":"public","department":[{"_id":"48"}],"publication":"IEEE Asian Test Symposium (ATS'23), October 2023","author":[{"first_name":"Somayeh","orcid":"https://orcid.org/0000-0001-7246-0610","full_name":"Sadeghi-Kohan, Somayeh","last_name":"Sadeghi-Kohan","id":"78614"},{"first_name":"Jan Dennis","full_name":"Reimer, Jan Dennis","last_name":"Reimer","id":"36703"},{"last_name":"Hellebrand","id":"209","first_name":"Sybille","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille"},{"last_name":"Wunderlich","first_name":"Hans-Joachim","full_name":"Wunderlich, Hans-Joachim"}]},{"language":[{"iso":"eng"}],"doi":"10.1109/mdat.2023.3298849","date_updated":"2024-03-22T17:15:10Z","publication_identifier":{"issn":["2168-2356","2168-2364"]},"publication_status":"published","department":[{"_id":"48"}],"title":"Workload-Aware Periodic Interconnect BIST","type":"journal_article","year":"2023","citation":{"bibtex":"@article{Sadeghi-Kohan_Hellebrand_Wunderlich_2023, title={Workload-Aware Periodic Interconnect BIST}, DOI={10.1109/mdat.2023.3298849}, journal={IEEE Design &Test}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2023}, pages={1–1} }","mla":"Sadeghi-Kohan, Somayeh, et al. “Workload-Aware Periodic Interconnect BIST.” IEEE Design &Test, Institute of Electrical and Electronics Engineers (IEEE), 2023, pp. 1–1, doi:10.1109/mdat.2023.3298849.","chicago":"Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Workload-Aware Periodic Interconnect BIST.” IEEE Design &Test, 2023, 1–1. https://doi.org/10.1109/mdat.2023.3298849.","apa":"Sadeghi-Kohan, S., Hellebrand, S., & Wunderlich, H.-J. (2023). Workload-Aware Periodic Interconnect BIST. IEEE Design &Test, 1–1. https://doi.org/10.1109/mdat.2023.3298849","ama":"Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Workload-Aware Periodic Interconnect BIST. IEEE Design &Test. Published online 2023:1-1. doi:10.1109/mdat.2023.3298849","ieee":"S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Workload-Aware Periodic Interconnect BIST,” IEEE Design &Test, pp. 1–1, 2023, doi: 10.1109/mdat.2023.3298849.","short":"S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, IEEE Design &Test (2023) 1–1."},"page":"1-1","main_file_link":[{"url":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10194315"}],"_id":"46264","status":"public","date_created":"2023-08-02T11:07:43Z","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","author":[{"first_name":"Somayeh","full_name":"Sadeghi-Kohan, Somayeh","orcid":"https://orcid.org/0000-0001-7246-0610","last_name":"Sadeghi-Kohan","id":"78614"},{"id":"209","last_name":"Hellebrand","full_name":"Hellebrand, Sybille","orcid":"0000-0002-3717-3939","first_name":"Sybille"},{"last_name":"Wunderlich","first_name":"Hans-Joachim","full_name":"Wunderlich, Hans-Joachim"}],"publication":"IEEE Design &Test","keyword":["Electrical and Electronic Engineering","Hardware and Architecture","Software"],"user_id":"209","article_type":"original","abstract":[{"text":"System-level interconnects provide the\r\nbackbone for increasingly complex systems on a chip. Their\r\nvulnerability to electromigration and crosstalk can lead to\r\nserious reliability and safety issues during the system lifetime.\r\nThis article presents an approach for periodic in-system testing\r\nwhich maintains a reliability profile to detect potential\r\nproblems before they actually cause a failure. Relying on a\r\ncommon infrastructure for EM-aware system workload\r\nmanagement and test, it minimizes the stress induced by the\r\ntest itself and contributes to the self-healing of system-induced\r\nelectromigration degradations. ","lang":"eng"}]}]