[{"department":[{"_id":"48"}],"user_id":"209","_id":"46264","language":[{"iso":"eng"}],"keyword":["Electrical and Electronic Engineering","Hardware and Architecture","Software"],"article_type":"original","publication":"IEEE Design &Test","type":"journal_article","status":"public","abstract":[{"lang":"eng","text":"System-level interconnects provide the\r\nbackbone for increasingly complex systems on a chip. Their\r\nvulnerability to electromigration and crosstalk can lead to\r\nserious reliability and safety issues during the system lifetime.\r\nThis article presents an approach for periodic in-system testing\r\nwhich maintains a reliability profile to detect potential\r\nproblems before they actually cause a failure. Relying on a\r\ncommon infrastructure for EM-aware system workload\r\nmanagement and test, it minimizes the stress induced by the\r\ntest itself and contributes to the self-healing of system-induced\r\nelectromigration degradations. "}],"author":[{"orcid":"https://orcid.org/0000-0001-7246-0610","last_name":"Sadeghi-Kohan","full_name":"Sadeghi-Kohan, Somayeh","id":"78614","first_name":"Somayeh"},{"first_name":"Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","id":"209","full_name":"Hellebrand, Sybille"},{"first_name":"Hans-Joachim","last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim"}],"date_created":"2023-08-02T11:07:43Z","date_updated":"2024-03-22T17:15:10Z","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","doi":"10.1109/mdat.2023.3298849","main_file_link":[{"url":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10194315"}],"title":"Workload-Aware Periodic Interconnect BIST","publication_identifier":{"issn":["2168-2356","2168-2364"]},"publication_status":"published","page":"1-1","citation":{"apa":"Sadeghi-Kohan, S., Hellebrand, S., &#38; Wunderlich, H.-J. (2023). Workload-Aware Periodic Interconnect BIST. <i>IEEE Design &#38;Test</i>, 1–1. <a href=\"https://doi.org/10.1109/mdat.2023.3298849\">https://doi.org/10.1109/mdat.2023.3298849</a>","bibtex":"@article{Sadeghi-Kohan_Hellebrand_Wunderlich_2023, title={Workload-Aware Periodic Interconnect BIST}, DOI={<a href=\"https://doi.org/10.1109/mdat.2023.3298849\">10.1109/mdat.2023.3298849</a>}, journal={IEEE Design &#38;Test}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2023}, pages={1–1} }","short":"S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, IEEE Design &#38;Test (2023) 1–1.","mla":"Sadeghi-Kohan, Somayeh, et al. “Workload-Aware Periodic Interconnect BIST.” <i>IEEE Design &#38;Test</i>, Institute of Electrical and Electronics Engineers (IEEE), 2023, pp. 1–1, doi:<a href=\"https://doi.org/10.1109/mdat.2023.3298849\">10.1109/mdat.2023.3298849</a>.","ama":"Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Workload-Aware Periodic Interconnect BIST. <i>IEEE Design &#38;Test</i>. Published online 2023:1-1. doi:<a href=\"https://doi.org/10.1109/mdat.2023.3298849\">10.1109/mdat.2023.3298849</a>","chicago":"Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Workload-Aware Periodic Interconnect BIST.” <i>IEEE Design &#38;Test</i>, 2023, 1–1. <a href=\"https://doi.org/10.1109/mdat.2023.3298849\">https://doi.org/10.1109/mdat.2023.3298849</a>.","ieee":"S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Workload-Aware Periodic Interconnect BIST,” <i>IEEE Design &#38;Test</i>, pp. 1–1, 2023, doi: <a href=\"https://doi.org/10.1109/mdat.2023.3298849\">10.1109/mdat.2023.3298849</a>."},"year":"2023"},{"publication_status":"published","place":"Anaheim, CA, USA","year":"2023","citation":{"apa":"Jafarzadeh, H., Klemme, F., Reimer, J. D., Najafi Haghi, Z. P.,  Amrouch, H., Hellebrand, S., &#38;  Wunderlich, H.-J. (2023). Robust Pattern Generation for Small Delay Faults under Process Variations. <i>IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023</i>. IEEE International Test Conference (ITC’23), Anaheim, USA.","short":"H. Jafarzadeh, F. Klemme, J.D. Reimer, Z.P. Najafi Haghi, H.  Amrouch, S. Hellebrand, H.-J.  Wunderlich, in: IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023, IEEE, Anaheim, CA, USA, 2023.","mla":"Jafarzadeh, Hanieh, et al. “Robust Pattern Generation for Small Delay Faults under Process Variations.” <i>IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023</i>, IEEE, 2023.","bibtex":"@inproceedings{Jafarzadeh_Klemme_Reimer_Najafi Haghi_ Amrouch_Hellebrand_ Wunderlich_2023, place={Anaheim, CA, USA}, title={Robust Pattern Generation for Small Delay Faults under Process Variations}, booktitle={IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023}, publisher={IEEE}, author={Jafarzadeh, Hanieh and Klemme, Florian and Reimer, Jan Dennis and Najafi Haghi, Zahra Paria and  Amrouch, Hussam and Hellebrand, Sybille and  Wunderlich, Hans-Joachim}, year={2023} }","ama":"Jafarzadeh H, Klemme F, Reimer JD, et al. Robust Pattern Generation for Small Delay Faults under Process Variations. In: <i>IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023</i>. IEEE; 2023.","chicago":"Jafarzadeh, Hanieh, Florian Klemme, Jan Dennis Reimer, Zahra Paria Najafi Haghi, Hussam  Amrouch, Sybille Hellebrand, and Hans-Joachim  Wunderlich. “Robust Pattern Generation for Small Delay Faults under Process Variations.” In <i>IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023</i>. Anaheim, CA, USA: IEEE, 2023.","ieee":"H. Jafarzadeh <i>et al.</i>, “Robust Pattern Generation for Small Delay Faults under Process Variations,” presented at the IEEE International Test Conference (ITC’23), Anaheim, USA, 2023."},"date_updated":"2024-03-22T17:14:02Z","publisher":"IEEE","author":[{"full_name":"Jafarzadeh, Hanieh","last_name":"Jafarzadeh","first_name":"Hanieh"},{"first_name":"Florian","last_name":"Klemme","full_name":"Klemme, Florian"},{"first_name":"Jan Dennis","full_name":"Reimer, Jan Dennis","id":"36703","last_name":"Reimer"},{"first_name":"Zahra Paria","last_name":"Najafi Haghi","full_name":"Najafi Haghi, Zahra Paria"},{"full_name":" Amrouch, Hussam","last_name":" Amrouch","first_name":"Hussam"},{"first_name":"Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","id":"209","full_name":"Hellebrand, Sybille"},{"first_name":"Hans-Joachim","last_name":" Wunderlich","full_name":" Wunderlich, Hans-Joachim"}],"date_created":"2023-07-03T08:20:17Z","title":"Robust Pattern Generation for Small Delay Faults under Process Variations","conference":{"location":"Anaheim, USA","end_date":"2023-10-13","start_date":"2023-10-08","name":"IEEE International Test Conference (ITC'23)"},"publication":"IEEE International Test Conference (ITC'23), Anaheim, USA, October 2023","type":"conference","status":"public","_id":"45830","department":[{"_id":"48"}],"user_id":"209","language":[{"iso":"eng"}]},{"type":"misc","status":"public","department":[{"_id":"48"}],"user_id":"36703","_id":"35204","language":[{"iso":"eng"}],"keyword":["WORKSHOP"],"page":"2","citation":{"ama":"Ghazal A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. <i>On Cryptography Effects on Interconnect Reliability</i>. 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023; 2023.","chicago":"Ghazal, Abdulkarim, Somayeh Sadeghi-Kohan, Jan Dennis Reimer, and Sybille Hellebrand. <i>On Cryptography Effects on Interconnect Reliability</i>. Erfurt, Germany: 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, 2023.","ieee":"A. Ghazal, S. Sadeghi-Kohan, J. D. Reimer, and S. Hellebrand, <i>On Cryptography Effects on Interconnect Reliability</i>. Erfurt, Germany: 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, 2023.","mla":"Ghazal, Abdulkarim, et al. <i>On Cryptography Effects on Interconnect Reliability</i>. 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, 2023.","bibtex":"@book{Ghazal_Sadeghi-Kohan_Reimer_Hellebrand_2023, place={Erfurt, Germany}, title={On Cryptography Effects on Interconnect Reliability}, publisher={35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023}, author={Ghazal, Abdulkarim and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille}, year={2023} }","short":"A. Ghazal, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, On Cryptography Effects on Interconnect Reliability, 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, Erfurt, Germany, 2023.","apa":"Ghazal, A., Sadeghi-Kohan, S., Reimer, J. D., &#38; Hellebrand, S. (2023). <i>On Cryptography Effects on Interconnect Reliability</i>. 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023."},"place":"Erfurt, Germany","year":"2023","author":[{"full_name":"Ghazal, Abdulkarim","last_name":"Ghazal","first_name":"Abdulkarim"},{"full_name":"Sadeghi-Kohan, Somayeh","id":"78614","last_name":"Sadeghi-Kohan","first_name":"Somayeh"},{"first_name":"Jan Dennis","full_name":"Reimer, Jan Dennis","id":"36703","last_name":"Reimer"},{"first_name":"Sybille","id":"209","full_name":"Hellebrand, Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand"}],"date_created":"2023-01-04T10:20:41Z","date_updated":"2023-04-06T21:06:37Z","publisher":"35. Workshop \"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen\" (TuZ'23), Feb. 2023","title":"On Cryptography Effects on Interconnect Reliability"},{"publication_status":"published","citation":{"mla":"Sprenger, Alexander. <i>Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen</i>. Universität Paderborn, 2023, doi:<a href=\"https://doi.org/10.17619/UNIPB/1-1787\">10.17619/UNIPB/1-1787</a>.","short":"A. Sprenger, Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen, Universität Paderborn, Paderborn, 2023.","bibtex":"@book{Sprenger_2023, place={Paderborn}, title={Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen}, DOI={<a href=\"https://doi.org/10.17619/UNIPB/1-1787\">10.17619/UNIPB/1-1787</a>}, publisher={Universität Paderborn}, author={Sprenger, Alexander}, year={2023} }","apa":"Sprenger, A. (2023). <i>Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen</i>. Universität Paderborn. <a href=\"https://doi.org/10.17619/UNIPB/1-1787\">https://doi.org/10.17619/UNIPB/1-1787</a>","ieee":"A. Sprenger, <i>Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen</i>. Paderborn: Universität Paderborn, 2023.","chicago":"Sprenger, Alexander. <i>Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen</i>. Paderborn: Universität Paderborn, 2023. <a href=\"https://doi.org/10.17619/UNIPB/1-1787\">https://doi.org/10.17619/UNIPB/1-1787</a>.","ama":"Sprenger A. <i>Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen</i>. Universität Paderborn; 2023. doi:<a href=\"https://doi.org/10.17619/UNIPB/1-1787\">10.17619/UNIPB/1-1787</a>"},"page":"xi, 160","place":"Paderborn","author":[{"full_name":"Sprenger, Alexander","id":"22707","orcid":"0000-0002-0775-7677","last_name":"Sprenger","first_name":"Alexander"}],"supervisor":[{"first_name":"Sybille","id":"209","full_name":"Hellebrand, Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939"},{"first_name":"Marco","last_name":"Platzner","id":"398","full_name":"Platzner, Marco"}],"date_updated":"2023-08-12T09:13:18Z","oa":"1","main_file_link":[{"url":"https://nbn-resolving.org/urn:nbn:de:hbz:466:2-45493","open_access":"1"}],"doi":"10.17619/UNIPB/1-1787","type":"dissertation","status":"public","user_id":"22707","department":[{"_id":"48"}],"_id":"46482","extern":"1","year":"2023","date_created":"2023-08-12T09:10:38Z","publisher":"Universität Paderborn","title":"Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen","abstract":[{"text":"Ever increasing demands on the performance of microchips are leading to ever more complex semiconductor technologies with ever shrinking feature sizes. Complex applications with high demands on safety and reliability, such as autonomous driving, are simultaneously driving the requirements for test and diagnosis of VLSI circuits. Throughout the life cycle of a microchip, uncertainties occur that affect its timing behavior. For example, weak circuit structures, aging effects, or process variations can lead to a change in the timing behavior of the circuit. While these uncertainties do not necessarily lead to a change of the functional behavior, they can lead to a reliability problem.\r\nWith modular and hybrid compaction two test instruments are presented in this work that can be used for X-tolerant test response compaction in the built-in Faster-than-At-Speed Test (FAST) which is used to detect uncertainties in VLSI circuits. One challenge for test response compaction during FAST is the high and varying X-rate at the outputs of the circuit under test. By dividing the circuit outputs into test groups and separately compacting these test groups using stochastic compactors, the modular compaction is able to handle these high and varying X-rates.\r\nTo deal with uncertainties on logic interconnects, a method for distinguishing crosstalk and process variation is presented. In current semiconductor technologies, the number of parasitic coupling capacitances between logic interconnects is growing. These coupling capacitances can lead to crosstalk, which causes increased current flow in the logic interconnects, which in turn can lead to increased electromigration. In the presented method, delay maps describing the timing behavior of the circuit outputs at different operating points are used to train artificial neural networks which classify the tested circuits into fault-free and faulty.","lang":"eng"},{"text":"Immer größere Anforderungen an die Leistungsfähigkeit von Mikrochips führen zu Halbleitertechnologien mit immer kleiner werdenden Strukturgrößen. Anwendungen mit hohen Ansprüchen an Sicherheit und Zuverlässigkeit, wie z.B. das autonome Fahren, treiben gleichzeitig die Anforderungen an den Test hochintegrierter Schaltungen an. Während des gesamten Lebenszyklus eines Mikrochips kommt es zu Unsicherheiten im Zeitverhalten. So können z.B. schwache Schaltungsstrukturen, Alterungseffekte oder Prozessvariationen zu einer Veränderung des Zeitverhaltens führen. Während diese Unsicherheiten nicht zu einer Veränderung des funktionalen Verhaltens führen müssen, können sie jedoch zu einem Zuverlässigkeitsproblem führen.\r\nMit der modularen und der hybriden Kompaktierung werden in dieser Arbeit zwei Testinstrumente vorgestellt, die für die X-tolerante Testantwortkompaktierung im eingebauten Hochgeschwindigkeitstest verwendet werden können. Eine Herausforderung für die Testantwortkompaktierung während des Hochgeschwindigkeitstests ist die hohe und variierende X-Rate an den Ausgängen der zu testenden Schaltung. Durch die Einteilung der Schaltungsausgänge in Prüfgruppen und die separierte Kompaktierung der Prüfgruppen mithilfe von stochastischen Kompaktierern, können die vorgestellten Verfahren diese hohen und variierenden X-Raten verarbeiten.\r\nFür den Umgang mit Unsicherheiten auf Verbindungsleitungen der Logik-Schaltung wird ein Verfahren zur Unterscheidung von Übersprechen und Prozessvariation vorgestellt. In aktuellen Halbleitertechnologien kommt es vermehrt zu parasitären Koppelkapazitäten zwischen den Verbindungsleitungen. In dem vorgestellten Verfahren werden künstliche neuronale Netze trainiert, um die Schaltungen in fehlerfrei und fehlerhaft zu klassifizieren.","lang":"ger"}],"language":[{"iso":"ger"}],"keyword":["Testantwortkompaktierung","Prozessvariation","Silicon Lifecycle Management"]},{"language":[{"iso":"eng"}],"_id":"46739","user_id":"78614","department":[{"_id":"48"}],"status":"public","type":"conference","publication":"2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)","title":"Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication","doi":"10.1109/dsn-w58399.2023.00056","publisher":"IEEE","date_updated":"2023-08-26T10:49:07Z","date_created":"2023-08-26T10:48:31Z","author":[{"id":"78614","full_name":"Sadeghi-Kohan, Somayeh","last_name":"Sadeghi-Kohan","orcid":"https://orcid.org/0000-0001-7246-0610","first_name":"Somayeh"},{"first_name":"Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","full_name":"Hellebrand, Sybille","id":"209"},{"first_name":"Hans-Joachim","full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich"}],"year":"2023","citation":{"apa":"Sadeghi-Kohan, S., Hellebrand, S., &#38; Wunderlich, H.-J. (2023). Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. <i>2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)</i>. <a href=\"https://doi.org/10.1109/dsn-w58399.2023.00056\">https://doi.org/10.1109/dsn-w58399.2023.00056</a>","short":"S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, in: 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), IEEE, 2023.","bibtex":"@inproceedings{Sadeghi-Kohan_Hellebrand_Wunderlich_2023, title={Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication}, DOI={<a href=\"https://doi.org/10.1109/dsn-w58399.2023.00056\">10.1109/dsn-w58399.2023.00056</a>}, booktitle={2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2023} }","mla":"Sadeghi-Kohan, Somayeh, et al. “Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication.” <i>2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)</i>, IEEE, 2023, doi:<a href=\"https://doi.org/10.1109/dsn-w58399.2023.00056\">10.1109/dsn-w58399.2023.00056</a>.","ama":"Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. In: <i>2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)</i>. IEEE; 2023. doi:<a href=\"https://doi.org/10.1109/dsn-w58399.2023.00056\">10.1109/dsn-w58399.2023.00056</a>","ieee":"S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication,” 2023, doi: <a href=\"https://doi.org/10.1109/dsn-w58399.2023.00056\">10.1109/dsn-w58399.2023.00056</a>.","chicago":"Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication.” In <i>2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)</i>. IEEE, 2023. <a href=\"https://doi.org/10.1109/dsn-w58399.2023.00056\">https://doi.org/10.1109/dsn-w58399.2023.00056</a>."},"publication_status":"published"},{"user_id":"209","department":[{"_id":"48"}],"_id":"29351","language":[{"iso":"eng"}],"article_type":"original","keyword":["Electrical and Electronic Engineering"],"type":"journal_article","publication":"Journal of Electronic Testing","status":"public","abstract":[{"lang":"eng","text":"Safety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. The required high fault coverage at runtime is usually obtained by a combination of concurrent error detection or correction and periodic tests within rather short time intervals. The concurrent scheme ensures the integrity of computed results while the periodic test has to identify potential aging problems and to prevent any fault accumulation which may invalidate the concurrent error detection mechanism. Such periodic built-in self-test (BIST) schemes are already commercialized for memories and for random logic. The paper at hand extends this approach to interconnect structures. A BIST scheme is presented which targets interconnect defects before they will actually affect the system functionality at nominal speed. A BIST schedule is developed which significantly reduces aging caused by electromigration during the lifetime application of the periodic test."}],"date_created":"2022-01-14T11:16:34Z","author":[{"last_name":"Sadeghi-Kohan","id":"78614","full_name":"Sadeghi-Kohan, Somayeh","first_name":"Somayeh"},{"id":"209","full_name":"Hellebrand, Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","first_name":"Sybille"},{"first_name":"Hans-Joachim","full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich"}],"publisher":"Springer Science and Business Media LLC","date_updated":"2022-05-11T16:10:01Z","doi":"10.1007/s10836-021-05979-5","title":"Stress-Aware Periodic Test of Interconnects","publication_status":"published","publication_identifier":{"issn":["0923-8174","1573-0727"]},"citation":{"apa":"Sadeghi-Kohan, S., Hellebrand, S., &#38; Wunderlich, H.-J. (2022). Stress-Aware Periodic Test of Interconnects. <i>Journal of Electronic Testing</i>. <a href=\"https://doi.org/10.1007/s10836-021-05979-5\">https://doi.org/10.1007/s10836-021-05979-5</a>","bibtex":"@article{Sadeghi-Kohan_Hellebrand_Wunderlich_2022, title={Stress-Aware Periodic Test of Interconnects}, DOI={<a href=\"https://doi.org/10.1007/s10836-021-05979-5\">10.1007/s10836-021-05979-5</a>}, journal={Journal of Electronic Testing}, publisher={Springer Science and Business Media LLC}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2022} }","short":"S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, Journal of Electronic Testing (2022).","mla":"Sadeghi-Kohan, Somayeh, et al. “Stress-Aware Periodic Test of Interconnects.” <i>Journal of Electronic Testing</i>, Springer Science and Business Media LLC, 2022, doi:<a href=\"https://doi.org/10.1007/s10836-021-05979-5\">10.1007/s10836-021-05979-5</a>.","ama":"Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Stress-Aware Periodic Test of Interconnects. <i>Journal of Electronic Testing</i>. Published online 2022. doi:<a href=\"https://doi.org/10.1007/s10836-021-05979-5\">10.1007/s10836-021-05979-5</a>","chicago":"Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Stress-Aware Periodic Test of Interconnects.” <i>Journal of Electronic Testing</i>, 2022. <a href=\"https://doi.org/10.1007/s10836-021-05979-5\">https://doi.org/10.1007/s10836-021-05979-5</a>.","ieee":"S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Stress-Aware Periodic Test of Interconnects,” <i>Journal of Electronic Testing</i>, 2022, doi: <a href=\"https://doi.org/10.1007/s10836-021-05979-5\">10.1007/s10836-021-05979-5</a>."},"year":"2022"},{"publisher":"European Workshop on Silicon Lifecycle Management, March 18, 2022","date_updated":"2022-05-11T17:07:24Z","date_created":"2022-02-19T14:21:24Z","author":[{"last_name":"Sadeghi-Kohan","id":"78614","full_name":"Sadeghi-Kohan, Somayeh","first_name":"Somayeh"},{"first_name":"Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","id":"209","full_name":"Hellebrand, Sybille"},{"last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim","first_name":"Hans-Joachim"}],"title":"EM-Aware Interconnect BIST","publication_status":"published","year":"2022","place":"Online","page":"2","citation":{"mla":"Sadeghi-Kohan, Somayeh, et al. <i>EM-Aware Interconnect BIST</i>. European Workshop on Silicon Lifecycle Management, March 18, 2022, 2022.","short":"S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, EM-Aware Interconnect BIST, European Workshop on Silicon Lifecycle Management, March 18, 2022, Online, 2022.","bibtex":"@book{Sadeghi-Kohan_Hellebrand_Wunderlich_2022, place={Online}, title={EM-Aware Interconnect BIST}, publisher={European Workshop on Silicon Lifecycle Management, March 18, 2022}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2022} }","apa":"Sadeghi-Kohan, S., Hellebrand, S., &#38; Wunderlich, H.-J. (2022). <i>EM-Aware Interconnect BIST</i>. European Workshop on Silicon Lifecycle Management, March 18, 2022.","chicago":"Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich. <i>EM-Aware Interconnect BIST</i>. Online: European Workshop on Silicon Lifecycle Management, March 18, 2022, 2022.","ieee":"S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, <i>EM-Aware Interconnect BIST</i>. Online: European Workshop on Silicon Lifecycle Management, March 18, 2022, 2022.","ama":"Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. <i>EM-Aware Interconnect BIST</i>. European Workshop on Silicon Lifecycle Management, March 18, 2022; 2022."},"_id":"29890","department":[{"_id":"48"}],"user_id":"209","keyword":["WORKSHOP"],"language":[{"iso":"eng"}],"type":"misc","status":"public"},{"publication_status":"published","year":"2020","place":"Virtual Conference - Originally Frascati (Rome), Italy","citation":{"apa":"Sprenger, A., Sadeghi-Kohan, S., Reimer, J. D., &#38; Hellebrand, S. (2020). Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020</i>.","short":"A. Sprenger, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020, Virtual Conference - Originally Frascati (Rome), Italy, 2020.","bibtex":"@inproceedings{Sprenger_Sadeghi-Kohan_Reimer_Hellebrand_2020, place={Virtual Conference - Originally Frascati (Rome), Italy}, title={Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study}, booktitle={IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020}, author={Sprenger, Alexander and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille}, year={2020} }","mla":"Sprenger, Alexander, et al. “Variation-Aware Test for Logic Interconnects Using Neural Networks - A Case Study.” <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020</i>, 2020.","ieee":"A. Sprenger, S. Sadeghi-Kohan, J. D. Reimer, and S. Hellebrand, “Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study,” 2020.","chicago":"Sprenger, Alexander, Somayeh Sadeghi-Kohan, Jan Dennis Reimer, and Sybille Hellebrand. “Variation-Aware Test for Logic Interconnects Using Neural Networks - A Case Study.” In <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020</i>. Virtual Conference - Originally Frascati (Rome), Italy, 2020.","ama":"Sprenger A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. In: <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020</i>. ; 2020."},"date_updated":"2022-02-19T14:16:58Z","date_created":"2020-09-15T14:03:02Z","author":[{"last_name":"Sprenger","full_name":"Sprenger, Alexander","id":"22707","first_name":"Alexander"},{"last_name":"Sadeghi-Kohan","id":"78614","full_name":"Sadeghi-Kohan, Somayeh","first_name":"Somayeh"},{"first_name":"Jan Dennis","full_name":"Reimer, Jan Dennis","id":"36703","last_name":"Reimer"},{"id":"209","full_name":"Hellebrand, Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","first_name":"Sybille"}],"title":"Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study","conference":{"end_date":"2020-10-21","start_date":"2020-10-19"},"type":"conference","publication":"IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020","status":"public","_id":"19422","user_id":"209","department":[{"_id":"48"}],"language":[{"iso":"eng"}]},{"publication_status":"published","citation":{"ama":"Sadeghi-Kohan S, Hellebrand S. <i>Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects</i>. 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020; 2020.","chicago":"Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. <i>Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects</i>. Ludwigsburg: 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020, 2020.","ieee":"S. Sadeghi-Kohan and S. Hellebrand, <i>Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects</i>. Ludwigsburg: 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020, 2020.","apa":"Sadeghi-Kohan, S., &#38; Hellebrand, S. (2020). <i>Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects</i>. 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020.","short":"S. Sadeghi-Kohan, S. Hellebrand, Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects, 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020, Ludwigsburg, 2020.","bibtex":"@book{Sadeghi-Kohan_Hellebrand_2020, place={Ludwigsburg}, title={Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects}, publisher={32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}, year={2020} }","mla":"Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. <i>Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects</i>. 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020, 2020."},"page":"4","year":"2020","place":"Ludwigsburg","date_created":"2019-12-29T16:13:58Z","author":[{"last_name":"Sadeghi-Kohan","full_name":"Sadeghi-Kohan, Somayeh","id":"78614","first_name":"Somayeh"},{"last_name":"Hellebrand","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","id":"209","first_name":"Sybille"}],"date_updated":"2022-04-04T12:30:02Z","publisher":"32. Workshop \"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen\" (TuZ'20), 16. - 18. Februar 2020","title":"Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects","type":"misc","status":"public","user_id":"209","department":[{"_id":"48"}],"_id":"15419","language":[{"iso":"eng"}],"keyword":["WORKSHOP"]},{"publication":"38th IEEE VLSI Test Symposium (VTS)","type":"conference","status":"public","_id":"29200","department":[{"_id":"48"}],"user_id":"209","language":[{"iso":"eng"}],"publication_status":"published","year":"2020","place":"Virtual Conference - Originally San Diego, CA, USA","citation":{"apa":"Sadeghi-Kohan, S., &#38; Hellebrand, S. (2020). Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. <i>38th IEEE VLSI Test Symposium (VTS)</i>. <a href=\"https://doi.org/10.1109/vts48691.2020.9107591\">https://doi.org/10.1109/vts48691.2020.9107591</a>","mla":"Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. “Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects.” <i>38th IEEE VLSI Test Symposium (VTS)</i>, IEEE, 2020, doi:<a href=\"https://doi.org/10.1109/vts48691.2020.9107591\">10.1109/vts48691.2020.9107591</a>.","bibtex":"@inproceedings{Sadeghi-Kohan_Hellebrand_2020, place={Virtual Conference - Originally San Diego, CA, USA}, title={Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects}, DOI={<a href=\"https://doi.org/10.1109/vts48691.2020.9107591\">10.1109/vts48691.2020.9107591</a>}, booktitle={38th IEEE VLSI Test Symposium (VTS)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}, year={2020} }","short":"S. Sadeghi-Kohan, S. Hellebrand, in: 38th IEEE VLSI Test Symposium (VTS), IEEE, Virtual Conference - Originally San Diego, CA, USA, 2020.","chicago":"Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. “Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects.” In <i>38th IEEE VLSI Test Symposium (VTS)</i>. Virtual Conference - Originally San Diego, CA, USA: IEEE, 2020. <a href=\"https://doi.org/10.1109/vts48691.2020.9107591\">https://doi.org/10.1109/vts48691.2020.9107591</a>.","ieee":"S. Sadeghi-Kohan and S. Hellebrand, “Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects,” 2020, doi: <a href=\"https://doi.org/10.1109/vts48691.2020.9107591\">10.1109/vts48691.2020.9107591</a>.","ama":"Sadeghi-Kohan S, Hellebrand S. Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. In: <i>38th IEEE VLSI Test Symposium (VTS)</i>. IEEE; 2020. doi:<a href=\"https://doi.org/10.1109/vts48691.2020.9107591\">10.1109/vts48691.2020.9107591</a>"},"publisher":"IEEE","date_updated":"2022-05-11T17:06:38Z","date_created":"2022-01-10T08:38:34Z","author":[{"first_name":"Somayeh","full_name":"Sadeghi-Kohan, Somayeh","id":"78614","last_name":"Sadeghi-Kohan"},{"first_name":"Sybille","id":"209","full_name":"Hellebrand, Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939"}],"title":"Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects","doi":"10.1109/vts48691.2020.9107591"},{"title":"Logic Fault Diagnosis of Hidden Delay Defects","date_updated":"2022-05-11T17:08:20Z","author":[{"last_name":"Holst","full_name":"Holst, Stefan","first_name":"Stefan"},{"id":"10935","full_name":"Kampmann, Matthias","last_name":"Kampmann","first_name":"Matthias"},{"full_name":"Sprenger, Alexander","id":"22707","last_name":"Sprenger","first_name":"Alexander"},{"id":"36703","full_name":"Reimer, Jan Dennis","last_name":"Reimer","first_name":"Jan Dennis"},{"first_name":"Sybille","id":"209","full_name":"Hellebrand, Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand"},{"first_name":"Hans-Joachim","full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich"},{"full_name":"Weng, Xiaoqing","last_name":"Weng","first_name":"Xiaoqing"}],"date_created":"2020-09-15T13:56:08Z","year":"2020","place":"Virtual Conference - Originally Washington, DC, USA","citation":{"chicago":"Holst, Stefan, Matthias Kampmann, Alexander Sprenger, Jan Dennis Reimer, Sybille Hellebrand, Hans-Joachim Wunderlich, and Xiaoqing Weng. “Logic Fault Diagnosis of Hidden Delay Defects.” In <i>IEEE International Test Conference (ITC’20), November 2020</i>. Virtual Conference - Originally Washington, DC, USA, 2020.","ieee":"S. Holst <i>et al.</i>, “Logic Fault Diagnosis of Hidden Delay Defects,” 2020.","ama":"Holst S, Kampmann M, Sprenger A, et al. Logic Fault Diagnosis of Hidden Delay Defects. In: <i>IEEE International Test Conference (ITC’20), November 2020</i>. ; 2020.","apa":"Holst, S., Kampmann, M., Sprenger, A., Reimer, J. D., Hellebrand, S., Wunderlich, H.-J., &#38; Weng, X. (2020). Logic Fault Diagnosis of Hidden Delay Defects. <i>IEEE International Test Conference (ITC’20), November 2020</i>.","bibtex":"@inproceedings{Holst_Kampmann_Sprenger_Reimer_Hellebrand_Wunderlich_Weng_2020, place={Virtual Conference - Originally Washington, DC, USA}, title={Logic Fault Diagnosis of Hidden Delay Defects}, booktitle={IEEE International Test Conference (ITC’20), November 2020}, author={Holst, Stefan and Kampmann, Matthias and Sprenger, Alexander and Reimer, Jan Dennis and Hellebrand, Sybille and Wunderlich, Hans-Joachim and Weng, Xiaoqing}, year={2020} }","mla":"Holst, Stefan, et al. “Logic Fault Diagnosis of Hidden Delay Defects.” <i>IEEE International Test Conference (ITC’20), November 2020</i>, 2020.","short":"S. Holst, M. Kampmann, A. Sprenger, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich, X. Weng, in: IEEE International Test Conference (ITC’20), November 2020, Virtual Conference - Originally Washington, DC, USA, 2020."},"publication_status":"published","language":[{"iso":"eng"}],"_id":"19421","user_id":"209","department":[{"_id":"48"}],"status":"public","type":"conference","publication":"IEEE International Test Conference (ITC'20), November 2020"},{"_id":"8112","user_id":"209","department":[{"_id":"48"}],"keyword":["WORKSHOP"],"language":[{"iso":"eng"}],"type":"misc","status":"public","publisher":"31. Workshop \"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen\" (TuZ'19)","date_updated":"2022-01-06T07:03:51Z","date_created":"2019-02-26T15:11:02Z","author":[{"first_name":"Mohammad Urf","last_name":"Maaz","full_name":"Maaz, Mohammad Urf","id":"49274"},{"last_name":"Sprenger","id":"22707","full_name":"Sprenger, Alexander","first_name":"Alexander"},{"first_name":"Sybille","id":"209","full_name":"Hellebrand, Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939"}],"title":"A Hybrid Space Compactor for Varying X-Rates","year":"2019","place":"Prien am Chiemsee","citation":{"chicago":"Maaz, Mohammad Urf, Alexander Sprenger, and Sybille Hellebrand. <i>A Hybrid Space Compactor for Varying X-Rates</i>. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19), 2019.","ieee":"M. U. Maaz, A. Sprenger, and S. Hellebrand, <i>A Hybrid Space Compactor for Varying X-Rates</i>. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19), 2019.","ama":"Maaz MU, Sprenger A, Hellebrand S. <i>A Hybrid Space Compactor for Varying X-Rates</i>. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19); 2019.","apa":"Maaz, M. U., Sprenger, A., &#38; Hellebrand, S. (2019). <i>A Hybrid Space Compactor for Varying X-Rates</i>. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19).","bibtex":"@book{Maaz_Sprenger_Hellebrand_2019, place={Prien am Chiemsee}, title={A Hybrid Space Compactor for Varying X-Rates}, publisher={31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19)}, author={Maaz, Mohammad Urf and Sprenger, Alexander and Hellebrand, Sybille}, year={2019} }","short":"M.U. Maaz, A. Sprenger, S. Hellebrand, A Hybrid Space Compactor for Varying X-Rates, 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19), Prien am Chiemsee, 2019.","mla":"Maaz, Mohammad Urf, et al. <i>A Hybrid Space Compactor for Varying X-Rates</i>. 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19), 2019."}},{"language":[{"iso":"eng"}],"publication":"Journal of Circuits, Systems and Computers","title":"Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test","date_created":"2019-03-27T08:57:42Z","publisher":"World Scientific Publishing Company","year":"2019","issue":"1","user_id":"59789","department":[{"_id":"48"}],"project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"_id":"8667","status":"public","type":"journal_article","doi":"10.1142/s0218126619400012","author":[{"id":"22707","full_name":"Sprenger, Alexander","last_name":"Sprenger","first_name":"Alexander"},{"id":"209","full_name":"Hellebrand, Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","first_name":"Sybille"}],"volume":28,"date_updated":"2022-01-06T07:03:58Z","citation":{"short":"A. Sprenger, S. Hellebrand, Journal of Circuits, Systems and Computers 28 (2019) 1–23.","bibtex":"@article{Sprenger_Hellebrand_2019, title={Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test}, volume={28}, DOI={<a href=\"https://doi.org/10.1142/s0218126619400012\">10.1142/s0218126619400012</a>}, number={1}, journal={Journal of Circuits, Systems and Computers}, publisher={World Scientific Publishing Company}, author={Sprenger, Alexander and Hellebrand, Sybille}, year={2019}, pages={1–23} }","mla":"Sprenger, Alexander, and Sybille Hellebrand. “Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test.” <i>Journal of Circuits, Systems and Computers</i>, vol. 28, no. 1, World Scientific Publishing Company, 2019, pp. 1–23, doi:<a href=\"https://doi.org/10.1142/s0218126619400012\">10.1142/s0218126619400012</a>.","apa":"Sprenger, A., &#38; Hellebrand, S. (2019). Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test. <i>Journal of Circuits, Systems and Computers</i>, <i>28</i>(1), 1–23. <a href=\"https://doi.org/10.1142/s0218126619400012\">https://doi.org/10.1142/s0218126619400012</a>","ama":"Sprenger A, Hellebrand S. Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test. <i>Journal of Circuits, Systems and Computers</i>. 2019;28(1):1-23. doi:<a href=\"https://doi.org/10.1142/s0218126619400012\">10.1142/s0218126619400012</a>","chicago":"Sprenger, Alexander, and Sybille Hellebrand. “Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test.” <i>Journal of Circuits, Systems and Computers</i> 28, no. 1 (2019): 1–23. <a href=\"https://doi.org/10.1142/s0218126619400012\">https://doi.org/10.1142/s0218126619400012</a>.","ieee":"A. Sprenger and S. Hellebrand, “Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test,” <i>Journal of Circuits, Systems and Computers</i>, vol. 28, no. 1, pp. 1–23, 2019."},"page":"1-23","intvolume":"        28","publication_status":"published","publication_identifier":{"issn":["0218-1266","1793-6454"]}},{"title":"Built-in Test for Hidden Delay Faults","date_updated":"2022-01-06T06:51:27Z","publisher":"IEEE","author":[{"last_name":"Kampmann","id":"10935","full_name":"Kampmann, Matthias","first_name":"Matthias"},{"last_name":"A. Kochte","full_name":"A. Kochte, Michael","first_name":"Michael"},{"last_name":"Liu","full_name":"Liu, Chang","first_name":"Chang"},{"first_name":"Eric","last_name":"Schneider","full_name":"Schneider, Eric"},{"id":"209","full_name":"Hellebrand, Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","first_name":"Sybille"},{"last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim","first_name":"Hans-Joachim"}],"date_created":"2019-08-28T11:44:25Z","volume":38,"year":"2019","citation":{"ama":"Kampmann M, A. Kochte M, Liu C, Schneider E, Hellebrand S, Wunderlich H-J. Built-in Test for Hidden Delay Faults. <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)</i>. 2019;38(10):1956-1968.","ieee":"M. Kampmann, M. A. Kochte, C. Liu, E. Schneider, S. Hellebrand, and H.-J. Wunderlich, “Built-in Test for Hidden Delay Faults,” <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)</i>, vol. 38, no. 10, pp. 1956–1968, 2019.","chicago":"Kampmann, Matthias, Michael A. Kochte, Chang Liu, Eric Schneider, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Built-in Test for Hidden Delay Faults.” <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)</i> 38, no. 10 (2019): 1956–68.","apa":"Kampmann, M., A. Kochte, M., Liu, C., Schneider, E., Hellebrand, S., &#38; Wunderlich, H.-J. (2019). Built-in Test for Hidden Delay Faults. <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)</i>, <i>38</i>(10), 1956–1968.","short":"M. Kampmann, M. A. Kochte, C. Liu, E. Schneider, S. Hellebrand, H.-J. Wunderlich, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 38 (2019) 1956–1968.","bibtex":"@article{Kampmann_A. Kochte_Liu_Schneider_Hellebrand_Wunderlich_2019, title={Built-in Test for Hidden Delay Faults}, volume={38}, number={10}, journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}, publisher={IEEE}, author={Kampmann, Matthias and A. Kochte, Michael and Liu, Chang and Schneider, Eric and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2019}, pages={1956–1968} }","mla":"Kampmann, Matthias, et al. “Built-in Test for Hidden Delay Faults.” <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)</i>, vol. 38, no. 10, IEEE, 2019, pp. 1956–68."},"intvolume":"        38","page":"1956 - 1968","publication_status":"published","publication_identifier":{"eissn":["1937-4151"]},"issue":"10","language":[{"iso":"eng"}],"_id":"13048","user_id":"209","department":[{"_id":"48"}],"abstract":[{"text":"Marginal hardware introduces severe reliability threats throughout the life cycle of a system. Although marginalities may not affect the functionality of a circuit immediately after manufacturing, they can degrade into hard failures and must be screened out during manufacturing test to prevent early life failures. Furthermore, their evolution in the field must be proactively monitored by periodic tests before actual failures occur. In recent years small delay faults have gained increasing attention as possible indicators of marginal hardware. However, small delay faults on short paths may be undetectable even with advanced timing aware ATPG. Faster-than-at-speed test (FAST) can detect such hidden delay faults, but so far FAST has mainly been restricted to manufacturing test.","lang":"eng"}],"status":"public","type":"journal_article","publication":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)"},{"_id":"12918","user_id":"209","department":[{"_id":"48"}],"keyword":["Faster-than-at-speed test","BIST","DFT","Test response compaction","Stochastic compactor","X-handling"],"language":[{"iso":"eng"}],"type":"conference","publication":"50th IEEE International Test Conference (ITC)","abstract":[{"lang":"eng","text":"The test for small delay faults is of major importance for predicting potential early life failures or wearout problems. Typically, a faster-than-at-speed test (FAST) with sev¬eral different frequencies is used to detect also hidden small delays, which can only be propagated over short paths. But then the outputs at the end of long paths may no longer reach their stable values at the nominal observation time and must be considered as unknown (X-values). Thus, test response compaction for FAST must be extremely flexible to cope with high X-rates, which also vary with the test frequencies. Stochastic compaction introduced by Mitra et al. is controlled by weighted pseudo-random signals allowing for easy adaptation to varying conditions. As demonstrated in previous work, the pseudo-random control can be optimized for high fault efficiency or X-reduction, but a given target in fault efficiency cannot be guaranteed. To close this gap, a hybrid space compactor is introduced in this paper. It is based on the observation that many faults are lost in the compaction of relatively few critical test patterns. For these critical patterns a deterministic compaction phase is added to the test, where the existing compactor structure is re-used, but controlled by specifically determined control vectors. "}],"status":"public","publisher":"IEEE","date_updated":"2022-05-11T17:09:35Z","author":[{"last_name":"Maaz","id":"49274","full_name":"Maaz, Mohammad Urf","first_name":"Mohammad Urf"},{"id":"22707","full_name":"Sprenger, Alexander","last_name":"Sprenger","first_name":"Alexander"},{"full_name":"Hellebrand, Sybille","id":"209","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","first_name":"Sybille"}],"date_created":"2019-08-14T06:59:04Z","title":"A Hybrid Space Compactor for Adaptive X-Handling","conference":{"name":"50th IEEE International Test Conference (ITC)","start_date":"2019-11-12","end_date":"2019-11-14","location":"Washington, DC, USA"},"publication_status":"published","quality_controlled":"1","place":"Washington, DC, USA","year":"2019","citation":{"bibtex":"@inproceedings{Maaz_Sprenger_Hellebrand_2019, place={Washington, DC, USA}, title={A Hybrid Space Compactor for Adaptive X-Handling}, booktitle={50th IEEE International Test Conference (ITC)}, publisher={IEEE}, author={Maaz, Mohammad Urf and Sprenger, Alexander and Hellebrand, Sybille}, year={2019}, pages={1–8} }","mla":"Maaz, Mohammad Urf, et al. “A Hybrid Space Compactor for Adaptive X-Handling.” <i>50th IEEE International Test Conference (ITC)</i>, IEEE, 2019, pp. 1–8.","short":"M.U. Maaz, A. Sprenger, S. Hellebrand, in: 50th IEEE International Test Conference (ITC), IEEE, Washington, DC, USA, 2019, pp. 1–8.","apa":"Maaz, M. U., Sprenger, A., &#38; Hellebrand, S. (2019). A Hybrid Space Compactor for Adaptive X-Handling. <i>50th IEEE International Test Conference (ITC)</i>, 1–8.","ieee":"M. U. Maaz, A. Sprenger, and S. Hellebrand, “A Hybrid Space Compactor for Adaptive X-Handling,” in <i>50th IEEE International Test Conference (ITC)</i>, Washington, DC, USA, 2019, pp. 1–8.","chicago":"Maaz, Mohammad Urf, Alexander Sprenger, and Sybille Hellebrand. “A Hybrid Space Compactor for Adaptive X-Handling.” In <i>50th IEEE International Test Conference (ITC)</i>, 1–8. Washington, DC, USA: IEEE, 2019.","ama":"Maaz MU, Sprenger A, Hellebrand S. A Hybrid Space Compactor for Adaptive X-Handling. In: <i>50th IEEE International Test Conference (ITC)</i>. IEEE; 2019:1-8."},"page":"1-8"},{"type":"misc","status":"public","user_id":"22707","department":[{"_id":"48"}],"_id":"4576","language":[{"iso":"ger"}],"keyword":["WORKSHOP"],"citation":{"short":"A. Sprenger, S. Hellebrand, Stochastische Kompaktierung für den Hochgeschwindigkeitstest, 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), Freiburg, Germany, 2018.","bibtex":"@book{Sprenger_Hellebrand_2018, place={Freiburg, Germany}, title={Stochastische Kompaktierung für den Hochgeschwindigkeitstest}, publisher={30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18)}, author={Sprenger, Alexander and Hellebrand, Sybille}, year={2018} }","mla":"Sprenger, Alexander, and Sybille Hellebrand. <i>Stochastische Kompaktierung für den Hochgeschwindigkeitstest</i>. 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), 2018.","apa":"Sprenger, A., &#38; Hellebrand, S. (2018). <i>Stochastische Kompaktierung für den Hochgeschwindigkeitstest</i>. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18).","chicago":"Sprenger, Alexander, and Sybille Hellebrand. <i>Stochastische Kompaktierung für den Hochgeschwindigkeitstest</i>. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), 2018.","ieee":"A. Sprenger and S. Hellebrand, <i>Stochastische Kompaktierung für den Hochgeschwindigkeitstest</i>. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), 2018.","ama":"Sprenger A, Hellebrand S. <i>Stochastische Kompaktierung für den Hochgeschwindigkeitstest</i>. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18); 2018."},"year":"2018","place":"Freiburg, Germany","author":[{"last_name":"Sprenger","full_name":"Sprenger, Alexander","id":"22707","first_name":"Alexander"},{"first_name":"Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","full_name":"Hellebrand, Sybille","id":"209"}],"date_created":"2018-10-02T12:29:44Z","date_updated":"2022-01-06T07:01:13Z","publisher":"30. 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Wunderlich, IEEE Embedded Systems Letters 10 (2018) 1–1.","apa":"Hellebrand, S., Henkel, J., Raghunathan, A., &#38; Wunderlich, H.-J. (2018). Guest Editors’ Introduction - Special Issue on Approximate Computing. <i>IEEE Embedded Systems Letters</i>, <i>10</i>(1), 1–1. <a href=\"https://doi.org/10.1109/les.2018.2789942\">https://doi.org/10.1109/les.2018.2789942</a>","ama":"Hellebrand S, Henkel J, Raghunathan A, Wunderlich H-J. Guest Editors’ Introduction - Special Issue on Approximate Computing. <i>IEEE Embedded Systems Letters</i>. 2018;10(1):1-1. doi:<a href=\"https://doi.org/10.1109/les.2018.2789942\">10.1109/les.2018.2789942</a>","ieee":"S. Hellebrand, J. Henkel, A. Raghunathan, and H.-J. Wunderlich, “Guest Editors’ Introduction - Special Issue on Approximate Computing,” <i>IEEE Embedded Systems Letters</i>, vol. 10, no. 1, pp. 1–1, 2018.","chicago":"Hellebrand, Sybille, Joerg Henkel, Anand Raghunathan, and Hans-Joachim Wunderlich. “Guest Editors’ Introduction - Special Issue on Approximate Computing.” <i>IEEE Embedded Systems Letters</i> 10, no. 1 (2018): 1–1. <a href=\"https://doi.org/10.1109/les.2018.2789942\">https://doi.org/10.1109/les.2018.2789942</a>."},"intvolume":"        10","page":"1-1","issue":"1","title":"Guest Editors' Introduction - Special Issue on Approximate Computing","doi":"10.1109/les.2018.2789942","publisher":"IEEE","date_updated":"2022-01-06T06:51:27Z","author":[{"id":"209","full_name":"Hellebrand, Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","first_name":"Sybille"},{"last_name":"Henkel","full_name":"Henkel, Joerg","first_name":"Joerg"},{"last_name":"Raghunathan","full_name":"Raghunathan, Anand","first_name":"Anand"},{"first_name":"Hans-Joachim","last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim"}],"date_created":"2019-08-28T08:40:58Z","volume":10,"status":"public","type":"journal_article","publication":"IEEE Embedded Systems Letters","language":[{"iso":"eng"}],"_id":"12974","user_id":"209","department":[{"_id":"48"}]},{"date_updated":"2022-01-06T06:51:27Z","date_created":"2019-08-28T11:49:25Z","author":[{"full_name":"Kampmann, Matthias","id":"10935","last_name":"Kampmann","first_name":"Matthias"},{"first_name":"Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","id":"209","full_name":"Hellebrand, Sybille"}],"volume":80,"title":"Design For Small Delay Test - A Simulation Study","year":"2018","citation":{"mla":"Kampmann, Matthias, and Sybille Hellebrand. “Design For Small Delay Test - A Simulation Study.” <i>Microelectronics Reliability</i>, vol. 80, 2018, pp. 124–33.","short":"M. Kampmann, S. Hellebrand, Microelectronics Reliability 80 (2018) 124–133.","bibtex":"@article{Kampmann_Hellebrand_2018, title={Design For Small Delay Test - A Simulation Study}, volume={80}, journal={Microelectronics Reliability}, author={Kampmann, Matthias and Hellebrand, Sybille}, year={2018}, pages={124–133} }","apa":"Kampmann, M., &#38; Hellebrand, S. (2018). Design For Small Delay Test - A Simulation Study. <i>Microelectronics Reliability</i>, <i>80</i>, 124–133.","ama":"Kampmann M, Hellebrand S. Design For Small Delay Test - A Simulation Study. <i>Microelectronics Reliability</i>. 2018;80:124-133.","chicago":"Kampmann, Matthias, and Sybille Hellebrand. “Design For Small Delay Test - A Simulation Study.” <i>Microelectronics Reliability</i> 80 (2018): 124–33.","ieee":"M. Kampmann and S. Hellebrand, “Design For Small Delay Test - A Simulation Study,” <i>Microelectronics Reliability</i>, vol. 80, pp. 124–133, 2018."},"page":"124-133","intvolume":"        80","_id":"13057","user_id":"659","department":[{"_id":"48"}],"language":[{"iso":"eng"}],"type":"journal_article","publication":"Microelectronics Reliability","status":"public"},{"citation":{"apa":"Kampmann, M., &#38; Hellebrand, S. (2018). <i>Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test</i>. 19th Workshop on RTL and High Level Testing (WRTLT’18), Hefei, Anhui, China.","bibtex":"@book{Kampmann_Hellebrand_2018, place={19th Workshop on RTL and High Level Testing (WRTLT’18), Hefei, Anhui, China}, title={Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test}, author={Kampmann, Matthias and Hellebrand, Sybille}, year={2018} }","mla":"Kampmann, Matthias, and Sybille Hellebrand. <i>Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test</i>. 2018.","short":"M. Kampmann, S. Hellebrand, Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test, 19th Workshop on RTL and High Level Testing (WRTLT’18), Hefei, Anhui, China, 2018.","ieee":"M. Kampmann and S. Hellebrand, <i>Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test</i>. 19th Workshop on RTL and High Level Testing (WRTLT’18), Hefei, Anhui, China, 2018.","chicago":"Kampmann, Matthias, and Sybille Hellebrand. <i>Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test</i>. 19th Workshop on RTL and High Level Testing (WRTLT’18), Hefei, Anhui, China, 2018.","ama":"Kampmann M, Hellebrand S. <i>Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test</i>. 19th Workshop on RTL and High Level Testing (WRTLT’18), Hefei, Anhui, China; 2018."},"year":"2018","place":"19th Workshop on RTL and High Level Testing (WRTLT'18), Hefei, Anhui, China","date_created":"2019-08-28T12:00:28Z","author":[{"first_name":"Matthias","id":"10935","full_name":"Kampmann, Matthias","last_name":"Kampmann"},{"first_name":"Sybille","last_name":"Hellebrand","full_name":"Hellebrand, Sybille"}],"date_updated":"2022-01-06T06:51:28Z","title":"Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test","type":"misc","status":"public","user_id":"659","department":[{"_id":"48"}],"_id":"13072","language":[{"iso":"eng"}],"keyword":["WORKSHOP"]},{"title":"Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture","doi":"10.1145/3194554.3194599","publisher":"ACM","date_updated":"2022-01-19T13:44:17Z","date_created":"2022-01-19T13:42:27Z","author":[{"first_name":"Ramin","last_name":"Rezaeizadeh Rookerd","full_name":"Rezaeizadeh Rookerd, Ramin"},{"id":"78614","full_name":"Sadeghi-Kohan, Somayeh","last_name":"Sadeghi-Kohan","first_name":"Somayeh"},{"first_name":"Zainalabedin","full_name":"Navabi, Zainalabedin","last_name":"Navabi"}],"year":"2018","citation":{"apa":"Rezaeizadeh Rookerd, R., Sadeghi-Kohan, S., &#38; Navabi, Z. (2018). Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture. <i>Proceedings of the 2018 on Great Lakes Symposium on VLSI</i>. <a href=\"https://doi.org/10.1145/3194554.3194599\">https://doi.org/10.1145/3194554.3194599</a>","short":"R. Rezaeizadeh Rookerd, S. Sadeghi-Kohan, Z. Navabi, in: Proceedings of the 2018 on Great Lakes Symposium on VLSI, ACM, 2018.","bibtex":"@inproceedings{Rezaeizadeh Rookerd_Sadeghi-Kohan_Navabi_2018, title={Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture}, DOI={<a href=\"https://doi.org/10.1145/3194554.3194599\">10.1145/3194554.3194599</a>}, booktitle={Proceedings of the 2018 on Great Lakes Symposium on VLSI}, publisher={ACM}, author={Rezaeizadeh Rookerd, Ramin and Sadeghi-Kohan, Somayeh and Navabi, Zainalabedin}, year={2018} }","mla":"Rezaeizadeh Rookerd, Ramin, et al. “Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture.” <i>Proceedings of the 2018 on Great Lakes Symposium on VLSI</i>, ACM, 2018, doi:<a href=\"https://doi.org/10.1145/3194554.3194599\">10.1145/3194554.3194599</a>.","ama":"Rezaeizadeh Rookerd R, Sadeghi-Kohan S, Navabi Z. Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture. In: <i>Proceedings of the 2018 on Great Lakes Symposium on VLSI</i>. ACM; 2018. doi:<a href=\"https://doi.org/10.1145/3194554.3194599\">10.1145/3194554.3194599</a>","chicago":"Rezaeizadeh Rookerd, Ramin, Somayeh Sadeghi-Kohan, and Zainalabedin Navabi. “Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture.” In <i>Proceedings of the 2018 on Great Lakes Symposium on VLSI</i>. ACM, 2018. <a href=\"https://doi.org/10.1145/3194554.3194599\">https://doi.org/10.1145/3194554.3194599</a>.","ieee":"R. Rezaeizadeh Rookerd, S. Sadeghi-Kohan, and Z. Navabi, “Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture,” 2018, doi: <a href=\"https://doi.org/10.1145/3194554.3194599\">10.1145/3194554.3194599</a>."},"publication_status":"published","language":[{"iso":"eng"}],"_id":"29460","user_id":"78614","department":[{"_id":"48"}],"abstract":[{"lang":"eng","text":"STT-RAM cells can be considered as an alternative or a hybrid addition to today's SRAM-based cache memories. This is mostly because of their scalability and low leakage power. Moreover, their data storing mechanism (storing the value as resistance) makes them very suitable and applicable for multivalue cache architectures. This feature results in system performance enhancement without any area overhead. On the other hand, the required two-step read/write procedure in multilevel cells results in a non-uniform time access and energy and power overhead on the system. In this paper, we propose a new architecture to dynamically swap data between soft (fast read access) and hard (slow read access) bits in ML cell. Moreover, by reconfiguring cache block size, the proposed architecture can switch between ML and SL modes at runtime. In other words, the swapping method places the hot part of each cache block into soft-bits and the less accessed part into the hard-bits. The SL/ML switching method benefits from the low latency and energy of SL mode and the high storing capacity of ML mode at the same time. Although experimental results show that our proposed method slightly increases the miss rate compared with the conventional ML caches, the performance and energy are improved by 4.9% and 6.5%, respectively. Also, the storage overhead of our method is about 1% that is negligible."}],"status":"public","type":"conference","publication":"Proceedings of the 2018 on Great Lakes Symposium on VLSI"}]