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Wunderlich, “Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair,” in <i>10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07)</i>, 2007, pp. 185–190, doi: <a href=\"https://doi.org/10.1109/ddecs.2007.4295278\">10.1109/ddecs.2007.4295278</a>.","ama":"Oehler P, Hellebrand S, Wunderlich H-J. Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. In: <i>10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07)</i>. 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Wunderlich, “An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy,” in <i>12th IEEE European Test Symposium (ETS’07)</i>, 2007, pp. 91–96, doi: <a href=\"https://doi.org/10.1109/ets.2007.10\">10.1109/ets.2007.10</a>.","bibtex":"@inproceedings{Oehler_Hellebrand_Wunderlich_2007, place={Freiburg, Germany}, title={An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy}, DOI={<a href=\"https://doi.org/10.1109/ets.2007.10\">10.1109/ets.2007.10</a>}, booktitle={12th IEEE European Test Symposium (ETS’07)}, publisher={IEEE}, author={Oehler, Philipp and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2007}, pages={91–96} }","short":"P. Oehler, S. Hellebrand, H.-J. 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