TY - CONF AB - The test for small delay faults is of major importance for predicting potential early life failures or wearout problems. Typically, a faster-than-at-speed test (FAST) with sev¬eral different frequencies is used to detect also hidden small delays, which can only be propagated over short paths. But then the outputs at the end of long paths may no longer reach their stable values at the nominal observation time and must be considered as unknown (X-values). Thus, test response compaction for FAST must be extremely flexible to cope with high X-rates, which also vary with the test frequencies. Stochastic compaction introduced by Mitra et al. is controlled by weighted pseudo-random signals allowing for easy adaptation to varying conditions. As demonstrated in previous work, the pseudo-random control can be optimized for high fault efficiency or X-reduction, but a given target in fault efficiency cannot be guaranteed. To close this gap, a hybrid space compactor is introduced in this paper. It is based on the observation that many faults are lost in the compaction of relatively few critical test patterns. For these critical patterns a deterministic compaction phase is added to the test, where the existing compactor structure is re-used, but controlled by specifically determined control vectors. AU - Maaz, Mohammad Urf AU - Sprenger, Alexander AU - Hellebrand, Sybille ID - 12918 KW - Faster-than-at-speed test KW - BIST KW - DFT KW - Test response compaction KW - Stochastic compactor KW - X-handling T2 - 50th IEEE International Test Conference (ITC) TI - A Hybrid Space Compactor for Adaptive X-Handling ER - TY - GEN AU - Sprenger, Alexander AU - Hellebrand, Sybille ID - 4576 KW - WORKSHOP TI - Stochastische Kompaktierung für den Hochgeschwindigkeitstest ER - TY - JOUR AU - Hellebrand, Sybille AU - Henkel, Joerg AU - Raghunathan, Anand AU - Wunderlich, Hans-Joachim ID - 12974 IS - 1 JF - IEEE Embedded Systems Letters TI - Guest Editors' Introduction - Special Issue on Approximate Computing VL - 10 ER - TY - JOUR AU - Kampmann, Matthias AU - Hellebrand, Sybille ID - 13057 JF - Microelectronics Reliability TI - Design For Small Delay Test - A Simulation Study VL - 80 ER - TY - GEN AU - Kampmann, Matthias AU - Hellebrand, Sybille ID - 13072 KW - WORKSHOP TI - Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test ER - TY - CONF AB - STT-RAM cells can be considered as an alternative or a hybrid addition to today's SRAM-based cache memories. This is mostly because of their scalability and low leakage power. Moreover, their data storing mechanism (storing the value as resistance) makes them very suitable and applicable for multivalue cache architectures. This feature results in system performance enhancement without any area overhead. On the other hand, the required two-step read/write procedure in multilevel cells results in a non-uniform time access and energy and power overhead on the system. In this paper, we propose a new architecture to dynamically swap data between soft (fast read access) and hard (slow read access) bits in ML cell. Moreover, by reconfiguring cache block size, the proposed architecture can switch between ML and SL modes at runtime. In other words, the swapping method places the hot part of each cache block into soft-bits and the less accessed part into the hard-bits. The SL/ML switching method benefits from the low latency and energy of SL mode and the high storing capacity of ML mode at the same time. Although experimental results show that our proposed method slightly increases the miss rate compared with the conventional ML caches, the performance and energy are improved by 4.9% and 6.5%, respectively. Also, the storage overhead of our method is about 1% that is negligible. AU - Rezaeizadeh Rookerd, Ramin AU - Sadeghi-Kohan, Somayeh AU - Navabi, Zainalabedin ID - 29460 T2 - Proceedings of the 2018 on Great Lakes Symposium on VLSI TI - Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture ER - TY - CONF AU - Sprenger, Alexander AU - Hellebrand, Sybille ID - 4575 SN - 9781538657546 T2 - 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) TI - Tuning Stochastic Space Compaction to Faster-than-at-Speed Test ER - TY - CONF AU - Liu, Chang AU - Schneider, Eric AU - Kampmann, Matthias AU - Hellebrand, Sybille AU - Wunderlich, Hans-Joachim ID - 10575 SN - 9781538694664 T2 - 27th IEEE Asian Test Symposium (ATS'18) TI - Extending Aging Monitors for Early Life and Wear-Out Failure Prevention ER - TY - CONF AB - Transistor and interconnect wearout is accelerated with transistor scaling resulting in timing variations and consequently reliability challenges in digital circuits. With the emergence of new issues like Electro-migration these problems are getting more crucial. Age monitoring methods can be used to predict and deal with the aging problem. Selecting appropriate locations for placement of aging monitors is an important issue. In this work we propose a procedure for selection of appropriate internal nodes that expose smaller overheads to the circuit, using correlation between nodes and the shareability amongst them. To select internal nodes, we first prune some nodes based on some attributes and thus provide a near-optimal solution that can effectively get a number of internal nodes and consider the effects of electro-migration as well. We have applied our proposed scheme to several processors and ITC benchmarks and have looked at its effectiveness for these circuits. AU - Sadeghi-Kohan, Somayeh AU - Vafaei, Arash AU - Navabi, Zainalabedin ID - 29459 T2 - 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) TI - Near-Optimal Node Selection Procedure for Aging Monitor Placement ER - TY - CONF AU - Deshmukh, Jyotirmoy AU - Kunz, Wolfgang AU - Wunderlich, Hans-Joachim AU - Hellebrand, Sybille ID - 12973 T2 - 35th IEEE VLSI Test Symposium (VTS'17) TI - Special Session on Early Life Failures ER - TY - GEN AU - Kampmann, Matthias AU - Hellebrand, Sybille ID - 13078 KW - WORKSHOP TI - X-tolerante Prüfzellengruppierung für den Test mit erhöhter Betriebsfrequenz ER - TY - CONF AU - Kampmann, Matthias AU - Hellebrand, Sybille ID - 10576 SN - 9781538604724 T2 - 20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS'17) TI - Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test ER - TY - JOUR AB - Time-variant age information of different parts of a system can be used for system-level performance improvement through high-level task scheduling, thus extending the life-time of the system. Progressive age information should provide the age state that the system is in, and the rate that it is being aged at. In this paper, we propose a structure that monitors certain paths of a circuit and detects its gradual age growth, and provides the aging rate and aging state of the circuit. The proposed monitors are placed on a selected set of nodes that represent a timing bottleneck of the system. These monitors sample expected data on these nodes, and compare them with the expected values. The timing of sampling changes as the circuit ages and its delay increases. The timing of sampling will provide a measure of aging advancement of a circuit. To assess the efficacy of the proposed method and compare it with other state-of-the-art aging monitors, we use them on selected nodes of the execution unit of different processors, as well as some circuits from ITC99 benchmarks. The results reveal that the precision of our proposed method is between 0.12 (ns) to 0.401 (ns). Its Area and power overhead are negligible and are about 2.13 and 0.69 percent respectively. AU - Sadeghi-Kohan, Somayeh AU - Kamal, Mehdi AU - Navabi, Zainalabedin ID - 29462 IS - 3 JF - IEEE Transactions on Emerging Topics in Computing KW - Age advancement KW - age monitoring clock KW - aging rate KW - self-adjusting monitors SN - 2168-6750 TI - Self-Adjusting Monitor for Measuring Aging Rate and Advancement VL - 8 ER - TY - CONF AB - In this paper we propose to think out of the box and discuss an approach for universal mitigation of Negative Bias Temperature Instability (NBTI) induced aging untied from the limitations of its modelling. The cost-effective approach exploits a simple property of a randomized design, i.e., the equalized signal probability and switching activity at gate inputs. The techniques considered for structural design randomization involve both the hardware architecture and embedded software layers. Ultimately, the proposed approach aims at extending the reliable lifetime of nanoelectronic systems. AU - Jenihhin, Maksim AU - Kamkin, Alexander AU - Navabi, Zainalabedin AU - Sadeghi-Kohan, Somayeh ID - 29463 T2 - 2016 IEEE East-West Design & Test Symposium (EWDTS) TI - Universal mitigation of NBTI-induced aging by design randomization ER - TY - CONF AU - Kampmann, Matthias AU - Hellebrand, Sybille ID - 12975 T2 - 25th IEEE Asian Test Symposium (ATS'16) TI - X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test ER - TY - CONF AU - Kampmann, Matthias AU - A. Kochte, Michael AU - Schneider, Eric AU - Indlekofer, Thomas AU - Hellebrand, Sybille AU - Wunderlich, Hans-Joachim ID - 12976 T2 - 24th IEEE Asian Test Symposium (ATS'15) TI - Optimized Selection of Frequencies for Faster-Than-at-Speed Test ER - TY - JOUR AU - Huang, Zhengfeng AU - Liang, Huaguo AU - Hellebrand, Sybille ID - 13056 IS - 4 JF - Journal of Electronic Testing - Theory and Applications (JETTA) TI - A High Performance SEU Tolerant Latch VL - 31 ER - TY - GEN AU - Hellebrand, Sybille AU - Indlekofer, Thomas AU - Kampmann, Matthias AU - Kochte, Michael AU - Liu, Chang AU - Wunderlich, Hans-Joachim ID - 13077 KW - Workshop TI - Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler ER - TY - CONF AB - Transistor and interconnect wearout is accelerated with transistor scaling resulting in timing variations and consequently reliability challenges in digital circuits. Age monitoring methods can be used to predict and deal with the aging problem. Selecting appropriate locations for placement of hardware aging monitors is an important issue. In this work we propose a procedure for selection of appropriate internal nodes in combinational clouds between pipeline stages or combinational parts of a sequential circuit to place hardware monitors that can effectively provide aging information of various components of a modern digital system. In order to implement the node selection procedure, we propose an object-oriented model. Object-oriented model of a circuit along with a probabilistic and logical simulation engine that we have developed can effectively be used for implementation and also fast evaluation of the proposed node selection mechanism. The proposed object-oriented C+ + models can be integrated into a SystemC RTL model making it possible to perform mixed-level simulation, and integrated evaluation of a complete system. We have applied our proposed scheme to several processors including MIPS, ARM, ALPHA and MiniRISC and have looked at its effectiveness for these processors. AU - Sadeghi-Kohan, Somayeh AU - Kamran, Arezoo AU - Forooghifar, Farnaz AU - Navabi, Zainalabedin ID - 29465 T2 - 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) TI - Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation ER - TY - CONF AB - Transistor and interconnect wearout is accelerated with transistor scaling that results in timing variations. Progressive age measurement of a circuit can help a better prevention mechanism for reducing more aging. This requires age monitors that collect progressive age information of the circuit. This paper focuses on monitor structures for implementation of progressive age detection. The monitors are self-adjusting that they adjust themselves to detect progressive changes in the timing of a circuit. Furthermore, the monitors are designed for low hardware overhead, and certainty in reported timing changes. AU - Sadeghi-Kohan, Somayeh AU - Kamal, Mehdi AU - McNeil, John AU - Prinetto, Paolo AU - Navabi, Zain ID - 29466 T2 - 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) TI - Online self adjusting progressive age monitoring of timing variations ER - TY - CONF AU - Hellebrand, Sybille AU - Indlekofer, Thomas AU - Kampmann, Matthias AU - A. Kochte, Michael AU - Liu, Chang AU - Wunderlich, Hans-Joachim ID - 12977 T2 - IEEE International Test Conference (ITC'14) TI - FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects ER - TY - JOUR AU - Hellebrand, Sybille AU - Wunderlich, Hans-Joachim ID - 13054 IS - 4 JF - DeGruyter Journal on Information Technology (it) TI - SAT-Based ATPG beyond Stuck-at Fault Testing VL - 56 ER - TY - JOUR AU - Rodriguez Gomez, Laura AU - Cook, Alejandro AU - Indlekofer, Thomas AU - Hellebrand, Sybille AU - Wunderlich, Hans-Joachim ID - 13055 IS - 5 JF - Journal of Electronic Testing - Theory and Applications (JETTA) TI - Adaptive Bayesian Diagnosis of Intermittent Faults VL - 30 ER - TY - JOUR AU - Alizadeh, Bijan AU - Behnam, Payman AU - Sadeghi-Kohan, Somayeh ID - 46266 JF - IEEE Transactions on Computers KW - Computational Theory and Mathematics KW - Hardware and Architecture KW - Theoretical Computer Science KW - Software SN - 0018-9340 TI - A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs ER - TY - CONF AU - Mohammadi, Marzieh AU - Sadeghi-Kohan, Somayeh AU - Masoumi, Nasser AU - Navabi, Zainalabedin ID - 46268 T2 - 2014 19th IEEE European Test Symposium (ETS) TI - An off-line MDSI interconnect BIST incorporated in BS 1149.1 ER - TY - CONF AU - Sadeghi-Kohan, Somayeh AU - Behnam, Payman AU - Alizadeh, Bijan AU - Fujita, Masahiro AU - Navabi, Zainalabedin ID - 46267 T2 - 2014 19th IEEE European Test Symposium (ETS) TI - Improving polynomial datapath debugging with HEDs ER - TY - CONF AU - Hellebrand, Sybille ID - 12979 T2 - 14th IEEE Latin American Test Workshop - (LATW'13) TI - Analyzing and Quantifying Fault Tolerance Properties ER - TY - GEN AU - Cook, Alejandro AU - Rodriguez Gomez, Laura AU - Hellebrand, Sybille AU - Indlekofer, Thomas AU - Wunderlich, Hans-Joachim ID - 13075 KW - WORKSHOP TI - Adaptive Test and Diagnosis of Intermittent Faults ER - TY - CONF AU - Sadeghi-Kohan, Somayeh AU - Namaki-Shoushtari, Majid AU - Javaheri, Fatemeh AU - Navabi, Zainalabedin ID - 46271 T2 - 2012 IEEE International Test Conference TI - BS 1149.1 extensions for an online interconnect fault detection and recovery ER - TY - CONF AU - Sadeghi-Kohan, Somayeh AU - Keshavarz, Shahrzad AU - Zokaee, Farzaneh AU - Farahmandi, Farimah AU - Navabi, Zainalabedin ID - 46270 T2 - East-West Design & Test Symposium (EWDTS 2013) TI - A new structure for interconnect offline testing ER - TY - CONF AU - Cook, Alejandro AU - Hellebrand, Sybille AU - E. Imhof, Michael AU - Mumtaz, Abdullah AU - Wunderlich, Hans-Joachim ID - 12980 T2 - 13th IEEE Latin American Test Workshop (LATW'12) TI - Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test ER - TY - CONF AU - Cook, Alejandro AU - Hellebrand, Sybille AU - Wunderlich, Hans-Joachim ID - 12981 T2 - 17th IEEE European Test Symposium (ETS'12) TI - Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test ER - TY - GEN AU - Cook, Alejandro AU - Hellebrand, Sybille AU - Wunderlich, Hans-Joachim ID - 13074 KW - WORKSHOP TI - Eingebaute Selbstdiagnose mit zufälligen und deterministischen Mustern ER - TY - CONF AU - Cook, Alejandro AU - Hellebrand, Sybille AU - Indlekofer, Thomas AU - Wunderlich, Hans-Joachim ID - 12982 T2 - 20th IEEE Asian Test Symposium (ATS'11) TI - Diagnostic Test of Robust Circuits ER - TY - CONF AU - Polian, Ilia AU - Becker, Bernd AU - Hellebrand, Sybille AU - Wunderlich, Hans-Joachim AU - Maxwell, Peter ID - 12984 T2 - 16th IEEE European Test Symposium Trondheim (ETS'11) TI - Towards Variation-Aware Test Methods ER - TY - CONF AU - Cook, Alejandro AU - Hellebrand, Sybille AU - Indlekofer, Thomas AU - Wunderlich, Hans-Joachim ID - 13053 T2 - 5. GMM/GI/ITG Fachtagung "Zuverlässigkeit und Entwurf" TI - Robuster Selbsttest mit Diagnose ER - TY - JOUR AU - Hopsch, Fabian AU - Becker, Bernd AU - Hellebrand, Sybille AU - Polian, Ilia AU - Straube, Bernd AU - Vermeiren, Wolfgang AU - Wunderlich, Hans-Joachim ID - 13052 IS - 4 JF - SCIENCE CHINA Information Sciences, Science China Press, co-published with Springer TI - Variation-Aware Fault Modeling VL - 54 ER - TY - CONF AU - Kamran, Arezoo AU - Nemati, Nastaran AU - Sadeghi-Kohan, Somayeh AU - Navabi, Zainalabedin ID - 46272 T2 - 2010 East-West Design & Test Symposium (EWDTS) TI - Virtual tester development using HDL/PLI ER - TY - GEN AU - Fröse, Viktor AU - Ibers, Rüdiger AU - Hellebrand, Sybille ID - 10670 KW - WORKSHOP TI - Testdatenkompression mit Hilfe der Netzwerkinfrastruktur ER - TY - CONF AU - Becker, Bernd AU - Hellebrand, Sybille AU - Polian, Ilia AU - Straube, Bernd AU - Vermeiren, Wolfgang AU - Wunderlich, Hans-Joachim ID - 12987 T2 - 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W'10) TI - Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits ER - TY - CONF AU - Hunger, Marc AU - Hellebrand, Sybille ID - 13051 T2 - 4. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf" TI - Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz ER - TY - GEN AU - Hellebrand, Sybille ID - 13073 TI - Nano-Electronic Systems ER - TY - CONF AU - Hopsch, Fabian AU - Becker, Bernd AU - Hellebrand, Sybille AU - Polian, Ilia AU - Straube, Bernd AU - Vermeiren, Wolfgang AU - Wunderlich, Hans-Joachim ID - 12983 T2 - 19th IEEE Asian Test Symposium (ATS'10) TI - Variation-Aware Fault Modeling ER - TY - CONF AU - Indlekofer, Thomas AU - Schnittger, Michael AU - Hellebrand, Sybille ID - 12985 T2 - 28th IEEE International Conference on Computer Design (ICCD'10) TI - Efficient Test Response Compaction for Robust BIST Using Parity Sequences ER - TY - CONF AU - Hunger, Marc AU - Hellebrand, Sybille ID - 12986 T2 - 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'10) TI - The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems ER - TY - CONF AU - Froese, Viktor AU - Ibers, Rüdiger AU - Hellebrand, Sybille ID - 12988 T2 - 28th IEEE VLSI Test Symposium (VTS'10) TI - Reusing NoC-Infrastructure for Test Data Compression ER - TY - CONF AU - Becker, Bernd AU - Hellebrand, Sybille AU - Polian, Ilia AU - Straube, Bernd AU - Vermeiren, Wolfgang AU - Wunderlich, Hans-Joachim ID - 13049 T2 - 4th Workshop on Dependable and Secure Nanocomputing (WDSN'10), (Invited Paper) TI - Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits ER - TY - CONF AU - Indlekofer, Thomas AU - Schnittger, Michael AU - Hellebrand, Sybille ID - 13050 T2 - 4. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf" TI - Robuster Selbsttest mit extremer Kompaktierung ER - TY - CONF AU - Hunger, Marc AU - Hellebrand, Sybille AU - Czutro, Alejandro AU - Polian, Ilia AU - Becker, Bernd ID - 12991 T2 - 15th IEEE International On-Line Testing Symposium (IOLTS'09 TI - ATPG-Based Grading of Strong Fault-Secureness ER - TY - CONF AU - Hellebrand, Sybille AU - Hunger, Marc ID - 12990 T2 - 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'09), (Invited Talk) TI - Are Robust Circuits Really Robust? ER -