X-tolerante Prüfzellengruppierung für den Test mit erhöhter Betriebsfrequenz - Kampmann, Matthias; Hellebrand, Sybille
Keywords: WORKSHOP

Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test - Kampmann, Matthias; Hellebrand, Sybille (20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS'17))

Self-Adjusting Monitor for Measuring Aging Rate and Advancement - Sadeghi-Kohan, Somayeh; Kamal, Mehdi; Navabi, Zainalabedin (IEEE Transactions on Emerging Topics in Computing)
Time-variant age information of different parts of a system can be used for system-level performance improvement through high-level task scheduling, thus extending the life-time of the system. Progressive age information should provide the age state that the system is in, and the rate that it is being aged at. In this paper, we propose a structure that monitors certain paths of a circuit and detects its gradual age growth, and provides the aging rate and aging state of the circuit. The proposed monitors are placed on a selected set of nodes that represent a timing bottleneck of the system. These monitors sample expected data on these nodes, and compare them with the expected values. The timing of sampling changes as the circuit ages and its delay increases. The timing of sampling will provide a measure of aging advancement of a circuit. To assess the efficacy of the proposed method and compare it with other state-of-the-art aging monitors, we use them on selected nodes of the execution unit of different processors, as well as some circuits from ITC99 benchmarks. The results reveal that the precision of our proposed method is between 0.12 (ns) to 0.401 (ns). Its Area and power overhead are negligible and are about 2.13 and 0.69 percent respectively.
Keywords: Age advancement; age monitoring clock; aging rate; self-adjusting monitors

Universal mitigation of NBTI-induced aging by design randomization - Jenihhin, Maksim; Kamkin, Alexander; Navabi, Zainalabedin; Sadeghi-Kohan, Somayeh (2016 IEEE East-West Design & Test Symposium (EWDTS))
In this paper we propose to think out of the box and discuss an approach for universal mitigation of Negative Bias Temperature Instability (NBTI) induced aging untied from the limitations of its modelling. The cost-effective approach exploits a simple property of a randomized design, i.e., the equalized signal probability and switching activity at gate inputs. The techniques considered for structural design randomization involve both the hardware architecture and embedded software layers. Ultimately, the proposed approach aims at extending the reliable lifetime of nanoelectronic systems.

X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test - Kampmann, Matthias; Hellebrand, Sybille (25th IEEE Asian Test Symposium (ATS'16))

Optimized Selection of Frequencies for Faster-Than-at-Speed Test - Kampmann, Matthias; A. Kochte, Michael; Schneider, Eric; Indlekofer, Thomas; Hellebrand, Sybille; Wunderlich, Hans-Joachim (24th IEEE Asian Test Symposium (ATS'15))

A High Performance SEU Tolerant Latch - Huang, Zhengfeng; Liang, Huaguo; Hellebrand, Sybille (Journal of Electronic Testing - Theory and Applications (JETTA))

Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler - Hellebrand, Sybille; Indlekofer, Thomas; Kampmann, Matthias; Kochte, Michael; Liu, Chang; Wunderlich, Hans-Joachim
Keywords: Workshop

Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation - Sadeghi-Kohan, Somayeh; Kamran, Arezoo; Forooghifar, Farnaz; Navabi, Zainalabedin (2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS))
Transistor and interconnect wearout is accelerated with transistor scaling resulting in timing variations and consequently reliability challenges in digital circuits. Age monitoring methods can be used to predict and deal with the aging problem. Selecting appropriate locations for placement of hardware aging monitors is an important issue. In this work we propose a procedure for selection of appropriate internal nodes in combinational clouds between pipeline stages or combinational parts of a sequential circuit to place hardware monitors that can effectively provide aging information of various components of a modern digital system. In order to implement the node selection procedure, we propose an object-oriented model. Object-oriented model of a circuit along with a probabilistic and logical simulation engine that we have developed can effectively be used for implementation and also fast evaluation of the proposed node selection mechanism. The proposed object-oriented C+ + models can be integrated into a SystemC RTL model making it possible to perform mixed-level simulation, and integrated evaluation of a complete system. We have applied our proposed scheme to several processors including MIPS, ARM, ALPHA and MiniRISC and have looked at its effectiveness for these processors.

Online self adjusting progressive age monitoring of timing variations - Sadeghi-Kohan, Somayeh; Kamal, Mehdi; McNeil, John; Prinetto, Paolo; Navabi, Zain (2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS))
Transistor and interconnect wearout is accelerated with transistor scaling that results in timing variations. Progressive age measurement of a circuit can help a better prevention mechanism for reducing more aging. This requires age monitors that collect progressive age information of the circuit. This paper focuses on monitor structures for implementation of progressive age detection. The monitors are self-adjusting that they adjust themselves to detect progressive changes in the timing of a circuit. Furthermore, the monitors are designed for low hardware overhead, and certainty in reported timing changes.

FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects - Hellebrand, Sybille; Indlekofer, Thomas; Kampmann, Matthias; A. Kochte, Michael; Liu, Chang; Wunderlich, Hans-Joachim (IEEE International Test Conference (ITC'14))

SAT-Based ATPG beyond Stuck-at Fault Testing - Hellebrand, Sybille; Wunderlich, Hans-Joachim (DeGruyter Journal on Information Technology (it))

Adaptive Bayesian Diagnosis of Intermittent Faults - Rodriguez Gomez, Laura; Cook, Alejandro; Indlekofer, Thomas; Hellebrand, Sybille; Wunderlich, Hans-Joachim (Journal of Electronic Testing - Theory and Applications (JETTA))

A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs - Alizadeh, Bijan; Behnam, Payman; Sadeghi-Kohan, Somayeh (IEEE Transactions on Computers)
Keywords: Computational Theory and Mathematics; Hardware and Architecture; Theoretical Computer Science; Software

An off-line MDSI interconnect BIST incorporated in BS 1149.1 - Mohammadi, Marzieh; Sadeghi-Kohan, Somayeh; Masoumi, Nasser; Navabi, Zainalabedin (2014 19th IEEE European Test Symposium (ETS))

Improving polynomial datapath debugging with HEDs - Sadeghi-Kohan, Somayeh; Behnam, Payman; Alizadeh, Bijan; Fujita, Masahiro; Navabi, Zainalabedin (2014 19th IEEE European Test Symposium (ETS))

Analyzing and Quantifying Fault Tolerance Properties - Hellebrand, Sybille (14th IEEE Latin American Test Workshop - (LATW'13))

Adaptive Test and Diagnosis of Intermittent Faults - Cook, Alejandro; Rodriguez Gomez, Laura; Hellebrand, Sybille; Indlekofer, Thomas; Wunderlich, Hans-Joachim
Keywords: WORKSHOP

BS 1149.1 extensions for an online interconnect fault detection and recovery - Sadeghi-Kohan, Somayeh; Namaki-Shoushtari, Majid; Javaheri, Fatemeh; Navabi, Zainalabedin (2012 IEEE International Test Conference)

A new structure for interconnect offline testing - Sadeghi-Kohan, Somayeh; Keshavarz, Shahrzad; Zokaee, Farzaneh; Farahmandi, Farimah; Navabi, Zainalabedin (East-West Design & Test Symposium (EWDTS 2013))

Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test - Cook, Alejandro; Hellebrand, Sybille; E. Imhof, Michael; Mumtaz, Abdullah; Wunderlich, Hans-Joachim (13th IEEE Latin American Test Workshop (LATW'12))

Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test - Cook, Alejandro; Hellebrand, Sybille; Wunderlich, Hans-Joachim (17th IEEE European Test Symposium (ETS'12))

Eingebaute Selbstdiagnose mit zufälligen und deterministischen Mustern - Cook, Alejandro; Hellebrand, Sybille; Wunderlich, Hans-Joachim
Keywords: WORKSHOP

Diagnostic Test of Robust Circuits - Cook, Alejandro; Hellebrand, Sybille; Indlekofer, Thomas; Wunderlich, Hans-Joachim (20th IEEE Asian Test Symposium (ATS'11))

Towards Variation-Aware Test Methods - Polian, Ilia; Becker, Bernd; Hellebrand, Sybille; Wunderlich, Hans-Joachim; Maxwell, Peter (16th IEEE European Test Symposium Trondheim (ETS'11))

Robuster Selbsttest mit Diagnose - Cook, Alejandro; Hellebrand, Sybille; Indlekofer, Thomas; Wunderlich, Hans-Joachim (5. GMM/GI/ITG Fachtagung "Zuverlässigkeit und Entwurf")

Variation-Aware Fault Modeling - Hopsch, Fabian; Becker, Bernd; Hellebrand, Sybille; Polian, Ilia; Straube, Bernd; Vermeiren, Wolfgang; Wunderlich, Hans-Joachim (SCIENCE CHINA Information Sciences, Science China Press, co-published with Springer)

Virtual tester development using HDL/PLI - Kamran, Arezoo; Nemati, Nastaran; Sadeghi-Kohan, Somayeh; Navabi, Zainalabedin (2010 East-West Design & Test Symposium (EWDTS))

Testdatenkompression mit Hilfe der Netzwerkinfrastruktur - Fröse, Viktor; Ibers, Rüdiger; Hellebrand, Sybille
Keywords: WORKSHOP

Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits - Becker, Bernd; Hellebrand, Sybille; Polian, Ilia; Straube, Bernd; Vermeiren, Wolfgang; Wunderlich, Hans-Joachim (40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W'10))

Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz - Hunger, Marc; Hellebrand, Sybille (4. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf")

Nano-Electronic Systems - Hellebrand, Sybille

Variation-Aware Fault Modeling - Hopsch, Fabian; Becker, Bernd; Hellebrand, Sybille; Polian, Ilia; Straube, Bernd; Vermeiren, Wolfgang; Wunderlich, Hans-Joachim (19th IEEE Asian Test Symposium (ATS'10))

Efficient Test Response Compaction for Robust BIST Using Parity Sequences - Indlekofer, Thomas; Schnittger, Michael; Hellebrand, Sybille (28th IEEE International Conference on Computer Design (ICCD'10))

The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems - Hunger, Marc; Hellebrand, Sybille (25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'10))

Reusing NoC-Infrastructure for Test Data Compression - Froese, Viktor; Ibers, Rüdiger; Hellebrand, Sybille (28th IEEE VLSI Test Symposium (VTS'10))

Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits - Becker, Bernd; Hellebrand, Sybille; Polian, Ilia; Straube, Bernd; Vermeiren, Wolfgang; Wunderlich, Hans-Joachim (4th Workshop on Dependable and Secure Nanocomputing (WDSN'10), (Invited Paper))

Robuster Selbsttest mit extremer Kompaktierung - Indlekofer, Thomas; Schnittger, Michael; Hellebrand, Sybille (4. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf")

ATPG-Based Grading of Strong Fault-Secureness - Hunger, Marc; Hellebrand, Sybille; Czutro, Alejandro; Polian, Ilia; Becker, Bernd (15th IEEE International On-Line Testing Symposium (IOLTS'09)

Are Robust Circuits Really Robust? - Hellebrand, Sybille; Hunger, Marc (24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'09), (Invited Talk))

Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung - Hunger, Marc; Hellebrand, Sybille; Czutro, Alexander; Polian, Ilia; Becker, Bernd (3. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf")

Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit - Coym, Torsten; Hellebrand, Sybille; Ludwig, Stefan; Straube, Bernd; Wunderlich, Hans-Joachim; G. Zoellin, Christian
Keywords: WORKSHOP

Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen - Amgalan, Uranmandakh; Hachmann, Christian; Hellebrand, Sybille; Wunderlich, Hans-Joachim
Keywords: WORKSHOP

A Modular Memory BIST for Optimized Memory Repair - Oehler, Philipp; Bosio, Alberto; di Natale, Giorgio; Hellebrand, Sybille (14th IEEE International On-Line Testing Symposium (IOLTS'08), (Poster))

Signature Rollback - A Technique for Testing Robust Circuits - Amgalan, Uranmandakh; Hachmann, Christian; Hellebrand, Sybille; Wunderlich, Hans-Joachim (26th IEEE VLSI Test Symposium (VTS'08))

Verification and Analysis of Self-Checking Properties through ATPG - Hunger, Marc; Hellebrand, Sybille (14th IEEE International On-Line Testing Symposium (IOLTS'08))

Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG - Hunger, Marc; Hellebrand, Sybille (2. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf")

Modularer Selbsttest und optimierte Reparaturanalyse - Oehler, Philipp; Bosio, Alberto; Di Natale, Giorgio; Hellebrand, Sybille (2. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf")

Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing - Hellebrand, Sybille
Keywords: WORKSHOP

An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips - Ali, Muhammad; Welzl, Michael; Hessler, Sven; Hellebrand, Sybille
Keywords: WORKSHOP