TY - CONF AU - Jafarzadeh, Hanieh AU - Klemme, Florian AU - Amrouch, Hussam AU - Hellebrand, Sybille AU - Wunderlich, Hans-Joachim ID - 52744 T2 - European Test Symposium, The Hague, Netherlands, May 20-24, 2024 TI - Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations ER - TY - CONF AU - Jafarzadeh, Hanieh AU - Klemme, Florian AU - Amrouch, Hussam AU - Hellebrand, Sybille AU - Wunderlich, Hans-Joachim ID - 52742 T2 - IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024 TI - Vmin Testing under Variations: Defect vs. Fault Coverage ER - TY - CONF AU - Hellebrand, Sybille AU - Sadeghi-Kohan, Somayeh AU - Wunderlich, Hans-Joachim ID - 52743 T2 - International Symposium of EDA (ISEDA), Xi'an, China, May 10-13, 2024 TI - Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle ER - TY - CONF AU - Wunderlich, Hans-Joachim AU - Jafarzadeh, Hanieh AU - Hellebrand, Sybille ID - 52745 T2 - International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024 TI - Robust Test of Small Delay Faults under PVT-Variations ER - TY - GEN AU - Stiballe, Alisa AU - Reimer, Jan Dennis AU - Sadeghi-Kohan, Somayeh AU - Hellebrand, Sybille ID - 50284 TI - Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression ER - TY - GEN AU - Ghazal, Abdulkarim AU - Sadeghi-Kohan, Somayeh AU - Reimer, Jan Dennis AU - Hellebrand, Sybille ID - 35204 KW - WORKSHOP TI - On Cryptography Effects on Interconnect Reliability ER - TY - THES AB - Ever increasing demands on the performance of microchips are leading to ever more complex semiconductor technologies with ever shrinking feature sizes. Complex applications with high demands on safety and reliability, such as autonomous driving, are simultaneously driving the requirements for test and diagnosis of VLSI circuits. Throughout the life cycle of a microchip, uncertainties occur that affect its timing behavior. For example, weak circuit structures, aging effects, or process variations can lead to a change in the timing behavior of the circuit. While these uncertainties do not necessarily lead to a change of the functional behavior, they can lead to a reliability problem. With modular and hybrid compaction two test instruments are presented in this work that can be used for X-tolerant test response compaction in the built-in Faster-than-At-Speed Test (FAST) which is used to detect uncertainties in VLSI circuits. One challenge for test response compaction during FAST is the high and varying X-rate at the outputs of the circuit under test. By dividing the circuit outputs into test groups and separately compacting these test groups using stochastic compactors, the modular compaction is able to handle these high and varying X-rates. To deal with uncertainties on logic interconnects, a method for distinguishing crosstalk and process variation is presented. In current semiconductor technologies, the number of parasitic coupling capacitances between logic interconnects is growing. These coupling capacitances can lead to crosstalk, which causes increased current flow in the logic interconnects, which in turn can lead to increased electromigration. In the presented method, delay maps describing the timing behavior of the circuit outputs at different operating points are used to train artificial neural networks which classify the tested circuits into fault-free and faulty. AU - Sprenger, Alexander ID - 46482 KW - Testantwortkompaktierung KW - Prozessvariation KW - Silicon Lifecycle Management TI - Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen ER - TY - CONF AU - Sadeghi-Kohan, Somayeh AU - Hellebrand, Sybille AU - Wunderlich, Hans-Joachim ID - 46739 T2 - 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W) TI - Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication ER - TY - CONF AU - Sadeghi-Kohan, Somayeh AU - Reimer, Jan Dennis AU - Hellebrand, Sybille AU - Wunderlich, Hans-Joachim ID - 46738 T2 - IEEE Asian Test Symposium (ATS'23), October 2023 TI - Optimizing the Streaming of Sensor Data with Approximate Communication ER - TY - JOUR AB - System-level interconnects provide the backbone for increasingly complex systems on a chip. Their vulnerability to electromigration and crosstalk can lead to serious reliability and safety issues during the system lifetime. This article presents an approach for periodic in-system testing which maintains a reliability profile to detect potential problems before they actually cause a failure. Relying on a common infrastructure for EM-aware system workload management and test, it minimizes the stress induced by the test itself and contributes to the self-healing of system-induced electromigration degradations. AU - Sadeghi-Kohan, Somayeh AU - Hellebrand, Sybille AU - Wunderlich, Hans-Joachim ID - 46264 JF - IEEE Design &Test KW - Electrical and Electronic Engineering KW - Hardware and Architecture KW - Software SN - 2168-2356 TI - Workload-Aware Periodic Interconnect BIST ER - TY - CONF AU - Jafarzadeh, Hanieh AU - Klemme, Florian AU - Reimer, Jan Dennis AU - Najafi Haghi, Zahra Paria AU - Amrouch, Hussam AU - Hellebrand, Sybille AU - Wunderlich, Hans-Joachim ID - 45830 T2 - IEEE International Test Conference (ITC'23), Anaheim, USA, October 2023 TI - Robust Pattern Generation for Small Delay Faults under Process Variations ER - TY - JOUR AB - Safety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. The required high fault coverage at runtime is usually obtained by a combination of concurrent error detection or correction and periodic tests within rather short time intervals. The concurrent scheme ensures the integrity of computed results while the periodic test has to identify potential aging problems and to prevent any fault accumulation which may invalidate the concurrent error detection mechanism. Such periodic built-in self-test (BIST) schemes are already commercialized for memories and for random logic. The paper at hand extends this approach to interconnect structures. A BIST scheme is presented which targets interconnect defects before they will actually affect the system functionality at nominal speed. A BIST schedule is developed which significantly reduces aging caused by electromigration during the lifetime application of the periodic test. AU - Sadeghi-Kohan, Somayeh AU - Hellebrand, Sybille AU - Wunderlich, Hans-Joachim ID - 29351 JF - Journal of Electronic Testing KW - Electrical and Electronic Engineering SN - 0923-8174 TI - Stress-Aware Periodic Test of Interconnects ER - TY - GEN AU - Sadeghi-Kohan, Somayeh AU - Hellebrand, Sybille AU - Wunderlich, Hans-Joachim ID - 29890 KW - WORKSHOP TI - EM-Aware Interconnect BIST ER - TY - CONF AU - Sprenger, Alexander AU - Sadeghi-Kohan, Somayeh AU - Reimer, Jan Dennis AU - Hellebrand, Sybille ID - 19422 T2 - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020 TI - Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study ER - TY - GEN AU - Sadeghi-Kohan, Somayeh AU - Hellebrand, Sybille ID - 15419 KW - WORKSHOP TI - Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects ER - TY - CONF AU - Sadeghi-Kohan, Somayeh AU - Hellebrand, Sybille ID - 29200 T2 - 38th IEEE VLSI Test Symposium (VTS) TI - Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects ER - TY - CONF AU - Holst, Stefan AU - Kampmann, Matthias AU - Sprenger, Alexander AU - Reimer, Jan Dennis AU - Hellebrand, Sybille AU - Wunderlich, Hans-Joachim AU - Weng, Xiaoqing ID - 19421 T2 - IEEE International Test Conference (ITC'20), November 2020 TI - Logic Fault Diagnosis of Hidden Delay Defects ER - TY - GEN AU - Maaz, Mohammad Urf AU - Sprenger, Alexander AU - Hellebrand, Sybille ID - 8112 KW - WORKSHOP TI - A Hybrid Space Compactor for Varying X-Rates ER - TY - JOUR AU - Sprenger, Alexander AU - Hellebrand, Sybille ID - 8667 IS - 1 JF - Journal of Circuits, Systems and Computers SN - 0218-1266 TI - Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test VL - 28 ER - TY - JOUR AB - Marginal hardware introduces severe reliability threats throughout the life cycle of a system. Although marginalities may not affect the functionality of a circuit immediately after manufacturing, they can degrade into hard failures and must be screened out during manufacturing test to prevent early life failures. Furthermore, their evolution in the field must be proactively monitored by periodic tests before actual failures occur. In recent years small delay faults have gained increasing attention as possible indicators of marginal hardware. However, small delay faults on short paths may be undetectable even with advanced timing aware ATPG. Faster-than-at-speed test (FAST) can detect such hidden delay faults, but so far FAST has mainly been restricted to manufacturing test. AU - Kampmann, Matthias AU - A. Kochte, Michael AU - Liu, Chang AU - Schneider, Eric AU - Hellebrand, Sybille AU - Wunderlich, Hans-Joachim ID - 13048 IS - 10 JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) TI - Built-in Test for Hidden Delay Faults VL - 38 ER -