A High Performance SEU Tolerant Latch - Huang, Zhengfeng; Liang, Huaguo; Hellebrand, Sybille (Journal of Electronic Testing - Theory and Applications (JETTA))

Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler - Hellebrand, Sybille; Indlekofer, Thomas; Kampmann, Matthias; Kochte, Michael; Liu, Chang; Wunderlich, Hans-Joachim
Keywords: Workshop

Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation - Sadeghi-Kohan, Somayeh; Kamran, Arezoo; Forooghifar, Farnaz; Navabi, Zainalabedin (2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS))
Transistor and interconnect wearout is accelerated with transistor scaling resulting in timing variations and consequently reliability challenges in digital circuits. Age monitoring methods can be used to predict and deal with the aging problem. Selecting appropriate locations for placement of hardware aging monitors is an important issue. In this work we propose a procedure for selection of appropriate internal nodes in combinational clouds between pipeline stages or combinational parts of a sequential circuit to place hardware monitors that can effectively provide aging information of various components of a modern digital system. In order to implement the node selection procedure, we propose an object-oriented model. Object-oriented model of a circuit along with a probabilistic and logical simulation engine that we have developed can effectively be used for implementation and also fast evaluation of the proposed node selection mechanism. The proposed object-oriented C+ + models can be integrated into a SystemC RTL model making it possible to perform mixed-level simulation, and integrated evaluation of a complete system. We have applied our proposed scheme to several processors including MIPS, ARM, ALPHA and MiniRISC and have looked at its effectiveness for these processors.

Online self adjusting progressive age monitoring of timing variations - Sadeghi-Kohan, Somayeh; Kamal, Mehdi; McNeil, John; Prinetto, Paolo; Navabi, Zain (2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS))
Transistor and interconnect wearout is accelerated with transistor scaling that results in timing variations. Progressive age measurement of a circuit can help a better prevention mechanism for reducing more aging. This requires age monitors that collect progressive age information of the circuit. This paper focuses on monitor structures for implementation of progressive age detection. The monitors are self-adjusting that they adjust themselves to detect progressive changes in the timing of a circuit. Furthermore, the monitors are designed for low hardware overhead, and certainty in reported timing changes.

FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects - Hellebrand, Sybille; Indlekofer, Thomas; Kampmann, Matthias; A. Kochte, Michael; Liu, Chang; Wunderlich, Hans-Joachim (IEEE International Test Conference (ITC'14))

SAT-Based ATPG beyond Stuck-at Fault Testing - Hellebrand, Sybille; Wunderlich, Hans-Joachim (DeGruyter Journal on Information Technology (it))

Adaptive Bayesian Diagnosis of Intermittent Faults - Rodriguez Gomez, Laura; Cook, Alejandro; Indlekofer, Thomas; Hellebrand, Sybille; Wunderlich, Hans-Joachim (Journal of Electronic Testing - Theory and Applications (JETTA))

A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs - Alizadeh, Bijan; Behnam, Payman; Sadeghi-Kohan, Somayeh (IEEE Transactions on Computers)
Keywords: Computational Theory and Mathematics; Hardware and Architecture; Theoretical Computer Science; Software

An off-line MDSI interconnect BIST incorporated in BS 1149.1 - Mohammadi, Marzieh; Sadeghi-Kohan, Somayeh; Masoumi, Nasser; Navabi, Zainalabedin (2014 19th IEEE European Test Symposium (ETS))

Improving polynomial datapath debugging with HEDs - Sadeghi-Kohan, Somayeh; Behnam, Payman; Alizadeh, Bijan; Fujita, Masahiro; Navabi, Zainalabedin (2014 19th IEEE European Test Symposium (ETS))

Analyzing and Quantifying Fault Tolerance Properties - Hellebrand, Sybille (14th IEEE Latin American Test Workshop - (LATW'13))

Adaptive Test and Diagnosis of Intermittent Faults - Cook, Alejandro; Rodriguez Gomez, Laura; Hellebrand, Sybille; Indlekofer, Thomas; Wunderlich, Hans-Joachim
Keywords: WORKSHOP

BS 1149.1 extensions for an online interconnect fault detection and recovery - Sadeghi-Kohan, Somayeh; Namaki-Shoushtari, Majid; Javaheri, Fatemeh; Navabi, Zainalabedin (2012 IEEE International Test Conference)

A new structure for interconnect offline testing - Sadeghi-Kohan, Somayeh; Keshavarz, Shahrzad; Zokaee, Farzaneh; Farahmandi, Farimah; Navabi, Zainalabedin (East-West Design & Test Symposium (EWDTS 2013))

Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test - Cook, Alejandro; Hellebrand, Sybille; E. Imhof, Michael; Mumtaz, Abdullah; Wunderlich, Hans-Joachim (13th IEEE Latin American Test Workshop (LATW'12))

Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test - Cook, Alejandro; Hellebrand, Sybille; Wunderlich, Hans-Joachim (17th IEEE European Test Symposium (ETS'12))

Eingebaute Selbstdiagnose mit zufälligen und deterministischen Mustern - Cook, Alejandro; Hellebrand, Sybille; Wunderlich, Hans-Joachim
Keywords: WORKSHOP

Diagnostic Test of Robust Circuits - Cook, Alejandro; Hellebrand, Sybille; Indlekofer, Thomas; Wunderlich, Hans-Joachim (20th IEEE Asian Test Symposium (ATS'11))

Towards Variation-Aware Test Methods - Polian, Ilia; Becker, Bernd; Hellebrand, Sybille; Wunderlich, Hans-Joachim; Maxwell, Peter (16th IEEE European Test Symposium Trondheim (ETS'11))

Robuster Selbsttest mit Diagnose - Cook, Alejandro; Hellebrand, Sybille; Indlekofer, Thomas; Wunderlich, Hans-Joachim (5. GMM/GI/ITG Fachtagung "Zuverlässigkeit und Entwurf")