--- _id: '13051' author: - first_name: Marc full_name: Hunger, Marc last_name: Hunger - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: 'Hunger M, Hellebrand S. Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz. In: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” Wildbad Kreuth, Germany; 2010:81-88.' apa: Hunger, M., & Hellebrand, S. (2010). Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz. In 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf” (pp. 81–88). Wildbad Kreuth, Germany. bibtex: '@inproceedings{Hunger_Hellebrand_2010, place={Wildbad Kreuth, Germany}, title={Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz}, booktitle={4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf”}, author={Hunger, Marc and Hellebrand, Sybille}, year={2010}, pages={81–88} }' chicago: Hunger, Marc, and Sybille Hellebrand. “Ausbeute Und Fehlertoleranz Bei Dreifach Modularer Redundanz.” In 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 81–88. Wildbad Kreuth, Germany, 2010. ieee: M. Hunger and S. Hellebrand, “Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz,” in 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf,” 2010, pp. 81–88. mla: Hunger, Marc, and Sybille Hellebrand. “Ausbeute Und Fehlertoleranz Bei Dreifach Modularer Redundanz.” 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2010, pp. 81–88. short: 'M. Hunger, S. Hellebrand, in: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Wildbad Kreuth, Germany, 2010, pp. 81–88.' date_created: 2019-08-28T11:46:41Z date_updated: 2022-01-06T06:51:27Z department: - _id: '48' language: - iso: eng page: 81-88 place: Wildbad Kreuth, Germany publication: 4. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf" status: public title: Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz type: conference user_id: '659' year: '2010' ... --- _id: '13073' author: - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: Hellebrand S. Nano-Electronic Systems. Editorial, it 4/2010, pp. 179-180; 2010. apa: Hellebrand, S. (2010). Nano-Electronic Systems. Editorial, it 4/2010, pp. 179-180. bibtex: '@book{Hellebrand_2010, place={Editorial, it 4/2010, pp. 179-180}, title={Nano-Electronic Systems}, author={Hellebrand, Sybille}, year={2010} }' chicago: Hellebrand, Sybille. Nano-Electronic Systems. Editorial, it 4/2010, pp. 179-180, 2010. ieee: S. Hellebrand, Nano-Electronic Systems. Editorial, it 4/2010, pp. 179-180, 2010. mla: Hellebrand, Sybille. Nano-Electronic Systems. 2010. short: S. Hellebrand, Nano-Electronic Systems, Editorial, it 4/2010, pp. 179-180, 2010. date_created: 2019-08-28T12:01:06Z date_updated: 2022-01-06T06:51:28Z department: - _id: '48' language: - iso: eng place: Editorial, it 4/2010, pp. 179-180 status: public title: Nano-Electronic Systems type: misc user_id: '659' year: '2010' ... --- _id: '12983' author: - first_name: Fabian full_name: Hopsch, Fabian last_name: Hopsch - first_name: Bernd full_name: Becker, Bernd last_name: Becker - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Ilia full_name: Polian, Ilia last_name: Polian - first_name: Bernd full_name: Straube, Bernd last_name: Straube - first_name: Wolfgang full_name: Vermeiren, Wolfgang last_name: Vermeiren - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich citation: ama: 'Hopsch F, Becker B, Hellebrand S, et al. Variation-Aware Fault Modeling. In: 19th IEEE Asian Test Symposium (ATS’10). IEEE; 2010:87-93. doi:10.1109/ats.2010.24' apa: Hopsch, F., Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., & Wunderlich, H.-J. (2010). Variation-Aware Fault Modeling. 19th IEEE Asian Test Symposium (ATS’10), 87–93. https://doi.org/10.1109/ats.2010.24 bibtex: '@inproceedings{Hopsch_Becker_Hellebrand_Polian_Straube_Vermeiren_Wunderlich_2010, place={Shanghai, China}, title={Variation-Aware Fault Modeling}, DOI={10.1109/ats.2010.24}, booktitle={19th IEEE Asian Test Symposium (ATS’10)}, publisher={IEEE}, author={Hopsch, Fabian and Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans-Joachim}, year={2010}, pages={87–93} }' chicago: 'Hopsch, Fabian, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, and Hans-Joachim Wunderlich. “Variation-Aware Fault Modeling.” In 19th IEEE Asian Test Symposium (ATS’10), 87–93. Shanghai, China: IEEE, 2010. https://doi.org/10.1109/ats.2010.24.' ieee: 'F. Hopsch et al., “Variation-Aware Fault Modeling,” in 19th IEEE Asian Test Symposium (ATS’10), 2010, pp. 87–93, doi: 10.1109/ats.2010.24.' mla: Hopsch, Fabian, et al. “Variation-Aware Fault Modeling.” 19th IEEE Asian Test Symposium (ATS’10), IEEE, 2010, pp. 87–93, doi:10.1109/ats.2010.24. short: 'F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: 19th IEEE Asian Test Symposium (ATS’10), IEEE, Shanghai, China, 2010, pp. 87–93.' date_created: 2019-08-28T09:20:51Z date_updated: 2022-05-11T16:20:07Z department: - _id: '48' doi: 10.1109/ats.2010.24 language: - iso: eng page: 87-93 place: Shanghai, China publication: 19th IEEE Asian Test Symposium (ATS'10) publisher: IEEE status: public title: Variation-Aware Fault Modeling type: conference user_id: '209' year: '2010' ... --- _id: '12985' author: - first_name: Thomas full_name: Indlekofer, Thomas last_name: Indlekofer - first_name: Michael full_name: Schnittger, Michael last_name: Schnittger - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: 'Indlekofer T, Schnittger M, Hellebrand S. Efficient Test Response Compaction for Robust BIST Using Parity Sequences. In: 28th IEEE International Conference on Computer Design (ICCD’10). IEEE; 2010:480-485. doi:10.1109/iccd.2010.5647648' apa: Indlekofer, T., Schnittger, M., & Hellebrand, S. (2010). Efficient Test Response Compaction for Robust BIST Using Parity Sequences. 28th IEEE International Conference on Computer Design (ICCD’10), 480–485. https://doi.org/10.1109/iccd.2010.5647648 bibtex: '@inproceedings{Indlekofer_Schnittger_Hellebrand_2010, place={Amsterdam, The Netherlands}, title={Efficient Test Response Compaction for Robust BIST Using Parity Sequences}, DOI={10.1109/iccd.2010.5647648}, booktitle={28th IEEE International Conference on Computer Design (ICCD’10)}, publisher={IEEE}, author={Indlekofer, Thomas and Schnittger, Michael and Hellebrand, Sybille}, year={2010}, pages={480–485} }' chicago: 'Indlekofer, Thomas, Michael Schnittger, and Sybille Hellebrand. “Efficient Test Response Compaction for Robust BIST Using Parity Sequences.” In 28th IEEE International Conference on Computer Design (ICCD’10), 480–85. Amsterdam, The Netherlands: IEEE, 2010. https://doi.org/10.1109/iccd.2010.5647648.' ieee: 'T. Indlekofer, M. Schnittger, and S. Hellebrand, “Efficient Test Response Compaction for Robust BIST Using Parity Sequences,” in 28th IEEE International Conference on Computer Design (ICCD’10), 2010, pp. 480–485, doi: 10.1109/iccd.2010.5647648.' mla: Indlekofer, Thomas, et al. “Efficient Test Response Compaction for Robust BIST Using Parity Sequences.” 28th IEEE International Conference on Computer Design (ICCD’10), IEEE, 2010, pp. 480–85, doi:10.1109/iccd.2010.5647648. short: 'T. Indlekofer, M. Schnittger, S. Hellebrand, in: 28th IEEE International Conference on Computer Design (ICCD’10), IEEE, Amsterdam, The Netherlands, 2010, pp. 480–485.' date_created: 2019-08-28T09:21:55Z date_updated: 2022-05-11T16:21:12Z department: - _id: '48' doi: 10.1109/iccd.2010.5647648 language: - iso: eng page: 480-485 place: Amsterdam, The Netherlands publication: 28th IEEE International Conference on Computer Design (ICCD'10) publisher: IEEE status: public title: Efficient Test Response Compaction for Robust BIST Using Parity Sequences type: conference user_id: '209' year: '2010' ... --- _id: '12986' author: - first_name: Marc full_name: Hunger, Marc last_name: Hunger - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: 'Hunger M, Hellebrand S. The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems. In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10). IEEE; 2010:101-108. doi:10.1109/dft.2010.19' apa: Hunger, M., & Hellebrand, S. (2010). The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems. 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), 101–108. https://doi.org/10.1109/dft.2010.19 bibtex: '@inproceedings{Hunger_Hellebrand_2010, place={Kyoto, Japan}, title={The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems}, DOI={10.1109/dft.2010.19}, booktitle={25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10)}, publisher={IEEE}, author={Hunger, Marc and Hellebrand, Sybille}, year={2010}, pages={101–108} }' chicago: 'Hunger, Marc, and Sybille Hellebrand. “The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems.” In 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), 101–8. Kyoto, Japan: IEEE, 2010. https://doi.org/10.1109/dft.2010.19.' ieee: 'M. Hunger and S. Hellebrand, “The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems,” in 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), 2010, pp. 101–108, doi: 10.1109/dft.2010.19.' mla: Hunger, Marc, and Sybille Hellebrand. “The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems.” 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), IEEE, 2010, pp. 101–08, doi:10.1109/dft.2010.19. short: 'M. Hunger, S. Hellebrand, in: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), IEEE, Kyoto, Japan, 2010, pp. 101–108.' date_created: 2019-08-28T09:21:57Z date_updated: 2022-05-11T16:21:52Z department: - _id: '48' doi: 10.1109/dft.2010.19 language: - iso: eng page: 101-108 place: Kyoto, Japan publication: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'10) publisher: IEEE status: public title: The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems type: conference user_id: '209' year: '2010' ... --- _id: '12988' author: - first_name: Viktor full_name: Froese, Viktor last_name: Froese - first_name: Rüdiger full_name: Ibers, Rüdiger id: '659' last_name: Ibers - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: 'Froese V, Ibers R, Hellebrand S. Reusing NoC-Infrastructure for Test Data Compression. In: 28th IEEE VLSI Test Symposium (VTS’10). IEEE; 2010:227-231. doi:10.1109/vts.2010.5469570' apa: Froese, V., Ibers, R., & Hellebrand, S. (2010). Reusing NoC-Infrastructure for Test Data Compression. 28th IEEE VLSI Test Symposium (VTS’10), 227–231. https://doi.org/10.1109/vts.2010.5469570 bibtex: '@inproceedings{Froese_Ibers_Hellebrand_2010, place={Santa Cruz, CA, USA}, title={Reusing NoC-Infrastructure for Test Data Compression}, DOI={10.1109/vts.2010.5469570}, booktitle={28th IEEE VLSI Test Symposium (VTS’10)}, publisher={IEEE}, author={Froese, Viktor and Ibers, Rüdiger and Hellebrand, Sybille}, year={2010}, pages={227–231} }' chicago: 'Froese, Viktor, Rüdiger Ibers, and Sybille Hellebrand. “Reusing NoC-Infrastructure for Test Data Compression.” In 28th IEEE VLSI Test Symposium (VTS’10), 227–31. Santa Cruz, CA, USA: IEEE, 2010. https://doi.org/10.1109/vts.2010.5469570.' ieee: 'V. Froese, R. Ibers, and S. Hellebrand, “Reusing NoC-Infrastructure for Test Data Compression,” in 28th IEEE VLSI Test Symposium (VTS’10), 2010, pp. 227–231, doi: 10.1109/vts.2010.5469570.' mla: Froese, Viktor, et al. “Reusing NoC-Infrastructure for Test Data Compression.” 28th IEEE VLSI Test Symposium (VTS’10), IEEE, 2010, pp. 227–31, doi:10.1109/vts.2010.5469570. short: 'V. Froese, R. Ibers, S. Hellebrand, in: 28th IEEE VLSI Test Symposium (VTS’10), IEEE, Santa Cruz, CA, USA, 2010, pp. 227–231.' date_created: 2019-08-28T09:22:54Z date_updated: 2022-05-11T16:22:36Z department: - _id: '48' doi: 10.1109/vts.2010.5469570 language: - iso: eng page: 227-231 place: Santa Cruz, CA, USA publication: 28th IEEE VLSI Test Symposium (VTS'10) publisher: IEEE status: public title: Reusing NoC-Infrastructure for Test Data Compression type: conference user_id: '209' year: '2010' ... --- _id: '13049' author: - first_name: Bernd full_name: Becker, Bernd last_name: Becker - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Ilia full_name: Polian, Ilia last_name: Polian - first_name: Bernd full_name: Straube, Bernd last_name: Straube - first_name: Wolfgang full_name: Vermeiren, Wolfgang last_name: Vermeiren - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich citation: ama: 'Becker B, Hellebrand S, Polian I, Straube B, Vermeiren W, Wunderlich H-J. Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. In: 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper). ; 2010.' apa: Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., & Wunderlich, H.-J. (2010). Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper). bibtex: '@inproceedings{Becker_Hellebrand_Polian_Straube_Vermeiren_Wunderlich_2010, place={Chicago, IL, USA}, title={Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits}, booktitle={4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper)}, author={Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans-Joachim}, year={2010} }' chicago: Becker, Bernd, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, and Hans-Joachim Wunderlich. “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits.” In 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper). Chicago, IL, USA, 2010. ieee: B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, and H.-J. Wunderlich, “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits,” 2010. mla: Becker, Bernd, et al. “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits.” 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper), 2010. short: 'B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper), Chicago, IL, USA, 2010.' date_created: 2019-08-28T11:45:36Z date_updated: 2022-05-11T16:26:18Z department: - _id: '48' language: - iso: eng place: Chicago, IL, USA publication: 4th Workshop on Dependable and Secure Nanocomputing (WDSN'10), (Invited Paper) status: public title: Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits type: conference user_id: '209' year: '2010' ... --- _id: '13050' author: - first_name: Thomas full_name: Indlekofer, Thomas last_name: Indlekofer - first_name: Michael full_name: Schnittger, Michael last_name: Schnittger - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: 'Indlekofer T, Schnittger M, Hellebrand S. Robuster Selbsttest mit extremer Kompaktierung. In: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2010:17-24.' apa: Indlekofer, T., Schnittger, M., & Hellebrand, S. (2010). Robuster Selbsttest mit extremer Kompaktierung. 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 17–24. bibtex: '@inproceedings{Indlekofer_Schnittger_Hellebrand_2010, place={Wildbad Kreuth, Germany}, title={Robuster Selbsttest mit extremer Kompaktierung}, booktitle={4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf”}, author={Indlekofer, Thomas and Schnittger, Michael and Hellebrand, Sybille}, year={2010}, pages={17–24} }' chicago: Indlekofer, Thomas, Michael Schnittger, and Sybille Hellebrand. “Robuster Selbsttest Mit Extremer Kompaktierung.” In 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 17–24. Wildbad Kreuth, Germany, 2010. ieee: T. Indlekofer, M. Schnittger, and S. Hellebrand, “Robuster Selbsttest mit extremer Kompaktierung,” in 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf,” 2010, pp. 17–24. mla: Indlekofer, Thomas, et al. “Robuster Selbsttest Mit Extremer Kompaktierung.” 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2010, pp. 17–24. short: 'T. Indlekofer, M. Schnittger, S. Hellebrand, in: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Wildbad Kreuth, Germany, 2010, pp. 17–24.' date_created: 2019-08-28T11:46:13Z date_updated: 2022-05-11T16:25:34Z department: - _id: '48' language: - iso: eng page: 17-24 place: Wildbad Kreuth, Germany publication: 4. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf" status: public title: Robuster Selbsttest mit extremer Kompaktierung type: conference user_id: '209' year: '2010' ... --- _id: '12991' author: - first_name: Marc full_name: Hunger, Marc last_name: Hunger - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Alejandro full_name: Czutro, Alejandro last_name: Czutro - first_name: Ilia full_name: Polian, Ilia last_name: Polian - first_name: Bernd full_name: Becker, Bernd last_name: Becker citation: ama: 'Hunger M, Hellebrand S, Czutro A, Polian I, Becker B. ATPG-Based Grading of Strong Fault-Secureness. In: 15th IEEE International On-Line Testing Symposium (IOLTS’09. IEEE; 2009. doi:10.1109/iolts.2009.5196027' apa: Hunger, M., Hellebrand, S., Czutro, A., Polian, I., & Becker, B. (2009). ATPG-Based Grading of Strong Fault-Secureness. 15th IEEE International On-Line Testing Symposium (IOLTS’09. https://doi.org/10.1109/iolts.2009.5196027 bibtex: '@inproceedings{Hunger_Hellebrand_Czutro_Polian_Becker_2009, place={Sesimbra-Lisbon, Portugal}, title={ATPG-Based Grading of Strong Fault-Secureness}, DOI={10.1109/iolts.2009.5196027}, booktitle={15th IEEE International On-Line Testing Symposium (IOLTS’09}, publisher={IEEE}, author={Hunger, Marc and Hellebrand, Sybille and Czutro, Alejandro and Polian, Ilia and Becker, Bernd}, year={2009} }' chicago: 'Hunger, Marc, Sybille Hellebrand, Alejandro Czutro, Ilia Polian, and Bernd Becker. “ATPG-Based Grading of Strong Fault-Secureness.” In 15th IEEE International On-Line Testing Symposium (IOLTS’09. Sesimbra-Lisbon, Portugal: IEEE, 2009. https://doi.org/10.1109/iolts.2009.5196027.' ieee: 'M. Hunger, S. Hellebrand, A. Czutro, I. Polian, and B. Becker, “ATPG-Based Grading of Strong Fault-Secureness,” 2009, doi: 10.1109/iolts.2009.5196027.' mla: Hunger, Marc, et al. “ATPG-Based Grading of Strong Fault-Secureness.” 15th IEEE International On-Line Testing Symposium (IOLTS’09, IEEE, 2009, doi:10.1109/iolts.2009.5196027. short: 'M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, in: 15th IEEE International On-Line Testing Symposium (IOLTS’09, IEEE, Sesimbra-Lisbon, Portugal, 2009.' date_created: 2019-08-28T10:17:16Z date_updated: 2022-05-11T16:27:48Z department: - _id: '48' doi: 10.1109/iolts.2009.5196027 language: - iso: eng place: Sesimbra-Lisbon, Portugal publication: 15th IEEE International On-Line Testing Symposium (IOLTS'09 publisher: IEEE status: public title: ATPG-Based Grading of Strong Fault-Secureness type: conference user_id: '209' year: '2009' ... --- _id: '12990' author: - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Marc full_name: Hunger, Marc last_name: Hunger citation: ama: 'Hellebrand S, Hunger M. Are Robust Circuits Really Robust? In: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk). IEEE; 2009:77. doi:10.1109/dft.2009.28' apa: Hellebrand, S., & Hunger, M. (2009). Are Robust Circuits Really Robust? 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), 77. https://doi.org/10.1109/dft.2009.28 bibtex: '@inproceedings{Hellebrand_Hunger_2009, place={Chicago, IL, USA}, title={Are Robust Circuits Really Robust?}, DOI={10.1109/dft.2009.28}, booktitle={24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk)}, publisher={IEEE}, author={Hellebrand, Sybille and Hunger, Marc}, year={2009}, pages={77} }' chicago: 'Hellebrand, Sybille, and Marc Hunger. “Are Robust Circuits Really Robust?” In 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), 77. Chicago, IL, USA: IEEE, 2009. https://doi.org/10.1109/dft.2009.28.' ieee: 'S. Hellebrand and M. Hunger, “Are Robust Circuits Really Robust?,” in 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), 2009, p. 77, doi: 10.1109/dft.2009.28.' mla: Hellebrand, Sybille, and Marc Hunger. “Are Robust Circuits Really Robust?” 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), IEEE, 2009, p. 77, doi:10.1109/dft.2009.28. short: 'S. Hellebrand, M. Hunger, in: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), IEEE, Chicago, IL, USA, 2009, p. 77.' date_created: 2019-08-28T10:17:14Z date_updated: 2022-05-11T16:27:03Z department: - _id: '48' doi: 10.1109/dft.2009.28 language: - iso: eng page: '77' place: Chicago, IL, USA publication: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'09), (Invited Talk) publisher: IEEE status: public title: Are Robust Circuits Really Robust? type: conference user_id: '209' year: '2009' ...