--- _id: '52744' author: - first_name: Hanieh full_name: Jafarzadeh, Hanieh last_name: Jafarzadeh - first_name: Florian full_name: Klemme, Florian last_name: Klemme - first_name: Hussam full_name: Amrouch, Hussam last_name: Amrouch - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich citation: ama: 'Jafarzadeh H, Klemme F, Amrouch H, Hellebrand S, Wunderlich H-J. Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations. In: European Test Symposium, The Hague, Netherlands, May 20-24, 2024. IEEE; :6.' apa: Jafarzadeh, H., Klemme, F., Amrouch, H., Hellebrand, S., & Wunderlich, H.-J. (n.d.). Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations. European Test Symposium, The Hague, Netherlands, May 20-24, 2024, 6. bibtex: '@inproceedings{Jafarzadeh_Klemme_Amrouch_Hellebrand_Wunderlich, title={Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations}, booktitle={European Test Symposium, The Hague, Netherlands, May 20-24, 2024}, publisher={IEEE}, author={Jafarzadeh, Hanieh and Klemme, Florian and Amrouch, Hussam and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, pages={6} }' chicago: Jafarzadeh, Hanieh, Florian Klemme, Hussam Amrouch, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Time and Space Optimized Storage-Based BIST under Multiple Voltages and Variations.” In European Test Symposium, The Hague, Netherlands, May 20-24, 2024, 6. IEEE, n.d. ieee: H. Jafarzadeh, F. Klemme, H. Amrouch, S. Hellebrand, and H.-J. Wunderlich, “Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations,” in European Test Symposium, The Hague, Netherlands, May 20-24, 2024, The Hague, NL, p. 6. mla: Jafarzadeh, Hanieh, et al. “Time and Space Optimized Storage-Based BIST under Multiple Voltages and Variations.” European Test Symposium, The Hague, Netherlands, May 20-24, 2024, IEEE, p. 6. short: 'H. Jafarzadeh, F. Klemme, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, in: European Test Symposium, The Hague, Netherlands, May 20-24, 2024, IEEE, n.d., p. 6.' conference: end_date: 2024-05-24 location: The Hague, NL name: IEEE European Test Symposium start_date: 2024-05-20 date_created: 2024-03-22T17:04:25Z date_updated: 2024-03-22T17:05:29Z department: - _id: '48' language: - iso: eng page: '6' publication: European Test Symposium, The Hague, Netherlands, May 20-24, 2024 publication_status: accepted publisher: IEEE quality_controlled: '1' status: public title: Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations type: conference user_id: '209' year: '2024' ... --- _id: '52742' author: - first_name: Hanieh full_name: Jafarzadeh, Hanieh last_name: Jafarzadeh - first_name: Florian full_name: Klemme, Florian last_name: Klemme - first_name: Hussam full_name: Amrouch, Hussam last_name: Amrouch - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich citation: ama: 'Jafarzadeh H, Klemme F, Amrouch H, Hellebrand S, Wunderlich H-J. Vmin Testing under Variations: Defect vs. Fault Coverage. In: IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024. IEEE; :6.' apa: 'Jafarzadeh, H., Klemme, F., Amrouch, H., Hellebrand, S., & Wunderlich, H.-J. (n.d.). Vmin Testing under Variations: Defect vs. Fault Coverage. IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, 6.' bibtex: '@inproceedings{Jafarzadeh_Klemme_Amrouch_Hellebrand_Wunderlich, title={Vmin Testing under Variations: Defect vs. Fault Coverage}, booktitle={IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024}, publisher={IEEE}, author={Jafarzadeh, Hanieh and Klemme, Florian and Amrouch, Hussam and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, pages={6} }' chicago: 'Jafarzadeh, Hanieh, Florian Klemme, Hussam Amrouch, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Vmin Testing under Variations: Defect vs. Fault Coverage.” In IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, 6. IEEE, n.d.' ieee: 'H. Jafarzadeh, F. Klemme, H. Amrouch, S. Hellebrand, and H.-J. Wunderlich, “Vmin Testing under Variations: Defect vs. Fault Coverage,” in IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, Maceió, p. 6.' mla: 'Jafarzadeh, Hanieh, et al. “Vmin Testing under Variations: Defect vs. Fault Coverage.” IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, IEEE, p. 6.' short: 'H. Jafarzadeh, F. Klemme, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, in: IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, IEEE, n.d., p. 6.' conference: end_date: 2024-04-12 location: Maceió name: IEEE Latin American Test Symposium (LATS) start_date: 2024-04-09 date_created: 2024-03-22T16:49:22Z date_updated: 2024-03-22T17:06:40Z department: - _id: '48' language: - iso: eng page: '6' publication: IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024 publication_status: accepted publisher: IEEE quality_controlled: '1' status: public title: 'Vmin Testing under Variations: Defect vs. Fault Coverage' type: conference user_id: '209' year: '2024' ... --- _id: '52743' author: - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Somayeh full_name: Sadeghi-Kohan, Somayeh id: '78614' last_name: Sadeghi-Kohan orcid: https://orcid.org/0000-0001-7246-0610 - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich citation: ama: 'Hellebrand S, Sadeghi-Kohan S, Wunderlich H-J. Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle. In: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024. ; :1.' apa: Hellebrand, S., Sadeghi-Kohan, S., & Wunderlich, H.-J. (n.d.). Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle. International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, 1. bibtex: '@inproceedings{Hellebrand_Sadeghi-Kohan_Wunderlich, title={Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle}, booktitle={International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024}, author={Hellebrand, Sybille and Sadeghi-Kohan, Somayeh and Wunderlich, Hans-Joachim}, pages={1} }' chicago: Hellebrand, Sybille, Somayeh Sadeghi-Kohan, and Hans-Joachim Wunderlich. “Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle.” In International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, 1, n.d. ieee: S. Hellebrand, S. Sadeghi-Kohan, and H.-J. Wunderlich, “Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle,” in International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, Xi’an, China, p. 1. mla: Hellebrand, Sybille, et al. “Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle.” International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, p. 1. short: 'S. Hellebrand, S. Sadeghi-Kohan, H.-J. Wunderlich, in: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, n.d., p. 1.' conference: end_date: 2024-05-13 location: Xi'an, China name: International Symposium of EDA (ISEDA) start_date: 2024-05-10 date_created: 2024-03-22T16:57:53Z date_updated: 2024-03-22T17:06:02Z department: - _id: '48' language: - iso: eng page: '1' publication: International Symposium of EDA (ISEDA), Xi'an, China, May 10-13, 2024 publication_status: accepted status: public title: Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle type: conference user_id: '209' year: '2024' ... --- _id: '52745' author: - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich - first_name: Hanieh full_name: Jafarzadeh, Hanieh last_name: Jafarzadeh - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: 'Wunderlich H-J, Jafarzadeh H, Hellebrand S. Robust Test of Small Delay Faults under  PVT-Variations. In: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024. ; :1.' apa: Wunderlich, H.-J., Jafarzadeh, H., & Hellebrand, S. (n.d.). Robust Test of Small Delay Faults under  PVT-Variations. International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, 1. bibtex: '@inproceedings{Wunderlich_Jafarzadeh_Hellebrand, title={Robust Test of Small Delay Faults under  PVT-Variations}, booktitle={International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024}, author={Wunderlich, Hans-Joachim and Jafarzadeh, Hanieh and Hellebrand, Sybille}, pages={1} }' chicago: Wunderlich, Hans-Joachim, Hanieh Jafarzadeh, and Sybille Hellebrand. “Robust Test of Small Delay Faults under  PVT-Variations.” In International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, 1, n.d. ieee: H.-J. Wunderlich, H. Jafarzadeh, and S. Hellebrand, “Robust Test of Small Delay Faults under  PVT-Variations,” in International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, Xi’an, China, p. 1. mla: Wunderlich, Hans-Joachim, et al. “Robust Test of Small Delay Faults under  PVT-Variations.” International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, p. 1. short: 'H.-J. Wunderlich, H. Jafarzadeh, S. Hellebrand, in: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, n.d., p. 1.' conference: end_date: 2024-05-13 location: Xi’an, China name: International Symposium of EDA (ISEDA) start_date: 2024-05-10 date_created: 2024-03-22T17:11:03Z date_updated: 2024-03-22T17:11:16Z department: - _id: '48' language: - iso: eng page: '1' publication: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024 publication_status: accepted status: public title: Robust Test of Small Delay Faults under PVT-Variations type: conference user_id: '209' year: '2024' ... --- _id: '50284' author: - first_name: Alisa full_name: Stiballe, Alisa last_name: Stiballe - first_name: Jan Dennis full_name: Reimer, Jan Dennis id: '36703' last_name: Reimer - first_name: Somayeh full_name: Sadeghi-Kohan, Somayeh id: '78614' last_name: Sadeghi-Kohan orcid: https://orcid.org/0000-0001-7246-0610 - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: Stiballe A, Reimer JD, Sadeghi-Kohan S, Hellebrand S. Modeling Crosstalk-Induced Interconnect Delay with Polynomial Regression. 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024; 2024. apa: Stiballe, A., Reimer, J. D., Sadeghi-Kohan, S., & Hellebrand, S. (2024). Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression. 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024. bibtex: '@book{Stiballe_Reimer_Sadeghi-Kohan_Hellebrand_2024, place={Darmstadt, Germany}, title={Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression}, publisher={37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024}, author={Stiballe, Alisa and Reimer, Jan Dennis and Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}, year={2024} }' chicago: 'Stiballe, Alisa, Jan Dennis Reimer, Somayeh Sadeghi-Kohan, and Sybille Hellebrand. Modeling Crosstalk-Induced Interconnect Delay with Polynomial Regression. Darmstadt, Germany: 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024, 2024.' ieee: 'A. Stiballe, J. D. Reimer, S. Sadeghi-Kohan, and S. Hellebrand, Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression. Darmstadt, Germany: 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024, 2024.' mla: Stiballe, Alisa, et al. Modeling Crosstalk-Induced Interconnect Delay with Polynomial Regression. 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024, 2024. short: A. Stiballe, J.D. Reimer, S. Sadeghi-Kohan, S. Hellebrand, Modeling Crosstalk-Induced Interconnect Delay with Polynomial Regression, 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024, Darmstadt, Germany, 2024. date_created: 2024-01-08T08:47:32Z date_updated: 2024-03-22T17:12:39Z department: - _id: '48' language: - iso: eng place: Darmstadt, Germany publication_status: published publisher: 37. ITG / GMM / GI -Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'24), Feb. 2024 status: public title: Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression type: misc user_id: '209' year: '2024' ... --- _id: '35204' author: - first_name: Abdulkarim full_name: Ghazal, Abdulkarim last_name: Ghazal - first_name: Somayeh full_name: Sadeghi-Kohan, Somayeh id: '78614' last_name: Sadeghi-Kohan - first_name: Jan Dennis full_name: Reimer, Jan Dennis id: '36703' last_name: Reimer - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: Ghazal A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. On Cryptography Effects on Interconnect Reliability. 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023; 2023. apa: Ghazal, A., Sadeghi-Kohan, S., Reimer, J. D., & Hellebrand, S. (2023). On Cryptography Effects on Interconnect Reliability. 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023. bibtex: '@book{Ghazal_Sadeghi-Kohan_Reimer_Hellebrand_2023, place={Erfurt, Germany}, title={On Cryptography Effects on Interconnect Reliability}, publisher={35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023}, author={Ghazal, Abdulkarim and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille}, year={2023} }' chicago: 'Ghazal, Abdulkarim, Somayeh Sadeghi-Kohan, Jan Dennis Reimer, and Sybille Hellebrand. On Cryptography Effects on Interconnect Reliability. Erfurt, Germany: 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, 2023.' ieee: 'A. Ghazal, S. Sadeghi-Kohan, J. D. Reimer, and S. Hellebrand, On Cryptography Effects on Interconnect Reliability. Erfurt, Germany: 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, 2023.' mla: Ghazal, Abdulkarim, et al. On Cryptography Effects on Interconnect Reliability. 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, 2023. short: A. Ghazal, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, On Cryptography Effects on Interconnect Reliability, 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, Erfurt, Germany, 2023. date_created: 2023-01-04T10:20:41Z date_updated: 2023-04-06T21:06:37Z department: - _id: '48' keyword: - WORKSHOP language: - iso: eng page: '2' place: Erfurt, Germany publisher: 35. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'23), Feb. 2023 status: public title: On Cryptography Effects on Interconnect Reliability type: misc user_id: '36703' year: '2023' ... --- _id: '46482' abstract: - lang: eng text: "Ever increasing demands on the performance of microchips are leading to ever more complex semiconductor technologies with ever shrinking feature sizes. Complex applications with high demands on safety and reliability, such as autonomous driving, are simultaneously driving the requirements for test and diagnosis of VLSI circuits. Throughout the life cycle of a microchip, uncertainties occur that affect its timing behavior. For example, weak circuit structures, aging effects, or process variations can lead to a change in the timing behavior of the circuit. While these uncertainties do not necessarily lead to a change of the functional behavior, they can lead to a reliability problem.\r\nWith modular and hybrid compaction two test instruments are presented in this work that can be used for X-tolerant test response compaction in the built-in Faster-than-At-Speed Test (FAST) which is used to detect uncertainties in VLSI circuits. One challenge for test response compaction during FAST is the high and varying X-rate at the outputs of the circuit under test. By dividing the circuit outputs into test groups and separately compacting these test groups using stochastic compactors, the modular compaction is able to handle these high and varying X-rates.\r\nTo deal with uncertainties on logic interconnects, a method for distinguishing crosstalk and process variation is presented. In current semiconductor technologies, the number of parasitic coupling capacitances between logic interconnects is growing. These coupling capacitances can lead to crosstalk, which causes increased current flow in the logic interconnects, which in turn can lead to increased electromigration. In the presented method, delay maps describing the timing behavior of the circuit outputs at different operating points are used to train artificial neural networks which classify the tested circuits into fault-free and faulty." - lang: ger text: "Immer größere Anforderungen an die Leistungsfähigkeit von Mikrochips führen zu Halbleitertechnologien mit immer kleiner werdenden Strukturgrößen. Anwendungen mit hohen Ansprüchen an Sicherheit und Zuverlässigkeit, wie z.B. das autonome Fahren, treiben gleichzeitig die Anforderungen an den Test hochintegrierter Schaltungen an. Während des gesamten Lebenszyklus eines Mikrochips kommt es zu Unsicherheiten im Zeitverhalten. So können z.B. schwache Schaltungsstrukturen, Alterungseffekte oder Prozessvariationen zu einer Veränderung des Zeitverhaltens führen. Während diese Unsicherheiten nicht zu einer Veränderung des funktionalen Verhaltens führen müssen, können sie jedoch zu einem Zuverlässigkeitsproblem führen.\r\nMit der modularen und der hybriden Kompaktierung werden in dieser Arbeit zwei Testinstrumente vorgestellt, die für die X-tolerante Testantwortkompaktierung im eingebauten Hochgeschwindigkeitstest verwendet werden können. Eine Herausforderung für die Testantwortkompaktierung während des Hochgeschwindigkeitstests ist die hohe und variierende X-Rate an den Ausgängen der zu testenden Schaltung. Durch die Einteilung der Schaltungsausgänge in Prüfgruppen und die separierte Kompaktierung der Prüfgruppen mithilfe von stochastischen Kompaktierern, können die vorgestellten Verfahren diese hohen und variierenden X-Raten verarbeiten.\r\nFür den Umgang mit Unsicherheiten auf Verbindungsleitungen der Logik-Schaltung wird ein Verfahren zur Unterscheidung von Übersprechen und Prozessvariation vorgestellt. In aktuellen Halbleitertechnologien kommt es vermehrt zu parasitären Koppelkapazitäten zwischen den Verbindungsleitungen. In dem vorgestellten Verfahren werden künstliche neuronale Netze trainiert, um die Schaltungen in fehlerfrei und fehlerhaft zu klassifizieren." author: - first_name: Alexander full_name: Sprenger, Alexander id: '22707' last_name: Sprenger orcid: 0000-0002-0775-7677 citation: ama: Sprenger A. Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen. Universität Paderborn; 2023. doi:10.17619/UNIPB/1-1787 apa: Sprenger, A. (2023). Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen. Universität Paderborn. https://doi.org/10.17619/UNIPB/1-1787 bibtex: '@book{Sprenger_2023, place={Paderborn}, title={Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen}, DOI={10.17619/UNIPB/1-1787}, publisher={Universität Paderborn}, author={Sprenger, Alexander}, year={2023} }' chicago: 'Sprenger, Alexander. Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen. Paderborn: Universität Paderborn, 2023. https://doi.org/10.17619/UNIPB/1-1787.' ieee: 'A. Sprenger, Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen. Paderborn: Universität Paderborn, 2023.' mla: Sprenger, Alexander. Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen. Universität Paderborn, 2023, doi:10.17619/UNIPB/1-1787. short: A. Sprenger, Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen, Universität Paderborn, Paderborn, 2023. date_created: 2023-08-12T09:10:38Z date_updated: 2023-08-12T09:13:18Z department: - _id: '48' doi: 10.17619/UNIPB/1-1787 extern: '1' keyword: - Testantwortkompaktierung - Prozessvariation - Silicon Lifecycle Management language: - iso: ger main_file_link: - open_access: '1' url: https://nbn-resolving.org/urn:nbn:de:hbz:466:2-45493 oa: '1' page: xi, 160 place: Paderborn publication_status: published publisher: Universität Paderborn status: public supervisor: - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner title: Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen type: dissertation user_id: '22707' year: '2023' ... --- _id: '46739' author: - first_name: Somayeh full_name: Sadeghi-Kohan, Somayeh id: '78614' last_name: Sadeghi-Kohan orcid: https://orcid.org/0000-0001-7246-0610 - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich citation: ama: 'Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. In: 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W). IEEE; 2023. doi:10.1109/dsn-w58399.2023.00056' apa: Sadeghi-Kohan, S., Hellebrand, S., & Wunderlich, H.-J. (2023). Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W). https://doi.org/10.1109/dsn-w58399.2023.00056 bibtex: '@inproceedings{Sadeghi-Kohan_Hellebrand_Wunderlich_2023, title={Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication}, DOI={10.1109/dsn-w58399.2023.00056}, booktitle={2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2023} }' chicago: Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication.” In 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W). IEEE, 2023. https://doi.org/10.1109/dsn-w58399.2023.00056. ieee: 'S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication,” 2023, doi: 10.1109/dsn-w58399.2023.00056.' mla: Sadeghi-Kohan, Somayeh, et al. “Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication.” 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), IEEE, 2023, doi:10.1109/dsn-w58399.2023.00056. short: 'S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, in: 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), IEEE, 2023.' date_created: 2023-08-26T10:48:31Z date_updated: 2023-08-26T10:49:07Z department: - _id: '48' doi: 10.1109/dsn-w58399.2023.00056 language: - iso: eng publication: 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W) publication_status: published publisher: IEEE status: public title: Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication type: conference user_id: '78614' year: '2023' ... --- _id: '46738' author: - first_name: Somayeh full_name: Sadeghi-Kohan, Somayeh id: '78614' last_name: Sadeghi-Kohan orcid: https://orcid.org/0000-0001-7246-0610 - first_name: Jan Dennis full_name: Reimer, Jan Dennis id: '36703' last_name: Reimer - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich citation: ama: 'Sadeghi-Kohan S, Reimer JD, Hellebrand S, Wunderlich H-J. Optimizing the Streaming of Sensor Data with Approximate Communication. In: IEEE Asian Test Symposium (ATS’23), October 2023. ; 2023.' apa: Sadeghi-Kohan, S., Reimer, J. D., Hellebrand, S., & Wunderlich, H.-J. (2023). Optimizing the Streaming of Sensor Data with Approximate Communication. IEEE Asian Test Symposium (ATS’23), October 2023. IEEE Asian Test Symposium (ATS’23). bibtex: '@inproceedings{Sadeghi-Kohan_Reimer_Hellebrand_Wunderlich_2023, place={Beijing, China}, title={Optimizing the Streaming of Sensor Data with Approximate Communication}, booktitle={IEEE Asian Test Symposium (ATS’23), October 2023}, author={Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2023} }' chicago: Sadeghi-Kohan, Somayeh, Jan Dennis Reimer, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Optimizing the Streaming of Sensor Data with Approximate Communication.” In IEEE Asian Test Symposium (ATS’23), October 2023. Beijing, China, 2023. ieee: S. Sadeghi-Kohan, J. D. Reimer, S. Hellebrand, and H.-J. Wunderlich, “Optimizing the Streaming of Sensor Data with Approximate Communication,” presented at the IEEE Asian Test Symposium (ATS’23), 2023. mla: Sadeghi-Kohan, Somayeh, et al. “Optimizing the Streaming of Sensor Data with Approximate Communication.” IEEE Asian Test Symposium (ATS’23), October 2023, 2023. short: 'S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich, in: IEEE Asian Test Symposium (ATS’23), October 2023, Beijing, China, 2023.' conference: end_date: 2023-10-17 name: IEEE Asian Test Symposium (ATS'23) start_date: 2023-10-14 date_created: 2023-08-26T08:47:52Z date_updated: 2024-01-08T08:49:08Z department: - _id: '48' language: - iso: eng place: Beijing, China publication: IEEE Asian Test Symposium (ATS'23), October 2023 status: public title: Optimizing the Streaming of Sensor Data with Approximate Communication type: conference user_id: '36703' year: '2023' ... --- _id: '46264' abstract: - lang: eng text: "System-level interconnects provide the\r\nbackbone for increasingly complex systems on a chip. Their\r\nvulnerability to electromigration and crosstalk can lead to\r\nserious reliability and safety issues during the system lifetime.\r\nThis article presents an approach for periodic in-system testing\r\nwhich maintains a reliability profile to detect potential\r\nproblems before they actually cause a failure. Relying on a\r\ncommon infrastructure for EM-aware system workload\r\nmanagement and test, it minimizes the stress induced by the\r\ntest itself and contributes to the self-healing of system-induced\r\nelectromigration degradations. " article_type: original author: - first_name: Somayeh full_name: Sadeghi-Kohan, Somayeh id: '78614' last_name: Sadeghi-Kohan orcid: https://orcid.org/0000-0001-7246-0610 - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich citation: ama: Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Workload-Aware Periodic Interconnect BIST. IEEE Design &Test. Published online 2023:1-1. doi:10.1109/mdat.2023.3298849 apa: Sadeghi-Kohan, S., Hellebrand, S., & Wunderlich, H.-J. (2023). Workload-Aware Periodic Interconnect BIST. IEEE Design &Test, 1–1. https://doi.org/10.1109/mdat.2023.3298849 bibtex: '@article{Sadeghi-Kohan_Hellebrand_Wunderlich_2023, title={Workload-Aware Periodic Interconnect BIST}, DOI={10.1109/mdat.2023.3298849}, journal={IEEE Design &Test}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2023}, pages={1–1} }' chicago: Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Workload-Aware Periodic Interconnect BIST.” IEEE Design &Test, 2023, 1–1. https://doi.org/10.1109/mdat.2023.3298849. ieee: 'S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Workload-Aware Periodic Interconnect BIST,” IEEE Design &Test, pp. 1–1, 2023, doi: 10.1109/mdat.2023.3298849.' mla: Sadeghi-Kohan, Somayeh, et al. “Workload-Aware Periodic Interconnect BIST.” IEEE Design &Test, Institute of Electrical and Electronics Engineers (IEEE), 2023, pp. 1–1, doi:10.1109/mdat.2023.3298849. short: S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, IEEE Design &Test (2023) 1–1. date_created: 2023-08-02T11:07:43Z date_updated: 2024-03-22T17:15:10Z department: - _id: '48' doi: 10.1109/mdat.2023.3298849 keyword: - Electrical and Electronic Engineering - Hardware and Architecture - Software language: - iso: eng main_file_link: - url: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10194315 page: 1-1 publication: IEEE Design &Test publication_identifier: issn: - 2168-2356 - 2168-2364 publication_status: published publisher: Institute of Electrical and Electronics Engineers (IEEE) status: public title: Workload-Aware Periodic Interconnect BIST type: journal_article user_id: '209' year: '2023' ... --- _id: '45830' author: - first_name: Hanieh full_name: Jafarzadeh, Hanieh last_name: Jafarzadeh - first_name: Florian full_name: Klemme, Florian last_name: Klemme - first_name: Jan Dennis full_name: Reimer, Jan Dennis id: '36703' last_name: Reimer - first_name: Zahra Paria full_name: Najafi Haghi, Zahra Paria last_name: Najafi Haghi - first_name: Hussam full_name: ' Amrouch, Hussam' last_name: ' Amrouch' - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Hans-Joachim full_name: ' Wunderlich, Hans-Joachim' last_name: ' Wunderlich' citation: ama: 'Jafarzadeh H, Klemme F, Reimer JD, et al. Robust Pattern Generation for Small Delay Faults under Process Variations. In: IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023. IEEE; 2023.' apa: Jafarzadeh, H., Klemme, F., Reimer, J. D., Najafi Haghi, Z. P., Amrouch, H., Hellebrand, S., & Wunderlich, H.-J. (2023). Robust Pattern Generation for Small Delay Faults under Process Variations. IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023. IEEE International Test Conference (ITC’23), Anaheim, USA. bibtex: '@inproceedings{Jafarzadeh_Klemme_Reimer_Najafi Haghi_ Amrouch_Hellebrand_ Wunderlich_2023, place={Anaheim, CA, USA}, title={Robust Pattern Generation for Small Delay Faults under Process Variations}, booktitle={IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023}, publisher={IEEE}, author={Jafarzadeh, Hanieh and Klemme, Florian and Reimer, Jan Dennis and Najafi Haghi, Zahra Paria and Amrouch, Hussam and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2023} }' chicago: 'Jafarzadeh, Hanieh, Florian Klemme, Jan Dennis Reimer, Zahra Paria Najafi Haghi, Hussam Amrouch, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Robust Pattern Generation for Small Delay Faults under Process Variations.” In IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023. Anaheim, CA, USA: IEEE, 2023.' ieee: H. Jafarzadeh et al., “Robust Pattern Generation for Small Delay Faults under Process Variations,” presented at the IEEE International Test Conference (ITC’23), Anaheim, USA, 2023. mla: Jafarzadeh, Hanieh, et al. “Robust Pattern Generation for Small Delay Faults under Process Variations.” IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023, IEEE, 2023. short: 'H. Jafarzadeh, F. Klemme, J.D. Reimer, Z.P. Najafi Haghi, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, in: IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023, IEEE, Anaheim, CA, USA, 2023.' conference: end_date: 2023-10-13 location: Anaheim, USA name: IEEE International Test Conference (ITC'23) start_date: 2023-10-08 date_created: 2023-07-03T08:20:17Z date_updated: 2024-03-22T17:14:02Z department: - _id: '48' language: - iso: eng place: Anaheim, CA, USA publication: IEEE International Test Conference (ITC'23), Anaheim, USA, October 2023 publication_status: published publisher: IEEE status: public title: Robust Pattern Generation for Small Delay Faults under Process Variations type: conference user_id: '209' year: '2023' ... --- _id: '29351' abstract: - lang: eng text: Safety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. The required high fault coverage at runtime is usually obtained by a combination of concurrent error detection or correction and periodic tests within rather short time intervals. The concurrent scheme ensures the integrity of computed results while the periodic test has to identify potential aging problems and to prevent any fault accumulation which may invalidate the concurrent error detection mechanism. Such periodic built-in self-test (BIST) schemes are already commercialized for memories and for random logic. The paper at hand extends this approach to interconnect structures. A BIST scheme is presented which targets interconnect defects before they will actually affect the system functionality at nominal speed. A BIST schedule is developed which significantly reduces aging caused by electromigration during the lifetime application of the periodic test. article_type: original author: - first_name: Somayeh full_name: Sadeghi-Kohan, Somayeh id: '78614' last_name: Sadeghi-Kohan - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich citation: ama: Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Stress-Aware Periodic Test of Interconnects. Journal of Electronic Testing. Published online 2022. doi:10.1007/s10836-021-05979-5 apa: Sadeghi-Kohan, S., Hellebrand, S., & Wunderlich, H.-J. (2022). Stress-Aware Periodic Test of Interconnects. Journal of Electronic Testing. https://doi.org/10.1007/s10836-021-05979-5 bibtex: '@article{Sadeghi-Kohan_Hellebrand_Wunderlich_2022, title={Stress-Aware Periodic Test of Interconnects}, DOI={10.1007/s10836-021-05979-5}, journal={Journal of Electronic Testing}, publisher={Springer Science and Business Media LLC}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2022} }' chicago: Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Stress-Aware Periodic Test of Interconnects.” Journal of Electronic Testing, 2022. https://doi.org/10.1007/s10836-021-05979-5. ieee: 'S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Stress-Aware Periodic Test of Interconnects,” Journal of Electronic Testing, 2022, doi: 10.1007/s10836-021-05979-5.' mla: Sadeghi-Kohan, Somayeh, et al. “Stress-Aware Periodic Test of Interconnects.” Journal of Electronic Testing, Springer Science and Business Media LLC, 2022, doi:10.1007/s10836-021-05979-5. short: S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, Journal of Electronic Testing (2022). date_created: 2022-01-14T11:16:34Z date_updated: 2022-05-11T16:10:01Z department: - _id: '48' doi: 10.1007/s10836-021-05979-5 keyword: - Electrical and Electronic Engineering language: - iso: eng publication: Journal of Electronic Testing publication_identifier: issn: - 0923-8174 - 1573-0727 publication_status: published publisher: Springer Science and Business Media LLC status: public title: Stress-Aware Periodic Test of Interconnects type: journal_article user_id: '209' year: '2022' ... --- _id: '29890' author: - first_name: Somayeh full_name: Sadeghi-Kohan, Somayeh id: '78614' last_name: Sadeghi-Kohan - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich citation: ama: Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. EM-Aware Interconnect BIST. European Workshop on Silicon Lifecycle Management, March 18, 2022; 2022. apa: Sadeghi-Kohan, S., Hellebrand, S., & Wunderlich, H.-J. (2022). EM-Aware Interconnect BIST. European Workshop on Silicon Lifecycle Management, March 18, 2022. bibtex: '@book{Sadeghi-Kohan_Hellebrand_Wunderlich_2022, place={Online}, title={EM-Aware Interconnect BIST}, publisher={European Workshop on Silicon Lifecycle Management, March 18, 2022}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2022} }' chicago: 'Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich. EM-Aware Interconnect BIST. Online: European Workshop on Silicon Lifecycle Management, March 18, 2022, 2022.' ieee: 'S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, EM-Aware Interconnect BIST. Online: European Workshop on Silicon Lifecycle Management, March 18, 2022, 2022.' mla: Sadeghi-Kohan, Somayeh, et al. EM-Aware Interconnect BIST. European Workshop on Silicon Lifecycle Management, March 18, 2022, 2022. short: S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, EM-Aware Interconnect BIST, European Workshop on Silicon Lifecycle Management, March 18, 2022, Online, 2022. date_created: 2022-02-19T14:21:24Z date_updated: 2022-05-11T17:07:24Z department: - _id: '48' keyword: - WORKSHOP language: - iso: eng page: '2' place: Online publication_status: published publisher: European Workshop on Silicon Lifecycle Management, March 18, 2022 status: public title: EM-Aware Interconnect BIST type: misc user_id: '209' year: '2022' ... --- _id: '19422' author: - first_name: Alexander full_name: Sprenger, Alexander id: '22707' last_name: Sprenger - first_name: Somayeh full_name: Sadeghi-Kohan, Somayeh id: '78614' last_name: Sadeghi-Kohan - first_name: Jan Dennis full_name: Reimer, Jan Dennis id: '36703' last_name: Reimer - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: 'Sprenger A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020. ; 2020.' apa: Sprenger, A., Sadeghi-Kohan, S., Reimer, J. D., & Hellebrand, S. (2020). Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020. bibtex: '@inproceedings{Sprenger_Sadeghi-Kohan_Reimer_Hellebrand_2020, place={Virtual Conference - Originally Frascati (Rome), Italy}, title={Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study}, booktitle={IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020}, author={Sprenger, Alexander and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille}, year={2020} }' chicago: Sprenger, Alexander, Somayeh Sadeghi-Kohan, Jan Dennis Reimer, and Sybille Hellebrand. “Variation-Aware Test for Logic Interconnects Using Neural Networks - A Case Study.” In IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020. Virtual Conference - Originally Frascati (Rome), Italy, 2020. ieee: A. Sprenger, S. Sadeghi-Kohan, J. D. Reimer, and S. Hellebrand, “Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study,” 2020. mla: Sprenger, Alexander, et al. “Variation-Aware Test for Logic Interconnects Using Neural Networks - A Case Study.” IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020, 2020. short: 'A. Sprenger, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020, Virtual Conference - Originally Frascati (Rome), Italy, 2020.' conference: end_date: 2020-10-21 start_date: 2020-10-19 date_created: 2020-09-15T14:03:02Z date_updated: 2022-02-19T14:16:58Z department: - _id: '48' language: - iso: eng place: Virtual Conference - Originally Frascati (Rome), Italy publication: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020 publication_status: published status: public title: Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study type: conference user_id: '209' year: '2020' ... --- _id: '15419' author: - first_name: Somayeh full_name: Sadeghi-Kohan, Somayeh id: '78614' last_name: Sadeghi-Kohan - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: Sadeghi-Kohan S, Hellebrand S. Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020; 2020. apa: Sadeghi-Kohan, S., & Hellebrand, S. (2020). Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020. bibtex: '@book{Sadeghi-Kohan_Hellebrand_2020, place={Ludwigsburg}, title={Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects}, publisher={32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}, year={2020} }' chicago: 'Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. Ludwigsburg: 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020, 2020.' ieee: 'S. Sadeghi-Kohan and S. Hellebrand, Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. Ludwigsburg: 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020, 2020.' mla: Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020, 2020. short: S. Sadeghi-Kohan, S. Hellebrand, Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects, 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020, Ludwigsburg, 2020. date_created: 2019-12-29T16:13:58Z date_updated: 2022-04-04T12:30:02Z department: - _id: '48' keyword: - WORKSHOP language: - iso: eng page: '4' place: Ludwigsburg publication_status: published publisher: 32. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'20), 16. - 18. Februar 2020 status: public title: Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects type: misc user_id: '209' year: '2020' ... --- _id: '29200' author: - first_name: Somayeh full_name: Sadeghi-Kohan, Somayeh id: '78614' last_name: Sadeghi-Kohan - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: 'Sadeghi-Kohan S, Hellebrand S. Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. In: 38th IEEE VLSI Test Symposium (VTS). IEEE; 2020. doi:10.1109/vts48691.2020.9107591' apa: Sadeghi-Kohan, S., & Hellebrand, S. (2020). Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. 38th IEEE VLSI Test Symposium (VTS). https://doi.org/10.1109/vts48691.2020.9107591 bibtex: '@inproceedings{Sadeghi-Kohan_Hellebrand_2020, place={Virtual Conference - Originally San Diego, CA, USA}, title={Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects}, DOI={10.1109/vts48691.2020.9107591}, booktitle={38th IEEE VLSI Test Symposium (VTS)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}, year={2020} }' chicago: 'Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. “Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects.” In 38th IEEE VLSI Test Symposium (VTS). Virtual Conference - Originally San Diego, CA, USA: IEEE, 2020. https://doi.org/10.1109/vts48691.2020.9107591.' ieee: 'S. Sadeghi-Kohan and S. Hellebrand, “Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects,” 2020, doi: 10.1109/vts48691.2020.9107591.' mla: Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. “Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects.” 38th IEEE VLSI Test Symposium (VTS), IEEE, 2020, doi:10.1109/vts48691.2020.9107591. short: 'S. Sadeghi-Kohan, S. Hellebrand, in: 38th IEEE VLSI Test Symposium (VTS), IEEE, Virtual Conference - Originally San Diego, CA, USA, 2020.' date_created: 2022-01-10T08:38:34Z date_updated: 2022-05-11T17:06:38Z department: - _id: '48' doi: 10.1109/vts48691.2020.9107591 language: - iso: eng place: Virtual Conference - Originally San Diego, CA, USA publication: 38th IEEE VLSI Test Symposium (VTS) publication_status: published publisher: IEEE status: public title: Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects type: conference user_id: '209' year: '2020' ... --- _id: '19421' author: - first_name: Stefan full_name: Holst, Stefan last_name: Holst - first_name: Matthias full_name: Kampmann, Matthias id: '10935' last_name: Kampmann - first_name: Alexander full_name: Sprenger, Alexander id: '22707' last_name: Sprenger - first_name: Jan Dennis full_name: Reimer, Jan Dennis id: '36703' last_name: Reimer - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich - first_name: Xiaoqing full_name: Weng, Xiaoqing last_name: Weng citation: ama: 'Holst S, Kampmann M, Sprenger A, et al. Logic Fault Diagnosis of Hidden Delay Defects. In: IEEE International Test Conference (ITC’20), November 2020. ; 2020.' apa: Holst, S., Kampmann, M., Sprenger, A., Reimer, J. D., Hellebrand, S., Wunderlich, H.-J., & Weng, X. (2020). Logic Fault Diagnosis of Hidden Delay Defects. IEEE International Test Conference (ITC’20), November 2020. bibtex: '@inproceedings{Holst_Kampmann_Sprenger_Reimer_Hellebrand_Wunderlich_Weng_2020, place={Virtual Conference - Originally Washington, DC, USA}, title={Logic Fault Diagnosis of Hidden Delay Defects}, booktitle={IEEE International Test Conference (ITC’20), November 2020}, author={Holst, Stefan and Kampmann, Matthias and Sprenger, Alexander and Reimer, Jan Dennis and Hellebrand, Sybille and Wunderlich, Hans-Joachim and Weng, Xiaoqing}, year={2020} }' chicago: Holst, Stefan, Matthias Kampmann, Alexander Sprenger, Jan Dennis Reimer, Sybille Hellebrand, Hans-Joachim Wunderlich, and Xiaoqing Weng. “Logic Fault Diagnosis of Hidden Delay Defects.” In IEEE International Test Conference (ITC’20), November 2020. Virtual Conference - Originally Washington, DC, USA, 2020. ieee: S. Holst et al., “Logic Fault Diagnosis of Hidden Delay Defects,” 2020. mla: Holst, Stefan, et al. “Logic Fault Diagnosis of Hidden Delay Defects.” IEEE International Test Conference (ITC’20), November 2020, 2020. short: 'S. Holst, M. Kampmann, A. Sprenger, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich, X. Weng, in: IEEE International Test Conference (ITC’20), November 2020, Virtual Conference - Originally Washington, DC, USA, 2020.' date_created: 2020-09-15T13:56:08Z date_updated: 2022-05-11T17:08:20Z department: - _id: '48' language: - iso: eng place: Virtual Conference - Originally Washington, DC, USA publication: IEEE International Test Conference (ITC'20), November 2020 publication_status: published status: public title: Logic Fault Diagnosis of Hidden Delay Defects type: conference user_id: '209' year: '2020' ... --- _id: '8112' author: - first_name: Mohammad Urf full_name: Maaz, Mohammad Urf id: '49274' last_name: Maaz - first_name: Alexander full_name: Sprenger, Alexander id: '22707' last_name: Sprenger - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: 'Maaz MU, Sprenger A, Hellebrand S. A Hybrid Space Compactor for Varying X-Rates. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19); 2019.' apa: 'Maaz, M. U., Sprenger, A., & Hellebrand, S. (2019). A Hybrid Space Compactor for Varying X-Rates. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19).' bibtex: '@book{Maaz_Sprenger_Hellebrand_2019, place={Prien am Chiemsee}, title={A Hybrid Space Compactor for Varying X-Rates}, publisher={31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19)}, author={Maaz, Mohammad Urf and Sprenger, Alexander and Hellebrand, Sybille}, year={2019} }' chicago: 'Maaz, Mohammad Urf, Alexander Sprenger, and Sybille Hellebrand. A Hybrid Space Compactor for Varying X-Rates. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19), 2019.' ieee: 'M. U. Maaz, A. Sprenger, and S. Hellebrand, A Hybrid Space Compactor for Varying X-Rates. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19), 2019.' mla: Maaz, Mohammad Urf, et al. A Hybrid Space Compactor for Varying X-Rates. 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19), 2019. short: M.U. Maaz, A. Sprenger, S. Hellebrand, A Hybrid Space Compactor for Varying X-Rates, 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19), Prien am Chiemsee, 2019. date_created: 2019-02-26T15:11:02Z date_updated: 2022-01-06T07:03:51Z department: - _id: '48' keyword: - WORKSHOP language: - iso: eng place: Prien am Chiemsee publisher: 31. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'19) status: public title: A Hybrid Space Compactor for Varying X-Rates type: misc user_id: '209' year: '2019' ... --- _id: '8667' author: - first_name: Alexander full_name: Sprenger, Alexander id: '22707' last_name: Sprenger - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: Sprenger A, Hellebrand S. Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test. Journal of Circuits, Systems and Computers. 2019;28(1):1-23. doi:10.1142/s0218126619400012 apa: Sprenger, A., & Hellebrand, S. (2019). Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test. Journal of Circuits, Systems and Computers, 28(1), 1–23. https://doi.org/10.1142/s0218126619400012 bibtex: '@article{Sprenger_Hellebrand_2019, title={Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test}, volume={28}, DOI={10.1142/s0218126619400012}, number={1}, journal={Journal of Circuits, Systems and Computers}, publisher={World Scientific Publishing Company}, author={Sprenger, Alexander and Hellebrand, Sybille}, year={2019}, pages={1–23} }' chicago: 'Sprenger, Alexander, and Sybille Hellebrand. “Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test.” Journal of Circuits, Systems and Computers 28, no. 1 (2019): 1–23. https://doi.org/10.1142/s0218126619400012.' ieee: A. Sprenger and S. Hellebrand, “Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test,” Journal of Circuits, Systems and Computers, vol. 28, no. 1, pp. 1–23, 2019. mla: Sprenger, Alexander, and Sybille Hellebrand. “Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test.” Journal of Circuits, Systems and Computers, vol. 28, no. 1, World Scientific Publishing Company, 2019, pp. 1–23, doi:10.1142/s0218126619400012. short: A. Sprenger, S. Hellebrand, Journal of Circuits, Systems and Computers 28 (2019) 1–23. date_created: 2019-03-27T08:57:42Z date_updated: 2022-01-06T07:03:58Z department: - _id: '48' doi: 10.1142/s0218126619400012 intvolume: ' 28' issue: '1' language: - iso: eng page: 1-23 project: - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: Journal of Circuits, Systems and Computers publication_identifier: issn: - 0218-1266 - 1793-6454 publication_status: published publisher: World Scientific Publishing Company status: public title: Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test type: journal_article user_id: '59789' volume: 28 year: '2019' ... --- _id: '13048' abstract: - lang: eng text: Marginal hardware introduces severe reliability threats throughout the life cycle of a system. Although marginalities may not affect the functionality of a circuit immediately after manufacturing, they can degrade into hard failures and must be screened out during manufacturing test to prevent early life failures. Furthermore, their evolution in the field must be proactively monitored by periodic tests before actual failures occur. In recent years small delay faults have gained increasing attention as possible indicators of marginal hardware. However, small delay faults on short paths may be undetectable even with advanced timing aware ATPG. Faster-than-at-speed test (FAST) can detect such hidden delay faults, but so far FAST has mainly been restricted to manufacturing test. author: - first_name: Matthias full_name: Kampmann, Matthias id: '10935' last_name: Kampmann - first_name: Michael full_name: A. Kochte, Michael last_name: A. Kochte - first_name: Chang full_name: Liu, Chang last_name: Liu - first_name: Eric full_name: Schneider, Eric last_name: Schneider - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich citation: ama: Kampmann M, A. Kochte M, Liu C, Schneider E, Hellebrand S, Wunderlich H-J. Built-in Test for Hidden Delay Faults. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). 2019;38(10):1956-1968. apa: Kampmann, M., A. Kochte, M., Liu, C., Schneider, E., Hellebrand, S., & Wunderlich, H.-J. (2019). Built-in Test for Hidden Delay Faults. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 38(10), 1956–1968. bibtex: '@article{Kampmann_A. Kochte_Liu_Schneider_Hellebrand_Wunderlich_2019, title={Built-in Test for Hidden Delay Faults}, volume={38}, number={10}, journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}, publisher={IEEE}, author={Kampmann, Matthias and A. Kochte, Michael and Liu, Chang and Schneider, Eric and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2019}, pages={1956–1968} }' chicago: 'Kampmann, Matthias, Michael A. Kochte, Chang Liu, Eric Schneider, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Built-in Test for Hidden Delay Faults.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 38, no. 10 (2019): 1956–68.' ieee: M. Kampmann, M. A. Kochte, C. Liu, E. Schneider, S. Hellebrand, and H.-J. Wunderlich, “Built-in Test for Hidden Delay Faults,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 38, no. 10, pp. 1956–1968, 2019. mla: Kampmann, Matthias, et al. “Built-in Test for Hidden Delay Faults.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 38, no. 10, IEEE, 2019, pp. 1956–68. short: M. Kampmann, M. A. Kochte, C. Liu, E. Schneider, S. Hellebrand, H.-J. Wunderlich, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 38 (2019) 1956–1968. date_created: 2019-08-28T11:44:25Z date_updated: 2022-01-06T06:51:27Z department: - _id: '48' intvolume: ' 38' issue: '10' language: - iso: eng page: 1956 - 1968 publication: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) publication_identifier: eissn: - 1937-4151 publication_status: published publisher: IEEE status: public title: Built-in Test for Hidden Delay Faults type: journal_article user_id: '209' volume: 38 year: '2019' ... --- _id: '12918' abstract: - lang: eng text: 'The test for small delay faults is of major importance for predicting potential early life failures or wearout problems. Typically, a faster-than-at-speed test (FAST) with sev¬eral different frequencies is used to detect also hidden small delays, which can only be propagated over short paths. But then the outputs at the end of long paths may no longer reach their stable values at the nominal observation time and must be considered as unknown (X-values). Thus, test response compaction for FAST must be extremely flexible to cope with high X-rates, which also vary with the test frequencies. Stochastic compaction introduced by Mitra et al. is controlled by weighted pseudo-random signals allowing for easy adaptation to varying conditions. As demonstrated in previous work, the pseudo-random control can be optimized for high fault efficiency or X-reduction, but a given target in fault efficiency cannot be guaranteed. To close this gap, a hybrid space compactor is introduced in this paper. It is based on the observation that many faults are lost in the compaction of relatively few critical test patterns. For these critical patterns a deterministic compaction phase is added to the test, where the existing compactor structure is re-used, but controlled by specifically determined control vectors. ' author: - first_name: Mohammad Urf full_name: Maaz, Mohammad Urf id: '49274' last_name: Maaz - first_name: Alexander full_name: Sprenger, Alexander id: '22707' last_name: Sprenger - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: 'Maaz MU, Sprenger A, Hellebrand S. A Hybrid Space Compactor for Adaptive X-Handling. In: 50th IEEE International Test Conference (ITC). IEEE; 2019:1-8.' apa: Maaz, M. U., Sprenger, A., & Hellebrand, S. (2019). A Hybrid Space Compactor for Adaptive X-Handling. 50th IEEE International Test Conference (ITC), 1–8. bibtex: '@inproceedings{Maaz_Sprenger_Hellebrand_2019, place={Washington, DC, USA}, title={A Hybrid Space Compactor for Adaptive X-Handling}, booktitle={50th IEEE International Test Conference (ITC)}, publisher={IEEE}, author={Maaz, Mohammad Urf and Sprenger, Alexander and Hellebrand, Sybille}, year={2019}, pages={1–8} }' chicago: 'Maaz, Mohammad Urf, Alexander Sprenger, and Sybille Hellebrand. “A Hybrid Space Compactor for Adaptive X-Handling.” In 50th IEEE International Test Conference (ITC), 1–8. Washington, DC, USA: IEEE, 2019.' ieee: M. U. Maaz, A. Sprenger, and S. Hellebrand, “A Hybrid Space Compactor for Adaptive X-Handling,” in 50th IEEE International Test Conference (ITC), Washington, DC, USA, 2019, pp. 1–8. mla: Maaz, Mohammad Urf, et al. “A Hybrid Space Compactor for Adaptive X-Handling.” 50th IEEE International Test Conference (ITC), IEEE, 2019, pp. 1–8. short: 'M.U. Maaz, A. Sprenger, S. Hellebrand, in: 50th IEEE International Test Conference (ITC), IEEE, Washington, DC, USA, 2019, pp. 1–8.' conference: end_date: 2019-11-14 location: Washington, DC, USA name: 50th IEEE International Test Conference (ITC) start_date: 2019-11-12 date_created: 2019-08-14T06:59:04Z date_updated: 2022-05-11T17:09:35Z department: - _id: '48' keyword: - Faster-than-at-speed test - BIST - DFT - Test response compaction - Stochastic compactor - X-handling language: - iso: eng page: 1-8 place: Washington, DC, USA publication: 50th IEEE International Test Conference (ITC) publication_status: published publisher: IEEE quality_controlled: '1' status: public title: A Hybrid Space Compactor for Adaptive X-Handling type: conference user_id: '209' year: '2019' ... --- _id: '4576' author: - first_name: Alexander full_name: Sprenger, Alexander id: '22707' last_name: Sprenger - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: 'Sprenger A, Hellebrand S. Stochastische Kompaktierung für den Hochgeschwindigkeitstest. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18); 2018.' apa: 'Sprenger, A., & Hellebrand, S. (2018). Stochastische Kompaktierung für den Hochgeschwindigkeitstest. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18).' bibtex: '@book{Sprenger_Hellebrand_2018, place={Freiburg, Germany}, title={Stochastische Kompaktierung für den Hochgeschwindigkeitstest}, publisher={30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18)}, author={Sprenger, Alexander and Hellebrand, Sybille}, year={2018} }' chicago: 'Sprenger, Alexander, and Sybille Hellebrand. Stochastische Kompaktierung für den Hochgeschwindigkeitstest. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), 2018.' ieee: 'A. Sprenger and S. Hellebrand, Stochastische Kompaktierung für den Hochgeschwindigkeitstest. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), 2018.' mla: Sprenger, Alexander, and Sybille Hellebrand. Stochastische Kompaktierung für den Hochgeschwindigkeitstest. 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), 2018. short: A. Sprenger, S. Hellebrand, Stochastische Kompaktierung für den Hochgeschwindigkeitstest, 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), Freiburg, Germany, 2018. date_created: 2018-10-02T12:29:44Z date_updated: 2022-01-06T07:01:13Z department: - _id: '48' keyword: - WORKSHOP language: - iso: ger place: Freiburg, Germany publisher: 30. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'18) status: public title: Stochastische Kompaktierung für den Hochgeschwindigkeitstest type: misc user_id: '22707' year: '2018' ... --- _id: '12974' author: - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Joerg full_name: Henkel, Joerg last_name: Henkel - first_name: Anand full_name: Raghunathan, Anand last_name: Raghunathan - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich citation: ama: Hellebrand S, Henkel J, Raghunathan A, Wunderlich H-J. Guest Editors’ Introduction - Special Issue on Approximate Computing. IEEE Embedded Systems Letters. 2018;10(1):1-1. doi:10.1109/les.2018.2789942 apa: Hellebrand, S., Henkel, J., Raghunathan, A., & Wunderlich, H.-J. (2018). Guest Editors’ Introduction - Special Issue on Approximate Computing. IEEE Embedded Systems Letters, 10(1), 1–1. https://doi.org/10.1109/les.2018.2789942 bibtex: '@article{Hellebrand_Henkel_Raghunathan_Wunderlich_2018, title={Guest Editors’ Introduction - Special Issue on Approximate Computing}, volume={10}, DOI={10.1109/les.2018.2789942}, number={1}, journal={IEEE Embedded Systems Letters}, publisher={IEEE}, author={Hellebrand, Sybille and Henkel, Joerg and Raghunathan, Anand and Wunderlich, Hans-Joachim}, year={2018}, pages={1–1} }' chicago: 'Hellebrand, Sybille, Joerg Henkel, Anand Raghunathan, and Hans-Joachim Wunderlich. “Guest Editors’ Introduction - Special Issue on Approximate Computing.” IEEE Embedded Systems Letters 10, no. 1 (2018): 1–1. https://doi.org/10.1109/les.2018.2789942.' ieee: S. Hellebrand, J. Henkel, A. Raghunathan, and H.-J. Wunderlich, “Guest Editors’ Introduction - Special Issue on Approximate Computing,” IEEE Embedded Systems Letters, vol. 10, no. 1, pp. 1–1, 2018. mla: Hellebrand, Sybille, et al. “Guest Editors’ Introduction - Special Issue on Approximate Computing.” IEEE Embedded Systems Letters, vol. 10, no. 1, IEEE, 2018, pp. 1–1, doi:10.1109/les.2018.2789942. short: S. Hellebrand, J. Henkel, A. Raghunathan, H.-J. Wunderlich, IEEE Embedded Systems Letters 10 (2018) 1–1. date_created: 2019-08-28T08:40:58Z date_updated: 2022-01-06T06:51:27Z department: - _id: '48' doi: 10.1109/les.2018.2789942 intvolume: ' 10' issue: '1' language: - iso: eng page: 1-1 publication: IEEE Embedded Systems Letters publisher: IEEE status: public title: Guest Editors' Introduction - Special Issue on Approximate Computing type: journal_article user_id: '209' volume: 10 year: '2018' ... --- _id: '13057' author: - first_name: Matthias full_name: Kampmann, Matthias id: '10935' last_name: Kampmann - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: Kampmann M, Hellebrand S. Design For Small Delay Test - A Simulation Study. Microelectronics Reliability. 2018;80:124-133. apa: Kampmann, M., & Hellebrand, S. (2018). Design For Small Delay Test - A Simulation Study. Microelectronics Reliability, 80, 124–133. bibtex: '@article{Kampmann_Hellebrand_2018, title={Design For Small Delay Test - A Simulation Study}, volume={80}, journal={Microelectronics Reliability}, author={Kampmann, Matthias and Hellebrand, Sybille}, year={2018}, pages={124–133} }' chicago: 'Kampmann, Matthias, and Sybille Hellebrand. “Design For Small Delay Test - A Simulation Study.” Microelectronics Reliability 80 (2018): 124–33.' ieee: M. Kampmann and S. Hellebrand, “Design For Small Delay Test - A Simulation Study,” Microelectronics Reliability, vol. 80, pp. 124–133, 2018. mla: Kampmann, Matthias, and Sybille Hellebrand. “Design For Small Delay Test - A Simulation Study.” Microelectronics Reliability, vol. 80, 2018, pp. 124–33. short: M. Kampmann, S. Hellebrand, Microelectronics Reliability 80 (2018) 124–133. date_created: 2019-08-28T11:49:25Z date_updated: 2022-01-06T06:51:27Z department: - _id: '48' intvolume: ' 80' language: - iso: eng page: 124-133 publication: Microelectronics Reliability status: public title: Design For Small Delay Test - A Simulation Study type: journal_article user_id: '659' volume: 80 year: '2018' ... --- _id: '13072' author: - first_name: Matthias full_name: Kampmann, Matthias id: '10935' last_name: Kampmann - first_name: Sybille full_name: Hellebrand, Sybille last_name: Hellebrand citation: ama: Kampmann M, Hellebrand S. Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test. 19th Workshop on RTL and High Level Testing (WRTLT’18), Hefei, Anhui, China; 2018. apa: Kampmann, M., & Hellebrand, S. (2018). Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test. 19th Workshop on RTL and High Level Testing (WRTLT’18), Hefei, Anhui, China. bibtex: '@book{Kampmann_Hellebrand_2018, place={19th Workshop on RTL and High Level Testing (WRTLT’18), Hefei, Anhui, China}, title={Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test}, author={Kampmann, Matthias and Hellebrand, Sybille}, year={2018} }' chicago: Kampmann, Matthias, and Sybille Hellebrand. Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test. 19th Workshop on RTL and High Level Testing (WRTLT’18), Hefei, Anhui, China, 2018. ieee: M. Kampmann and S. Hellebrand, Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test. 19th Workshop on RTL and High Level Testing (WRTLT’18), Hefei, Anhui, China, 2018. mla: Kampmann, Matthias, and Sybille Hellebrand. Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test. 2018. short: M. Kampmann, S. Hellebrand, Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test, 19th Workshop on RTL and High Level Testing (WRTLT’18), Hefei, Anhui, China, 2018. date_created: 2019-08-28T12:00:28Z date_updated: 2022-01-06T06:51:28Z department: - _id: '48' keyword: - WORKSHOP language: - iso: eng place: 19th Workshop on RTL and High Level Testing (WRTLT'18), Hefei, Anhui, China status: public title: Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test type: misc user_id: '659' year: '2018' ... --- _id: '29460' abstract: - lang: eng text: STT-RAM cells can be considered as an alternative or a hybrid addition to today's SRAM-based cache memories. This is mostly because of their scalability and low leakage power. Moreover, their data storing mechanism (storing the value as resistance) makes them very suitable and applicable for multivalue cache architectures. This feature results in system performance enhancement without any area overhead. On the other hand, the required two-step read/write procedure in multilevel cells results in a non-uniform time access and energy and power overhead on the system. In this paper, we propose a new architecture to dynamically swap data between soft (fast read access) and hard (slow read access) bits in ML cell. Moreover, by reconfiguring cache block size, the proposed architecture can switch between ML and SL modes at runtime. In other words, the swapping method places the hot part of each cache block into soft-bits and the less accessed part into the hard-bits. The SL/ML switching method benefits from the low latency and energy of SL mode and the high storing capacity of ML mode at the same time. Although experimental results show that our proposed method slightly increases the miss rate compared with the conventional ML caches, the performance and energy are improved by 4.9% and 6.5%, respectively. Also, the storage overhead of our method is about 1% that is negligible. author: - first_name: Ramin full_name: Rezaeizadeh Rookerd, Ramin last_name: Rezaeizadeh Rookerd - first_name: Somayeh full_name: Sadeghi-Kohan, Somayeh id: '78614' last_name: Sadeghi-Kohan - first_name: Zainalabedin full_name: Navabi, Zainalabedin last_name: Navabi citation: ama: 'Rezaeizadeh Rookerd R, Sadeghi-Kohan S, Navabi Z. Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture. In: Proceedings of the 2018 on Great Lakes Symposium on VLSI. ACM; 2018. doi:10.1145/3194554.3194599' apa: Rezaeizadeh Rookerd, R., Sadeghi-Kohan, S., & Navabi, Z. (2018). Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture. Proceedings of the 2018 on Great Lakes Symposium on VLSI. https://doi.org/10.1145/3194554.3194599 bibtex: '@inproceedings{Rezaeizadeh Rookerd_Sadeghi-Kohan_Navabi_2018, title={Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture}, DOI={10.1145/3194554.3194599}, booktitle={Proceedings of the 2018 on Great Lakes Symposium on VLSI}, publisher={ACM}, author={Rezaeizadeh Rookerd, Ramin and Sadeghi-Kohan, Somayeh and Navabi, Zainalabedin}, year={2018} }' chicago: Rezaeizadeh Rookerd, Ramin, Somayeh Sadeghi-Kohan, and Zainalabedin Navabi. “Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture.” In Proceedings of the 2018 on Great Lakes Symposium on VLSI. ACM, 2018. https://doi.org/10.1145/3194554.3194599. ieee: 'R. Rezaeizadeh Rookerd, S. Sadeghi-Kohan, and Z. Navabi, “Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture,” 2018, doi: 10.1145/3194554.3194599.' mla: Rezaeizadeh Rookerd, Ramin, et al. “Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture.” Proceedings of the 2018 on Great Lakes Symposium on VLSI, ACM, 2018, doi:10.1145/3194554.3194599. short: 'R. Rezaeizadeh Rookerd, S. Sadeghi-Kohan, Z. Navabi, in: Proceedings of the 2018 on Great Lakes Symposium on VLSI, ACM, 2018.' date_created: 2022-01-19T13:42:27Z date_updated: 2022-01-19T13:44:17Z department: - _id: '48' doi: 10.1145/3194554.3194599 language: - iso: eng publication: Proceedings of the 2018 on Great Lakes Symposium on VLSI publication_status: published publisher: ACM status: public title: Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture type: conference user_id: '78614' year: '2018' ... --- _id: '4575' author: - first_name: Alexander full_name: Sprenger, Alexander id: '22707' last_name: Sprenger - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: 'Sprenger A, Hellebrand S. Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. In: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE; 2018. doi:10.1109/ddecs.2018.00020' apa: Sprenger, A., & Hellebrand, S. (2018). Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). https://doi.org/10.1109/ddecs.2018.00020 bibtex: '@inproceedings{Sprenger_Hellebrand_2018, place={Budapest, Hungary}, title={Tuning Stochastic Space Compaction to Faster-than-at-Speed Test}, DOI={10.1109/ddecs.2018.00020}, booktitle={2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)}, publisher={IEEE}, author={Sprenger, Alexander and Hellebrand, Sybille}, year={2018} }' chicago: 'Sprenger, Alexander, and Sybille Hellebrand. “Tuning Stochastic Space Compaction to Faster-than-at-Speed Test.” In 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Budapest, Hungary: IEEE, 2018. https://doi.org/10.1109/ddecs.2018.00020.' ieee: 'A. Sprenger and S. Hellebrand, “Tuning Stochastic Space Compaction to Faster-than-at-Speed Test,” 2018, doi: 10.1109/ddecs.2018.00020.' mla: Sprenger, Alexander, and Sybille Hellebrand. “Tuning Stochastic Space Compaction to Faster-than-at-Speed Test.” 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, 2018, doi:10.1109/ddecs.2018.00020. short: 'A. Sprenger, S. Hellebrand, in: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, Budapest, Hungary, 2018.' date_created: 2018-10-02T12:18:46Z date_updated: 2022-05-11T17:10:37Z department: - _id: '48' doi: 10.1109/ddecs.2018.00020 language: - iso: eng place: Budapest, Hungary project: - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) publication_identifier: isbn: - '9781538657546' publication_status: published publisher: IEEE status: public title: Tuning Stochastic Space Compaction to Faster-than-at-Speed Test type: conference user_id: '209' year: '2018' ... --- _id: '10575' author: - first_name: Chang full_name: Liu, Chang last_name: Liu - first_name: Eric full_name: Schneider, Eric last_name: Schneider - first_name: Matthias full_name: Kampmann, Matthias id: '10935' last_name: Kampmann - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich citation: ama: 'Liu C, Schneider E, Kampmann M, Hellebrand S, Wunderlich H-J. Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. In: 27th IEEE Asian Test Symposium (ATS’18). ; 2018. doi:10.1109/ats.2018.00028' apa: Liu, C., Schneider, E., Kampmann, M., Hellebrand, S., & Wunderlich, H.-J. (2018). Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. 27th IEEE Asian Test Symposium (ATS’18). https://doi.org/10.1109/ats.2018.00028 bibtex: '@inproceedings{Liu_Schneider_Kampmann_Hellebrand_Wunderlich_2018, title={Extending Aging Monitors for Early Life and Wear-Out Failure Prevention}, DOI={10.1109/ats.2018.00028}, booktitle={27th IEEE Asian Test Symposium (ATS’18)}, author={Liu, Chang and Schneider, Eric and Kampmann, Matthias and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2018} }' chicago: Liu, Chang, Eric Schneider, Matthias Kampmann, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Extending Aging Monitors for Early Life and Wear-Out Failure Prevention.” In 27th IEEE Asian Test Symposium (ATS’18), 2018. https://doi.org/10.1109/ats.2018.00028. ieee: 'C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, and H.-J. Wunderlich, “Extending Aging Monitors for Early Life and Wear-Out Failure Prevention,” 2018, doi: 10.1109/ats.2018.00028.' mla: Liu, Chang, et al. “Extending Aging Monitors for Early Life and Wear-Out Failure Prevention.” 27th IEEE Asian Test Symposium (ATS’18), 2018, doi:10.1109/ats.2018.00028. short: 'C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, H.-J. Wunderlich, in: 27th IEEE Asian Test Symposium (ATS’18), 2018.' date_created: 2019-07-05T08:14:58Z date_updated: 2022-05-11T17:11:53Z department: - _id: '48' doi: 10.1109/ats.2018.00028 language: - iso: eng publication: 27th IEEE Asian Test Symposium (ATS'18) publication_identifier: isbn: - '9781538694664' publication_status: published status: public title: Extending Aging Monitors for Early Life and Wear-Out Failure Prevention type: conference user_id: '209' year: '2018' ... --- _id: '29459' abstract: - lang: eng text: Transistor and interconnect wearout is accelerated with transistor scaling resulting in timing variations and consequently reliability challenges in digital circuits. With the emergence of new issues like Electro-migration these problems are getting more crucial. Age monitoring methods can be used to predict and deal with the aging problem. Selecting appropriate locations for placement of aging monitors is an important issue. In this work we propose a procedure for selection of appropriate internal nodes that expose smaller overheads to the circuit, using correlation between nodes and the shareability amongst them. To select internal nodes, we first prune some nodes based on some attributes and thus provide a near-optimal solution that can effectively get a number of internal nodes and consider the effects of electro-migration as well. We have applied our proposed scheme to several processors and ITC benchmarks and have looked at its effectiveness for these circuits. author: - first_name: Somayeh full_name: Sadeghi-Kohan, Somayeh id: '78614' last_name: Sadeghi-Kohan orcid: https://orcid.org/0000-0001-7246-0610 - first_name: Arash full_name: Vafaei, Arash last_name: Vafaei - first_name: Zainalabedin full_name: Navabi, Zainalabedin last_name: Navabi citation: ama: 'Sadeghi-Kohan S, Vafaei A, Navabi Z. Near-Optimal Node Selection Procedure for Aging Monitor Placement. In: 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS). IEEE; 2018. doi:10.1109/iolts.2018.8474120' apa: Sadeghi-Kohan, S., Vafaei, A., & Navabi, Z. (2018). Near-Optimal Node Selection Procedure for Aging Monitor Placement. 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS). https://doi.org/10.1109/iolts.2018.8474120 bibtex: '@inproceedings{Sadeghi-Kohan_Vafaei_Navabi_2018, title={Near-Optimal Node Selection Procedure for Aging Monitor Placement}, DOI={10.1109/iolts.2018.8474120}, booktitle={2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Vafaei, Arash and Navabi, Zainalabedin}, year={2018} }' chicago: Sadeghi-Kohan, Somayeh, Arash Vafaei, and Zainalabedin Navabi. “Near-Optimal Node Selection Procedure for Aging Monitor Placement.” In 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS). IEEE, 2018. https://doi.org/10.1109/iolts.2018.8474120. ieee: 'S. Sadeghi-Kohan, A. Vafaei, and Z. Navabi, “Near-Optimal Node Selection Procedure for Aging Monitor Placement,” 2018, doi: 10.1109/iolts.2018.8474120.' mla: Sadeghi-Kohan, Somayeh, et al. “Near-Optimal Node Selection Procedure for Aging Monitor Placement.” 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), IEEE, 2018, doi:10.1109/iolts.2018.8474120. short: 'S. Sadeghi-Kohan, A. Vafaei, Z. Navabi, in: 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), IEEE, 2018.' date_created: 2022-01-19T13:35:37Z date_updated: 2023-08-02T11:36:15Z department: - _id: '48' doi: 10.1109/iolts.2018.8474120 extern: '1' language: - iso: eng publication: 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) publication_status: published publisher: IEEE status: public title: Near-Optimal Node Selection Procedure for Aging Monitor Placement type: conference user_id: '78614' year: '2018' ... --- _id: '12973' author: - first_name: Jyotirmoy full_name: Deshmukh, Jyotirmoy last_name: Deshmukh - first_name: Wolfgang full_name: Kunz, Wolfgang last_name: Kunz - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: 'Deshmukh J, Kunz W, Wunderlich H-J, Hellebrand S. Special Session on Early Life Failures. In: 35th IEEE VLSI Test Symposium (VTS’17). Caesars Palace, Las Vegas, Nevada, USA: IEEE; 2017. doi:10.1109/vts.2017.7928933' apa: 'Deshmukh, J., Kunz, W., Wunderlich, H.-J., & Hellebrand, S. (2017). Special Session on Early Life Failures. In 35th IEEE VLSI Test Symposium (VTS’17). Caesars Palace, Las Vegas, Nevada, USA: IEEE. https://doi.org/10.1109/vts.2017.7928933' bibtex: '@inproceedings{Deshmukh_Kunz_Wunderlich_Hellebrand_2017, place={Caesars Palace, Las Vegas, Nevada, USA}, title={Special Session on Early Life Failures}, DOI={10.1109/vts.2017.7928933}, booktitle={35th IEEE VLSI Test Symposium (VTS’17)}, publisher={IEEE}, author={Deshmukh, Jyotirmoy and Kunz, Wolfgang and Wunderlich, Hans-Joachim and Hellebrand, Sybille}, year={2017} }' chicago: 'Deshmukh, Jyotirmoy, Wolfgang Kunz, Hans-Joachim Wunderlich, and Sybille Hellebrand. “Special Session on Early Life Failures.” In 35th IEEE VLSI Test Symposium (VTS’17). Caesars Palace, Las Vegas, Nevada, USA: IEEE, 2017. https://doi.org/10.1109/vts.2017.7928933.' ieee: J. Deshmukh, W. Kunz, H.-J. Wunderlich, and S. Hellebrand, “Special Session on Early Life Failures,” in 35th IEEE VLSI Test Symposium (VTS’17), 2017. mla: Deshmukh, Jyotirmoy, et al. “Special Session on Early Life Failures.” 35th IEEE VLSI Test Symposium (VTS’17), IEEE, 2017, doi:10.1109/vts.2017.7928933. short: 'J. Deshmukh, W. Kunz, H.-J. Wunderlich, S. Hellebrand, in: 35th IEEE VLSI Test Symposium (VTS’17), IEEE, Caesars Palace, Las Vegas, Nevada, USA, 2017.' date_created: 2019-08-28T08:37:58Z date_updated: 2022-01-06T06:51:27Z department: - _id: '48' doi: 10.1109/vts.2017.7928933 language: - iso: eng place: Caesars Palace, Las Vegas, Nevada, USA publication: 35th IEEE VLSI Test Symposium (VTS'17) publisher: IEEE status: public title: Special Session on Early Life Failures type: conference user_id: '209' year: '2017' ... --- _id: '13078' author: - first_name: Matthias full_name: Kampmann, Matthias id: '10935' last_name: Kampmann - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: Kampmann M, Hellebrand S. X-Tolerante Prüfzellengruppierung Für Den Test Mit Erhöhter Betriebsfrequenz.; 2017. apa: Kampmann, M., & Hellebrand, S. (2017). X-tolerante Prüfzellengruppierung für den Test mit erhöhter Betriebsfrequenz. bibtex: '@book{Kampmann_Hellebrand_2017, place={29. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’17), Lübeck, Germany}, title={X-tolerante Prüfzellengruppierung für den Test mit erhöhter Betriebsfrequenz}, author={Kampmann, Matthias and Hellebrand, Sybille}, year={2017} }' chicago: Kampmann, Matthias, and Sybille Hellebrand. X-Tolerante Prüfzellengruppierung Für Den Test Mit Erhöhter Betriebsfrequenz. 29. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’17), Lübeck, Germany, 2017. ieee: M. Kampmann and S. Hellebrand, X-tolerante Prüfzellengruppierung für den Test mit erhöhter Betriebsfrequenz. 29. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’17), Lübeck, Germany, 2017. mla: Kampmann, Matthias, and Sybille Hellebrand. X-Tolerante Prüfzellengruppierung Für Den Test Mit Erhöhter Betriebsfrequenz. 2017. short: M. Kampmann, S. Hellebrand, X-Tolerante Prüfzellengruppierung Für Den Test Mit Erhöhter Betriebsfrequenz, 29. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’17), Lübeck, Germany, 2017. date_created: 2019-08-28T12:06:26Z date_updated: 2022-05-11T16:17:41Z department: - _id: '48' keyword: - WORKSHOP language: - iso: eng place: 29. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'17), Lübeck, Germany status: public title: X-tolerante Prüfzellengruppierung für den Test mit erhöhter Betriebsfrequenz type: misc user_id: '209' year: '2017' ... --- _id: '10576' author: - first_name: Matthias full_name: Kampmann, Matthias id: '10935' last_name: Kampmann - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: 'Kampmann M, Hellebrand S. Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test. In: 20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17). IEEE; 2017. doi:10.1109/ddecs.2017.7934564' apa: 'Kampmann, M., & Hellebrand, S. (2017). Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test. 20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17). https://doi.org/10.1109/ddecs.2017.7934564' bibtex: '@inproceedings{Kampmann_Hellebrand_2017, title={Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test}, DOI={10.1109/ddecs.2017.7934564}, booktitle={20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17)}, publisher={IEEE}, author={Kampmann, Matthias and Hellebrand, Sybille}, year={2017} }' chicago: 'Kampmann, Matthias, and Sybille Hellebrand. “Design-for-FAST: Supporting X-Tolerant Compaction during Faster-than-at-Speed Test.” In 20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17). IEEE, 2017. https://doi.org/10.1109/ddecs.2017.7934564.' ieee: 'M. Kampmann and S. Hellebrand, “Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test,” 2017, doi: 10.1109/ddecs.2017.7934564.' mla: 'Kampmann, Matthias, and Sybille Hellebrand. “Design-for-FAST: Supporting X-Tolerant Compaction during Faster-than-at-Speed Test.” 20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17), IEEE, 2017, doi:10.1109/ddecs.2017.7934564.' short: 'M. Kampmann, S. Hellebrand, in: 20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17), IEEE, 2017.' date_created: 2019-07-05T08:23:56Z date_updated: 2022-05-11T17:14:51Z department: - _id: '48' doi: 10.1109/ddecs.2017.7934564 language: - iso: eng publication: 20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS'17) publication_identifier: isbn: - '9781538604724' publication_status: published publisher: IEEE status: public title: 'Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test' type: conference user_id: '209' year: '2017' ... --- _id: '29462' abstract: - lang: eng text: Time-variant age information of different parts of a system can be used for system-level performance improvement through high-level task scheduling, thus extending the life-time of the system. Progressive age information should provide the age state that the system is in, and the rate that it is being aged at. In this paper, we propose a structure that monitors certain paths of a circuit and detects its gradual age growth, and provides the aging rate and aging state of the circuit. The proposed monitors are placed on a selected set of nodes that represent a timing bottleneck of the system. These monitors sample expected data on these nodes, and compare them with the expected values. The timing of sampling changes as the circuit ages and its delay increases. The timing of sampling will provide a measure of aging advancement of a circuit. To assess the efficacy of the proposed method and compare it with other state-of-the-art aging monitors, we use them on selected nodes of the execution unit of different processors, as well as some circuits from ITC99 benchmarks. The results reveal that the precision of our proposed method is between 0.12 (ns) to 0.401 (ns). Its Area and power overhead are negligible and are about 2.13 and 0.69 percent respectively. author: - first_name: Somayeh full_name: Sadeghi-Kohan, Somayeh id: '78614' last_name: Sadeghi-Kohan orcid: https://orcid.org/0000-0001-7246-0610 - first_name: Mehdi full_name: Kamal, Mehdi last_name: Kamal - first_name: Zainalabedin full_name: Navabi, Zainalabedin last_name: Navabi citation: ama: Sadeghi-Kohan S, Kamal M, Navabi Z. Self-Adjusting Monitor for Measuring Aging Rate and Advancement. IEEE Transactions on Emerging Topics in Computing. 2017;8(3):627-641. doi:10.1109/tetc.2017.2771441 apa: Sadeghi-Kohan, S., Kamal, M., & Navabi, Z. (2017). Self-Adjusting Monitor for Measuring Aging Rate and Advancement. IEEE Transactions on Emerging Topics in Computing, 8(3), 627–641. https://doi.org/10.1109/tetc.2017.2771441 bibtex: '@article{Sadeghi-Kohan_Kamal_Navabi_2017, title={Self-Adjusting Monitor for Measuring Aging Rate and Advancement}, volume={8}, DOI={10.1109/tetc.2017.2771441}, number={3}, journal={IEEE Transactions on Emerging Topics in Computing}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Sadeghi-Kohan, Somayeh and Kamal, Mehdi and Navabi, Zainalabedin}, year={2017}, pages={627–641} }' chicago: 'Sadeghi-Kohan, Somayeh, Mehdi Kamal, and Zainalabedin Navabi. “Self-Adjusting Monitor for Measuring Aging Rate and Advancement.” IEEE Transactions on Emerging Topics in Computing 8, no. 3 (2017): 627–41. https://doi.org/10.1109/tetc.2017.2771441.' ieee: 'S. Sadeghi-Kohan, M. Kamal, and Z. Navabi, “Self-Adjusting Monitor for Measuring Aging Rate and Advancement,” IEEE Transactions on Emerging Topics in Computing, vol. 8, no. 3, pp. 627–641, 2017, doi: 10.1109/tetc.2017.2771441.' mla: Sadeghi-Kohan, Somayeh, et al. “Self-Adjusting Monitor for Measuring Aging Rate and Advancement.” IEEE Transactions on Emerging Topics in Computing, vol. 8, no. 3, Institute of Electrical and Electronics Engineers (IEEE), 2017, pp. 627–41, doi:10.1109/tetc.2017.2771441. short: S. Sadeghi-Kohan, M. Kamal, Z. Navabi, IEEE Transactions on Emerging Topics in Computing 8 (2017) 627–641. date_created: 2022-01-19T13:45:51Z date_updated: 2023-08-02T11:36:30Z department: - _id: '48' doi: 10.1109/tetc.2017.2771441 extern: '1' intvolume: ' 8' issue: '3' keyword: - Age advancement - age monitoring clock - aging rate - self-adjusting monitors language: - iso: eng page: 627-641 publication: IEEE Transactions on Emerging Topics in Computing publication_identifier: issn: - 2168-6750 - 2376-4562 publication_status: published publisher: Institute of Electrical and Electronics Engineers (IEEE) status: public title: Self-Adjusting Monitor for Measuring Aging Rate and Advancement type: journal_article user_id: '78614' volume: 8 year: '2017' ... --- _id: '29463' abstract: - lang: eng text: In this paper we propose to think out of the box and discuss an approach for universal mitigation of Negative Bias Temperature Instability (NBTI) induced aging untied from the limitations of its modelling. The cost-effective approach exploits a simple property of a randomized design, i.e., the equalized signal probability and switching activity at gate inputs. The techniques considered for structural design randomization involve both the hardware architecture and embedded software layers. Ultimately, the proposed approach aims at extending the reliable lifetime of nanoelectronic systems. author: - first_name: Maksim full_name: Jenihhin, Maksim last_name: Jenihhin - first_name: Alexander full_name: Kamkin, Alexander last_name: Kamkin - first_name: Zainalabedin full_name: Navabi, Zainalabedin last_name: Navabi - first_name: Somayeh full_name: Sadeghi-Kohan, Somayeh id: '78614' last_name: Sadeghi-Kohan orcid: https://orcid.org/0000-0001-7246-0610 citation: ama: 'Jenihhin M, Kamkin A, Navabi Z, Sadeghi-Kohan S. Universal mitigation of NBTI-induced aging by design randomization. In: 2016 IEEE East-West Design & Test Symposium (EWDTS). IEEE; 2017. doi:10.1109/ewdts.2016.7807635' apa: Jenihhin, M., Kamkin, A., Navabi, Z., & Sadeghi-Kohan, S. (2017). Universal mitigation of NBTI-induced aging by design randomization. 2016 IEEE East-West Design & Test Symposium (EWDTS). https://doi.org/10.1109/ewdts.2016.7807635 bibtex: '@inproceedings{Jenihhin_Kamkin_Navabi_Sadeghi-Kohan_2017, title={Universal mitigation of NBTI-induced aging by design randomization}, DOI={10.1109/ewdts.2016.7807635}, booktitle={2016 IEEE East-West Design & Test Symposium (EWDTS)}, publisher={IEEE}, author={Jenihhin, Maksim and Kamkin, Alexander and Navabi, Zainalabedin and Sadeghi-Kohan, Somayeh}, year={2017} }' chicago: Jenihhin, Maksim, Alexander Kamkin, Zainalabedin Navabi, and Somayeh Sadeghi-Kohan. “Universal Mitigation of NBTI-Induced Aging by Design Randomization.” In 2016 IEEE East-West Design & Test Symposium (EWDTS). IEEE, 2017. https://doi.org/10.1109/ewdts.2016.7807635. ieee: 'M. Jenihhin, A. Kamkin, Z. Navabi, and S. Sadeghi-Kohan, “Universal mitigation of NBTI-induced aging by design randomization,” 2017, doi: 10.1109/ewdts.2016.7807635.' mla: Jenihhin, Maksim, et al. “Universal Mitigation of NBTI-Induced Aging by Design Randomization.” 2016 IEEE East-West Design & Test Symposium (EWDTS), IEEE, 2017, doi:10.1109/ewdts.2016.7807635. short: 'M. Jenihhin, A. Kamkin, Z. Navabi, S. Sadeghi-Kohan, in: 2016 IEEE East-West Design & Test Symposium (EWDTS), IEEE, 2017.' date_created: 2022-01-19T13:50:13Z date_updated: 2023-08-02T11:36:43Z department: - _id: '48' doi: 10.1109/ewdts.2016.7807635 extern: '1' language: - iso: eng publication: 2016 IEEE East-West Design & Test Symposium (EWDTS) publication_status: published publisher: IEEE status: public title: Universal mitigation of NBTI-induced aging by design randomization type: conference user_id: '78614' year: '2017' ... --- _id: '12975' author: - first_name: Matthias full_name: Kampmann, Matthias id: '10935' last_name: Kampmann - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: 'Kampmann M, Hellebrand S. X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test. In: 25th IEEE Asian Test Symposium (ATS’16). Hiroshima, Japan: IEEE; 2016:1-6. doi:10.1109/ats.2016.20' apa: 'Kampmann, M., & Hellebrand, S. (2016). X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test. In 25th IEEE Asian Test Symposium (ATS’16) (pp. 1–6). Hiroshima, Japan: IEEE. https://doi.org/10.1109/ats.2016.20' bibtex: '@inproceedings{Kampmann_Hellebrand_2016, place={Hiroshima, Japan}, title={X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test}, DOI={10.1109/ats.2016.20}, booktitle={25th IEEE Asian Test Symposium (ATS’16)}, publisher={IEEE}, author={Kampmann, Matthias and Hellebrand, Sybille}, year={2016}, pages={1–6} }' chicago: 'Kampmann, Matthias, and Sybille Hellebrand. “X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test.” In 25th IEEE Asian Test Symposium (ATS’16), 1–6. Hiroshima, Japan: IEEE, 2016. https://doi.org/10.1109/ats.2016.20.' ieee: 'M. Kampmann and S. Hellebrand, “X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test,” in 25th IEEE Asian Test Symposium (ATS’16), 2016, pp. 1–6.' mla: 'Kampmann, Matthias, and Sybille Hellebrand. “X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test.” 25th IEEE Asian Test Symposium (ATS’16), IEEE, 2016, pp. 1–6, doi:10.1109/ats.2016.20.' short: 'M. Kampmann, S. Hellebrand, in: 25th IEEE Asian Test Symposium (ATS’16), IEEE, Hiroshima, Japan, 2016, pp. 1–6.' date_created: 2019-08-28T08:53:04Z date_updated: 2022-01-06T06:51:27Z department: - _id: '48' doi: 10.1109/ats.2016.20 language: - iso: eng page: 1-6 place: Hiroshima, Japan publication: 25th IEEE Asian Test Symposium (ATS'16) publisher: IEEE status: public title: 'X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test' type: conference user_id: '209' year: '2016' ... --- _id: '12976' author: - first_name: Matthias full_name: Kampmann, Matthias id: '10935' last_name: Kampmann - first_name: Michael full_name: A. Kochte, Michael last_name: A. Kochte - first_name: Eric full_name: Schneider, Eric last_name: Schneider - first_name: Thomas full_name: Indlekofer, Thomas last_name: Indlekofer - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich citation: ama: 'Kampmann M, A. Kochte M, Schneider E, Indlekofer T, Hellebrand S, Wunderlich H-J. Optimized Selection of Frequencies for Faster-Than-at-Speed Test. In: 24th IEEE Asian Test Symposium (ATS’15). Mumbai, India: IEEE; 2015:109-114. doi:10.1109/ats.2015.26' apa: 'Kampmann, M., A. Kochte, M., Schneider, E., Indlekofer, T., Hellebrand, S., & Wunderlich, H.-J. (2015). Optimized Selection of Frequencies for Faster-Than-at-Speed Test. In 24th IEEE Asian Test Symposium (ATS’15) (pp. 109–114). Mumbai, India: IEEE. https://doi.org/10.1109/ats.2015.26' bibtex: '@inproceedings{Kampmann_A. Kochte_Schneider_Indlekofer_Hellebrand_Wunderlich_2015, place={Mumbai, India}, title={Optimized Selection of Frequencies for Faster-Than-at-Speed Test}, DOI={10.1109/ats.2015.26}, booktitle={24th IEEE Asian Test Symposium (ATS’15)}, publisher={IEEE}, author={Kampmann, Matthias and A. Kochte, Michael and Schneider, Eric and Indlekofer, Thomas and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2015}, pages={109–114} }' chicago: 'Kampmann, Matthias, Michael A. Kochte, Eric Schneider, Thomas Indlekofer, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Optimized Selection of Frequencies for Faster-Than-at-Speed Test.” In 24th IEEE Asian Test Symposium (ATS’15), 109–14. Mumbai, India: IEEE, 2015. https://doi.org/10.1109/ats.2015.26.' ieee: M. Kampmann, M. A. Kochte, E. Schneider, T. Indlekofer, S. Hellebrand, and H.-J. Wunderlich, “Optimized Selection of Frequencies for Faster-Than-at-Speed Test,” in 24th IEEE Asian Test Symposium (ATS’15), 2015, pp. 109–114. mla: Kampmann, Matthias, et al. “Optimized Selection of Frequencies for Faster-Than-at-Speed Test.” 24th IEEE Asian Test Symposium (ATS’15), IEEE, 2015, pp. 109–14, doi:10.1109/ats.2015.26. short: 'M. Kampmann, M. A. Kochte, E. Schneider, T. Indlekofer, S. Hellebrand, H.-J. Wunderlich, in: 24th IEEE Asian Test Symposium (ATS’15), IEEE, Mumbai, India, 2015, pp. 109–114.' date_created: 2019-08-28T09:03:08Z date_updated: 2022-01-06T06:51:27Z department: - _id: '48' doi: 10.1109/ats.2015.26 language: - iso: eng page: 109-114 place: Mumbai, India publication: 24th IEEE Asian Test Symposium (ATS'15) publisher: IEEE status: public title: Optimized Selection of Frequencies for Faster-Than-at-Speed Test type: conference user_id: '209' year: '2015' ... --- _id: '13056' author: - first_name: Zhengfeng full_name: Huang, Zhengfeng last_name: Huang - first_name: Huaguo full_name: Liang, Huaguo last_name: Liang - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: Huang Z, Liang H, Hellebrand S. A High Performance SEU Tolerant Latch. Journal of Electronic Testing - Theory and Applications (JETTA). 2015;31(4):349-359. apa: Huang, Z., Liang, H., & Hellebrand, S. (2015). A High Performance SEU Tolerant Latch. Journal of Electronic Testing - Theory and Applications (JETTA), 31(4), 349–359. bibtex: '@article{Huang_Liang_Hellebrand_2015, title={A High Performance SEU Tolerant Latch}, volume={31}, number={4}, journal={Journal of Electronic Testing - Theory and Applications (JETTA)}, publisher={Springer}, author={Huang, Zhengfeng and Liang, Huaguo and Hellebrand, Sybille}, year={2015}, pages={349–359} }' chicago: 'Huang, Zhengfeng, Huaguo Liang, and Sybille Hellebrand. “A High Performance SEU Tolerant Latch.” Journal of Electronic Testing - Theory and Applications (JETTA) 31, no. 4 (2015): 349–59.' ieee: Z. Huang, H. Liang, and S. Hellebrand, “A High Performance SEU Tolerant Latch,” Journal of Electronic Testing - Theory and Applications (JETTA), vol. 31, no. 4, pp. 349–359, 2015. mla: Huang, Zhengfeng, et al. “A High Performance SEU Tolerant Latch.” Journal of Electronic Testing - Theory and Applications (JETTA), vol. 31, no. 4, Springer, 2015, pp. 349–59. short: Z. Huang, H. Liang, S. Hellebrand, Journal of Electronic Testing - Theory and Applications (JETTA) 31 (2015) 349–359. date_created: 2019-08-28T11:48:55Z date_updated: 2022-01-06T06:51:27Z department: - _id: '48' intvolume: ' 31' issue: '4' language: - iso: eng page: 349-359 publication: Journal of Electronic Testing - Theory and Applications (JETTA) publisher: Springer status: public title: A High Performance SEU Tolerant Latch type: journal_article user_id: '209' volume: 31 year: '2015' ... --- _id: '13077' author: - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Thomas full_name: Indlekofer, Thomas last_name: Indlekofer - first_name: Matthias full_name: Kampmann, Matthias id: '10935' last_name: Kampmann - first_name: Michael full_name: Kochte, Michael last_name: Kochte - first_name: Chang full_name: Liu, Chang last_name: Liu - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich citation: ama: Hellebrand S, Indlekofer T, Kampmann M, Kochte M, Liu C, Wunderlich H-J. Effiziente Auswahl von Testfrequenzen Für Den Test Kleiner Verzögerungsfehler. 27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany; 2015. apa: Hellebrand, S., Indlekofer, T., Kampmann, M., Kochte, M., Liu, C., & Wunderlich, H.-J. (2015). Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler. 27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany. bibtex: '@book{Hellebrand_Indlekofer_Kampmann_Kochte_Liu_Wunderlich_2015, place={27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany}, title={Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler}, author={Hellebrand, Sybille and Indlekofer, Thomas and Kampmann, Matthias and Kochte, Michael and Liu, Chang and Wunderlich, Hans-Joachim}, year={2015} }' chicago: Hellebrand, Sybille, Thomas Indlekofer, Matthias Kampmann, Michael Kochte, Chang Liu, and Hans-Joachim Wunderlich. Effiziente Auswahl von Testfrequenzen Für Den Test Kleiner Verzögerungsfehler. 27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany, 2015. ieee: S. Hellebrand, T. Indlekofer, M. Kampmann, M. Kochte, C. Liu, and H.-J. Wunderlich, Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler. 27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany, 2015. mla: Hellebrand, Sybille, et al. Effiziente Auswahl von Testfrequenzen Für Den Test Kleiner Verzögerungsfehler. 2015. short: S. Hellebrand, T. Indlekofer, M. Kampmann, M. Kochte, C. Liu, H.-J. Wunderlich, Effiziente Auswahl von Testfrequenzen Für Den Test Kleiner Verzögerungsfehler, 27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany, 2015. date_created: 2019-08-28T12:05:44Z date_updated: 2022-01-06T06:51:28Z department: - _id: '48' keyword: - Workshop language: - iso: eng place: 27. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'15), Bad Urach, Germany status: public title: Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler type: misc user_id: '659' year: '2015' ... --- _id: '29465' abstract: - lang: eng text: Transistor and interconnect wearout is accelerated with transistor scaling resulting in timing variations and consequently reliability challenges in digital circuits. Age monitoring methods can be used to predict and deal with the aging problem. Selecting appropriate locations for placement of hardware aging monitors is an important issue. In this work we propose a procedure for selection of appropriate internal nodes in combinational clouds between pipeline stages or combinational parts of a sequential circuit to place hardware monitors that can effectively provide aging information of various components of a modern digital system. In order to implement the node selection procedure, we propose an object-oriented model. Object-oriented model of a circuit along with a probabilistic and logical simulation engine that we have developed can effectively be used for implementation and also fast evaluation of the proposed node selection mechanism. The proposed object-oriented C+ + models can be integrated into a SystemC RTL model making it possible to perform mixed-level simulation, and integrated evaluation of a complete system. We have applied our proposed scheme to several processors including MIPS, ARM, ALPHA and MiniRISC and have looked at its effectiveness for these processors. author: - first_name: Somayeh full_name: Sadeghi-Kohan, Somayeh id: '78614' last_name: Sadeghi-Kohan orcid: https://orcid.org/0000-0001-7246-0610 - first_name: Arezoo full_name: Kamran, Arezoo last_name: Kamran - first_name: Farnaz full_name: Forooghifar, Farnaz last_name: Forooghifar - first_name: Zainalabedin full_name: Navabi, Zainalabedin last_name: Navabi citation: ama: 'Sadeghi-Kohan S, Kamran A, Forooghifar F, Navabi Z. Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation. In: 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). IEEE; 2015. doi:10.1109/dtis.2015.7127373' apa: 'Sadeghi-Kohan, S., Kamran, A., Forooghifar, F., & Navabi, Z. (2015). Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation. 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). https://doi.org/10.1109/dtis.2015.7127373' bibtex: '@inproceedings{Sadeghi-Kohan_Kamran_Forooghifar_Navabi_2015, title={Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation}, DOI={10.1109/dtis.2015.7127373}, booktitle={2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Kamran, Arezoo and Forooghifar, Farnaz and Navabi, Zainalabedin}, year={2015} }' chicago: 'Sadeghi-Kohan, Somayeh, Arezoo Kamran, Farnaz Forooghifar, and Zainalabedin Navabi. “Aging in Digital Circuits and Age Monitoring: Object-Oriented Modeling and Evaluation.” In 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). IEEE, 2015. https://doi.org/10.1109/dtis.2015.7127373.' ieee: 'S. Sadeghi-Kohan, A. Kamran, F. Forooghifar, and Z. Navabi, “Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation,” 2015, doi: 10.1109/dtis.2015.7127373.' mla: 'Sadeghi-Kohan, Somayeh, et al. “Aging in Digital Circuits and Age Monitoring: Object-Oriented Modeling and Evaluation.” 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE, 2015, doi:10.1109/dtis.2015.7127373.' short: 'S. Sadeghi-Kohan, A. Kamran, F. Forooghifar, Z. Navabi, in: 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE, 2015.' date_created: 2022-01-19T13:51:35Z date_updated: 2023-08-02T11:35:56Z department: - _id: '48' doi: 10.1109/dtis.2015.7127373 extern: '1' language: - iso: eng publication: 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) publication_status: published publisher: IEEE status: public title: 'Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation' type: conference user_id: '78614' year: '2015' ... --- _id: '29466' abstract: - lang: eng text: Transistor and interconnect wearout is accelerated with transistor scaling that results in timing variations. Progressive age measurement of a circuit can help a better prevention mechanism for reducing more aging. This requires age monitors that collect progressive age information of the circuit. This paper focuses on monitor structures for implementation of progressive age detection. The monitors are self-adjusting that they adjust themselves to detect progressive changes in the timing of a circuit. Furthermore, the monitors are designed for low hardware overhead, and certainty in reported timing changes. author: - first_name: Somayeh full_name: Sadeghi-Kohan, Somayeh id: '78614' last_name: Sadeghi-Kohan orcid: https://orcid.org/0000-0001-7246-0610 - first_name: Mehdi full_name: Kamal, Mehdi last_name: Kamal - first_name: John full_name: McNeil, John last_name: McNeil - first_name: Paolo full_name: Prinetto, Paolo last_name: Prinetto - first_name: Zain full_name: Navabi, Zain last_name: Navabi citation: ama: 'Sadeghi-Kohan S, Kamal M, McNeil J, Prinetto P, Navabi Z. Online self adjusting progressive age monitoring of timing variations. In: 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). IEEE; 2015. doi:10.1109/dtis.2015.7127368' apa: Sadeghi-Kohan, S., Kamal, M., McNeil, J., Prinetto, P., & Navabi, Z. (2015). Online self adjusting progressive age monitoring of timing variations. 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). https://doi.org/10.1109/dtis.2015.7127368 bibtex: '@inproceedings{Sadeghi-Kohan_Kamal_McNeil_Prinetto_Navabi_2015, title={Online self adjusting progressive age monitoring of timing variations}, DOI={10.1109/dtis.2015.7127368}, booktitle={2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Kamal, Mehdi and McNeil, John and Prinetto, Paolo and Navabi, Zain}, year={2015} }' chicago: Sadeghi-Kohan, Somayeh, Mehdi Kamal, John McNeil, Paolo Prinetto, and Zain Navabi. “Online Self Adjusting Progressive Age Monitoring of Timing Variations.” In 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). IEEE, 2015. https://doi.org/10.1109/dtis.2015.7127368. ieee: 'S. Sadeghi-Kohan, M. Kamal, J. McNeil, P. Prinetto, and Z. Navabi, “Online self adjusting progressive age monitoring of timing variations,” 2015, doi: 10.1109/dtis.2015.7127368.' mla: Sadeghi-Kohan, Somayeh, et al. “Online Self Adjusting Progressive Age Monitoring of Timing Variations.” 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE, 2015, doi:10.1109/dtis.2015.7127368. short: 'S. Sadeghi-Kohan, M. Kamal, J. McNeil, P. Prinetto, Z. Navabi, in: 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), IEEE, 2015.' date_created: 2022-01-19T13:52:32Z date_updated: 2023-08-02T11:36:58Z department: - _id: '48' doi: 10.1109/dtis.2015.7127368 extern: '1' language: - iso: eng publication: 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) publication_status: published publisher: IEEE status: public title: Online self adjusting progressive age monitoring of timing variations type: conference user_id: '78614' year: '2015' ... --- _id: '12977' author: - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Thomas full_name: Indlekofer, Thomas last_name: Indlekofer - first_name: Matthias full_name: Kampmann, Matthias id: '10935' last_name: Kampmann - first_name: Michael full_name: A. Kochte, Michael last_name: A. Kochte - first_name: Chang full_name: Liu, Chang last_name: Liu - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich citation: ama: 'Hellebrand S, Indlekofer T, Kampmann M, A. Kochte M, Liu C, Wunderlich H-J. FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects. In: IEEE International Test Conference (ITC’14). Seattle, Washington, USA: IEEE; 2014. doi:10.1109/test.2014.7035360' apa: 'Hellebrand, S., Indlekofer, T., Kampmann, M., A. Kochte, M., Liu, C., & Wunderlich, H.-J. (2014). FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects. In IEEE International Test Conference (ITC’14). Seattle, Washington, USA: IEEE. https://doi.org/10.1109/test.2014.7035360' bibtex: '@inproceedings{Hellebrand_Indlekofer_Kampmann_A. Kochte_Liu_Wunderlich_2014, place={Seattle, Washington, USA}, title={FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects}, DOI={10.1109/test.2014.7035360}, booktitle={IEEE International Test Conference (ITC’14)}, publisher={IEEE}, author={Hellebrand, Sybille and Indlekofer, Thomas and Kampmann, Matthias and A. Kochte, Michael and Liu, Chang and Wunderlich, Hans-Joachim}, year={2014} }' chicago: 'Hellebrand, Sybille, Thomas Indlekofer, Matthias Kampmann, Michael A. Kochte, Chang Liu, and Hans-Joachim Wunderlich. “FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects.” In IEEE International Test Conference (ITC’14). Seattle, Washington, USA: IEEE, 2014. https://doi.org/10.1109/test.2014.7035360.' ieee: 'S. Hellebrand, T. Indlekofer, M. Kampmann, M. A. Kochte, C. Liu, and H.-J. Wunderlich, “FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects,” in IEEE International Test Conference (ITC’14), 2014.' mla: 'Hellebrand, Sybille, et al. “FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects.” IEEE International Test Conference (ITC’14), IEEE, 2014, doi:10.1109/test.2014.7035360.' short: 'S. Hellebrand, T. Indlekofer, M. Kampmann, M. A. Kochte, C. Liu, H.-J. Wunderlich, in: IEEE International Test Conference (ITC’14), IEEE, Seattle, Washington, USA, 2014.' date_created: 2019-08-28T09:04:45Z date_updated: 2022-01-06T06:51:27Z department: - _id: '48' doi: 10.1109/test.2014.7035360 language: - iso: eng place: Seattle, Washington, USA publication: IEEE International Test Conference (ITC'14) publisher: IEEE status: public title: 'FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects' type: conference user_id: '209' year: '2014' ... --- _id: '13054' author: - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich citation: ama: Hellebrand S, Wunderlich H-J. SAT-Based ATPG beyond Stuck-at Fault Testing. DeGruyter Journal on Information Technology (it). 2014;56(4):165-172. apa: Hellebrand, S., & Wunderlich, H.-J. (2014). SAT-Based ATPG beyond Stuck-at Fault Testing. DeGruyter Journal on Information Technology (It), 56(4), 165–172. bibtex: '@article{Hellebrand_Wunderlich_2014, title={SAT-Based ATPG beyond Stuck-at Fault Testing}, volume={56}, number={4}, journal={DeGruyter Journal on Information Technology (it)}, publisher={DeGruyter}, author={Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2014}, pages={165–172} }' chicago: 'Hellebrand, Sybille, and Hans-Joachim Wunderlich. “SAT-Based ATPG beyond Stuck-at Fault Testing.” DeGruyter Journal on Information Technology (It) 56, no. 4 (2014): 165–72.' ieee: S. Hellebrand and H.-J. Wunderlich, “SAT-Based ATPG beyond Stuck-at Fault Testing,” DeGruyter Journal on Information Technology (it), vol. 56, no. 4, pp. 165–172, 2014. mla: Hellebrand, Sybille, and Hans-Joachim Wunderlich. “SAT-Based ATPG beyond Stuck-at Fault Testing.” DeGruyter Journal on Information Technology (It), vol. 56, no. 4, DeGruyter, 2014, pp. 165–72. short: S. Hellebrand, H.-J. Wunderlich, DeGruyter Journal on Information Technology (It) 56 (2014) 165–172. date_created: 2019-08-28T11:48:13Z date_updated: 2022-01-06T06:51:27Z department: - _id: '48' intvolume: ' 56' issue: '4' language: - iso: eng page: 165-172 publication: DeGruyter Journal on Information Technology (it) publisher: DeGruyter status: public title: SAT-Based ATPG beyond Stuck-at Fault Testing type: journal_article user_id: '209' volume: 56 year: '2014' ... --- _id: '13055' author: - first_name: Laura full_name: Rodriguez Gomez, Laura last_name: Rodriguez Gomez - first_name: Alejandro full_name: Cook, Alejandro last_name: Cook - first_name: Thomas full_name: Indlekofer, Thomas last_name: Indlekofer - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich citation: ama: Rodriguez Gomez L, Cook A, Indlekofer T, Hellebrand S, Wunderlich H-J. Adaptive Bayesian Diagnosis of Intermittent Faults. Journal of Electronic Testing - Theory and Applications (JETTA). 2014;30(5):527-540. apa: Rodriguez Gomez, L., Cook, A., Indlekofer, T., Hellebrand, S., & Wunderlich, H.-J. (2014). Adaptive Bayesian Diagnosis of Intermittent Faults. Journal of Electronic Testing - Theory and Applications (JETTA), 30(5), 527–540. bibtex: '@article{Rodriguez Gomez_Cook_Indlekofer_Hellebrand_Wunderlich_2014, title={Adaptive Bayesian Diagnosis of Intermittent Faults}, volume={30}, number={5}, journal={Journal of Electronic Testing - Theory and Applications (JETTA)}, publisher={Springer}, author={Rodriguez Gomez, Laura and Cook, Alejandro and Indlekofer, Thomas and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2014}, pages={527–540} }' chicago: 'Rodriguez Gomez, Laura, Alejandro Cook, Thomas Indlekofer, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Adaptive Bayesian Diagnosis of Intermittent Faults.” Journal of Electronic Testing - Theory and Applications (JETTA) 30, no. 5 (2014): 527–40.' ieee: L. Rodriguez Gomez, A. Cook, T. Indlekofer, S. Hellebrand, and H.-J. Wunderlich, “Adaptive Bayesian Diagnosis of Intermittent Faults,” Journal of Electronic Testing - Theory and Applications (JETTA), vol. 30, no. 5, pp. 527–540, 2014. mla: Rodriguez Gomez, Laura, et al. “Adaptive Bayesian Diagnosis of Intermittent Faults.” Journal of Electronic Testing - Theory and Applications (JETTA), vol. 30, no. 5, Springer, 2014, pp. 527–40. short: L. Rodriguez Gomez, A. Cook, T. Indlekofer, S. Hellebrand, H.-J. Wunderlich, Journal of Electronic Testing - Theory and Applications (JETTA) 30 (2014) 527–540. date_created: 2019-08-28T11:48:33Z date_updated: 2022-01-06T06:51:27Z department: - _id: '48' intvolume: ' 30' issue: '5' language: - iso: eng page: 527-540 publication: Journal of Electronic Testing - Theory and Applications (JETTA) publisher: Springer status: public title: Adaptive Bayesian Diagnosis of Intermittent Faults type: journal_article user_id: '209' volume: 30 year: '2014' ... --- _id: '46266' author: - first_name: Bijan full_name: Alizadeh, Bijan last_name: Alizadeh - first_name: Payman full_name: Behnam, Payman last_name: Behnam - first_name: Somayeh full_name: Sadeghi-Kohan, Somayeh id: '78614' last_name: Sadeghi-Kohan orcid: https://orcid.org/0000-0001-7246-0610 citation: ama: Alizadeh B, Behnam P, Sadeghi-Kohan S. A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. IEEE Transactions on Computers. Published online 2014:1-1. doi:10.1109/tc.2014.2329687 apa: Alizadeh, B., Behnam, P., & Sadeghi-Kohan, S. (2014). A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. IEEE Transactions on Computers, 1–1. https://doi.org/10.1109/tc.2014.2329687 bibtex: '@article{Alizadeh_Behnam_Sadeghi-Kohan_2014, title={A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs}, DOI={10.1109/tc.2014.2329687}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Alizadeh, Bijan and Behnam, Payman and Sadeghi-Kohan, Somayeh}, year={2014}, pages={1–1} }' chicago: Alizadeh, Bijan, Payman Behnam, and Somayeh Sadeghi-Kohan. “A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs.” IEEE Transactions on Computers, 2014, 1–1. https://doi.org/10.1109/tc.2014.2329687. ieee: 'B. Alizadeh, P. Behnam, and S. Sadeghi-Kohan, “A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs,” IEEE Transactions on Computers, pp. 1–1, 2014, doi: 10.1109/tc.2014.2329687.' mla: Alizadeh, Bijan, et al. “A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs.” IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers (IEEE), 2014, pp. 1–1, doi:10.1109/tc.2014.2329687. short: B. Alizadeh, P. Behnam, S. Sadeghi-Kohan, IEEE Transactions on Computers (2014) 1–1. date_created: 2023-08-02T11:15:22Z date_updated: 2023-08-02T11:32:37Z department: - _id: '48' doi: 10.1109/tc.2014.2329687 extern: '1' keyword: - Computational Theory and Mathematics - Hardware and Architecture - Theoretical Computer Science - Software language: - iso: eng page: 1-1 publication: IEEE Transactions on Computers publication_identifier: issn: - 0018-9340 publication_status: published publisher: Institute of Electrical and Electronics Engineers (IEEE) status: public title: A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs type: journal_article user_id: '78614' year: '2014' ... --- _id: '46268' author: - first_name: Marzieh full_name: Mohammadi, Marzieh last_name: Mohammadi - first_name: Somayeh full_name: Sadeghi-Kohan, Somayeh id: '78614' last_name: Sadeghi-Kohan orcid: https://orcid.org/0000-0001-7246-0610 - first_name: Nasser full_name: Masoumi, Nasser last_name: Masoumi - first_name: Zainalabedin full_name: Navabi, Zainalabedin last_name: Navabi citation: ama: 'Mohammadi M, Sadeghi-Kohan S, Masoumi N, Navabi Z. An off-line MDSI interconnect BIST incorporated in BS 1149.1. In: 2014 19th IEEE European Test Symposium (ETS). IEEE; 2014. doi:10.1109/ets.2014.6847847' apa: Mohammadi, M., Sadeghi-Kohan, S., Masoumi, N., & Navabi, Z. (2014). An off-line MDSI interconnect BIST incorporated in BS 1149.1. 2014 19th IEEE European Test Symposium (ETS). https://doi.org/10.1109/ets.2014.6847847 bibtex: '@inproceedings{Mohammadi_Sadeghi-Kohan_Masoumi_Navabi_2014, title={An off-line MDSI interconnect BIST incorporated in BS 1149.1}, DOI={10.1109/ets.2014.6847847}, booktitle={2014 19th IEEE European Test Symposium (ETS)}, publisher={IEEE}, author={Mohammadi, Marzieh and Sadeghi-Kohan, Somayeh and Masoumi, Nasser and Navabi, Zainalabedin}, year={2014} }' chicago: Mohammadi, Marzieh, Somayeh Sadeghi-Kohan, Nasser Masoumi, and Zainalabedin Navabi. “An Off-Line MDSI Interconnect BIST Incorporated in BS 1149.1.” In 2014 19th IEEE European Test Symposium (ETS). IEEE, 2014. https://doi.org/10.1109/ets.2014.6847847. ieee: 'M. Mohammadi, S. Sadeghi-Kohan, N. Masoumi, and Z. Navabi, “An off-line MDSI interconnect BIST incorporated in BS 1149.1,” 2014, doi: 10.1109/ets.2014.6847847.' mla: Mohammadi, Marzieh, et al. “An Off-Line MDSI Interconnect BIST Incorporated in BS 1149.1.” 2014 19th IEEE European Test Symposium (ETS), IEEE, 2014, doi:10.1109/ets.2014.6847847. short: 'M. Mohammadi, S. Sadeghi-Kohan, N. Masoumi, Z. Navabi, in: 2014 19th IEEE European Test Symposium (ETS), IEEE, 2014.' date_created: 2023-08-02T11:18:26Z date_updated: 2023-08-02T11:32:48Z department: - _id: '48' doi: 10.1109/ets.2014.6847847 extern: '1' language: - iso: eng publication: 2014 19th IEEE European Test Symposium (ETS) publication_status: published publisher: IEEE status: public title: An off-line MDSI interconnect BIST incorporated in BS 1149.1 type: conference user_id: '78614' year: '2014' ... --- _id: '46267' author: - first_name: Somayeh full_name: Sadeghi-Kohan, Somayeh id: '78614' last_name: Sadeghi-Kohan orcid: https://orcid.org/0000-0001-7246-0610 - first_name: Payman full_name: Behnam, Payman last_name: Behnam - first_name: Bijan full_name: Alizadeh, Bijan last_name: Alizadeh - first_name: Masahiro full_name: Fujita, Masahiro last_name: Fujita - first_name: Zainalabedin full_name: Navabi, Zainalabedin last_name: Navabi citation: ama: 'Sadeghi-Kohan S, Behnam P, Alizadeh B, Fujita M, Navabi Z. Improving polynomial datapath debugging with HEDs. In: 2014 19th IEEE European Test Symposium (ETS). IEEE; 2014. doi:10.1109/ets.2014.6847797' apa: Sadeghi-Kohan, S., Behnam, P., Alizadeh, B., Fujita, M., & Navabi, Z. (2014). Improving polynomial datapath debugging with HEDs. 2014 19th IEEE European Test Symposium (ETS). https://doi.org/10.1109/ets.2014.6847797 bibtex: '@inproceedings{Sadeghi-Kohan_Behnam_Alizadeh_Fujita_Navabi_2014, title={Improving polynomial datapath debugging with HEDs}, DOI={10.1109/ets.2014.6847797}, booktitle={2014 19th IEEE European Test Symposium (ETS)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Behnam, Payman and Alizadeh, Bijan and Fujita, Masahiro and Navabi, Zainalabedin}, year={2014} }' chicago: Sadeghi-Kohan, Somayeh, Payman Behnam, Bijan Alizadeh, Masahiro Fujita, and Zainalabedin Navabi. “Improving Polynomial Datapath Debugging with HEDs.” In 2014 19th IEEE European Test Symposium (ETS). IEEE, 2014. https://doi.org/10.1109/ets.2014.6847797. ieee: 'S. Sadeghi-Kohan, P. Behnam, B. Alizadeh, M. Fujita, and Z. Navabi, “Improving polynomial datapath debugging with HEDs,” 2014, doi: 10.1109/ets.2014.6847797.' mla: Sadeghi-Kohan, Somayeh, et al. “Improving Polynomial Datapath Debugging with HEDs.” 2014 19th IEEE European Test Symposium (ETS), IEEE, 2014, doi:10.1109/ets.2014.6847797. short: 'S. Sadeghi-Kohan, P. Behnam, B. Alizadeh, M. Fujita, Z. Navabi, in: 2014 19th IEEE European Test Symposium (ETS), IEEE, 2014.' date_created: 2023-08-02T11:17:08Z date_updated: 2023-08-02T11:34:10Z department: - _id: '48' doi: 10.1109/ets.2014.6847797 extern: '1' language: - iso: eng publication: 2014 19th IEEE European Test Symposium (ETS) publication_status: published publisher: IEEE status: public title: Improving polynomial datapath debugging with HEDs type: conference user_id: '78614' year: '2014' ... --- _id: '12979' author: - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: 'Hellebrand S. Analyzing and Quantifying Fault Tolerance Properties. In: 14th IEEE Latin American Test Workshop - (LATW’13). Cordoba, Argentina: IEEE; 2013. doi:10.1109/latw.2013.6562662' apa: 'Hellebrand, S. (2013). Analyzing and Quantifying Fault Tolerance Properties. In 14th IEEE Latin American Test Workshop - (LATW’13). Cordoba, Argentina: IEEE. https://doi.org/10.1109/latw.2013.6562662' bibtex: '@inproceedings{Hellebrand_2013, place={Cordoba, Argentina}, title={Analyzing and Quantifying Fault Tolerance Properties}, DOI={10.1109/latw.2013.6562662}, booktitle={14th IEEE Latin American Test Workshop - (LATW’13)}, publisher={IEEE}, author={Hellebrand, Sybille}, year={2013} }' chicago: 'Hellebrand, Sybille. “Analyzing and Quantifying Fault Tolerance Properties.” In 14th IEEE Latin American Test Workshop - (LATW’13). Cordoba, Argentina: IEEE, 2013. https://doi.org/10.1109/latw.2013.6562662.' ieee: S. Hellebrand, “Analyzing and Quantifying Fault Tolerance Properties,” in 14th IEEE Latin American Test Workshop - (LATW’13), 2013. mla: Hellebrand, Sybille. “Analyzing and Quantifying Fault Tolerance Properties.” 14th IEEE Latin American Test Workshop - (LATW’13), IEEE, 2013, doi:10.1109/latw.2013.6562662. short: 'S. Hellebrand, in: 14th IEEE Latin American Test Workshop - (LATW’13), IEEE, Cordoba, Argentina, 2013.' date_created: 2019-08-28T09:16:51Z date_updated: 2022-01-06T06:51:27Z department: - _id: '48' doi: 10.1109/latw.2013.6562662 language: - iso: eng place: Cordoba, Argentina publication: 14th IEEE Latin American Test Workshop - (LATW'13) publisher: IEEE status: public title: Analyzing and Quantifying Fault Tolerance Properties type: conference user_id: '209' year: '2013' ... --- _id: '13075' author: - first_name: Alejandro full_name: Cook, Alejandro last_name: Cook - first_name: Laura full_name: Rodriguez Gomez, Laura last_name: Rodriguez Gomez - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Thomas full_name: Indlekofer, Thomas last_name: Indlekofer - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich citation: ama: Cook A, Rodriguez Gomez L, Hellebrand S, Indlekofer T, Wunderlich H-J. Adaptive Test and Diagnosis of Intermittent Faults. 14th Latin American Test Workshop, Cordoba, Argentina; 2013. apa: Cook, A., Rodriguez Gomez, L., Hellebrand, S., Indlekofer, T., & Wunderlich, H.-J. (2013). Adaptive Test and Diagnosis of Intermittent Faults. 14th Latin American Test Workshop, Cordoba, Argentina. bibtex: '@book{Cook_Rodriguez Gomez_Hellebrand_Indlekofer_Wunderlich_2013, place={14th Latin American Test Workshop, Cordoba, Argentina}, title={Adaptive Test and Diagnosis of Intermittent Faults}, author={Cook, Alejandro and Rodriguez Gomez, Laura and Hellebrand, Sybille and Indlekofer, Thomas and Wunderlich, Hans-Joachim}, year={2013} }' chicago: Cook, Alejandro, Laura Rodriguez Gomez, Sybille Hellebrand, Thomas Indlekofer, and Hans-Joachim Wunderlich. Adaptive Test and Diagnosis of Intermittent Faults. 14th Latin American Test Workshop, Cordoba, Argentina, 2013. ieee: A. Cook, L. Rodriguez Gomez, S. Hellebrand, T. Indlekofer, and H.-J. Wunderlich, Adaptive Test and Diagnosis of Intermittent Faults. 14th Latin American Test Workshop, Cordoba, Argentina, 2013. mla: Cook, Alejandro, et al. Adaptive Test and Diagnosis of Intermittent Faults. 2013. short: A. Cook, L. Rodriguez Gomez, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, Adaptive Test and Diagnosis of Intermittent Faults, 14th Latin American Test Workshop, Cordoba, Argentina, 2013. date_created: 2019-08-28T12:04:38Z date_updated: 2022-01-06T06:51:28Z department: - _id: '48' keyword: - WORKSHOP language: - iso: eng place: 14th Latin American Test Workshop, Cordoba, Argentina status: public title: Adaptive Test and Diagnosis of Intermittent Faults type: misc user_id: '659' year: '2013' ... --- _id: '46271' author: - first_name: Somayeh full_name: Sadeghi-Kohan, Somayeh id: '78614' last_name: Sadeghi-Kohan orcid: https://orcid.org/0000-0001-7246-0610 - first_name: Majid full_name: Namaki-Shoushtari, Majid last_name: Namaki-Shoushtari - first_name: Fatemeh full_name: Javaheri, Fatemeh last_name: Javaheri - first_name: Zainalabedin full_name: Navabi, Zainalabedin last_name: Navabi citation: ama: 'Sadeghi-Kohan S, Namaki-Shoushtari M, Javaheri F, Navabi Z. BS 1149.1 extensions for an online interconnect fault detection and recovery. In: 2012 IEEE International Test Conference. IEEE; 2013. doi:10.1109/test.2012.6401583' apa: Sadeghi-Kohan, S., Namaki-Shoushtari, M., Javaheri, F., & Navabi, Z. (2013). BS 1149.1 extensions for an online interconnect fault detection and recovery. 2012 IEEE International Test Conference. https://doi.org/10.1109/test.2012.6401583 bibtex: '@inproceedings{Sadeghi-Kohan_Namaki-Shoushtari_Javaheri_Navabi_2013, title={BS 1149.1 extensions for an online interconnect fault detection and recovery}, DOI={10.1109/test.2012.6401583}, booktitle={2012 IEEE International Test Conference}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Namaki-Shoushtari, Majid and Javaheri, Fatemeh and Navabi, Zainalabedin}, year={2013} }' chicago: Sadeghi-Kohan, Somayeh, Majid Namaki-Shoushtari, Fatemeh Javaheri, and Zainalabedin Navabi. “BS 1149.1 Extensions for an Online Interconnect Fault Detection and Recovery.” In 2012 IEEE International Test Conference. IEEE, 2013. https://doi.org/10.1109/test.2012.6401583. ieee: 'S. Sadeghi-Kohan, M. Namaki-Shoushtari, F. Javaheri, and Z. Navabi, “BS 1149.1 extensions for an online interconnect fault detection and recovery,” 2013, doi: 10.1109/test.2012.6401583.' mla: Sadeghi-Kohan, Somayeh, et al. “BS 1149.1 Extensions for an Online Interconnect Fault Detection and Recovery.” 2012 IEEE International Test Conference, IEEE, 2013, doi:10.1109/test.2012.6401583. short: 'S. Sadeghi-Kohan, M. Namaki-Shoushtari, F. Javaheri, Z. Navabi, in: 2012 IEEE International Test Conference, IEEE, 2013.' date_created: 2023-08-02T11:20:19Z date_updated: 2023-08-02T11:33:26Z department: - _id: '48' doi: 10.1109/test.2012.6401583 extern: '1' language: - iso: eng publication: 2012 IEEE International Test Conference publication_status: published publisher: IEEE status: public title: BS 1149.1 extensions for an online interconnect fault detection and recovery type: conference user_id: '78614' year: '2013' ... --- _id: '46270' author: - first_name: Somayeh full_name: Sadeghi-Kohan, Somayeh id: '78614' last_name: Sadeghi-Kohan orcid: https://orcid.org/0000-0001-7246-0610 - first_name: Shahrzad full_name: Keshavarz, Shahrzad last_name: Keshavarz - first_name: Farzaneh full_name: Zokaee, Farzaneh last_name: Zokaee - first_name: Farimah full_name: Farahmandi, Farimah last_name: Farahmandi - first_name: Zainalabedin full_name: Navabi, Zainalabedin last_name: Navabi citation: ama: 'Sadeghi-Kohan S, Keshavarz S, Zokaee F, Farahmandi F, Navabi Z. A new structure for interconnect offline testing. In: East-West Design & Test Symposium (EWDTS 2013). IEEE; 2013. doi:10.1109/ewdts.2013.6673207' apa: Sadeghi-Kohan, S., Keshavarz, S., Zokaee, F., Farahmandi, F., & Navabi, Z. (2013). A new structure for interconnect offline testing. East-West Design & Test Symposium (EWDTS 2013). https://doi.org/10.1109/ewdts.2013.6673207 bibtex: '@inproceedings{Sadeghi-Kohan_Keshavarz_Zokaee_Farahmandi_Navabi_2013, title={A new structure for interconnect offline testing}, DOI={10.1109/ewdts.2013.6673207}, booktitle={East-West Design & Test Symposium (EWDTS 2013)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Keshavarz, Shahrzad and Zokaee, Farzaneh and Farahmandi, Farimah and Navabi, Zainalabedin}, year={2013} }' chicago: Sadeghi-Kohan, Somayeh, Shahrzad Keshavarz, Farzaneh Zokaee, Farimah Farahmandi, and Zainalabedin Navabi. “A New Structure for Interconnect Offline Testing.” In East-West Design & Test Symposium (EWDTS 2013). IEEE, 2013. https://doi.org/10.1109/ewdts.2013.6673207. ieee: 'S. Sadeghi-Kohan, S. Keshavarz, F. Zokaee, F. Farahmandi, and Z. Navabi, “A new structure for interconnect offline testing,” 2013, doi: 10.1109/ewdts.2013.6673207.' mla: Sadeghi-Kohan, Somayeh, et al. “A New Structure for Interconnect Offline Testing.” East-West Design & Test Symposium (EWDTS 2013), IEEE, 2013, doi:10.1109/ewdts.2013.6673207. short: 'S. Sadeghi-Kohan, S. Keshavarz, F. Zokaee, F. Farahmandi, Z. Navabi, in: East-West Design & Test Symposium (EWDTS 2013), IEEE, 2013.' date_created: 2023-08-02T11:19:36Z date_updated: 2023-08-02T11:33:58Z department: - _id: '48' doi: 10.1109/ewdts.2013.6673207 extern: '1' language: - iso: eng publication: East-West Design & Test Symposium (EWDTS 2013) publication_status: published publisher: IEEE status: public title: A new structure for interconnect offline testing type: conference user_id: '78614' year: '2013' ...