---
_id: '4575'
author:
- first_name: Alexander
full_name: Sprenger, Alexander
id: '22707'
last_name: Sprenger
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Sprenger A, Hellebrand S. Tuning Stochastic Space Compaction to Faster-than-at-Speed
Test. In: 2018 IEEE 21st International Symposium on Design and Diagnostics
of Electronic Circuits & Systems (DDECS). IEEE; 2018. doi:10.1109/ddecs.2018.00020'
apa: Sprenger, A., & Hellebrand, S. (2018). Tuning Stochastic Space Compaction
to Faster-than-at-Speed Test. 2018 IEEE 21st International Symposium on Design
and Diagnostics of Electronic Circuits & Systems (DDECS). https://doi.org/10.1109/ddecs.2018.00020
bibtex: '@inproceedings{Sprenger_Hellebrand_2018, place={Budapest, Hungary}, title={Tuning
Stochastic Space Compaction to Faster-than-at-Speed Test}, DOI={10.1109/ddecs.2018.00020},
booktitle={2018 IEEE 21st International Symposium on Design and Diagnostics of
Electronic Circuits & Systems (DDECS)}, publisher={IEEE}, author={Sprenger,
Alexander and Hellebrand, Sybille}, year={2018} }'
chicago: 'Sprenger, Alexander, and Sybille Hellebrand. “Tuning Stochastic Space
Compaction to Faster-than-at-Speed Test.” In 2018 IEEE 21st International Symposium
on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Budapest,
Hungary: IEEE, 2018. https://doi.org/10.1109/ddecs.2018.00020.'
ieee: 'A. Sprenger and S. Hellebrand, “Tuning Stochastic Space Compaction to Faster-than-at-Speed
Test,” 2018, doi: 10.1109/ddecs.2018.00020.'
mla: Sprenger, Alexander, and Sybille Hellebrand. “Tuning Stochastic Space Compaction
to Faster-than-at-Speed Test.” 2018 IEEE 21st International Symposium on Design
and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, 2018,
doi:10.1109/ddecs.2018.00020.
short: 'A. Sprenger, S. Hellebrand, in: 2018 IEEE 21st International Symposium on
Design and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, Budapest,
Hungary, 2018.'
date_created: 2018-10-02T12:18:46Z
date_updated: 2022-05-11T17:10:37Z
department:
- _id: '48'
doi: 10.1109/ddecs.2018.00020
language:
- iso: eng
place: Budapest, Hungary
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic
Circuits & Systems (DDECS)
publication_identifier:
isbn:
- '9781538657546'
publication_status: published
publisher: IEEE
status: public
title: Tuning Stochastic Space Compaction to Faster-than-at-Speed Test
type: conference
user_id: '209'
year: '2018'
...
---
_id: '10575'
author:
- first_name: Chang
full_name: Liu, Chang
last_name: Liu
- first_name: Eric
full_name: Schneider, Eric
last_name: Schneider
- first_name: Matthias
full_name: Kampmann, Matthias
id: '10935'
last_name: Kampmann
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
citation:
ama: 'Liu C, Schneider E, Kampmann M, Hellebrand S, Wunderlich H-J. Extending Aging
Monitors for Early Life and Wear-Out Failure Prevention. In: 27th IEEE Asian
Test Symposium (ATS’18). ; 2018. doi:10.1109/ats.2018.00028'
apa: Liu, C., Schneider, E., Kampmann, M., Hellebrand, S., & Wunderlich, H.-J.
(2018). Extending Aging Monitors for Early Life and Wear-Out Failure Prevention.
27th IEEE Asian Test Symposium (ATS’18). https://doi.org/10.1109/ats.2018.00028
bibtex: '@inproceedings{Liu_Schneider_Kampmann_Hellebrand_Wunderlich_2018, title={Extending
Aging Monitors for Early Life and Wear-Out Failure Prevention}, DOI={10.1109/ats.2018.00028},
booktitle={27th IEEE Asian Test Symposium (ATS’18)}, author={Liu, Chang and Schneider,
Eric and Kampmann, Matthias and Hellebrand, Sybille and Wunderlich, Hans-Joachim},
year={2018} }'
chicago: Liu, Chang, Eric Schneider, Matthias Kampmann, Sybille Hellebrand, and
Hans-Joachim Wunderlich. “Extending Aging Monitors for Early Life and Wear-Out
Failure Prevention.” In 27th IEEE Asian Test Symposium (ATS’18), 2018.
https://doi.org/10.1109/ats.2018.00028.
ieee: 'C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, and H.-J. Wunderlich, “Extending
Aging Monitors for Early Life and Wear-Out Failure Prevention,” 2018, doi: 10.1109/ats.2018.00028.'
mla: Liu, Chang, et al. “Extending Aging Monitors for Early Life and Wear-Out Failure
Prevention.” 27th IEEE Asian Test Symposium (ATS’18), 2018, doi:10.1109/ats.2018.00028.
short: 'C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, H.-J. Wunderlich, in:
27th IEEE Asian Test Symposium (ATS’18), 2018.'
date_created: 2019-07-05T08:14:58Z
date_updated: 2022-05-11T17:11:53Z
department:
- _id: '48'
doi: 10.1109/ats.2018.00028
language:
- iso: eng
publication: 27th IEEE Asian Test Symposium (ATS'18)
publication_identifier:
isbn:
- '9781538694664'
publication_status: published
status: public
title: Extending Aging Monitors for Early Life and Wear-Out Failure Prevention
type: conference
user_id: '209'
year: '2018'
...
---
_id: '29459'
abstract:
- lang: eng
text: Transistor and interconnect wearout is accelerated with transistor scaling
resulting in timing variations and consequently reliability challenges in digital
circuits. With the emergence of new issues like Electro-migration these problems
are getting more crucial. Age monitoring methods can be used to predict and deal
with the aging problem. Selecting appropriate locations for placement of aging
monitors is an important issue. In this work we propose a procedure for selection
of appropriate internal nodes that expose smaller overheads to the circuit, using
correlation between nodes and the shareability amongst them. To select internal
nodes, we first prune some nodes based on some attributes and thus provide a near-optimal
solution that can effectively get a number of internal nodes and consider the
effects of electro-migration as well. We have applied our proposed scheme to several
processors and ITC benchmarks and have looked at its effectiveness for these circuits.
author:
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
- first_name: Arash
full_name: Vafaei, Arash
last_name: Vafaei
- first_name: Zainalabedin
full_name: Navabi, Zainalabedin
last_name: Navabi
citation:
ama: 'Sadeghi-Kohan S, Vafaei A, Navabi Z. Near-Optimal Node Selection Procedure
for Aging Monitor Placement. In: 2018 IEEE 24th International Symposium on
On-Line Testing And Robust System Design (IOLTS). IEEE; 2018. doi:10.1109/iolts.2018.8474120'
apa: Sadeghi-Kohan, S., Vafaei, A., & Navabi, Z. (2018). Near-Optimal Node Selection
Procedure for Aging Monitor Placement. 2018 IEEE 24th International Symposium
on On-Line Testing And Robust System Design (IOLTS). https://doi.org/10.1109/iolts.2018.8474120
bibtex: '@inproceedings{Sadeghi-Kohan_Vafaei_Navabi_2018, title={Near-Optimal Node
Selection Procedure for Aging Monitor Placement}, DOI={10.1109/iolts.2018.8474120},
booktitle={2018 IEEE 24th International Symposium on On-Line Testing And Robust
System Design (IOLTS)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Vafaei,
Arash and Navabi, Zainalabedin}, year={2018} }'
chicago: Sadeghi-Kohan, Somayeh, Arash Vafaei, and Zainalabedin Navabi. “Near-Optimal
Node Selection Procedure for Aging Monitor Placement.” In 2018 IEEE 24th International
Symposium on On-Line Testing And Robust System Design (IOLTS). IEEE, 2018.
https://doi.org/10.1109/iolts.2018.8474120.
ieee: 'S. Sadeghi-Kohan, A. Vafaei, and Z. Navabi, “Near-Optimal Node Selection
Procedure for Aging Monitor Placement,” 2018, doi: 10.1109/iolts.2018.8474120.'
mla: Sadeghi-Kohan, Somayeh, et al. “Near-Optimal Node Selection Procedure for Aging
Monitor Placement.” 2018 IEEE 24th International Symposium on On-Line Testing
And Robust System Design (IOLTS), IEEE, 2018, doi:10.1109/iolts.2018.8474120.
short: 'S. Sadeghi-Kohan, A. Vafaei, Z. Navabi, in: 2018 IEEE 24th International
Symposium on On-Line Testing And Robust System Design (IOLTS), IEEE, 2018.'
date_created: 2022-01-19T13:35:37Z
date_updated: 2023-08-02T11:36:15Z
department:
- _id: '48'
doi: 10.1109/iolts.2018.8474120
extern: '1'
language:
- iso: eng
publication: 2018 IEEE 24th International Symposium on On-Line Testing And Robust
System Design (IOLTS)
publication_status: published
publisher: IEEE
status: public
title: Near-Optimal Node Selection Procedure for Aging Monitor Placement
type: conference
user_id: '78614'
year: '2018'
...
---
_id: '12973'
author:
- first_name: Jyotirmoy
full_name: Deshmukh, Jyotirmoy
last_name: Deshmukh
- first_name: Wolfgang
full_name: Kunz, Wolfgang
last_name: Kunz
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Deshmukh J, Kunz W, Wunderlich H-J, Hellebrand S. Special Session on Early
Life Failures. In: 35th IEEE VLSI Test Symposium (VTS’17). Caesars Palace,
Las Vegas, Nevada, USA: IEEE; 2017. doi:10.1109/vts.2017.7928933'
apa: 'Deshmukh, J., Kunz, W., Wunderlich, H.-J., & Hellebrand, S. (2017). Special
Session on Early Life Failures. In 35th IEEE VLSI Test Symposium (VTS’17).
Caesars Palace, Las Vegas, Nevada, USA: IEEE. https://doi.org/10.1109/vts.2017.7928933'
bibtex: '@inproceedings{Deshmukh_Kunz_Wunderlich_Hellebrand_2017, place={Caesars
Palace, Las Vegas, Nevada, USA}, title={Special Session on Early Life Failures},
DOI={10.1109/vts.2017.7928933},
booktitle={35th IEEE VLSI Test Symposium (VTS’17)}, publisher={IEEE}, author={Deshmukh,
Jyotirmoy and Kunz, Wolfgang and Wunderlich, Hans-Joachim and Hellebrand, Sybille},
year={2017} }'
chicago: 'Deshmukh, Jyotirmoy, Wolfgang Kunz, Hans-Joachim Wunderlich, and Sybille
Hellebrand. “Special Session on Early Life Failures.” In 35th IEEE VLSI Test
Symposium (VTS’17). Caesars Palace, Las Vegas, Nevada, USA: IEEE, 2017. https://doi.org/10.1109/vts.2017.7928933.'
ieee: J. Deshmukh, W. Kunz, H.-J. Wunderlich, and S. Hellebrand, “Special Session
on Early Life Failures,” in 35th IEEE VLSI Test Symposium (VTS’17), 2017.
mla: Deshmukh, Jyotirmoy, et al. “Special Session on Early Life Failures.” 35th
IEEE VLSI Test Symposium (VTS’17), IEEE, 2017, doi:10.1109/vts.2017.7928933.
short: 'J. Deshmukh, W. Kunz, H.-J. Wunderlich, S. Hellebrand, in: 35th IEEE VLSI
Test Symposium (VTS’17), IEEE, Caesars Palace, Las Vegas, Nevada, USA, 2017.'
date_created: 2019-08-28T08:37:58Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '48'
doi: 10.1109/vts.2017.7928933
language:
- iso: eng
place: Caesars Palace, Las Vegas, Nevada, USA
publication: 35th IEEE VLSI Test Symposium (VTS'17)
publisher: IEEE
status: public
title: Special Session on Early Life Failures
type: conference
user_id: '209'
year: '2017'
...
---
_id: '13078'
author:
- first_name: Matthias
full_name: Kampmann, Matthias
id: '10935'
last_name: Kampmann
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: Kampmann M, Hellebrand S. X-Tolerante Prüfzellengruppierung Für Den Test
Mit Erhöhter Betriebsfrequenz.; 2017.
apa: Kampmann, M., & Hellebrand, S. (2017). X-tolerante Prüfzellengruppierung
für den Test mit erhöhter Betriebsfrequenz.
bibtex: '@book{Kampmann_Hellebrand_2017, place={29. Workshop “Testmethoden und Zuverlässigkeit
von Schaltungen und Systemen” (TuZ’17), Lübeck, Germany}, title={X-tolerante Prüfzellengruppierung
für den Test mit erhöhter Betriebsfrequenz}, author={Kampmann, Matthias and Hellebrand,
Sybille}, year={2017} }'
chicago: Kampmann, Matthias, and Sybille Hellebrand. X-Tolerante Prüfzellengruppierung
Für Den Test Mit Erhöhter Betriebsfrequenz. 29. Workshop “Testmethoden und
Zuverlässigkeit von Schaltungen und Systemen” (TuZ’17), Lübeck, Germany, 2017.
ieee: M. Kampmann and S. Hellebrand, X-tolerante Prüfzellengruppierung für den
Test mit erhöhter Betriebsfrequenz. 29. Workshop “Testmethoden und Zuverlässigkeit
von Schaltungen und Systemen” (TuZ’17), Lübeck, Germany, 2017.
mla: Kampmann, Matthias, and Sybille Hellebrand. X-Tolerante Prüfzellengruppierung
Für Den Test Mit Erhöhter Betriebsfrequenz. 2017.
short: M. Kampmann, S. Hellebrand, X-Tolerante Prüfzellengruppierung Für Den Test
Mit Erhöhter Betriebsfrequenz, 29. Workshop “Testmethoden und Zuverlässigkeit
von Schaltungen und Systemen” (TuZ’17), Lübeck, Germany, 2017.
date_created: 2019-08-28T12:06:26Z
date_updated: 2022-05-11T16:17:41Z
department:
- _id: '48'
keyword:
- WORKSHOP
language:
- iso: eng
place: 29. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
(TuZ'17), Lübeck, Germany
status: public
title: X-tolerante Prüfzellengruppierung für den Test mit erhöhter Betriebsfrequenz
type: misc
user_id: '209'
year: '2017'
...
---
_id: '10576'
author:
- first_name: Matthias
full_name: Kampmann, Matthias
id: '10935'
last_name: Kampmann
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Kampmann M, Hellebrand S. Design-for-FAST: Supporting X-tolerant compaction
during Faster-than-at-Speed Test. In: 20th IEEE International Symposium on
Design & Diagnostics of Electronic Circuits & Systems (DDECS’17).
IEEE; 2017. doi:10.1109/ddecs.2017.7934564'
apa: 'Kampmann, M., & Hellebrand, S. (2017). Design-for-FAST: Supporting X-tolerant
compaction during Faster-than-at-Speed Test. 20th IEEE International Symposium
on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17).
https://doi.org/10.1109/ddecs.2017.7934564'
bibtex: '@inproceedings{Kampmann_Hellebrand_2017, title={Design-for-FAST: Supporting
X-tolerant compaction during Faster-than-at-Speed Test}, DOI={10.1109/ddecs.2017.7934564},
booktitle={20th IEEE International Symposium on Design & Diagnostics of Electronic
Circuits & Systems (DDECS’17)}, publisher={IEEE}, author={Kampmann, Matthias
and Hellebrand, Sybille}, year={2017} }'
chicago: 'Kampmann, Matthias, and Sybille Hellebrand. “Design-for-FAST: Supporting
X-Tolerant Compaction during Faster-than-at-Speed Test.” In 20th IEEE International
Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17).
IEEE, 2017. https://doi.org/10.1109/ddecs.2017.7934564.'
ieee: 'M. Kampmann and S. Hellebrand, “Design-for-FAST: Supporting X-tolerant compaction
during Faster-than-at-Speed Test,” 2017, doi: 10.1109/ddecs.2017.7934564.'
mla: 'Kampmann, Matthias, and Sybille Hellebrand. “Design-for-FAST: Supporting X-Tolerant
Compaction during Faster-than-at-Speed Test.” 20th IEEE International Symposium
on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17),
IEEE, 2017, doi:10.1109/ddecs.2017.7934564.'
short: 'M. Kampmann, S. Hellebrand, in: 20th IEEE International Symposium on Design
& Diagnostics of Electronic Circuits & Systems (DDECS’17), IEEE, 2017.'
date_created: 2019-07-05T08:23:56Z
date_updated: 2022-05-11T17:14:51Z
department:
- _id: '48'
doi: 10.1109/ddecs.2017.7934564
language:
- iso: eng
publication: 20th IEEE International Symposium on Design & Diagnostics of Electronic
Circuits & Systems (DDECS'17)
publication_identifier:
isbn:
- '9781538604724'
publication_status: published
publisher: IEEE
status: public
title: 'Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed
Test'
type: conference
user_id: '209'
year: '2017'
...
---
_id: '29462'
abstract:
- lang: eng
text: Time-variant age information of different parts of a system can be used for
system-level performance improvement through high-level task scheduling, thus
extending the life-time of the system. Progressive age information should provide
the age state that the system is in, and the rate that it is being aged at. In
this paper, we propose a structure that monitors certain paths of a circuit and
detects its gradual age growth, and provides the aging rate and aging state of
the circuit. The proposed monitors are placed on a selected set of nodes that
represent a timing bottleneck of the system. These monitors sample expected data
on these nodes, and compare them with the expected values. The timing of sampling
changes as the circuit ages and its delay increases. The timing of sampling will
provide a measure of aging advancement of a circuit. To assess the efficacy of
the proposed method and compare it with other state-of-the-art aging monitors,
we use them on selected nodes of the execution unit of different processors, as
well as some circuits from ITC99 benchmarks. The results reveal that the precision
of our proposed method is between 0.12 (ns) to 0.401 (ns). Its Area and power
overhead are negligible and are about 2.13 and 0.69 percent respectively.
author:
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
- first_name: Mehdi
full_name: Kamal, Mehdi
last_name: Kamal
- first_name: Zainalabedin
full_name: Navabi, Zainalabedin
last_name: Navabi
citation:
ama: Sadeghi-Kohan S, Kamal M, Navabi Z. Self-Adjusting Monitor for Measuring Aging
Rate and Advancement. IEEE Transactions on Emerging Topics in Computing.
2017;8(3):627-641. doi:10.1109/tetc.2017.2771441
apa: Sadeghi-Kohan, S., Kamal, M., & Navabi, Z. (2017). Self-Adjusting Monitor
for Measuring Aging Rate and Advancement. IEEE Transactions on Emerging Topics
in Computing, 8(3), 627–641. https://doi.org/10.1109/tetc.2017.2771441
bibtex: '@article{Sadeghi-Kohan_Kamal_Navabi_2017, title={Self-Adjusting Monitor
for Measuring Aging Rate and Advancement}, volume={8}, DOI={10.1109/tetc.2017.2771441},
number={3}, journal={IEEE Transactions on Emerging Topics in Computing}, publisher={Institute
of Electrical and Electronics Engineers (IEEE)}, author={Sadeghi-Kohan, Somayeh
and Kamal, Mehdi and Navabi, Zainalabedin}, year={2017}, pages={627–641} }'
chicago: 'Sadeghi-Kohan, Somayeh, Mehdi Kamal, and Zainalabedin Navabi. “Self-Adjusting
Monitor for Measuring Aging Rate and Advancement.” IEEE Transactions on Emerging
Topics in Computing 8, no. 3 (2017): 627–41. https://doi.org/10.1109/tetc.2017.2771441.'
ieee: 'S. Sadeghi-Kohan, M. Kamal, and Z. Navabi, “Self-Adjusting Monitor for Measuring
Aging Rate and Advancement,” IEEE Transactions on Emerging Topics in Computing,
vol. 8, no. 3, pp. 627–641, 2017, doi: 10.1109/tetc.2017.2771441.'
mla: Sadeghi-Kohan, Somayeh, et al. “Self-Adjusting Monitor for Measuring Aging
Rate and Advancement.” IEEE Transactions on Emerging Topics in Computing,
vol. 8, no. 3, Institute of Electrical and Electronics Engineers (IEEE), 2017,
pp. 627–41, doi:10.1109/tetc.2017.2771441.
short: S. Sadeghi-Kohan, M. Kamal, Z. Navabi, IEEE Transactions on Emerging Topics
in Computing 8 (2017) 627–641.
date_created: 2022-01-19T13:45:51Z
date_updated: 2023-08-02T11:36:30Z
department:
- _id: '48'
doi: 10.1109/tetc.2017.2771441
extern: '1'
intvolume: ' 8'
issue: '3'
keyword:
- Age advancement
- age monitoring clock
- aging rate
- self-adjusting monitors
language:
- iso: eng
page: 627-641
publication: IEEE Transactions on Emerging Topics in Computing
publication_identifier:
issn:
- 2168-6750
- 2376-4562
publication_status: published
publisher: Institute of Electrical and Electronics Engineers (IEEE)
status: public
title: Self-Adjusting Monitor for Measuring Aging Rate and Advancement
type: journal_article
user_id: '78614'
volume: 8
year: '2017'
...
---
_id: '29463'
abstract:
- lang: eng
text: In this paper we propose to think out of the box and discuss an approach for
universal mitigation of Negative Bias Temperature Instability (NBTI) induced aging
untied from the limitations of its modelling. The cost-effective approach exploits
a simple property of a randomized design, i.e., the equalized signal probability
and switching activity at gate inputs. The techniques considered for structural
design randomization involve both the hardware architecture and embedded software
layers. Ultimately, the proposed approach aims at extending the reliable lifetime
of nanoelectronic systems.
author:
- first_name: Maksim
full_name: Jenihhin, Maksim
last_name: Jenihhin
- first_name: Alexander
full_name: Kamkin, Alexander
last_name: Kamkin
- first_name: Zainalabedin
full_name: Navabi, Zainalabedin
last_name: Navabi
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
citation:
ama: 'Jenihhin M, Kamkin A, Navabi Z, Sadeghi-Kohan S. Universal mitigation of NBTI-induced
aging by design randomization. In: 2016 IEEE East-West Design & Test Symposium
(EWDTS). IEEE; 2017. doi:10.1109/ewdts.2016.7807635'
apa: Jenihhin, M., Kamkin, A., Navabi, Z., & Sadeghi-Kohan, S. (2017). Universal
mitigation of NBTI-induced aging by design randomization. 2016 IEEE East-West
Design & Test Symposium (EWDTS). https://doi.org/10.1109/ewdts.2016.7807635
bibtex: '@inproceedings{Jenihhin_Kamkin_Navabi_Sadeghi-Kohan_2017, title={Universal
mitigation of NBTI-induced aging by design randomization}, DOI={10.1109/ewdts.2016.7807635},
booktitle={2016 IEEE East-West Design & Test Symposium (EWDTS)}, publisher={IEEE},
author={Jenihhin, Maksim and Kamkin, Alexander and Navabi, Zainalabedin and Sadeghi-Kohan,
Somayeh}, year={2017} }'
chicago: Jenihhin, Maksim, Alexander Kamkin, Zainalabedin Navabi, and Somayeh Sadeghi-Kohan.
“Universal Mitigation of NBTI-Induced Aging by Design Randomization.” In 2016
IEEE East-West Design & Test Symposium (EWDTS). IEEE, 2017. https://doi.org/10.1109/ewdts.2016.7807635.
ieee: 'M. Jenihhin, A. Kamkin, Z. Navabi, and S. Sadeghi-Kohan, “Universal mitigation
of NBTI-induced aging by design randomization,” 2017, doi: 10.1109/ewdts.2016.7807635.'
mla: Jenihhin, Maksim, et al. “Universal Mitigation of NBTI-Induced Aging by Design
Randomization.” 2016 IEEE East-West Design & Test Symposium (EWDTS),
IEEE, 2017, doi:10.1109/ewdts.2016.7807635.
short: 'M. Jenihhin, A. Kamkin, Z. Navabi, S. Sadeghi-Kohan, in: 2016 IEEE East-West
Design & Test Symposium (EWDTS), IEEE, 2017.'
date_created: 2022-01-19T13:50:13Z
date_updated: 2023-08-02T11:36:43Z
department:
- _id: '48'
doi: 10.1109/ewdts.2016.7807635
extern: '1'
language:
- iso: eng
publication: 2016 IEEE East-West Design & Test Symposium (EWDTS)
publication_status: published
publisher: IEEE
status: public
title: Universal mitigation of NBTI-induced aging by design randomization
type: conference
user_id: '78614'
year: '2017'
...
---
_id: '12975'
author:
- first_name: Matthias
full_name: Kampmann, Matthias
id: '10935'
last_name: Kampmann
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Kampmann M, Hellebrand S. X Marks the Spot: Scan-Flip-Flop Clustering for
Faster-than-at-Speed Test. In: 25th IEEE Asian Test Symposium (ATS’16).
Hiroshima, Japan: IEEE; 2016:1-6. doi:10.1109/ats.2016.20'
apa: 'Kampmann, M., & Hellebrand, S. (2016). X Marks the Spot: Scan-Flip-Flop
Clustering for Faster-than-at-Speed Test. In 25th IEEE Asian Test Symposium
(ATS’16) (pp. 1–6). Hiroshima, Japan: IEEE. https://doi.org/10.1109/ats.2016.20'
bibtex: '@inproceedings{Kampmann_Hellebrand_2016, place={Hiroshima, Japan}, title={X
Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test}, DOI={10.1109/ats.2016.20}, booktitle={25th
IEEE Asian Test Symposium (ATS’16)}, publisher={IEEE}, author={Kampmann, Matthias
and Hellebrand, Sybille}, year={2016}, pages={1–6} }'
chicago: 'Kampmann, Matthias, and Sybille Hellebrand. “X Marks the Spot: Scan-Flip-Flop
Clustering for Faster-than-at-Speed Test.” In 25th IEEE Asian Test Symposium
(ATS’16), 1–6. Hiroshima, Japan: IEEE, 2016. https://doi.org/10.1109/ats.2016.20.'
ieee: 'M. Kampmann and S. Hellebrand, “X Marks the Spot: Scan-Flip-Flop Clustering
for Faster-than-at-Speed Test,” in 25th IEEE Asian Test Symposium (ATS’16),
2016, pp. 1–6.'
mla: 'Kampmann, Matthias, and Sybille Hellebrand. “X Marks the Spot: Scan-Flip-Flop
Clustering for Faster-than-at-Speed Test.” 25th IEEE Asian Test Symposium (ATS’16),
IEEE, 2016, pp. 1–6, doi:10.1109/ats.2016.20.'
short: 'M. Kampmann, S. Hellebrand, in: 25th IEEE Asian Test Symposium (ATS’16),
IEEE, Hiroshima, Japan, 2016, pp. 1–6.'
date_created: 2019-08-28T08:53:04Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '48'
doi: 10.1109/ats.2016.20
language:
- iso: eng
page: 1-6
place: Hiroshima, Japan
publication: 25th IEEE Asian Test Symposium (ATS'16)
publisher: IEEE
status: public
title: 'X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test'
type: conference
user_id: '209'
year: '2016'
...
---
_id: '12976'
author:
- first_name: Matthias
full_name: Kampmann, Matthias
id: '10935'
last_name: Kampmann
- first_name: Michael
full_name: A. Kochte, Michael
last_name: A. Kochte
- first_name: Eric
full_name: Schneider, Eric
last_name: Schneider
- first_name: Thomas
full_name: Indlekofer, Thomas
last_name: Indlekofer
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
citation:
ama: 'Kampmann M, A. Kochte M, Schneider E, Indlekofer T, Hellebrand S, Wunderlich
H-J. Optimized Selection of Frequencies for Faster-Than-at-Speed Test. In: 24th
IEEE Asian Test Symposium (ATS’15). Mumbai, India: IEEE; 2015:109-114. doi:10.1109/ats.2015.26'
apa: 'Kampmann, M., A. Kochte, M., Schneider, E., Indlekofer, T., Hellebrand, S.,
& Wunderlich, H.-J. (2015). Optimized Selection of Frequencies for Faster-Than-at-Speed
Test. In 24th IEEE Asian Test Symposium (ATS’15) (pp. 109–114). Mumbai,
India: IEEE. https://doi.org/10.1109/ats.2015.26'
bibtex: '@inproceedings{Kampmann_A. Kochte_Schneider_Indlekofer_Hellebrand_Wunderlich_2015,
place={Mumbai, India}, title={Optimized Selection of Frequencies for Faster-Than-at-Speed
Test}, DOI={10.1109/ats.2015.26},
booktitle={24th IEEE Asian Test Symposium (ATS’15)}, publisher={IEEE}, author={Kampmann,
Matthias and A. Kochte, Michael and Schneider, Eric and Indlekofer, Thomas and
Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2015}, pages={109–114}
}'
chicago: 'Kampmann, Matthias, Michael A. Kochte, Eric Schneider, Thomas Indlekofer,
Sybille Hellebrand, and Hans-Joachim Wunderlich. “Optimized Selection of Frequencies
for Faster-Than-at-Speed Test.” In 24th IEEE Asian Test Symposium (ATS’15),
109–14. Mumbai, India: IEEE, 2015. https://doi.org/10.1109/ats.2015.26.'
ieee: M. Kampmann, M. A. Kochte, E. Schneider, T. Indlekofer, S. Hellebrand, and
H.-J. Wunderlich, “Optimized Selection of Frequencies for Faster-Than-at-Speed
Test,” in 24th IEEE Asian Test Symposium (ATS’15), 2015, pp. 109–114.
mla: Kampmann, Matthias, et al. “Optimized Selection of Frequencies for Faster-Than-at-Speed
Test.” 24th IEEE Asian Test Symposium (ATS’15), IEEE, 2015, pp. 109–14,
doi:10.1109/ats.2015.26.
short: 'M. Kampmann, M. A. Kochte, E. Schneider, T. Indlekofer, S. Hellebrand, H.-J.
Wunderlich, in: 24th IEEE Asian Test Symposium (ATS’15), IEEE, Mumbai, India,
2015, pp. 109–114.'
date_created: 2019-08-28T09:03:08Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '48'
doi: 10.1109/ats.2015.26
language:
- iso: eng
page: 109-114
place: Mumbai, India
publication: 24th IEEE Asian Test Symposium (ATS'15)
publisher: IEEE
status: public
title: Optimized Selection of Frequencies for Faster-Than-at-Speed Test
type: conference
user_id: '209'
year: '2015'
...
---
_id: '13056'
author:
- first_name: Zhengfeng
full_name: Huang, Zhengfeng
last_name: Huang
- first_name: Huaguo
full_name: Liang, Huaguo
last_name: Liang
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: Huang Z, Liang H, Hellebrand S. A High Performance SEU Tolerant Latch. Journal
of Electronic Testing - Theory and Applications (JETTA). 2015;31(4):349-359.
apa: Huang, Z., Liang, H., & Hellebrand, S. (2015). A High Performance SEU Tolerant
Latch. Journal of Electronic Testing - Theory and Applications (JETTA),
31(4), 349–359.
bibtex: '@article{Huang_Liang_Hellebrand_2015, title={A High Performance SEU Tolerant
Latch}, volume={31}, number={4}, journal={Journal of Electronic Testing - Theory
and Applications (JETTA)}, publisher={Springer}, author={Huang, Zhengfeng and
Liang, Huaguo and Hellebrand, Sybille}, year={2015}, pages={349–359} }'
chicago: 'Huang, Zhengfeng, Huaguo Liang, and Sybille Hellebrand. “A High Performance
SEU Tolerant Latch.” Journal of Electronic Testing - Theory and Applications
(JETTA) 31, no. 4 (2015): 349–59.'
ieee: Z. Huang, H. Liang, and S. Hellebrand, “A High Performance SEU Tolerant Latch,”
Journal of Electronic Testing - Theory and Applications (JETTA), vol. 31,
no. 4, pp. 349–359, 2015.
mla: Huang, Zhengfeng, et al. “A High Performance SEU Tolerant Latch.” Journal
of Electronic Testing - Theory and Applications (JETTA), vol. 31, no. 4, Springer,
2015, pp. 349–59.
short: Z. Huang, H. Liang, S. Hellebrand, Journal of Electronic Testing - Theory
and Applications (JETTA) 31 (2015) 349–359.
date_created: 2019-08-28T11:48:55Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '48'
intvolume: ' 31'
issue: '4'
language:
- iso: eng
page: 349-359
publication: Journal of Electronic Testing - Theory and Applications (JETTA)
publisher: Springer
status: public
title: A High Performance SEU Tolerant Latch
type: journal_article
user_id: '209'
volume: 31
year: '2015'
...
---
_id: '13077'
author:
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Thomas
full_name: Indlekofer, Thomas
last_name: Indlekofer
- first_name: Matthias
full_name: Kampmann, Matthias
id: '10935'
last_name: Kampmann
- first_name: Michael
full_name: Kochte, Michael
last_name: Kochte
- first_name: Chang
full_name: Liu, Chang
last_name: Liu
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
citation:
ama: Hellebrand S, Indlekofer T, Kampmann M, Kochte M, Liu C, Wunderlich H-J. Effiziente
Auswahl von Testfrequenzen Für Den Test Kleiner Verzögerungsfehler. 27. Workshop
“Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad
Urach, Germany; 2015.
apa: Hellebrand, S., Indlekofer, T., Kampmann, M., Kochte, M., Liu, C., & Wunderlich,
H.-J. (2015). Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler.
27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15),
Bad Urach, Germany.
bibtex: '@book{Hellebrand_Indlekofer_Kampmann_Kochte_Liu_Wunderlich_2015, place={27.
Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15),
Bad Urach, Germany}, title={Effiziente Auswahl von Testfrequenzen für den Test
kleiner Verzögerungsfehler}, author={Hellebrand, Sybille and Indlekofer, Thomas
and Kampmann, Matthias and Kochte, Michael and Liu, Chang and Wunderlich, Hans-Joachim},
year={2015} }'
chicago: Hellebrand, Sybille, Thomas Indlekofer, Matthias Kampmann, Michael Kochte,
Chang Liu, and Hans-Joachim Wunderlich. Effiziente Auswahl von Testfrequenzen
Für Den Test Kleiner Verzögerungsfehler. 27. Workshop “Testmethoden und Zuverlässigkeit
von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany, 2015.
ieee: S. Hellebrand, T. Indlekofer, M. Kampmann, M. Kochte, C. Liu, and H.-J. Wunderlich,
Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler.
27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15),
Bad Urach, Germany, 2015.
mla: Hellebrand, Sybille, et al. Effiziente Auswahl von Testfrequenzen Für Den
Test Kleiner Verzögerungsfehler. 2015.
short: S. Hellebrand, T. Indlekofer, M. Kampmann, M. Kochte, C. Liu, H.-J. Wunderlich,
Effiziente Auswahl von Testfrequenzen Für Den Test Kleiner Verzögerungsfehler,
27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15),
Bad Urach, Germany, 2015.
date_created: 2019-08-28T12:05:44Z
date_updated: 2022-01-06T06:51:28Z
department:
- _id: '48'
keyword:
- Workshop
language:
- iso: eng
place: 27. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
(TuZ'15), Bad Urach, Germany
status: public
title: Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler
type: misc
user_id: '659'
year: '2015'
...
---
_id: '29465'
abstract:
- lang: eng
text: Transistor and interconnect wearout is accelerated with transistor scaling
resulting in timing variations and consequently reliability challenges in digital
circuits. Age monitoring methods can be used to predict and deal with the aging
problem. Selecting appropriate locations for placement of hardware aging monitors
is an important issue. In this work we propose a procedure for selection of appropriate
internal nodes in combinational clouds between pipeline stages or combinational
parts of a sequential circuit to place hardware monitors that can effectively
provide aging information of various components of a modern digital system. In
order to implement the node selection procedure, we propose an object-oriented
model. Object-oriented model of a circuit along with a probabilistic and logical
simulation engine that we have developed can effectively be used for implementation
and also fast evaluation of the proposed node selection mechanism. The proposed
object-oriented C+ + models can be integrated into a SystemC RTL model making
it possible to perform mixed-level simulation, and integrated evaluation of a
complete system. We have applied our proposed scheme to several processors including
MIPS, ARM, ALPHA and MiniRISC and have looked at its effectiveness for these processors.
author:
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
- first_name: Arezoo
full_name: Kamran, Arezoo
last_name: Kamran
- first_name: Farnaz
full_name: Forooghifar, Farnaz
last_name: Forooghifar
- first_name: Zainalabedin
full_name: Navabi, Zainalabedin
last_name: Navabi
citation:
ama: 'Sadeghi-Kohan S, Kamran A, Forooghifar F, Navabi Z. Aging in digital circuits
and age monitoring: Object-oriented modeling and evaluation. In: 2015 10th
International Conference on Design & Technology of Integrated Systems in Nanoscale
Era (DTIS). IEEE; 2015. doi:10.1109/dtis.2015.7127373'
apa: 'Sadeghi-Kohan, S., Kamran, A., Forooghifar, F., & Navabi, Z. (2015). Aging
in digital circuits and age monitoring: Object-oriented modeling and evaluation.
2015 10th International Conference on Design & Technology of Integrated
Systems in Nanoscale Era (DTIS). https://doi.org/10.1109/dtis.2015.7127373'
bibtex: '@inproceedings{Sadeghi-Kohan_Kamran_Forooghifar_Navabi_2015, title={Aging
in digital circuits and age monitoring: Object-oriented modeling and evaluation},
DOI={10.1109/dtis.2015.7127373},
booktitle={2015 10th International Conference on Design & Technology of Integrated
Systems in Nanoscale Era (DTIS)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh
and Kamran, Arezoo and Forooghifar, Farnaz and Navabi, Zainalabedin}, year={2015}
}'
chicago: 'Sadeghi-Kohan, Somayeh, Arezoo Kamran, Farnaz Forooghifar, and Zainalabedin
Navabi. “Aging in Digital Circuits and Age Monitoring: Object-Oriented Modeling
and Evaluation.” In 2015 10th International Conference on Design & Technology
of Integrated Systems in Nanoscale Era (DTIS). IEEE, 2015. https://doi.org/10.1109/dtis.2015.7127373.'
ieee: 'S. Sadeghi-Kohan, A. Kamran, F. Forooghifar, and Z. Navabi, “Aging in digital
circuits and age monitoring: Object-oriented modeling and evaluation,” 2015, doi:
10.1109/dtis.2015.7127373.'
mla: 'Sadeghi-Kohan, Somayeh, et al. “Aging in Digital Circuits and Age Monitoring:
Object-Oriented Modeling and Evaluation.” 2015 10th International Conference
on Design & Technology of Integrated Systems in Nanoscale Era (DTIS),
IEEE, 2015, doi:10.1109/dtis.2015.7127373.'
short: 'S. Sadeghi-Kohan, A. Kamran, F. Forooghifar, Z. Navabi, in: 2015 10th International
Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS),
IEEE, 2015.'
date_created: 2022-01-19T13:51:35Z
date_updated: 2023-08-02T11:35:56Z
department:
- _id: '48'
doi: 10.1109/dtis.2015.7127373
extern: '1'
language:
- iso: eng
publication: 2015 10th International Conference on Design & Technology of Integrated
Systems in Nanoscale Era (DTIS)
publication_status: published
publisher: IEEE
status: public
title: 'Aging in digital circuits and age monitoring: Object-oriented modeling and
evaluation'
type: conference
user_id: '78614'
year: '2015'
...
---
_id: '29466'
abstract:
- lang: eng
text: Transistor and interconnect wearout is accelerated with transistor scaling
that results in timing variations. Progressive age measurement of a circuit can
help a better prevention mechanism for reducing more aging. This requires age
monitors that collect progressive age information of the circuit. This paper focuses
on monitor structures for implementation of progressive age detection. The monitors
are self-adjusting that they adjust themselves to detect progressive changes in
the timing of a circuit. Furthermore, the monitors are designed for low hardware
overhead, and certainty in reported timing changes.
author:
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
- first_name: Mehdi
full_name: Kamal, Mehdi
last_name: Kamal
- first_name: John
full_name: McNeil, John
last_name: McNeil
- first_name: Paolo
full_name: Prinetto, Paolo
last_name: Prinetto
- first_name: Zain
full_name: Navabi, Zain
last_name: Navabi
citation:
ama: 'Sadeghi-Kohan S, Kamal M, McNeil J, Prinetto P, Navabi Z. Online self adjusting
progressive age monitoring of timing variations. In: 2015 10th International
Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).
IEEE; 2015. doi:10.1109/dtis.2015.7127368'
apa: Sadeghi-Kohan, S., Kamal, M., McNeil, J., Prinetto, P., & Navabi, Z. (2015).
Online self adjusting progressive age monitoring of timing variations. 2015
10th International Conference on Design & Technology of Integrated Systems
in Nanoscale Era (DTIS). https://doi.org/10.1109/dtis.2015.7127368
bibtex: '@inproceedings{Sadeghi-Kohan_Kamal_McNeil_Prinetto_Navabi_2015, title={Online
self adjusting progressive age monitoring of timing variations}, DOI={10.1109/dtis.2015.7127368},
booktitle={2015 10th International Conference on Design & Technology of Integrated
Systems in Nanoscale Era (DTIS)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh
and Kamal, Mehdi and McNeil, John and Prinetto, Paolo and Navabi, Zain}, year={2015}
}'
chicago: Sadeghi-Kohan, Somayeh, Mehdi Kamal, John McNeil, Paolo Prinetto, and Zain
Navabi. “Online Self Adjusting Progressive Age Monitoring of Timing Variations.”
In 2015 10th International Conference on Design & Technology of Integrated
Systems in Nanoscale Era (DTIS). IEEE, 2015. https://doi.org/10.1109/dtis.2015.7127368.
ieee: 'S. Sadeghi-Kohan, M. Kamal, J. McNeil, P. Prinetto, and Z. Navabi, “Online
self adjusting progressive age monitoring of timing variations,” 2015, doi: 10.1109/dtis.2015.7127368.'
mla: Sadeghi-Kohan, Somayeh, et al. “Online Self Adjusting Progressive Age Monitoring
of Timing Variations.” 2015 10th International Conference on Design & Technology
of Integrated Systems in Nanoscale Era (DTIS), IEEE, 2015, doi:10.1109/dtis.2015.7127368.
short: 'S. Sadeghi-Kohan, M. Kamal, J. McNeil, P. Prinetto, Z. Navabi, in: 2015
10th International Conference on Design & Technology of Integrated Systems
in Nanoscale Era (DTIS), IEEE, 2015.'
date_created: 2022-01-19T13:52:32Z
date_updated: 2023-08-02T11:36:58Z
department:
- _id: '48'
doi: 10.1109/dtis.2015.7127368
extern: '1'
language:
- iso: eng
publication: 2015 10th International Conference on Design & Technology of Integrated
Systems in Nanoscale Era (DTIS)
publication_status: published
publisher: IEEE
status: public
title: Online self adjusting progressive age monitoring of timing variations
type: conference
user_id: '78614'
year: '2015'
...
---
_id: '12977'
author:
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Thomas
full_name: Indlekofer, Thomas
last_name: Indlekofer
- first_name: Matthias
full_name: Kampmann, Matthias
id: '10935'
last_name: Kampmann
- first_name: Michael
full_name: A. Kochte, Michael
last_name: A. Kochte
- first_name: Chang
full_name: Liu, Chang
last_name: Liu
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
citation:
ama: 'Hellebrand S, Indlekofer T, Kampmann M, A. Kochte M, Liu C, Wunderlich H-J.
FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects. In: IEEE
International Test Conference (ITC’14). Seattle, Washington, USA: IEEE; 2014.
doi:10.1109/test.2014.7035360'
apa: 'Hellebrand, S., Indlekofer, T., Kampmann, M., A. Kochte, M., Liu, C., &
Wunderlich, H.-J. (2014). FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden
Delay Defects. In IEEE International Test Conference (ITC’14). Seattle,
Washington, USA: IEEE. https://doi.org/10.1109/test.2014.7035360'
bibtex: '@inproceedings{Hellebrand_Indlekofer_Kampmann_A. Kochte_Liu_Wunderlich_2014,
place={Seattle, Washington, USA}, title={FAST-BIST: Faster-than-at-Speed BIST
Targeting Hidden Delay Defects}, DOI={10.1109/test.2014.7035360},
booktitle={IEEE International Test Conference (ITC’14)}, publisher={IEEE}, author={Hellebrand,
Sybille and Indlekofer, Thomas and Kampmann, Matthias and A. Kochte, Michael and
Liu, Chang and Wunderlich, Hans-Joachim}, year={2014} }'
chicago: 'Hellebrand, Sybille, Thomas Indlekofer, Matthias Kampmann, Michael A.
Kochte, Chang Liu, and Hans-Joachim Wunderlich. “FAST-BIST: Faster-than-at-Speed
BIST Targeting Hidden Delay Defects.” In IEEE International Test Conference
(ITC’14). Seattle, Washington, USA: IEEE, 2014. https://doi.org/10.1109/test.2014.7035360.'
ieee: 'S. Hellebrand, T. Indlekofer, M. Kampmann, M. A. Kochte, C. Liu, and H.-J.
Wunderlich, “FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects,”
in IEEE International Test Conference (ITC’14), 2014.'
mla: 'Hellebrand, Sybille, et al. “FAST-BIST: Faster-than-at-Speed BIST Targeting
Hidden Delay Defects.” IEEE International Test Conference (ITC’14), IEEE,
2014, doi:10.1109/test.2014.7035360.'
short: 'S. Hellebrand, T. Indlekofer, M. Kampmann, M. A. Kochte, C. Liu, H.-J. Wunderlich,
in: IEEE International Test Conference (ITC’14), IEEE, Seattle, Washington, USA,
2014.'
date_created: 2019-08-28T09:04:45Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '48'
doi: 10.1109/test.2014.7035360
language:
- iso: eng
place: Seattle, Washington, USA
publication: IEEE International Test Conference (ITC'14)
publisher: IEEE
status: public
title: 'FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects'
type: conference
user_id: '209'
year: '2014'
...
---
_id: '13054'
author:
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
citation:
ama: Hellebrand S, Wunderlich H-J. SAT-Based ATPG beyond Stuck-at Fault Testing.
DeGruyter Journal on Information Technology (it). 2014;56(4):165-172.
apa: Hellebrand, S., & Wunderlich, H.-J. (2014). SAT-Based ATPG beyond Stuck-at
Fault Testing. DeGruyter Journal on Information Technology (It), 56(4),
165–172.
bibtex: '@article{Hellebrand_Wunderlich_2014, title={SAT-Based ATPG beyond Stuck-at
Fault Testing}, volume={56}, number={4}, journal={DeGruyter Journal on Information
Technology (it)}, publisher={DeGruyter}, author={Hellebrand, Sybille and Wunderlich,
Hans-Joachim}, year={2014}, pages={165–172} }'
chicago: 'Hellebrand, Sybille, and Hans-Joachim Wunderlich. “SAT-Based ATPG beyond
Stuck-at Fault Testing.” DeGruyter Journal on Information Technology (It)
56, no. 4 (2014): 165–72.'
ieee: S. Hellebrand and H.-J. Wunderlich, “SAT-Based ATPG beyond Stuck-at Fault
Testing,” DeGruyter Journal on Information Technology (it), vol. 56, no.
4, pp. 165–172, 2014.
mla: Hellebrand, Sybille, and Hans-Joachim Wunderlich. “SAT-Based ATPG beyond Stuck-at
Fault Testing.” DeGruyter Journal on Information Technology (It), vol.
56, no. 4, DeGruyter, 2014, pp. 165–72.
short: S. Hellebrand, H.-J. Wunderlich, DeGruyter Journal on Information Technology
(It) 56 (2014) 165–172.
date_created: 2019-08-28T11:48:13Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '48'
intvolume: ' 56'
issue: '4'
language:
- iso: eng
page: 165-172
publication: DeGruyter Journal on Information Technology (it)
publisher: DeGruyter
status: public
title: SAT-Based ATPG beyond Stuck-at Fault Testing
type: journal_article
user_id: '209'
volume: 56
year: '2014'
...
---
_id: '13055'
author:
- first_name: Laura
full_name: Rodriguez Gomez, Laura
last_name: Rodriguez Gomez
- first_name: Alejandro
full_name: Cook, Alejandro
last_name: Cook
- first_name: Thomas
full_name: Indlekofer, Thomas
last_name: Indlekofer
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
citation:
ama: Rodriguez Gomez L, Cook A, Indlekofer T, Hellebrand S, Wunderlich H-J. Adaptive
Bayesian Diagnosis of Intermittent Faults. Journal of Electronic Testing -
Theory and Applications (JETTA). 2014;30(5):527-540.
apa: Rodriguez Gomez, L., Cook, A., Indlekofer, T., Hellebrand, S., & Wunderlich,
H.-J. (2014). Adaptive Bayesian Diagnosis of Intermittent Faults. Journal of
Electronic Testing - Theory and Applications (JETTA), 30(5), 527–540.
bibtex: '@article{Rodriguez Gomez_Cook_Indlekofer_Hellebrand_Wunderlich_2014, title={Adaptive
Bayesian Diagnosis of Intermittent Faults}, volume={30}, number={5}, journal={Journal
of Electronic Testing - Theory and Applications (JETTA)}, publisher={Springer},
author={Rodriguez Gomez, Laura and Cook, Alejandro and Indlekofer, Thomas and
Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2014}, pages={527–540}
}'
chicago: 'Rodriguez Gomez, Laura, Alejandro Cook, Thomas Indlekofer, Sybille Hellebrand,
and Hans-Joachim Wunderlich. “Adaptive Bayesian Diagnosis of Intermittent Faults.”
Journal of Electronic Testing - Theory and Applications (JETTA) 30, no.
5 (2014): 527–40.'
ieee: L. Rodriguez Gomez, A. Cook, T. Indlekofer, S. Hellebrand, and H.-J. Wunderlich,
“Adaptive Bayesian Diagnosis of Intermittent Faults,” Journal of Electronic
Testing - Theory and Applications (JETTA), vol. 30, no. 5, pp. 527–540, 2014.
mla: Rodriguez Gomez, Laura, et al. “Adaptive Bayesian Diagnosis of Intermittent
Faults.” Journal of Electronic Testing - Theory and Applications (JETTA),
vol. 30, no. 5, Springer, 2014, pp. 527–40.
short: L. Rodriguez Gomez, A. Cook, T. Indlekofer, S. Hellebrand, H.-J. Wunderlich,
Journal of Electronic Testing - Theory and Applications (JETTA) 30 (2014) 527–540.
date_created: 2019-08-28T11:48:33Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '48'
intvolume: ' 30'
issue: '5'
language:
- iso: eng
page: 527-540
publication: Journal of Electronic Testing - Theory and Applications (JETTA)
publisher: Springer
status: public
title: Adaptive Bayesian Diagnosis of Intermittent Faults
type: journal_article
user_id: '209'
volume: 30
year: '2014'
...
---
_id: '46266'
author:
- first_name: Bijan
full_name: Alizadeh, Bijan
last_name: Alizadeh
- first_name: Payman
full_name: Behnam, Payman
last_name: Behnam
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
citation:
ama: Alizadeh B, Behnam P, Sadeghi-Kohan S. A Scalable Formal Debugging Approach
with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for
RTL Datapath Designs. IEEE Transactions on Computers. Published online
2014:1-1. doi:10.1109/tc.2014.2329687
apa: Alizadeh, B., Behnam, P., & Sadeghi-Kohan, S. (2014). A Scalable Formal
Debugging Approach with Auto-Correction Capability based on Static Slicing and
Dynamic Ranking for RTL Datapath Designs. IEEE Transactions on Computers,
1–1. https://doi.org/10.1109/tc.2014.2329687
bibtex: '@article{Alizadeh_Behnam_Sadeghi-Kohan_2014, title={A Scalable Formal Debugging
Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking
for RTL Datapath Designs}, DOI={10.1109/tc.2014.2329687},
journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and
Electronics Engineers (IEEE)}, author={Alizadeh, Bijan and Behnam, Payman and
Sadeghi-Kohan, Somayeh}, year={2014}, pages={1–1} }'
chicago: Alizadeh, Bijan, Payman Behnam, and Somayeh Sadeghi-Kohan. “A Scalable
Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing
and Dynamic Ranking for RTL Datapath Designs.” IEEE Transactions on Computers,
2014, 1–1. https://doi.org/10.1109/tc.2014.2329687.
ieee: 'B. Alizadeh, P. Behnam, and S. Sadeghi-Kohan, “A Scalable Formal Debugging
Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking
for RTL Datapath Designs,” IEEE Transactions on Computers, pp. 1–1, 2014,
doi: 10.1109/tc.2014.2329687.'
mla: Alizadeh, Bijan, et al. “A Scalable Formal Debugging Approach with Auto-Correction
Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs.”
IEEE Transactions on Computers, Institute of Electrical and Electronics
Engineers (IEEE), 2014, pp. 1–1, doi:10.1109/tc.2014.2329687.
short: B. Alizadeh, P. Behnam, S. Sadeghi-Kohan, IEEE Transactions on Computers
(2014) 1–1.
date_created: 2023-08-02T11:15:22Z
date_updated: 2023-08-02T11:32:37Z
department:
- _id: '48'
doi: 10.1109/tc.2014.2329687
extern: '1'
keyword:
- Computational Theory and Mathematics
- Hardware and Architecture
- Theoretical Computer Science
- Software
language:
- iso: eng
page: 1-1
publication: IEEE Transactions on Computers
publication_identifier:
issn:
- 0018-9340
publication_status: published
publisher: Institute of Electrical and Electronics Engineers (IEEE)
status: public
title: A Scalable Formal Debugging Approach with Auto-Correction Capability based
on Static Slicing and Dynamic Ranking for RTL Datapath Designs
type: journal_article
user_id: '78614'
year: '2014'
...
---
_id: '46268'
author:
- first_name: Marzieh
full_name: Mohammadi, Marzieh
last_name: Mohammadi
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
- first_name: Nasser
full_name: Masoumi, Nasser
last_name: Masoumi
- first_name: Zainalabedin
full_name: Navabi, Zainalabedin
last_name: Navabi
citation:
ama: 'Mohammadi M, Sadeghi-Kohan S, Masoumi N, Navabi Z. An off-line MDSI interconnect
BIST incorporated in BS 1149.1. In: 2014 19th IEEE European Test Symposium
(ETS). IEEE; 2014. doi:10.1109/ets.2014.6847847'
apa: Mohammadi, M., Sadeghi-Kohan, S., Masoumi, N., & Navabi, Z. (2014). An
off-line MDSI interconnect BIST incorporated in BS 1149.1. 2014 19th IEEE European
Test Symposium (ETS). https://doi.org/10.1109/ets.2014.6847847
bibtex: '@inproceedings{Mohammadi_Sadeghi-Kohan_Masoumi_Navabi_2014, title={An off-line
MDSI interconnect BIST incorporated in BS 1149.1}, DOI={10.1109/ets.2014.6847847},
booktitle={2014 19th IEEE European Test Symposium (ETS)}, publisher={IEEE}, author={Mohammadi,
Marzieh and Sadeghi-Kohan, Somayeh and Masoumi, Nasser and Navabi, Zainalabedin},
year={2014} }'
chicago: Mohammadi, Marzieh, Somayeh Sadeghi-Kohan, Nasser Masoumi, and Zainalabedin
Navabi. “An Off-Line MDSI Interconnect BIST Incorporated in BS 1149.1.” In 2014
19th IEEE European Test Symposium (ETS). IEEE, 2014. https://doi.org/10.1109/ets.2014.6847847.
ieee: 'M. Mohammadi, S. Sadeghi-Kohan, N. Masoumi, and Z. Navabi, “An off-line MDSI
interconnect BIST incorporated in BS 1149.1,” 2014, doi: 10.1109/ets.2014.6847847.'
mla: Mohammadi, Marzieh, et al. “An Off-Line MDSI Interconnect BIST Incorporated
in BS 1149.1.” 2014 19th IEEE European Test Symposium (ETS), IEEE, 2014,
doi:10.1109/ets.2014.6847847.
short: 'M. Mohammadi, S. Sadeghi-Kohan, N. Masoumi, Z. Navabi, in: 2014 19th IEEE
European Test Symposium (ETS), IEEE, 2014.'
date_created: 2023-08-02T11:18:26Z
date_updated: 2023-08-02T11:32:48Z
department:
- _id: '48'
doi: 10.1109/ets.2014.6847847
extern: '1'
language:
- iso: eng
publication: 2014 19th IEEE European Test Symposium (ETS)
publication_status: published
publisher: IEEE
status: public
title: An off-line MDSI interconnect BIST incorporated in BS 1149.1
type: conference
user_id: '78614'
year: '2014'
...
---
_id: '46267'
author:
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
- first_name: Payman
full_name: Behnam, Payman
last_name: Behnam
- first_name: Bijan
full_name: Alizadeh, Bijan
last_name: Alizadeh
- first_name: Masahiro
full_name: Fujita, Masahiro
last_name: Fujita
- first_name: Zainalabedin
full_name: Navabi, Zainalabedin
last_name: Navabi
citation:
ama: 'Sadeghi-Kohan S, Behnam P, Alizadeh B, Fujita M, Navabi Z. Improving polynomial
datapath debugging with HEDs. In: 2014 19th IEEE European Test Symposium (ETS).
IEEE; 2014. doi:10.1109/ets.2014.6847797'
apa: Sadeghi-Kohan, S., Behnam, P., Alizadeh, B., Fujita, M., & Navabi, Z. (2014).
Improving polynomial datapath debugging with HEDs. 2014 19th IEEE European
Test Symposium (ETS). https://doi.org/10.1109/ets.2014.6847797
bibtex: '@inproceedings{Sadeghi-Kohan_Behnam_Alizadeh_Fujita_Navabi_2014, title={Improving
polynomial datapath debugging with HEDs}, DOI={10.1109/ets.2014.6847797},
booktitle={2014 19th IEEE European Test Symposium (ETS)}, publisher={IEEE}, author={Sadeghi-Kohan,
Somayeh and Behnam, Payman and Alizadeh, Bijan and Fujita, Masahiro and Navabi,
Zainalabedin}, year={2014} }'
chicago: Sadeghi-Kohan, Somayeh, Payman Behnam, Bijan Alizadeh, Masahiro Fujita,
and Zainalabedin Navabi. “Improving Polynomial Datapath Debugging with HEDs.”
In 2014 19th IEEE European Test Symposium (ETS). IEEE, 2014. https://doi.org/10.1109/ets.2014.6847797.
ieee: 'S. Sadeghi-Kohan, P. Behnam, B. Alizadeh, M. Fujita, and Z. Navabi, “Improving
polynomial datapath debugging with HEDs,” 2014, doi: 10.1109/ets.2014.6847797.'
mla: Sadeghi-Kohan, Somayeh, et al. “Improving Polynomial Datapath Debugging with
HEDs.” 2014 19th IEEE European Test Symposium (ETS), IEEE, 2014, doi:10.1109/ets.2014.6847797.
short: 'S. Sadeghi-Kohan, P. Behnam, B. Alizadeh, M. Fujita, Z. Navabi, in: 2014
19th IEEE European Test Symposium (ETS), IEEE, 2014.'
date_created: 2023-08-02T11:17:08Z
date_updated: 2023-08-02T11:34:10Z
department:
- _id: '48'
doi: 10.1109/ets.2014.6847797
extern: '1'
language:
- iso: eng
publication: 2014 19th IEEE European Test Symposium (ETS)
publication_status: published
publisher: IEEE
status: public
title: Improving polynomial datapath debugging with HEDs
type: conference
user_id: '78614'
year: '2014'
...