--- _id: '13051' author: - first_name: Marc full_name: Hunger, Marc last_name: Hunger - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: 'Hunger M, Hellebrand S. Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz. In: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” Wildbad Kreuth, Germany; 2010:81-88.' apa: Hunger, M., & Hellebrand, S. (2010). Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz. In 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf” (pp. 81–88). Wildbad Kreuth, Germany. bibtex: '@inproceedings{Hunger_Hellebrand_2010, place={Wildbad Kreuth, Germany}, title={Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz}, booktitle={4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf”}, author={Hunger, Marc and Hellebrand, Sybille}, year={2010}, pages={81–88} }' chicago: Hunger, Marc, and Sybille Hellebrand. “Ausbeute Und Fehlertoleranz Bei Dreifach Modularer Redundanz.” In 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 81–88. Wildbad Kreuth, Germany, 2010. ieee: M. Hunger and S. Hellebrand, “Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz,” in 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf,” 2010, pp. 81–88. mla: Hunger, Marc, and Sybille Hellebrand. “Ausbeute Und Fehlertoleranz Bei Dreifach Modularer Redundanz.” 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2010, pp. 81–88. short: 'M. Hunger, S. Hellebrand, in: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Wildbad Kreuth, Germany, 2010, pp. 81–88.' date_created: 2019-08-28T11:46:41Z date_updated: 2022-01-06T06:51:27Z department: - _id: '48' language: - iso: eng page: 81-88 place: Wildbad Kreuth, Germany publication: 4. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf" status: public title: Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz type: conference user_id: '659' year: '2010' ... --- _id: '13073' author: - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: Hellebrand S. Nano-Electronic Systems. Editorial, it 4/2010, pp. 179-180; 2010. apa: Hellebrand, S. (2010). Nano-Electronic Systems. Editorial, it 4/2010, pp. 179-180. bibtex: '@book{Hellebrand_2010, place={Editorial, it 4/2010, pp. 179-180}, title={Nano-Electronic Systems}, author={Hellebrand, Sybille}, year={2010} }' chicago: Hellebrand, Sybille. Nano-Electronic Systems. Editorial, it 4/2010, pp. 179-180, 2010. ieee: S. Hellebrand, Nano-Electronic Systems. Editorial, it 4/2010, pp. 179-180, 2010. mla: Hellebrand, Sybille. Nano-Electronic Systems. 2010. short: S. Hellebrand, Nano-Electronic Systems, Editorial, it 4/2010, pp. 179-180, 2010. date_created: 2019-08-28T12:01:06Z date_updated: 2022-01-06T06:51:28Z department: - _id: '48' language: - iso: eng place: Editorial, it 4/2010, pp. 179-180 status: public title: Nano-Electronic Systems type: misc user_id: '659' year: '2010' ... --- _id: '12983' author: - first_name: Fabian full_name: Hopsch, Fabian last_name: Hopsch - first_name: Bernd full_name: Becker, Bernd last_name: Becker - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Ilia full_name: Polian, Ilia last_name: Polian - first_name: Bernd full_name: Straube, Bernd last_name: Straube - first_name: Wolfgang full_name: Vermeiren, Wolfgang last_name: Vermeiren - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich citation: ama: 'Hopsch F, Becker B, Hellebrand S, et al. Variation-Aware Fault Modeling. In: 19th IEEE Asian Test Symposium (ATS’10). IEEE; 2010:87-93. doi:10.1109/ats.2010.24' apa: Hopsch, F., Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., & Wunderlich, H.-J. (2010). Variation-Aware Fault Modeling. 19th IEEE Asian Test Symposium (ATS’10), 87–93. https://doi.org/10.1109/ats.2010.24 bibtex: '@inproceedings{Hopsch_Becker_Hellebrand_Polian_Straube_Vermeiren_Wunderlich_2010, place={Shanghai, China}, title={Variation-Aware Fault Modeling}, DOI={10.1109/ats.2010.24}, booktitle={19th IEEE Asian Test Symposium (ATS’10)}, publisher={IEEE}, author={Hopsch, Fabian and Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans-Joachim}, year={2010}, pages={87–93} }' chicago: 'Hopsch, Fabian, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, and Hans-Joachim Wunderlich. “Variation-Aware Fault Modeling.” In 19th IEEE Asian Test Symposium (ATS’10), 87–93. Shanghai, China: IEEE, 2010. https://doi.org/10.1109/ats.2010.24.' ieee: 'F. Hopsch et al., “Variation-Aware Fault Modeling,” in 19th IEEE Asian Test Symposium (ATS’10), 2010, pp. 87–93, doi: 10.1109/ats.2010.24.' mla: Hopsch, Fabian, et al. “Variation-Aware Fault Modeling.” 19th IEEE Asian Test Symposium (ATS’10), IEEE, 2010, pp. 87–93, doi:10.1109/ats.2010.24. short: 'F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: 19th IEEE Asian Test Symposium (ATS’10), IEEE, Shanghai, China, 2010, pp. 87–93.' date_created: 2019-08-28T09:20:51Z date_updated: 2022-05-11T16:20:07Z department: - _id: '48' doi: 10.1109/ats.2010.24 language: - iso: eng page: 87-93 place: Shanghai, China publication: 19th IEEE Asian Test Symposium (ATS'10) publisher: IEEE status: public title: Variation-Aware Fault Modeling type: conference user_id: '209' year: '2010' ... --- _id: '12985' author: - first_name: Thomas full_name: Indlekofer, Thomas last_name: Indlekofer - first_name: Michael full_name: Schnittger, Michael last_name: Schnittger - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: 'Indlekofer T, Schnittger M, Hellebrand S. Efficient Test Response Compaction for Robust BIST Using Parity Sequences. In: 28th IEEE International Conference on Computer Design (ICCD’10). IEEE; 2010:480-485. doi:10.1109/iccd.2010.5647648' apa: Indlekofer, T., Schnittger, M., & Hellebrand, S. (2010). Efficient Test Response Compaction for Robust BIST Using Parity Sequences. 28th IEEE International Conference on Computer Design (ICCD’10), 480–485. https://doi.org/10.1109/iccd.2010.5647648 bibtex: '@inproceedings{Indlekofer_Schnittger_Hellebrand_2010, place={Amsterdam, The Netherlands}, title={Efficient Test Response Compaction for Robust BIST Using Parity Sequences}, DOI={10.1109/iccd.2010.5647648}, booktitle={28th IEEE International Conference on Computer Design (ICCD’10)}, publisher={IEEE}, author={Indlekofer, Thomas and Schnittger, Michael and Hellebrand, Sybille}, year={2010}, pages={480–485} }' chicago: 'Indlekofer, Thomas, Michael Schnittger, and Sybille Hellebrand. “Efficient Test Response Compaction for Robust BIST Using Parity Sequences.” In 28th IEEE International Conference on Computer Design (ICCD’10), 480–85. Amsterdam, The Netherlands: IEEE, 2010. https://doi.org/10.1109/iccd.2010.5647648.' ieee: 'T. Indlekofer, M. Schnittger, and S. Hellebrand, “Efficient Test Response Compaction for Robust BIST Using Parity Sequences,” in 28th IEEE International Conference on Computer Design (ICCD’10), 2010, pp. 480–485, doi: 10.1109/iccd.2010.5647648.' mla: Indlekofer, Thomas, et al. “Efficient Test Response Compaction for Robust BIST Using Parity Sequences.” 28th IEEE International Conference on Computer Design (ICCD’10), IEEE, 2010, pp. 480–85, doi:10.1109/iccd.2010.5647648. short: 'T. Indlekofer, M. Schnittger, S. Hellebrand, in: 28th IEEE International Conference on Computer Design (ICCD’10), IEEE, Amsterdam, The Netherlands, 2010, pp. 480–485.' date_created: 2019-08-28T09:21:55Z date_updated: 2022-05-11T16:21:12Z department: - _id: '48' doi: 10.1109/iccd.2010.5647648 language: - iso: eng page: 480-485 place: Amsterdam, The Netherlands publication: 28th IEEE International Conference on Computer Design (ICCD'10) publisher: IEEE status: public title: Efficient Test Response Compaction for Robust BIST Using Parity Sequences type: conference user_id: '209' year: '2010' ... --- _id: '12986' author: - first_name: Marc full_name: Hunger, Marc last_name: Hunger - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: 'Hunger M, Hellebrand S. The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems. In: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10). IEEE; 2010:101-108. doi:10.1109/dft.2010.19' apa: Hunger, M., & Hellebrand, S. (2010). The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems. 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), 101–108. https://doi.org/10.1109/dft.2010.19 bibtex: '@inproceedings{Hunger_Hellebrand_2010, place={Kyoto, Japan}, title={The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems}, DOI={10.1109/dft.2010.19}, booktitle={25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10)}, publisher={IEEE}, author={Hunger, Marc and Hellebrand, Sybille}, year={2010}, pages={101–108} }' chicago: 'Hunger, Marc, and Sybille Hellebrand. “The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems.” In 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), 101–8. Kyoto, Japan: IEEE, 2010. https://doi.org/10.1109/dft.2010.19.' ieee: 'M. Hunger and S. Hellebrand, “The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems,” in 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), 2010, pp. 101–108, doi: 10.1109/dft.2010.19.' mla: Hunger, Marc, and Sybille Hellebrand. “The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems.” 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), IEEE, 2010, pp. 101–08, doi:10.1109/dft.2010.19. short: 'M. Hunger, S. Hellebrand, in: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), IEEE, Kyoto, Japan, 2010, pp. 101–108.' date_created: 2019-08-28T09:21:57Z date_updated: 2022-05-11T16:21:52Z department: - _id: '48' doi: 10.1109/dft.2010.19 language: - iso: eng page: 101-108 place: Kyoto, Japan publication: 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'10) publisher: IEEE status: public title: The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems type: conference user_id: '209' year: '2010' ... --- _id: '12988' author: - first_name: Viktor full_name: Froese, Viktor last_name: Froese - first_name: Rüdiger full_name: Ibers, Rüdiger id: '659' last_name: Ibers - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: 'Froese V, Ibers R, Hellebrand S. Reusing NoC-Infrastructure for Test Data Compression. In: 28th IEEE VLSI Test Symposium (VTS’10). IEEE; 2010:227-231. doi:10.1109/vts.2010.5469570' apa: Froese, V., Ibers, R., & Hellebrand, S. (2010). Reusing NoC-Infrastructure for Test Data Compression. 28th IEEE VLSI Test Symposium (VTS’10), 227–231. https://doi.org/10.1109/vts.2010.5469570 bibtex: '@inproceedings{Froese_Ibers_Hellebrand_2010, place={Santa Cruz, CA, USA}, title={Reusing NoC-Infrastructure for Test Data Compression}, DOI={10.1109/vts.2010.5469570}, booktitle={28th IEEE VLSI Test Symposium (VTS’10)}, publisher={IEEE}, author={Froese, Viktor and Ibers, Rüdiger and Hellebrand, Sybille}, year={2010}, pages={227–231} }' chicago: 'Froese, Viktor, Rüdiger Ibers, and Sybille Hellebrand. “Reusing NoC-Infrastructure for Test Data Compression.” In 28th IEEE VLSI Test Symposium (VTS’10), 227–31. Santa Cruz, CA, USA: IEEE, 2010. https://doi.org/10.1109/vts.2010.5469570.' ieee: 'V. Froese, R. Ibers, and S. Hellebrand, “Reusing NoC-Infrastructure for Test Data Compression,” in 28th IEEE VLSI Test Symposium (VTS’10), 2010, pp. 227–231, doi: 10.1109/vts.2010.5469570.' mla: Froese, Viktor, et al. “Reusing NoC-Infrastructure for Test Data Compression.” 28th IEEE VLSI Test Symposium (VTS’10), IEEE, 2010, pp. 227–31, doi:10.1109/vts.2010.5469570. short: 'V. Froese, R. Ibers, S. Hellebrand, in: 28th IEEE VLSI Test Symposium (VTS’10), IEEE, Santa Cruz, CA, USA, 2010, pp. 227–231.' date_created: 2019-08-28T09:22:54Z date_updated: 2022-05-11T16:22:36Z department: - _id: '48' doi: 10.1109/vts.2010.5469570 language: - iso: eng page: 227-231 place: Santa Cruz, CA, USA publication: 28th IEEE VLSI Test Symposium (VTS'10) publisher: IEEE status: public title: Reusing NoC-Infrastructure for Test Data Compression type: conference user_id: '209' year: '2010' ... --- _id: '13049' author: - first_name: Bernd full_name: Becker, Bernd last_name: Becker - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Ilia full_name: Polian, Ilia last_name: Polian - first_name: Bernd full_name: Straube, Bernd last_name: Straube - first_name: Wolfgang full_name: Vermeiren, Wolfgang last_name: Vermeiren - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich citation: ama: 'Becker B, Hellebrand S, Polian I, Straube B, Vermeiren W, Wunderlich H-J. Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. In: 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper). ; 2010.' apa: Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., & Wunderlich, H.-J. (2010). Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper). bibtex: '@inproceedings{Becker_Hellebrand_Polian_Straube_Vermeiren_Wunderlich_2010, place={Chicago, IL, USA}, title={Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits}, booktitle={4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper)}, author={Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans-Joachim}, year={2010} }' chicago: Becker, Bernd, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, and Hans-Joachim Wunderlich. “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits.” In 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper). Chicago, IL, USA, 2010. ieee: B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, and H.-J. Wunderlich, “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits,” 2010. mla: Becker, Bernd, et al. “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits.” 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper), 2010. short: 'B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper), Chicago, IL, USA, 2010.' date_created: 2019-08-28T11:45:36Z date_updated: 2022-05-11T16:26:18Z department: - _id: '48' language: - iso: eng place: Chicago, IL, USA publication: 4th Workshop on Dependable and Secure Nanocomputing (WDSN'10), (Invited Paper) status: public title: Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits type: conference user_id: '209' year: '2010' ... --- _id: '13050' author: - first_name: Thomas full_name: Indlekofer, Thomas last_name: Indlekofer - first_name: Michael full_name: Schnittger, Michael last_name: Schnittger - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: 'Indlekofer T, Schnittger M, Hellebrand S. Robuster Selbsttest mit extremer Kompaktierung. In: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2010:17-24.' apa: Indlekofer, T., Schnittger, M., & Hellebrand, S. (2010). Robuster Selbsttest mit extremer Kompaktierung. 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 17–24. bibtex: '@inproceedings{Indlekofer_Schnittger_Hellebrand_2010, place={Wildbad Kreuth, Germany}, title={Robuster Selbsttest mit extremer Kompaktierung}, booktitle={4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf”}, author={Indlekofer, Thomas and Schnittger, Michael and Hellebrand, Sybille}, year={2010}, pages={17–24} }' chicago: Indlekofer, Thomas, Michael Schnittger, and Sybille Hellebrand. “Robuster Selbsttest Mit Extremer Kompaktierung.” In 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 17–24. Wildbad Kreuth, Germany, 2010. ieee: T. Indlekofer, M. Schnittger, and S. Hellebrand, “Robuster Selbsttest mit extremer Kompaktierung,” in 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf,” 2010, pp. 17–24. mla: Indlekofer, Thomas, et al. “Robuster Selbsttest Mit Extremer Kompaktierung.” 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2010, pp. 17–24. short: 'T. Indlekofer, M. Schnittger, S. Hellebrand, in: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Wildbad Kreuth, Germany, 2010, pp. 17–24.' date_created: 2019-08-28T11:46:13Z date_updated: 2022-05-11T16:25:34Z department: - _id: '48' language: - iso: eng page: 17-24 place: Wildbad Kreuth, Germany publication: 4. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf" status: public title: Robuster Selbsttest mit extremer Kompaktierung type: conference user_id: '209' year: '2010' ... --- _id: '12991' author: - first_name: Marc full_name: Hunger, Marc last_name: Hunger - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Alejandro full_name: Czutro, Alejandro last_name: Czutro - first_name: Ilia full_name: Polian, Ilia last_name: Polian - first_name: Bernd full_name: Becker, Bernd last_name: Becker citation: ama: 'Hunger M, Hellebrand S, Czutro A, Polian I, Becker B. ATPG-Based Grading of Strong Fault-Secureness. In: 15th IEEE International On-Line Testing Symposium (IOLTS’09. IEEE; 2009. doi:10.1109/iolts.2009.5196027' apa: Hunger, M., Hellebrand, S., Czutro, A., Polian, I., & Becker, B. (2009). ATPG-Based Grading of Strong Fault-Secureness. 15th IEEE International On-Line Testing Symposium (IOLTS’09. https://doi.org/10.1109/iolts.2009.5196027 bibtex: '@inproceedings{Hunger_Hellebrand_Czutro_Polian_Becker_2009, place={Sesimbra-Lisbon, Portugal}, title={ATPG-Based Grading of Strong Fault-Secureness}, DOI={10.1109/iolts.2009.5196027}, booktitle={15th IEEE International On-Line Testing Symposium (IOLTS’09}, publisher={IEEE}, author={Hunger, Marc and Hellebrand, Sybille and Czutro, Alejandro and Polian, Ilia and Becker, Bernd}, year={2009} }' chicago: 'Hunger, Marc, Sybille Hellebrand, Alejandro Czutro, Ilia Polian, and Bernd Becker. “ATPG-Based Grading of Strong Fault-Secureness.” In 15th IEEE International On-Line Testing Symposium (IOLTS’09. Sesimbra-Lisbon, Portugal: IEEE, 2009. https://doi.org/10.1109/iolts.2009.5196027.' ieee: 'M. Hunger, S. Hellebrand, A. Czutro, I. Polian, and B. Becker, “ATPG-Based Grading of Strong Fault-Secureness,” 2009, doi: 10.1109/iolts.2009.5196027.' mla: Hunger, Marc, et al. “ATPG-Based Grading of Strong Fault-Secureness.” 15th IEEE International On-Line Testing Symposium (IOLTS’09, IEEE, 2009, doi:10.1109/iolts.2009.5196027. short: 'M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, in: 15th IEEE International On-Line Testing Symposium (IOLTS’09, IEEE, Sesimbra-Lisbon, Portugal, 2009.' date_created: 2019-08-28T10:17:16Z date_updated: 2022-05-11T16:27:48Z department: - _id: '48' doi: 10.1109/iolts.2009.5196027 language: - iso: eng place: Sesimbra-Lisbon, Portugal publication: 15th IEEE International On-Line Testing Symposium (IOLTS'09 publisher: IEEE status: public title: ATPG-Based Grading of Strong Fault-Secureness type: conference user_id: '209' year: '2009' ... --- _id: '12990' author: - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Marc full_name: Hunger, Marc last_name: Hunger citation: ama: 'Hellebrand S, Hunger M. Are Robust Circuits Really Robust? In: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk). IEEE; 2009:77. doi:10.1109/dft.2009.28' apa: Hellebrand, S., & Hunger, M. (2009). Are Robust Circuits Really Robust? 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), 77. https://doi.org/10.1109/dft.2009.28 bibtex: '@inproceedings{Hellebrand_Hunger_2009, place={Chicago, IL, USA}, title={Are Robust Circuits Really Robust?}, DOI={10.1109/dft.2009.28}, booktitle={24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk)}, publisher={IEEE}, author={Hellebrand, Sybille and Hunger, Marc}, year={2009}, pages={77} }' chicago: 'Hellebrand, Sybille, and Marc Hunger. “Are Robust Circuits Really Robust?” In 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), 77. Chicago, IL, USA: IEEE, 2009. https://doi.org/10.1109/dft.2009.28.' ieee: 'S. Hellebrand and M. Hunger, “Are Robust Circuits Really Robust?,” in 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), 2009, p. 77, doi: 10.1109/dft.2009.28.' mla: Hellebrand, Sybille, and Marc Hunger. “Are Robust Circuits Really Robust?” 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), IEEE, 2009, p. 77, doi:10.1109/dft.2009.28. short: 'S. Hellebrand, M. Hunger, in: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), IEEE, Chicago, IL, USA, 2009, p. 77.' date_created: 2019-08-28T10:17:14Z date_updated: 2022-05-11T16:27:03Z department: - _id: '48' doi: 10.1109/dft.2009.28 language: - iso: eng page: '77' place: Chicago, IL, USA publication: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'09), (Invited Talk) publisher: IEEE status: public title: Are Robust Circuits Really Robust? type: conference user_id: '209' year: '2009' ... --- _id: '13030' author: - first_name: Marc full_name: Hunger, Marc last_name: Hunger - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Alexander full_name: Czutro, Alexander last_name: Czutro - first_name: Ilia full_name: Polian, Ilia last_name: Polian - first_name: Bernd full_name: Becker, Bernd last_name: Becker citation: ama: 'Hunger M, Hellebrand S, Czutro A, Polian I, Becker B. Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung. In: 3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2009.' apa: Hunger, M., Hellebrand, S., Czutro, A., Polian, I., & Becker, B. (2009). Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung. 3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” bibtex: '@inproceedings{Hunger_Hellebrand_Czutro_Polian_Becker_2009, place={Stuttgart, Germany}, title={Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung}, booktitle={3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf”}, author={Hunger, Marc and Hellebrand, Sybille and Czutro, Alexander and Polian, Ilia and Becker, Bernd}, year={2009} }' chicago: Hunger, Marc, Sybille Hellebrand, Alexander Czutro, Ilia Polian, and Bernd Becker. “Robustheitsanalyse Stark Fehlersicherer Schaltungen Mit SAT-Basierter Testmustererzeugung.” In 3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” Stuttgart, Germany, 2009. ieee: M. Hunger, S. Hellebrand, A. Czutro, I. Polian, and B. Becker, “Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung,” 2009. mla: Hunger, Marc, et al. “Robustheitsanalyse Stark Fehlersicherer Schaltungen Mit SAT-Basierter Testmustererzeugung.” 3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2009. short: 'M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, in: 3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Stuttgart, Germany, 2009.' date_created: 2019-08-28T10:35:48Z date_updated: 2022-05-11T16:28:31Z department: - _id: '48' language: - iso: eng place: Stuttgart, Germany publication: 3. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf" status: public title: Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung type: conference user_id: '209' year: '2009' ... --- _id: '13033' author: - first_name: Torsten full_name: Coym, Torsten last_name: Coym - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Stefan full_name: Ludwig, Stefan last_name: Ludwig - first_name: Bernd full_name: Straube, Bernd last_name: Straube - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich - first_name: Christian full_name: G. Zoellin, Christian last_name: G. Zoellin citation: ama: Coym T, Hellebrand S, Ludwig S, Straube B, Wunderlich H-J, G. Zoellin C. Ein Verfeinertes Elektrisches Modell Für Teilchentreffer Und Dessen Auswirkung Auf Die Bewertung Der Schaltungsempfindlichkeit. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich; 2008. apa: Coym, T., Hellebrand, S., Ludwig, S., Straube, B., Wunderlich, H.-J., & G. Zoellin, C. (2008). Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich. bibtex: '@book{Coym_Hellebrand_Ludwig_Straube_Wunderlich_G. Zoellin_2008, place={20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich}, title={Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit}, author={Coym, Torsten and Hellebrand, Sybille and Ludwig, Stefan and Straube, Bernd and Wunderlich, Hans-Joachim and G. Zoellin, Christian}, year={2008} }' chicago: Coym, Torsten, Sybille Hellebrand, Stefan Ludwig, Bernd Straube, Hans-Joachim Wunderlich, and Christian G. Zoellin. Ein Verfeinertes Elektrisches Modell Für Teilchentreffer Und Dessen Auswirkung Auf Die Bewertung Der Schaltungsempfindlichkeit. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich, 2008. ieee: T. Coym, S. Hellebrand, S. Ludwig, B. Straube, H.-J. Wunderlich, and C. G. Zoellin, Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich, 2008. mla: Coym, Torsten, et al. Ein Verfeinertes Elektrisches Modell Für Teilchentreffer Und Dessen Auswirkung Auf Die Bewertung Der Schaltungsempfindlichkeit. 2008. short: T. Coym, S. Hellebrand, S. Ludwig, B. Straube, H.-J. Wunderlich, C. G. Zoellin, Ein Verfeinertes Elektrisches Modell Für Teilchentreffer Und Dessen Auswirkung Auf Die Bewertung Der Schaltungsempfindlichkeit, 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich, 2008. date_created: 2019-08-28T10:37:06Z date_updated: 2022-01-06T06:51:27Z department: - _id: '48' keyword: - WORKSHOP language: - iso: eng place: 20. ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (Poster), Wien, Österreich status: public title: Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit type: misc user_id: '659' year: '2008' ... --- _id: '13035' author: - first_name: Uranmandakh full_name: Amgalan, Uranmandakh last_name: Amgalan - first_name: Christian full_name: Hachmann, Christian last_name: Hachmann - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich citation: ama: Amgalan U, Hachmann C, Hellebrand S, Wunderlich H-J. Testen Mit Rücksetzpunkten - Ein Ansatz Zur Verbesserung Der Ausbeute Bei Robusten Schaltungen. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich; 2008. apa: Amgalan, U., Hachmann, C., Hellebrand, S., & Wunderlich, H.-J. (2008). Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich. bibtex: '@book{Amgalan_Hachmann_Hellebrand_Wunderlich_2008, place={20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich}, title={Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen}, author={Amgalan, Uranmandakh and Hachmann, Christian and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2008} }' chicago: Amgalan, Uranmandakh, Christian Hachmann, Sybille Hellebrand, and Hans-Joachim Wunderlich. Testen Mit Rücksetzpunkten - Ein Ansatz Zur Verbesserung Der Ausbeute Bei Robusten Schaltungen. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich, 2008. ieee: U. Amgalan, C. Hachmann, S. Hellebrand, and H.-J. Wunderlich, Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich, 2008. mla: Amgalan, Uranmandakh, et al. Testen Mit Rücksetzpunkten - Ein Ansatz Zur Verbesserung Der Ausbeute Bei Robusten Schaltungen. 2008. short: U. Amgalan, C. Hachmann, S. Hellebrand, H.-J. Wunderlich, Testen Mit Rücksetzpunkten - Ein Ansatz Zur Verbesserung Der Ausbeute Bei Robusten Schaltungen, 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich, 2008. date_created: 2019-08-28T10:37:09Z date_updated: 2022-01-06T06:51:27Z department: - _id: '48' keyword: - WORKSHOP language: - iso: eng place: 20. ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Wien, Österreich status: public title: Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen type: misc user_id: '659' year: '2008' ... --- _id: '12992' author: - first_name: Philipp full_name: Oehler, Philipp last_name: Oehler - first_name: Alberto full_name: Bosio, Alberto last_name: Bosio - first_name: Giorgio full_name: di Natale, Giorgio last_name: di Natale - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: 'Oehler P, Bosio A, di Natale G, Hellebrand S. A Modular Memory BIST for Optimized Memory Repair. In: 14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster). IEEE; 2008. doi:10.1109/iolts.2008.30' apa: Oehler, P., Bosio, A., di Natale, G., & Hellebrand, S. (2008). A Modular Memory BIST for Optimized Memory Repair. 14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster). https://doi.org/10.1109/iolts.2008.30 bibtex: '@inproceedings{Oehler_Bosio_di Natale_Hellebrand_2008, place={Rhodos, Greece}, title={A Modular Memory BIST for Optimized Memory Repair}, DOI={10.1109/iolts.2008.30}, booktitle={14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster)}, publisher={IEEE}, author={Oehler, Philipp and Bosio, Alberto and di Natale, Giorgio and Hellebrand, Sybille}, year={2008} }' chicago: 'Oehler, Philipp, Alberto Bosio, Giorgio di Natale, and Sybille Hellebrand. “A Modular Memory BIST for Optimized Memory Repair.” In 14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster). Rhodos, Greece: IEEE, 2008. https://doi.org/10.1109/iolts.2008.30.' ieee: 'P. Oehler, A. Bosio, G. di Natale, and S. Hellebrand, “A Modular Memory BIST for Optimized Memory Repair,” 2008, doi: 10.1109/iolts.2008.30.' mla: Oehler, Philipp, et al. “A Modular Memory BIST for Optimized Memory Repair.” 14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster), IEEE, 2008, doi:10.1109/iolts.2008.30. short: 'P. Oehler, A. Bosio, G. di Natale, S. Hellebrand, in: 14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster), IEEE, Rhodos, Greece, 2008.' date_created: 2019-08-28T10:18:10Z date_updated: 2022-05-11T16:29:13Z department: - _id: '48' doi: 10.1109/iolts.2008.30 language: - iso: eng place: Rhodos, Greece publication: 14th IEEE International On-Line Testing Symposium (IOLTS'08), (Poster) publisher: IEEE status: public title: A Modular Memory BIST for Optimized Memory Repair type: conference user_id: '209' year: '2008' ... --- _id: '12994' author: - first_name: Uranmandakh full_name: Amgalan, Uranmandakh last_name: Amgalan - first_name: Christian full_name: Hachmann, Christian last_name: Hachmann - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 - first_name: Hans-Joachim full_name: Wunderlich, Hans-Joachim last_name: Wunderlich citation: ama: 'Amgalan U, Hachmann C, Hellebrand S, Wunderlich H-J. Signature Rollback - A Technique for Testing Robust Circuits. In: 26th IEEE VLSI Test Symposium (VTS’08). IEEE; 2008:125-130. doi:10.1109/vts.2008.34' apa: Amgalan, U., Hachmann, C., Hellebrand, S., & Wunderlich, H.-J. (2008). Signature Rollback - A Technique for Testing Robust Circuits. 26th IEEE VLSI Test Symposium (VTS’08), 125–130. https://doi.org/10.1109/vts.2008.34 bibtex: '@inproceedings{Amgalan_Hachmann_Hellebrand_Wunderlich_2008, place={San Diego, CA, USA}, title={Signature Rollback - A Technique for Testing Robust Circuits}, DOI={10.1109/vts.2008.34}, booktitle={26th IEEE VLSI Test Symposium (VTS’08)}, publisher={IEEE}, author={Amgalan, Uranmandakh and Hachmann, Christian and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2008}, pages={125–130} }' chicago: 'Amgalan, Uranmandakh, Christian Hachmann, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Signature Rollback - A Technique for Testing Robust Circuits.” In 26th IEEE VLSI Test Symposium (VTS’08), 125–30. San Diego, CA, USA: IEEE, 2008. https://doi.org/10.1109/vts.2008.34.' ieee: 'U. Amgalan, C. Hachmann, S. Hellebrand, and H.-J. Wunderlich, “Signature Rollback - A Technique for Testing Robust Circuits,” in 26th IEEE VLSI Test Symposium (VTS’08), 2008, pp. 125–130, doi: 10.1109/vts.2008.34.' mla: Amgalan, Uranmandakh, et al. “Signature Rollback - A Technique for Testing Robust Circuits.” 26th IEEE VLSI Test Symposium (VTS’08), IEEE, 2008, pp. 125–30, doi:10.1109/vts.2008.34. short: 'U. Amgalan, C. Hachmann, S. Hellebrand, H.-J. Wunderlich, in: 26th IEEE VLSI Test Symposium (VTS’08), IEEE, San Diego, CA, USA, 2008, pp. 125–130.' date_created: 2019-08-28T10:18:56Z date_updated: 2022-05-11T16:30:36Z department: - _id: '48' doi: 10.1109/vts.2008.34 language: - iso: eng page: 125-130 place: San Diego, CA, USA publication: 26th IEEE VLSI Test Symposium (VTS'08) publisher: IEEE status: public title: Signature Rollback - A Technique for Testing Robust Circuits type: conference user_id: '209' year: '2008' ... --- _id: '12993' author: - first_name: Marc full_name: Hunger, Marc last_name: Hunger - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: 'Hunger M, Hellebrand S. Verification and Analysis of Self-Checking Properties through ATPG. In: 14th IEEE International On-Line Testing Symposium (IOLTS’08). IEEE; 2008. doi:10.1109/iolts.2008.32' apa: Hunger, M., & Hellebrand, S. (2008). Verification and Analysis of Self-Checking Properties through ATPG. 14th IEEE International On-Line Testing Symposium (IOLTS’08). https://doi.org/10.1109/iolts.2008.32 bibtex: '@inproceedings{Hunger_Hellebrand_2008, place={Rhodos, Greece}, title={Verification and Analysis of Self-Checking Properties through ATPG}, DOI={10.1109/iolts.2008.32}, booktitle={14th IEEE International On-Line Testing Symposium (IOLTS’08)}, publisher={IEEE}, author={Hunger, Marc and Hellebrand, Sybille}, year={2008} }' chicago: 'Hunger, Marc, and Sybille Hellebrand. “Verification and Analysis of Self-Checking Properties through ATPG.” In 14th IEEE International On-Line Testing Symposium (IOLTS’08). Rhodos, Greece: IEEE, 2008. https://doi.org/10.1109/iolts.2008.32.' ieee: 'M. Hunger and S. Hellebrand, “Verification and Analysis of Self-Checking Properties through ATPG,” 2008, doi: 10.1109/iolts.2008.32.' mla: Hunger, Marc, and Sybille Hellebrand. “Verification and Analysis of Self-Checking Properties through ATPG.” 14th IEEE International On-Line Testing Symposium (IOLTS’08), IEEE, 2008, doi:10.1109/iolts.2008.32. short: 'M. Hunger, S. Hellebrand, in: 14th IEEE International On-Line Testing Symposium (IOLTS’08), IEEE, Rhodos, Greece, 2008.' date_created: 2019-08-28T10:18:11Z date_updated: 2022-05-11T16:29:56Z department: - _id: '48' doi: 10.1109/iolts.2008.32 language: - iso: eng place: Rhodos, Greece publication: 14th IEEE International On-Line Testing Symposium (IOLTS'08) publisher: IEEE status: public title: Verification and Analysis of Self-Checking Properties through ATPG type: conference user_id: '209' year: '2008' ... --- _id: '13031' author: - first_name: Marc full_name: Hunger, Marc last_name: Hunger - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: 'Hunger M, Hellebrand S. Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG. In: 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2008.' apa: Hunger, M., & Hellebrand, S. (2008). Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG. 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” bibtex: '@inproceedings{Hunger_Hellebrand_2008, place={Ingolstadt, Germany}, title={Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG}, booktitle={2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf”}, author={Hunger, Marc and Hellebrand, Sybille}, year={2008} }' chicago: Hunger, Marc, and Sybille Hellebrand. “Analyse Selbstprüfender Schaltungen – Nachweis von Fehlersicherheit Und Selbsttestbarkeit Mit ATPG.” In 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” Ingolstadt, Germany, 2008. ieee: M. Hunger and S. Hellebrand, “Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG,” 2008. mla: Hunger, Marc, and Sybille Hellebrand. “Analyse Selbstprüfender Schaltungen – Nachweis von Fehlersicherheit Und Selbsttestbarkeit Mit ATPG.” 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2008. short: 'M. Hunger, S. Hellebrand, in: 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Ingolstadt, Germany, 2008.' date_created: 2019-08-28T10:35:49Z date_updated: 2022-05-11T16:31:25Z department: - _id: '48' language: - iso: eng place: Ingolstadt, Germany publication: 2. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf" status: public title: Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG type: conference user_id: '209' year: '2008' ... --- _id: '13032' author: - first_name: Philipp full_name: Oehler, Philipp last_name: Oehler - first_name: Alberto full_name: Bosio, Alberto last_name: Bosio - first_name: Giorgio full_name: Di Natale, Giorgio last_name: Di Natale - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: 'Oehler P, Bosio A, Di Natale G, Hellebrand S. Modularer Selbsttest und optimierte Reparaturanalyse. In: 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” ; 2008.' apa: Oehler, P., Bosio, A., Di Natale, G., & Hellebrand, S. (2008). Modularer Selbsttest und optimierte Reparaturanalyse. 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” bibtex: '@inproceedings{Oehler_Bosio_Di Natale_Hellebrand_2008, place={Ingolstadt, Germany}, title={Modularer Selbsttest und optimierte Reparaturanalyse}, booktitle={2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf”}, author={Oehler, Philipp and Bosio, Alberto and Di Natale, Giorgio and Hellebrand, Sybille}, year={2008} }' chicago: Oehler, Philipp, Alberto Bosio, Giorgio Di Natale, and Sybille Hellebrand. “Modularer Selbsttest Und Optimierte Reparaturanalyse.” In 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” Ingolstadt, Germany, 2008. ieee: P. Oehler, A. Bosio, G. Di Natale, and S. Hellebrand, “Modularer Selbsttest und optimierte Reparaturanalyse,” 2008. mla: Oehler, Philipp, et al. “Modularer Selbsttest Und Optimierte Reparaturanalyse.” 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 2008. short: 'P. Oehler, A. Bosio, G. Di Natale, S. Hellebrand, in: 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Ingolstadt, Germany, 2008.' date_created: 2019-08-28T10:35:50Z date_updated: 2022-05-11T16:34:03Z department: - _id: '48' language: - iso: eng place: Ingolstadt, Germany publication: 2. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf" status: public title: Modularer Selbsttest und optimierte Reparaturanalyse type: conference user_id: '209' year: '2008' ... --- _id: '13038' author: - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: Hellebrand S. Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing. 5th IEEE East-West Design \& Test Symposium, Yerevan, Armenia (Invited Talk); 2007. apa: Hellebrand, S. (2007). Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing. 5th IEEE East-West Design \& Test Symposium, Yerevan, Armenia (Invited Talk). bibtex: '@book{Hellebrand_2007, place={5th IEEE East-West Design \& Test Symposium, Yerevan, Armenia (Invited Talk)}, title={Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing}, author={Hellebrand, Sybille}, year={2007} }' chicago: Hellebrand, Sybille. Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing. 5th IEEE East-West Design \& Test Symposium, Yerevan, Armenia (Invited Talk), 2007. ieee: S. Hellebrand, Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing. 5th IEEE East-West Design \& Test Symposium, Yerevan, Armenia (Invited Talk), 2007. mla: Hellebrand, Sybille. Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing. 2007. short: S. Hellebrand, Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing, 5th IEEE East-West Design \& Test Symposium, Yerevan, Armenia (Invited Talk), 2007. date_created: 2019-08-28T10:40:47Z date_updated: 2022-01-06T06:51:27Z department: - _id: '48' keyword: - WORKSHOP language: - iso: eng place: 5th IEEE East-West Design \& Test Symposium, Yerevan, Armenia (Invited Talk) status: public title: Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing type: misc user_id: '659' year: '2007' ... --- _id: '13039' author: - first_name: Muhammad full_name: Ali, Muhammad last_name: Ali - first_name: Michael full_name: Welzl, Michael last_name: Welzl - first_name: Sven full_name: Hessler, Sven last_name: Hessler - first_name: Sybille full_name: Hellebrand, Sybille id: '209' last_name: Hellebrand orcid: 0000-0002-3717-3939 citation: ama: Ali M, Welzl M, Hessler S, Hellebrand S. An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips. DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster); 2007. apa: Ali, M., Welzl, M., Hessler, S., & Hellebrand, S. (2007). An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips. DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster). bibtex: '@book{Ali_Welzl_Hessler_Hellebrand_2007, place={DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster)}, title={An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips}, author={Ali, Muhammad and Welzl, Michael and Hessler, Sven and Hellebrand, Sybille}, year={2007} }' chicago: Ali, Muhammad, Michael Welzl, Sven Hessler, and Sybille Hellebrand. An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips. DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster), 2007. ieee: M. Ali, M. Welzl, S. Hessler, and S. Hellebrand, An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips. DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster), 2007. mla: Ali, Muhammad, et al. An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips. 2007. short: M. Ali, M. Welzl, S. Hessler, S. Hellebrand, An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips, DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster), 2007. date_created: 2019-08-28T10:41:29Z date_updated: 2022-01-06T06:51:27Z department: - _id: '48' keyword: - WORKSHOP language: - iso: eng place: DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster) status: public title: An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips type: misc user_id: '659' year: '2007' ...