---
_id: '13049'
author:
- first_name: Bernd
  full_name: Becker, Bernd
  last_name: Becker
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
- first_name: Ilia
  full_name: Polian, Ilia
  last_name: Polian
- first_name: Bernd
  full_name: Straube, Bernd
  last_name: Straube
- first_name: Wolfgang
  full_name: Vermeiren, Wolfgang
  last_name: Vermeiren
- first_name: Hans-Joachim
  full_name: Wunderlich, Hans-Joachim
  last_name: Wunderlich
citation:
  ama: 'Becker B, Hellebrand S, Polian I, Straube B, Vermeiren W, Wunderlich H-J.
    Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic
    Circuits. In: <i>4th Workshop on Dependable and Secure Nanocomputing (WDSN’10),
    (Invited Paper)</i>. ; 2010.'
  apa: Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., &#38; Wunderlich,
    H.-J. (2010). Massive Statistical Process Variations - A Grand Challenge for Testing
    Nanoelectronic Circuits. <i>4th Workshop on Dependable and Secure Nanocomputing
    (WDSN’10), (Invited Paper)</i>.
  bibtex: '@inproceedings{Becker_Hellebrand_Polian_Straube_Vermeiren_Wunderlich_2010,
    place={Chicago, IL, USA}, title={Massive Statistical Process Variations - A Grand
    Challenge for Testing Nanoelectronic Circuits}, booktitle={4th Workshop on Dependable
    and Secure Nanocomputing (WDSN’10), (Invited Paper)}, author={Becker, Bernd and
    Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang
    and Wunderlich, Hans-Joachim}, year={2010} }'
  chicago: Becker, Bernd, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang
    Vermeiren, and Hans-Joachim Wunderlich. “Massive Statistical Process Variations
    - A Grand Challenge for Testing Nanoelectronic Circuits.” In <i>4th Workshop on
    Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper)</i>. Chicago, IL,
    USA, 2010.
  ieee: B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, and H.-J. Wunderlich,
    “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic
    Circuits,” 2010.
  mla: Becker, Bernd, et al. “Massive Statistical Process Variations - A Grand Challenge
    for Testing Nanoelectronic Circuits.” <i>4th Workshop on Dependable and Secure
    Nanocomputing (WDSN’10), (Invited Paper)</i>, 2010.
  short: 'B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich,
    in: 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper),
    Chicago, IL, USA, 2010.'
date_created: 2019-08-28T11:45:36Z
date_updated: 2022-05-11T16:26:18Z
department:
- _id: '48'
language:
- iso: eng
place: Chicago, IL, USA
publication: 4th Workshop on Dependable and Secure Nanocomputing (WDSN'10), (Invited
  Paper)
status: public
title: Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic
  Circuits
type: conference
user_id: '209'
year: '2010'
...
---
_id: '13050'
author:
- first_name: Thomas
  full_name: Indlekofer, Thomas
  last_name: Indlekofer
- first_name: Michael
  full_name: Schnittger, Michael
  last_name: Schnittger
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
citation:
  ama: 'Indlekofer T, Schnittger M, Hellebrand S. Robuster Selbsttest mit extremer
    Kompaktierung. In: <i>4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”</i>
    ; 2010:17-24.'
  apa: Indlekofer, T., Schnittger, M., &#38; Hellebrand, S. (2010). Robuster Selbsttest
    mit extremer Kompaktierung. <i>4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,”</i>
    17–24.
  bibtex: '@inproceedings{Indlekofer_Schnittger_Hellebrand_2010, place={Wildbad Kreuth,
    Germany}, title={Robuster Selbsttest mit extremer Kompaktierung}, booktitle={4.
    GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf”}, author={Indlekofer, Thomas
    and Schnittger, Michael and Hellebrand, Sybille}, year={2010}, pages={17–24} }'
  chicago: Indlekofer, Thomas, Michael Schnittger, and Sybille Hellebrand. “Robuster
    Selbsttest Mit Extremer Kompaktierung.” In <i>4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit
    Und Entwurf,”</i> 17–24. Wildbad Kreuth, Germany, 2010.
  ieee: T. Indlekofer, M. Schnittger, and S. Hellebrand, “Robuster Selbsttest mit
    extremer Kompaktierung,” in <i>4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf,”</i>
    2010, pp. 17–24.
  mla: Indlekofer, Thomas, et al. “Robuster Selbsttest Mit Extremer Kompaktierung.”
    <i>4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,”</i> 2010, pp. 17–24.
  short: 'T. Indlekofer, M. Schnittger, S. Hellebrand, in: 4. GMM/GI/ITG-Fachtagung
    “Zuverlässigkeit Und Entwurf,” Wildbad Kreuth, Germany, 2010, pp. 17–24.'
date_created: 2019-08-28T11:46:13Z
date_updated: 2022-05-11T16:25:34Z
department:
- _id: '48'
language:
- iso: eng
page: 17-24
place: Wildbad Kreuth, Germany
publication: 4. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf"
status: public
title: Robuster Selbsttest mit extremer Kompaktierung
type: conference
user_id: '209'
year: '2010'
...
---
_id: '12991'
author:
- first_name: Marc
  full_name: Hunger, Marc
  last_name: Hunger
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
- first_name: Alejandro
  full_name: Czutro, Alejandro
  last_name: Czutro
- first_name: Ilia
  full_name: Polian, Ilia
  last_name: Polian
- first_name: Bernd
  full_name: Becker, Bernd
  last_name: Becker
citation:
  ama: 'Hunger M, Hellebrand S, Czutro A, Polian I, Becker B. ATPG-Based Grading of
    Strong Fault-Secureness. In: <i>15th IEEE International On-Line Testing Symposium
    (IOLTS’09</i>. IEEE; 2009. doi:<a href="https://doi.org/10.1109/iolts.2009.5196027">10.1109/iolts.2009.5196027</a>'
  apa: Hunger, M., Hellebrand, S., Czutro, A., Polian, I., &#38; Becker, B. (2009).
    ATPG-Based Grading of Strong Fault-Secureness. <i>15th IEEE International On-Line
    Testing Symposium (IOLTS’09</i>. <a href="https://doi.org/10.1109/iolts.2009.5196027">https://doi.org/10.1109/iolts.2009.5196027</a>
  bibtex: '@inproceedings{Hunger_Hellebrand_Czutro_Polian_Becker_2009, place={Sesimbra-Lisbon,
    Portugal}, title={ATPG-Based Grading of Strong Fault-Secureness}, DOI={<a href="https://doi.org/10.1109/iolts.2009.5196027">10.1109/iolts.2009.5196027</a>},
    booktitle={15th IEEE International On-Line Testing Symposium (IOLTS’09}, publisher={IEEE},
    author={Hunger, Marc and Hellebrand, Sybille and Czutro, Alejandro and Polian,
    Ilia and Becker, Bernd}, year={2009} }'
  chicago: 'Hunger, Marc, Sybille Hellebrand, Alejandro Czutro, Ilia Polian, and Bernd
    Becker. “ATPG-Based Grading of Strong Fault-Secureness.” In <i>15th IEEE International
    On-Line Testing Symposium (IOLTS’09</i>. Sesimbra-Lisbon, Portugal: IEEE, 2009.
    <a href="https://doi.org/10.1109/iolts.2009.5196027">https://doi.org/10.1109/iolts.2009.5196027</a>.'
  ieee: 'M. Hunger, S. Hellebrand, A. Czutro, I. Polian, and B. Becker, “ATPG-Based
    Grading of Strong Fault-Secureness,” 2009, doi: <a href="https://doi.org/10.1109/iolts.2009.5196027">10.1109/iolts.2009.5196027</a>.'
  mla: Hunger, Marc, et al. “ATPG-Based Grading of Strong Fault-Secureness.” <i>15th
    IEEE International On-Line Testing Symposium (IOLTS’09</i>, IEEE, 2009, doi:<a
    href="https://doi.org/10.1109/iolts.2009.5196027">10.1109/iolts.2009.5196027</a>.
  short: 'M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, in: 15th IEEE
    International On-Line Testing Symposium (IOLTS’09, IEEE, Sesimbra-Lisbon, Portugal,
    2009.'
date_created: 2019-08-28T10:17:16Z
date_updated: 2022-05-11T16:27:48Z
department:
- _id: '48'
doi: 10.1109/iolts.2009.5196027
language:
- iso: eng
place: Sesimbra-Lisbon, Portugal
publication: 15th IEEE International On-Line Testing Symposium (IOLTS'09
publisher: IEEE
status: public
title: ATPG-Based Grading of Strong Fault-Secureness
type: conference
user_id: '209'
year: '2009'
...
---
_id: '12990'
author:
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
- first_name: Marc
  full_name: Hunger, Marc
  last_name: Hunger
citation:
  ama: 'Hellebrand S, Hunger M. Are Robust Circuits Really Robust? In: <i>24th IEEE
    International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09),
    (Invited Talk)</i>. IEEE; 2009:77. doi:<a href="https://doi.org/10.1109/dft.2009.28">10.1109/dft.2009.28</a>'
  apa: Hellebrand, S., &#38; Hunger, M. (2009). Are Robust Circuits Really Robust?
    <i>24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
    (DFT’09), (Invited Talk)</i>, 77. <a href="https://doi.org/10.1109/dft.2009.28">https://doi.org/10.1109/dft.2009.28</a>
  bibtex: '@inproceedings{Hellebrand_Hunger_2009, place={Chicago, IL, USA}, title={Are
    Robust Circuits Really Robust?}, DOI={<a href="https://doi.org/10.1109/dft.2009.28">10.1109/dft.2009.28</a>},
    booktitle={24th IEEE International Symposium on Defect and Fault Tolerance in
    VLSI Systems (DFT’09), (Invited Talk)}, publisher={IEEE}, author={Hellebrand,
    Sybille and Hunger, Marc}, year={2009}, pages={77} }'
  chicago: 'Hellebrand, Sybille, and Marc Hunger. “Are Robust Circuits Really Robust?”
    In <i>24th IEEE International Symposium on Defect and Fault Tolerance in VLSI
    Systems (DFT’09), (Invited Talk)</i>, 77. Chicago, IL, USA: IEEE, 2009. <a href="https://doi.org/10.1109/dft.2009.28">https://doi.org/10.1109/dft.2009.28</a>.'
  ieee: 'S. Hellebrand and M. Hunger, “Are Robust Circuits Really Robust?,” in <i>24th
    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09),
    (Invited Talk)</i>, 2009, p. 77, doi: <a href="https://doi.org/10.1109/dft.2009.28">10.1109/dft.2009.28</a>.'
  mla: Hellebrand, Sybille, and Marc Hunger. “Are Robust Circuits Really Robust?”
    <i>24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
    (DFT’09), (Invited Talk)</i>, IEEE, 2009, p. 77, doi:<a href="https://doi.org/10.1109/dft.2009.28">10.1109/dft.2009.28</a>.
  short: 'S. Hellebrand, M. Hunger, in: 24th IEEE International Symposium on Defect
    and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), IEEE, Chicago, IL,
    USA, 2009, p. 77.'
date_created: 2019-08-28T10:17:14Z
date_updated: 2022-05-11T16:27:03Z
department:
- _id: '48'
doi: 10.1109/dft.2009.28
language:
- iso: eng
page: '77'
place: Chicago, IL, USA
publication: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI
  Systems (DFT'09), (Invited Talk)
publisher: IEEE
status: public
title: Are Robust Circuits Really Robust?
type: conference
user_id: '209'
year: '2009'
...
---
_id: '13030'
author:
- first_name: Marc
  full_name: Hunger, Marc
  last_name: Hunger
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
- first_name: Alexander
  full_name: Czutro, Alexander
  last_name: Czutro
- first_name: Ilia
  full_name: Polian, Ilia
  last_name: Polian
- first_name: Bernd
  full_name: Becker, Bernd
  last_name: Becker
citation:
  ama: 'Hunger M, Hellebrand S, Czutro A, Polian I, Becker B. Robustheitsanalyse stark
    fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung. In: <i>3. GMM/GI/ITG-Fachtagung
    “Zuverlässigkeit Und Entwurf.”</i> ; 2009.'
  apa: Hunger, M., Hellebrand, S., Czutro, A., Polian, I., &#38; Becker, B. (2009).
    Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung.
    <i>3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”</i>
  bibtex: '@inproceedings{Hunger_Hellebrand_Czutro_Polian_Becker_2009, place={Stuttgart,
    Germany}, title={Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter
    Testmustererzeugung}, booktitle={3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und
    Entwurf”}, author={Hunger, Marc and Hellebrand, Sybille and Czutro, Alexander
    and Polian, Ilia and Becker, Bernd}, year={2009} }'
  chicago: Hunger, Marc, Sybille Hellebrand, Alexander Czutro, Ilia Polian, and Bernd
    Becker. “Robustheitsanalyse Stark Fehlersicherer Schaltungen Mit SAT-Basierter
    Testmustererzeugung.” In <i>3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”</i>
    Stuttgart, Germany, 2009.
  ieee: M. Hunger, S. Hellebrand, A. Czutro, I. Polian, and B. Becker, “Robustheitsanalyse
    stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung,” 2009.
  mla: Hunger, Marc, et al. “Robustheitsanalyse Stark Fehlersicherer Schaltungen Mit
    SAT-Basierter Testmustererzeugung.” <i>3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit
    Und Entwurf,”</i> 2009.
  short: 'M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, in: 3. GMM/GI/ITG-Fachtagung
    “Zuverlässigkeit Und Entwurf,” Stuttgart, Germany, 2009.'
date_created: 2019-08-28T10:35:48Z
date_updated: 2022-05-11T16:28:31Z
department:
- _id: '48'
language:
- iso: eng
place: Stuttgart, Germany
publication: 3. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf"
status: public
title: Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung
type: conference
user_id: '209'
year: '2009'
...
---
_id: '13033'
author:
- first_name: Torsten
  full_name: Coym, Torsten
  last_name: Coym
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
- first_name: Stefan
  full_name: Ludwig, Stefan
  last_name: Ludwig
- first_name: Bernd
  full_name: Straube, Bernd
  last_name: Straube
- first_name: Hans-Joachim
  full_name: Wunderlich, Hans-Joachim
  last_name: Wunderlich
- first_name: Christian
  full_name: G. Zoellin, Christian
  last_name: G. Zoellin
citation:
  ama: Coym T, Hellebrand S, Ludwig S, Straube B, Wunderlich H-J, G. Zoellin C. <i>Ein
    Verfeinertes Elektrisches Modell Für Teilchentreffer Und Dessen Auswirkung Auf
    Die Bewertung Der Schaltungsempfindlichkeit</i>. 20. ITG/GI/GMM Workshop “Testmethoden
    und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich;
    2008.
  apa: Coym, T., Hellebrand, S., Ludwig, S., Straube, B., Wunderlich, H.-J., &#38;
    G. Zoellin, C. (2008). <i>Ein verfeinertes elektrisches Modell für Teilchentreffer
    und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit</i>. 20.
    ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    (Poster), Wien, Österreich.
  bibtex: '@book{Coym_Hellebrand_Ludwig_Straube_Wunderlich_G. Zoellin_2008, place={20.
    ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
    (Poster), Wien, Österreich}, title={Ein verfeinertes elektrisches Modell für Teilchentreffer
    und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit}, author={Coym,
    Torsten and Hellebrand, Sybille and Ludwig, Stefan and Straube, Bernd and Wunderlich,
    Hans-Joachim and G. Zoellin, Christian}, year={2008} }'
  chicago: Coym, Torsten, Sybille Hellebrand, Stefan Ludwig, Bernd Straube, Hans-Joachim
    Wunderlich, and Christian G. Zoellin. <i>Ein Verfeinertes Elektrisches Modell
    Für Teilchentreffer Und Dessen Auswirkung Auf Die Bewertung Der Schaltungsempfindlichkeit</i>.
    20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und
    Systemen” (Poster), Wien, Österreich, 2008.
  ieee: T. Coym, S. Hellebrand, S. Ludwig, B. Straube, H.-J. Wunderlich, and C. G.
    Zoellin, <i>Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen
    Auswirkung auf die Bewertung der Schaltungsempfindlichkeit</i>. 20. ITG/GI/GMM
    Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster),
    Wien, Österreich, 2008.
  mla: Coym, Torsten, et al. <i>Ein Verfeinertes Elektrisches Modell Für Teilchentreffer
    Und Dessen Auswirkung Auf Die Bewertung Der Schaltungsempfindlichkeit</i>. 2008.
  short: T. Coym, S. Hellebrand, S. Ludwig, B. Straube, H.-J. Wunderlich, C. G. Zoellin,
    Ein Verfeinertes Elektrisches Modell Für Teilchentreffer Und Dessen Auswirkung
    Auf Die Bewertung Der Schaltungsempfindlichkeit, 20. ITG/GI/GMM Workshop “Testmethoden
    und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich,
    2008.
date_created: 2019-08-28T10:37:06Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '48'
keyword:
- WORKSHOP
language:
- iso: eng
place: 20. ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und
  Systemen" (Poster), Wien, Österreich
status: public
title: Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung
  auf die Bewertung der Schaltungsempfindlichkeit
type: misc
user_id: '659'
year: '2008'
...
---
_id: '13035'
author:
- first_name: Uranmandakh
  full_name: Amgalan, Uranmandakh
  last_name: Amgalan
- first_name: Christian
  full_name: Hachmann, Christian
  last_name: Hachmann
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
  full_name: Wunderlich, Hans-Joachim
  last_name: Wunderlich
citation:
  ama: Amgalan U, Hachmann C, Hellebrand S, Wunderlich H-J. <i>Testen Mit Rücksetzpunkten
    - Ein Ansatz Zur Verbesserung Der Ausbeute Bei Robusten Schaltungen</i>. 20. ITG/GI/GMM
    Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien,
    Österreich; 2008.
  apa: Amgalan, U., Hachmann, C., Hellebrand, S., &#38; Wunderlich, H.-J. (2008).
    <i>Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten
    Schaltungen</i>. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von
    Schaltungen und Systemen”, Wien, Österreich.
  bibtex: '@book{Amgalan_Hachmann_Hellebrand_Wunderlich_2008, place={20. ITG/GI/GMM
    Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien,
    Österreich}, title={Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der
    Ausbeute bei robusten Schaltungen}, author={Amgalan, Uranmandakh and Hachmann,
    Christian and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2008} }'
  chicago: Amgalan, Uranmandakh, Christian Hachmann, Sybille Hellebrand, and Hans-Joachim
    Wunderlich. <i>Testen Mit Rücksetzpunkten - Ein Ansatz Zur Verbesserung Der Ausbeute
    Bei Robusten Schaltungen</i>. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit
    von Schaltungen und Systemen”, Wien, Österreich, 2008.
  ieee: U. Amgalan, C. Hachmann, S. Hellebrand, and H.-J. Wunderlich, <i>Testen mit
    Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen</i>.
    20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und
    Systemen”, Wien, Österreich, 2008.
  mla: Amgalan, Uranmandakh, et al. <i>Testen Mit Rücksetzpunkten - Ein Ansatz Zur
    Verbesserung Der Ausbeute Bei Robusten Schaltungen</i>. 2008.
  short: U. Amgalan, C. Hachmann, S. Hellebrand, H.-J. Wunderlich, Testen Mit Rücksetzpunkten
    - Ein Ansatz Zur Verbesserung Der Ausbeute Bei Robusten Schaltungen, 20. ITG/GI/GMM
    Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien,
    Österreich, 2008.
date_created: 2019-08-28T10:37:09Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '48'
keyword:
- WORKSHOP
language:
- iso: eng
place: 20. ITG/GI/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und
  Systemen", Wien, Österreich
status: public
title: Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten
  Schaltungen
type: misc
user_id: '659'
year: '2008'
...
---
_id: '12992'
author:
- first_name: Philipp
  full_name: Oehler, Philipp
  last_name: Oehler
- first_name: Alberto
  full_name: Bosio, Alberto
  last_name: Bosio
- first_name: Giorgio
  full_name: di Natale, Giorgio
  last_name: di Natale
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
citation:
  ama: 'Oehler P, Bosio A, di Natale G, Hellebrand S. A Modular Memory BIST for Optimized
    Memory Repair. In: <i>14th IEEE International On-Line Testing Symposium (IOLTS’08),
    (Poster)</i>. IEEE; 2008. doi:<a href="https://doi.org/10.1109/iolts.2008.30">10.1109/iolts.2008.30</a>'
  apa: Oehler, P., Bosio, A., di Natale, G., &#38; Hellebrand, S. (2008). A Modular
    Memory BIST for Optimized Memory Repair. <i>14th IEEE International On-Line Testing
    Symposium (IOLTS’08), (Poster)</i>. <a href="https://doi.org/10.1109/iolts.2008.30">https://doi.org/10.1109/iolts.2008.30</a>
  bibtex: '@inproceedings{Oehler_Bosio_di Natale_Hellebrand_2008, place={Rhodos, Greece},
    title={A Modular Memory BIST for Optimized Memory Repair}, DOI={<a href="https://doi.org/10.1109/iolts.2008.30">10.1109/iolts.2008.30</a>},
    booktitle={14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster)},
    publisher={IEEE}, author={Oehler, Philipp and Bosio, Alberto and di Natale, Giorgio
    and Hellebrand, Sybille}, year={2008} }'
  chicago: 'Oehler, Philipp, Alberto Bosio, Giorgio di Natale, and Sybille Hellebrand.
    “A Modular Memory BIST for Optimized Memory Repair.” In <i>14th IEEE International
    On-Line Testing Symposium (IOLTS’08), (Poster)</i>. Rhodos, Greece: IEEE, 2008.
    <a href="https://doi.org/10.1109/iolts.2008.30">https://doi.org/10.1109/iolts.2008.30</a>.'
  ieee: 'P. Oehler, A. Bosio, G. di Natale, and S. Hellebrand, “A Modular Memory BIST
    for Optimized Memory Repair,” 2008, doi: <a href="https://doi.org/10.1109/iolts.2008.30">10.1109/iolts.2008.30</a>.'
  mla: Oehler, Philipp, et al. “A Modular Memory BIST for Optimized Memory Repair.”
    <i>14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster)</i>,
    IEEE, 2008, doi:<a href="https://doi.org/10.1109/iolts.2008.30">10.1109/iolts.2008.30</a>.
  short: 'P. Oehler, A. Bosio, G. di Natale, S. Hellebrand, in: 14th IEEE International
    On-Line Testing Symposium (IOLTS’08), (Poster), IEEE, Rhodos, Greece, 2008.'
date_created: 2019-08-28T10:18:10Z
date_updated: 2022-05-11T16:29:13Z
department:
- _id: '48'
doi: 10.1109/iolts.2008.30
language:
- iso: eng
place: Rhodos, Greece
publication: 14th IEEE International On-Line Testing Symposium (IOLTS'08), (Poster)
publisher: IEEE
status: public
title: A Modular Memory BIST for Optimized Memory Repair
type: conference
user_id: '209'
year: '2008'
...
---
_id: '12994'
author:
- first_name: Uranmandakh
  full_name: Amgalan, Uranmandakh
  last_name: Amgalan
- first_name: Christian
  full_name: Hachmann, Christian
  last_name: Hachmann
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
  full_name: Wunderlich, Hans-Joachim
  last_name: Wunderlich
citation:
  ama: 'Amgalan U, Hachmann C, Hellebrand S, Wunderlich H-J. Signature Rollback -
    A Technique for Testing Robust Circuits. In: <i>26th IEEE VLSI Test Symposium
    (VTS’08)</i>. IEEE; 2008:125-130. doi:<a href="https://doi.org/10.1109/vts.2008.34">10.1109/vts.2008.34</a>'
  apa: Amgalan, U., Hachmann, C., Hellebrand, S., &#38; Wunderlich, H.-J. (2008).
    Signature Rollback - A Technique for Testing Robust Circuits. <i>26th IEEE VLSI
    Test Symposium (VTS’08)</i>, 125–130. <a href="https://doi.org/10.1109/vts.2008.34">https://doi.org/10.1109/vts.2008.34</a>
  bibtex: '@inproceedings{Amgalan_Hachmann_Hellebrand_Wunderlich_2008, place={San
    Diego, CA, USA}, title={Signature Rollback - A Technique for Testing Robust Circuits},
    DOI={<a href="https://doi.org/10.1109/vts.2008.34">10.1109/vts.2008.34</a>}, booktitle={26th
    IEEE VLSI Test Symposium (VTS’08)}, publisher={IEEE}, author={Amgalan, Uranmandakh
    and Hachmann, Christian and Hellebrand, Sybille and Wunderlich, Hans-Joachim},
    year={2008}, pages={125–130} }'
  chicago: 'Amgalan, Uranmandakh, Christian Hachmann, Sybille Hellebrand, and Hans-Joachim
    Wunderlich. “Signature Rollback - A Technique for Testing Robust Circuits.” In
    <i>26th IEEE VLSI Test Symposium (VTS’08)</i>, 125–30. San Diego, CA, USA: IEEE,
    2008. <a href="https://doi.org/10.1109/vts.2008.34">https://doi.org/10.1109/vts.2008.34</a>.'
  ieee: 'U. Amgalan, C. Hachmann, S. Hellebrand, and H.-J. Wunderlich, “Signature
    Rollback - A Technique for Testing Robust Circuits,” in <i>26th IEEE VLSI Test
    Symposium (VTS’08)</i>, 2008, pp. 125–130, doi: <a href="https://doi.org/10.1109/vts.2008.34">10.1109/vts.2008.34</a>.'
  mla: Amgalan, Uranmandakh, et al. “Signature Rollback - A Technique for Testing
    Robust Circuits.” <i>26th IEEE VLSI Test Symposium (VTS’08)</i>, IEEE, 2008, pp.
    125–30, doi:<a href="https://doi.org/10.1109/vts.2008.34">10.1109/vts.2008.34</a>.
  short: 'U. Amgalan, C. Hachmann, S. Hellebrand, H.-J. Wunderlich, in: 26th IEEE
    VLSI Test Symposium (VTS’08), IEEE, San Diego, CA, USA, 2008, pp. 125–130.'
date_created: 2019-08-28T10:18:56Z
date_updated: 2022-05-11T16:30:36Z
department:
- _id: '48'
doi: 10.1109/vts.2008.34
language:
- iso: eng
page: 125-130
place: San Diego, CA, USA
publication: 26th IEEE VLSI Test Symposium (VTS'08)
publisher: IEEE
status: public
title: Signature Rollback - A Technique for Testing Robust Circuits
type: conference
user_id: '209'
year: '2008'
...
---
_id: '12993'
author:
- first_name: Marc
  full_name: Hunger, Marc
  last_name: Hunger
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
citation:
  ama: 'Hunger M, Hellebrand S. Verification and Analysis of Self-Checking Properties
    through ATPG. In: <i>14th IEEE International On-Line Testing Symposium (IOLTS’08)</i>.
    IEEE; 2008. doi:<a href="https://doi.org/10.1109/iolts.2008.32">10.1109/iolts.2008.32</a>'
  apa: Hunger, M., &#38; Hellebrand, S. (2008). Verification and Analysis of Self-Checking
    Properties through ATPG. <i>14th IEEE International On-Line Testing Symposium
    (IOLTS’08)</i>. <a href="https://doi.org/10.1109/iolts.2008.32">https://doi.org/10.1109/iolts.2008.32</a>
  bibtex: '@inproceedings{Hunger_Hellebrand_2008, place={Rhodos, Greece}, title={Verification
    and Analysis of Self-Checking Properties through ATPG}, DOI={<a href="https://doi.org/10.1109/iolts.2008.32">10.1109/iolts.2008.32</a>},
    booktitle={14th IEEE International On-Line Testing Symposium (IOLTS’08)}, publisher={IEEE},
    author={Hunger, Marc and Hellebrand, Sybille}, year={2008} }'
  chicago: 'Hunger, Marc, and Sybille Hellebrand. “Verification and Analysis of Self-Checking
    Properties through ATPG.” In <i>14th IEEE International On-Line Testing Symposium
    (IOLTS’08)</i>. Rhodos, Greece: IEEE, 2008. <a href="https://doi.org/10.1109/iolts.2008.32">https://doi.org/10.1109/iolts.2008.32</a>.'
  ieee: 'M. Hunger and S. Hellebrand, “Verification and Analysis of Self-Checking
    Properties through ATPG,” 2008, doi: <a href="https://doi.org/10.1109/iolts.2008.32">10.1109/iolts.2008.32</a>.'
  mla: Hunger, Marc, and Sybille Hellebrand. “Verification and Analysis of Self-Checking
    Properties through ATPG.” <i>14th IEEE International On-Line Testing Symposium
    (IOLTS’08)</i>, IEEE, 2008, doi:<a href="https://doi.org/10.1109/iolts.2008.32">10.1109/iolts.2008.32</a>.
  short: 'M. Hunger, S. Hellebrand, in: 14th IEEE International On-Line Testing Symposium
    (IOLTS’08), IEEE, Rhodos, Greece, 2008.'
date_created: 2019-08-28T10:18:11Z
date_updated: 2022-05-11T16:29:56Z
department:
- _id: '48'
doi: 10.1109/iolts.2008.32
language:
- iso: eng
place: Rhodos, Greece
publication: 14th IEEE International On-Line Testing Symposium (IOLTS'08)
publisher: IEEE
status: public
title: Verification and Analysis of Self-Checking Properties through ATPG
type: conference
user_id: '209'
year: '2008'
...
---
_id: '13031'
author:
- first_name: Marc
  full_name: Hunger, Marc
  last_name: Hunger
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
citation:
  ama: 'Hunger M, Hellebrand S. Analyse selbstprüfender Schaltungen – Nachweis von
    Fehlersicherheit und Selbsttestbarkeit mit ATPG. In: <i>2. GMM/GI/ITG-Fachtagung
    “Zuverlässigkeit Und Entwurf.”</i> ; 2008.'
  apa: Hunger, M., &#38; Hellebrand, S. (2008). Analyse selbstprüfender Schaltungen
    – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG. <i>2. GMM/GI/ITG-Fachtagung
    “Zuverlässigkeit Und Entwurf.”</i>
  bibtex: '@inproceedings{Hunger_Hellebrand_2008, place={Ingolstadt, Germany}, title={Analyse
    selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit
    mit ATPG}, booktitle={2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf”},
    author={Hunger, Marc and Hellebrand, Sybille}, year={2008} }'
  chicago: Hunger, Marc, and Sybille Hellebrand. “Analyse Selbstprüfender Schaltungen
    – Nachweis von Fehlersicherheit Und Selbsttestbarkeit Mit ATPG.” In <i>2. GMM/GI/ITG-Fachtagung
    “Zuverlässigkeit Und Entwurf.”</i> Ingolstadt, Germany, 2008.
  ieee: M. Hunger and S. Hellebrand, “Analyse selbstprüfender Schaltungen – Nachweis
    von Fehlersicherheit und Selbsttestbarkeit mit ATPG,” 2008.
  mla: Hunger, Marc, and Sybille Hellebrand. “Analyse Selbstprüfender Schaltungen
    – Nachweis von Fehlersicherheit Und Selbsttestbarkeit Mit ATPG.” <i>2. GMM/GI/ITG-Fachtagung
    “Zuverlässigkeit Und Entwurf,”</i> 2008.
  short: 'M. Hunger, S. Hellebrand, in: 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit
    Und Entwurf,” Ingolstadt, Germany, 2008.'
date_created: 2019-08-28T10:35:49Z
date_updated: 2022-05-11T16:31:25Z
department:
- _id: '48'
language:
- iso: eng
place: Ingolstadt, Germany
publication: 2. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf"
status: public
title: Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit
  mit ATPG
type: conference
user_id: '209'
year: '2008'
...
---
_id: '13032'
author:
- first_name: Philipp
  full_name: Oehler, Philipp
  last_name: Oehler
- first_name: Alberto
  full_name: Bosio, Alberto
  last_name: Bosio
- first_name: Giorgio
  full_name: Di Natale, Giorgio
  last_name: Di Natale
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
citation:
  ama: 'Oehler P, Bosio A, Di Natale G, Hellebrand S. Modularer Selbsttest und optimierte
    Reparaturanalyse. In: <i>2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”</i>
    ; 2008.'
  apa: Oehler, P., Bosio, A., Di Natale, G., &#38; Hellebrand, S. (2008). Modularer
    Selbsttest und optimierte Reparaturanalyse. <i>2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit
    Und Entwurf.”</i>
  bibtex: '@inproceedings{Oehler_Bosio_Di Natale_Hellebrand_2008, place={Ingolstadt,
    Germany}, title={Modularer Selbsttest und optimierte Reparaturanalyse}, booktitle={2.
    GMM/GI/ITG-Fachtagung “Zuverlässigkeit und Entwurf”}, author={Oehler, Philipp
    and Bosio, Alberto and Di Natale, Giorgio and Hellebrand, Sybille}, year={2008}
    }'
  chicago: Oehler, Philipp, Alberto Bosio, Giorgio Di Natale, and Sybille Hellebrand.
    “Modularer Selbsttest Und Optimierte Reparaturanalyse.” In <i>2. GMM/GI/ITG-Fachtagung
    “Zuverlässigkeit Und Entwurf.”</i> Ingolstadt, Germany, 2008.
  ieee: P. Oehler, A. Bosio, G. Di Natale, and S. Hellebrand, “Modularer Selbsttest
    und optimierte Reparaturanalyse,” 2008.
  mla: Oehler, Philipp, et al. “Modularer Selbsttest Und Optimierte Reparaturanalyse.”
    <i>2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,”</i> 2008.
  short: 'P. Oehler, A. Bosio, G. Di Natale, S. Hellebrand, in: 2. GMM/GI/ITG-Fachtagung
    “Zuverlässigkeit Und Entwurf,” Ingolstadt, Germany, 2008.'
date_created: 2019-08-28T10:35:50Z
date_updated: 2022-05-11T16:34:03Z
department:
- _id: '48'
language:
- iso: eng
place: Ingolstadt, Germany
publication: 2. GMM/GI/ITG-Fachtagung "Zuverlässigkeit und Entwurf"
status: public
title: Modularer Selbsttest und optimierte Reparaturanalyse
type: conference
user_id: '209'
year: '2008'
...
---
_id: '13038'
author:
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
citation:
  ama: Hellebrand S. <i>Reliable Nanoscale Systems - Challenges and Strategies for
    On- and Offline Testing</i>. 5th IEEE East-West Design \&#38; Test Symposium,
    Yerevan, Armenia (Invited Talk); 2007.
  apa: Hellebrand, S. (2007). <i>Reliable Nanoscale Systems - Challenges and Strategies
    for On- and Offline Testing</i>. 5th IEEE East-West Design \&#38; Test Symposium,
    Yerevan, Armenia (Invited Talk).
  bibtex: '@book{Hellebrand_2007, place={5th IEEE East-West Design \&#38; Test Symposium,
    Yerevan, Armenia (Invited Talk)}, title={Reliable Nanoscale Systems - Challenges
    and Strategies for On- and Offline Testing}, author={Hellebrand, Sybille}, year={2007}
    }'
  chicago: Hellebrand, Sybille. <i>Reliable Nanoscale Systems - Challenges and Strategies
    for On- and Offline Testing</i>. 5th IEEE East-West Design \&#38; Test Symposium,
    Yerevan, Armenia (Invited Talk), 2007.
  ieee: S. Hellebrand, <i>Reliable Nanoscale Systems - Challenges and Strategies for
    On- and Offline Testing</i>. 5th IEEE East-West Design \&#38; Test Symposium,
    Yerevan, Armenia (Invited Talk), 2007.
  mla: Hellebrand, Sybille. <i>Reliable Nanoscale Systems - Challenges and Strategies
    for On- and Offline Testing</i>. 2007.
  short: S. Hellebrand, Reliable Nanoscale Systems - Challenges and Strategies for
    On- and Offline Testing, 5th IEEE East-West Design \&#38; Test Symposium, Yerevan,
    Armenia (Invited Talk), 2007.
date_created: 2019-08-28T10:40:47Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '48'
keyword:
- WORKSHOP
language:
- iso: eng
place: 5th IEEE East-West Design \& Test Symposium, Yerevan, Armenia (Invited Talk)
status: public
title: Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline
  Testing
type: misc
user_id: '659'
year: '2007'
...
---
_id: '13039'
author:
- first_name: Muhammad
  full_name: Ali, Muhammad
  last_name: Ali
- first_name: Michael
  full_name: Welzl, Michael
  last_name: Welzl
- first_name: Sven
  full_name: Hessler, Sven
  last_name: Hessler
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
citation:
  ama: Ali M, Welzl M, Hessler S, Hellebrand S. <i>An End-to-End Reliability Protocol
    to Address Transient Faults in Network on Chips</i>. DATE 2007 Friday Workshop
    on Diagnostic Services in Network-on-Chips, Nice, France, (Poster); 2007.
  apa: Ali, M., Welzl, M., Hessler, S., &#38; Hellebrand, S. (2007). <i>An End-to-End
    Reliability Protocol to Address Transient Faults in Network on Chips</i>. DATE
    2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France,
    (Poster).
  bibtex: '@book{Ali_Welzl_Hessler_Hellebrand_2007, place={DATE 2007 Friday Workshop
    on Diagnostic Services in Network-on-Chips, Nice, France, (Poster)}, title={An
    End-to-End Reliability Protocol to Address Transient Faults in Network on Chips},
    author={Ali, Muhammad and Welzl, Michael and Hessler, Sven and Hellebrand, Sybille},
    year={2007} }'
  chicago: Ali, Muhammad, Michael Welzl, Sven Hessler, and Sybille Hellebrand. <i>An
    End-to-End Reliability Protocol to Address Transient Faults in Network on Chips</i>.
    DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France,
    (Poster), 2007.
  ieee: M. Ali, M. Welzl, S. Hessler, and S. Hellebrand, <i>An End-to-End Reliability
    Protocol to Address Transient Faults in Network on Chips</i>. DATE 2007 Friday
    Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster), 2007.
  mla: Ali, Muhammad, et al. <i>An End-to-End Reliability Protocol to Address Transient
    Faults in Network on Chips</i>. 2007.
  short: M. Ali, M. Welzl, S. Hessler, S. Hellebrand, An End-to-End Reliability Protocol
    to Address Transient Faults in Network on Chips, DATE 2007 Friday Workshop on
    Diagnostic Services in Network-on-Chips, Nice, France, (Poster), 2007.
date_created: 2019-08-28T10:41:29Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '48'
keyword:
- WORKSHOP
language:
- iso: eng
place: DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice,
  France, (Poster)
status: public
title: An End-to-End Reliability Protocol to Address Transient Faults in Network on
  Chips
type: misc
user_id: '659'
year: '2007'
...
---
_id: '13042'
author:
- first_name: Philipp
  full_name: Oehler, Philipp
  last_name: Oehler
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
  full_name: Wunderlich, Hans-Joachim
  last_name: Wunderlich
citation:
  ama: Oehler P, Hellebrand S, Wunderlich H-J. <i>An Integrated Built-in Test and
    Repair Approach for Memories with 2D Redundancy</i>. 17th GI/ITG/GMM Workshop
    “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany;
    2007.
  apa: Oehler, P., Hellebrand, S., &#38; Wunderlich, H.-J. (2007). <i>An Integrated
    Built-in Test and Repair Approach for Memories with 2D Redundancy</i>. 17th GI/ITG/GMM
    Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen,
    Germany.
  bibtex: '@book{Oehler_Hellebrand_Wunderlich_2007, place={17th GI/ITG/GMM Workshop
    “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany},
    title={An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy},
    author={Oehler, Philipp and Hellebrand, Sybille and Wunderlich, Hans-Joachim},
    year={2007} }'
  chicago: Oehler, Philipp, Sybille Hellebrand, and Hans-Joachim Wunderlich. <i>An
    Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy</i>.
    17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und
    Systemen”, Erlangen, Germany, 2007.
  ieee: P. Oehler, S. Hellebrand, and H.-J. Wunderlich, <i>An Integrated Built-in
    Test and Repair Approach for Memories with 2D Redundancy</i>. 17th GI/ITG/GMM
    Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen,
    Germany, 2007.
  mla: Oehler, Philipp, et al. <i>An Integrated Built-in Test and Repair Approach
    for Memories with 2D Redundancy</i>. 2007.
  short: P. Oehler, S. Hellebrand, H.-J. Wunderlich, An Integrated Built-in Test and
    Repair Approach for Memories with 2D Redundancy, 17th GI/ITG/GMM Workshop “Testmethoden
    und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany, 2007.
date_created: 2019-08-28T10:43:12Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '48'
keyword:
- WORKSHOP
language:
- iso: eng
place: 17th GI/ITG/GMM Workshop "Testmethoden und Zuverlässigkeit von Schaltungen
  und Systemen", Erlangen, Germany
status: public
title: An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy
type: misc
user_id: '659'
year: '2007'
...
---
_id: '13043'
author:
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
citation:
  ama: Hellebrand S. <i>Qualitätssicherung Für Nanochips - Wie IT-Produkte Zuverlässig
    Werden</i>. ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany; 2007.
  apa: Hellebrand, S. (2007). <i>Qualitätssicherung für Nanochips - Wie IT-Produkte
    zuverlässig werden</i>. ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany.
  bibtex: '@book{Hellebrand_2007, place={ForschungsForum Paderborn, 10. Ausgabe, Paderborn,
    Germany}, title={Qualitätssicherung für Nanochips - Wie IT-Produkte zuverlässig
    werden}, author={Hellebrand, Sybille}, year={2007} }'
  chicago: Hellebrand, Sybille. <i>Qualitätssicherung Für Nanochips - Wie IT-Produkte
    Zuverlässig Werden</i>. ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany,
    2007.
  ieee: S. Hellebrand, <i>Qualitätssicherung für Nanochips - Wie IT-Produkte zuverlässig
    werden</i>. ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany, 2007.
  mla: Hellebrand, Sybille. <i>Qualitätssicherung Für Nanochips - Wie IT-Produkte
    Zuverlässig Werden</i>. 2007.
  short: S. Hellebrand, Qualitätssicherung Für Nanochips - Wie IT-Produkte Zuverlässig
    Werden, ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany, 2007.
date_created: 2019-08-28T10:43:54Z
date_updated: 2022-01-06T06:51:27Z
department:
- _id: '48'
language:
- iso: eng
place: ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany
status: public
title: Qualitätssicherung für Nanochips - Wie IT-Produkte zuverlässig werden
type: misc
user_id: '659'
year: '2007'
...
---
_id: '12995'
author:
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
- first_name: Christian
  full_name: G. Zoellin, Christian
  last_name: G. Zoellin
- first_name: Hans-Joachim
  full_name: Wunderlich, Hans-Joachim
  last_name: Wunderlich
- first_name: Stefan
  full_name: Ludwig, Stefan
  last_name: Ludwig
- first_name: Torsten
  full_name: Coym, Torsten
  last_name: Coym
- first_name: Bernd
  full_name: Straube, Bernd
  last_name: Straube
citation:
  ama: 'Hellebrand S, G. Zoellin C, Wunderlich H-J, Ludwig S, Coym T, Straube B. A
    Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction.
    In: <i>22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI
    Systems (DFT’07)</i>. IEEE; 2007:50-58. doi:<a href="https://doi.org/10.1109/dft.2007.43">10.1109/dft.2007.43</a>'
  apa: Hellebrand, S., G. Zoellin, C., Wunderlich, H.-J., Ludwig, S., Coym, T., &#38;
    Straube, B. (2007). A Refined Electrical Model for Particle Strikes and its Impact
    on SEU Prediction. <i>22nd IEEE International Symposium on Defect and Fault-Tolerance
    in VLSI Systems (DFT’07)</i>, 50–58. <a href="https://doi.org/10.1109/dft.2007.43">https://doi.org/10.1109/dft.2007.43</a>
  bibtex: '@inproceedings{Hellebrand_G. Zoellin_Wunderlich_Ludwig_Coym_Straube_2007,
    place={Rome, Italy}, title={A Refined Electrical Model for Particle Strikes and
    its Impact on SEU Prediction}, DOI={<a href="https://doi.org/10.1109/dft.2007.43">10.1109/dft.2007.43</a>},
    booktitle={22nd IEEE International Symposium on Defect and Fault-Tolerance in
    VLSI Systems (DFT’07)}, publisher={IEEE}, author={Hellebrand, Sybille and G. Zoellin,
    Christian and Wunderlich, Hans-Joachim and Ludwig, Stefan and Coym, Torsten and
    Straube, Bernd}, year={2007}, pages={50–58} }'
  chicago: 'Hellebrand, Sybille, Christian G. Zoellin, Hans-Joachim Wunderlich, Stefan
    Ludwig, Torsten Coym, and Bernd Straube. “A Refined Electrical Model for Particle
    Strikes and Its Impact on SEU Prediction.” In <i>22nd IEEE International Symposium
    on Defect and Fault-Tolerance in VLSI Systems (DFT’07)</i>, 50–58. Rome, Italy:
    IEEE, 2007. <a href="https://doi.org/10.1109/dft.2007.43">https://doi.org/10.1109/dft.2007.43</a>.'
  ieee: 'S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B.
    Straube, “A Refined Electrical Model for Particle Strikes and its Impact on SEU
    Prediction,” in <i>22nd IEEE International Symposium on Defect and Fault-Tolerance
    in VLSI Systems (DFT’07)</i>, 2007, pp. 50–58, doi: <a href="https://doi.org/10.1109/dft.2007.43">10.1109/dft.2007.43</a>.'
  mla: Hellebrand, Sybille, et al. “A Refined Electrical Model for Particle Strikes
    and Its Impact on SEU Prediction.” <i>22nd IEEE International Symposium on Defect
    and Fault-Tolerance in VLSI Systems (DFT’07)</i>, IEEE, 2007, pp. 50–58, doi:<a
    href="https://doi.org/10.1109/dft.2007.43">10.1109/dft.2007.43</a>.
  short: 'S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube,
    in: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
    (DFT’07), IEEE, Rome, Italy, 2007, pp. 50–58.'
date_created: 2019-08-28T10:18:57Z
date_updated: 2022-05-11T16:32:38Z
department:
- _id: '48'
doi: 10.1109/dft.2007.43
language:
- iso: eng
page: 50-58
place: Rome, Italy
publication: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI
  Systems (DFT'07)
publisher: IEEE
status: public
title: A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction
type: conference
user_id: '209'
year: '2007'
...
---
_id: '12996'
author:
- first_name: Philipp
  full_name: Oehler, Philipp
  last_name: Oehler
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
  full_name: Wunderlich, Hans-Joachim
  last_name: Wunderlich
citation:
  ama: 'Oehler P, Hellebrand S, Wunderlich H-J. Analyzing Test and Repair Times for
    2D Integrated Memory Built-in Test and Repair. In: <i>10th IEEE Workshop on Design
    and Diagnostics of Electronic Circuits and Systems (DDECS’07)</i>. IEEE; 2007:185-190.
    doi:<a href="https://doi.org/10.1109/ddecs.2007.4295278">10.1109/ddecs.2007.4295278</a>'
  apa: Oehler, P., Hellebrand, S., &#38; Wunderlich, H.-J. (2007). Analyzing Test
    and Repair Times for 2D Integrated Memory Built-in Test and Repair. <i>10th IEEE
    Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07)</i>,
    185–190. <a href="https://doi.org/10.1109/ddecs.2007.4295278">https://doi.org/10.1109/ddecs.2007.4295278</a>
  bibtex: '@inproceedings{Oehler_Hellebrand_Wunderlich_2007, place={Krakow, Poland},
    title={Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test
    and Repair}, DOI={<a href="https://doi.org/10.1109/ddecs.2007.4295278">10.1109/ddecs.2007.4295278</a>},
    booktitle={10th IEEE Workshop on Design and Diagnostics of Electronic Circuits
    and Systems (DDECS’07)}, publisher={IEEE}, author={Oehler, Philipp and Hellebrand,
    Sybille and Wunderlich, Hans-Joachim}, year={2007}, pages={185–190} }'
  chicago: 'Oehler, Philipp, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Analyzing
    Test and Repair Times for 2D Integrated Memory Built-in Test and Repair.” In <i>10th
    IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07)</i>,
    185–90. Krakow, Poland: IEEE, 2007. <a href="https://doi.org/10.1109/ddecs.2007.4295278">https://doi.org/10.1109/ddecs.2007.4295278</a>.'
  ieee: 'P. Oehler, S. Hellebrand, and H.-J. Wunderlich, “Analyzing Test and Repair
    Times for 2D Integrated Memory Built-in Test and Repair,” in <i>10th IEEE Workshop
    on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07)</i>, 2007,
    pp. 185–190, doi: <a href="https://doi.org/10.1109/ddecs.2007.4295278">10.1109/ddecs.2007.4295278</a>.'
  mla: Oehler, Philipp, et al. “Analyzing Test and Repair Times for 2D Integrated
    Memory Built-in Test and Repair.” <i>10th IEEE Workshop on Design and Diagnostics
    of Electronic Circuits and Systems (DDECS’07)</i>, IEEE, 2007, pp. 185–90, doi:<a
    href="https://doi.org/10.1109/ddecs.2007.4295278">10.1109/ddecs.2007.4295278</a>.
  short: 'P. Oehler, S. Hellebrand, H.-J. Wunderlich, in: 10th IEEE Workshop on Design
    and Diagnostics of Electronic Circuits and Systems (DDECS’07), IEEE, Krakow, Poland,
    2007, pp. 185–190.'
date_created: 2019-08-28T10:19:52Z
date_updated: 2022-05-11T16:34:43Z
department:
- _id: '48'
doi: 10.1109/ddecs.2007.4295278
language:
- iso: eng
page: 185-190
place: Krakow, Poland
publication: 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and
  Systems (DDECS'07)
publisher: IEEE
status: public
title: Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and
  Repair
type: conference
user_id: '209'
year: '2007'
...
---
_id: '12997'
author:
- first_name: Philipp
  full_name: Oehler, Philipp
  last_name: Oehler
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
  full_name: Wunderlich, Hans-Joachim
  last_name: Wunderlich
citation:
  ama: 'Oehler P, Hellebrand S, Wunderlich H-J. An Integrated Built-In Test and Repair
    Approach for Memories with 2D Redundancy. In: <i>12th IEEE European Test Symposium
    (ETS’07)</i>. IEEE; 2007:91-96. doi:<a href="https://doi.org/10.1109/ets.2007.10">10.1109/ets.2007.10</a>'
  apa: Oehler, P., Hellebrand, S., &#38; Wunderlich, H.-J. (2007). An Integrated Built-In
    Test and Repair Approach for Memories with 2D Redundancy. <i>12th IEEE European
    Test Symposium (ETS’07)</i>, 91–96. <a href="https://doi.org/10.1109/ets.2007.10">https://doi.org/10.1109/ets.2007.10</a>
  bibtex: '@inproceedings{Oehler_Hellebrand_Wunderlich_2007, place={Freiburg, Germany},
    title={An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy},
    DOI={<a href="https://doi.org/10.1109/ets.2007.10">10.1109/ets.2007.10</a>}, booktitle={12th
    IEEE European Test Symposium (ETS’07)}, publisher={IEEE}, author={Oehler, Philipp
    and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2007}, pages={91–96}
    }'
  chicago: 'Oehler, Philipp, Sybille Hellebrand, and Hans-Joachim Wunderlich. “An
    Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy.”
    In <i>12th IEEE European Test Symposium (ETS’07)</i>, 91–96. Freiburg, Germany:
    IEEE, 2007. <a href="https://doi.org/10.1109/ets.2007.10">https://doi.org/10.1109/ets.2007.10</a>.'
  ieee: 'P. Oehler, S. Hellebrand, and H.-J. Wunderlich, “An Integrated Built-In Test
    and Repair Approach for Memories with 2D Redundancy,” in <i>12th IEEE European
    Test Symposium (ETS’07)</i>, 2007, pp. 91–96, doi: <a href="https://doi.org/10.1109/ets.2007.10">10.1109/ets.2007.10</a>.'
  mla: Oehler, Philipp, et al. “An Integrated Built-In Test and Repair Approach for
    Memories with 2D Redundancy.” <i>12th IEEE European Test Symposium (ETS’07)</i>,
    IEEE, 2007, pp. 91–96, doi:<a href="https://doi.org/10.1109/ets.2007.10">10.1109/ets.2007.10</a>.
  short: 'P. Oehler, S. Hellebrand, H.-J. Wunderlich, in: 12th IEEE European Test
    Symposium (ETS’07), IEEE, Freiburg, Germany, 2007, pp. 91–96.'
date_created: 2019-08-28T10:19:53Z
date_updated: 2022-05-11T16:33:32Z
department:
- _id: '48'
doi: 10.1109/ets.2007.10
language:
- iso: eng
page: 91-96
place: Freiburg, Germany
publication: 12th IEEE European Test Symposium (ETS'07)
publisher: IEEE
status: public
title: An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy
type: conference
user_id: '209'
year: '2007'
...
---
_id: '13037'
author:
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
- first_name: Christian
  full_name: G. Zoellin, Christian
  last_name: G. Zoellin
- first_name: Hans-Joachim
  full_name: Wunderlich, Hans-Joachim
  last_name: Wunderlich
- first_name: Stefan
  full_name: Ludwig, Stefan
  last_name: Ludwig
- first_name: Torsten
  full_name: Coym, Torsten
  last_name: Coym
- first_name: Bernd
  full_name: Straube, Bernd
  last_name: Straube
citation:
  ama: 'Hellebrand S, G. Zoellin C, Wunderlich H-J, Ludwig S, Coym T, Straube B. Testing
    and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality
    Assurance. In: <i>43rd International Conference on Microelectronics, Devices and
    Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper)</i>.
    ; 2007.'
  apa: Hellebrand, S., G. Zoellin, C., Wunderlich, H.-J., Ludwig, S., Coym, T., &#38;
    Straube, B. (2007). Testing and Monitoring Nanoscale Systems - Challenges and
    Strategies for Advanced Quality Assurance. <i>43rd International Conference on
    Microelectronics, Devices and Material with the Workshop on Electronic Testing
    (MIDEM’07), (Invited Paper)</i>.
  bibtex: '@inproceedings{Hellebrand_G. Zoellin_Wunderlich_Ludwig_Coym_Straube_2007,
    place={Bled, Slovenia}, title={Testing and Monitoring Nanoscale Systems - Challenges
    and Strategies for Advanced Quality Assurance}, booktitle={43rd International
    Conference on Microelectronics, Devices and Material with the Workshop on Electronic
    Testing (MIDEM’07), (Invited Paper)}, author={Hellebrand, Sybille and G. Zoellin,
    Christian and Wunderlich, Hans-Joachim and Ludwig, Stefan and Coym, Torsten and
    Straube, Bernd}, year={2007} }'
  chicago: Hellebrand, Sybille, Christian G. Zoellin, Hans-Joachim Wunderlich, Stefan
    Ludwig, Torsten Coym, and Bernd Straube. “Testing and Monitoring Nanoscale Systems
    - Challenges and Strategies for Advanced Quality Assurance.” In <i>43rd International
    Conference on Microelectronics, Devices and Material with the Workshop on Electronic
    Testing (MIDEM’07), (Invited Paper)</i>. Bled, Slovenia, 2007.
  ieee: S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, and B.
    Straube, “Testing and Monitoring Nanoscale Systems - Challenges and Strategies
    for Advanced Quality Assurance,” 2007.
  mla: Hellebrand, Sybille, et al. “Testing and Monitoring Nanoscale Systems - Challenges
    and Strategies for Advanced Quality Assurance.” <i>43rd International Conference
    on Microelectronics, Devices and Material with the Workshop on Electronic Testing
    (MIDEM’07), (Invited Paper)</i>, 2007.
  short: 'S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube,
    in: 43rd International Conference on Microelectronics, Devices and Material with
    the Workshop on Electronic Testing (MIDEM’07), (Invited Paper), Bled, Slovenia,
    2007.'
date_created: 2019-08-28T10:40:00Z
date_updated: 2022-05-11T16:35:35Z
department:
- _id: '48'
language:
- iso: eng
place: Bled, Slovenia
publication: 43rd International Conference on Microelectronics, Devices and Material
  with the Workshop on Electronic Testing (MIDEM'07), (Invited Paper)
status: public
title: Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced
  Quality Assurance
type: conference
user_id: '209'
year: '2007'
...