[{"abstract":[{"text":"While FPGA accelerator boards and their respective high-level design tools are maturing, there is still a lack of multi-FPGA applications, libraries, and not least, benchmarks and reference implementations towards sustained HPC usage of these devices. As in the early days of GPUs in HPC, for workloads that can reasonably be decoupled into loosely coupled working sets, multi-accelerator support can be achieved by using standard communication interfaces like MPI on the host side. However, for performance and productivity, some applications can profit from a tighter coupling of the accelerators. FPGAs offer unique opportunities here when extending the dataflow characteristics to their communication interfaces.\r\n In this work, we extend the HPCC FPGA benchmark suite by multi-FPGA support and three missing benchmarks that particularly characterize or stress inter-device communication: b_eff, PTRANS, and LINPACK. With all benchmarks implemented for current boards with Intel and Xilinx FPGAs, we established a baseline for multi-FPGA performance. Additionally, for the communication-centric benchmarks, we explored the potential of direct FPGA-to-FPGA communication with a circuit-switched inter-FPGA network that is currently only available for one of the boards. The evaluation with parallel execution on up to 26 FPGA boards makes use of one of the largest academic FPGA installations.","lang":"eng"}],"user_id":"24135","publication":"ACM Transactions on Reconfigurable Technology and Systems","keyword":["General Computer Science"],"quality_controlled":"1","author":[{"last_name":"Meyer","id":"40778","first_name":"Marius","full_name":"Meyer, Marius"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"publisher":"Association for Computing Machinery (ACM)","date_created":"2023-01-23T08:40:42Z","status":"public","_id":"38041","main_file_link":[{"open_access":"1","url":"https://dl.acm.org/doi/10.1145/3576200"}],"citation":{"ama":"Meyer M, Kenter T, Plessl C. Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks. ACM Transactions on Reconfigurable Technology and Systems. Published online 2023. doi:10.1145/3576200","apa":"Meyer, M., Kenter, T., & Plessl, C. (2023). Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks. ACM Transactions on Reconfigurable Technology and Systems. https://doi.org/10.1145/3576200","chicago":"Meyer, Marius, Tobias Kenter, and Christian Plessl. “Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks.” ACM Transactions on Reconfigurable Technology and Systems, 2023. https://doi.org/10.1145/3576200.","bibtex":"@article{Meyer_Kenter_Plessl_2023, title={Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks}, DOI={10.1145/3576200}, journal={ACM Transactions on Reconfigurable Technology and Systems}, publisher={Association for Computing Machinery (ACM)}, author={Meyer, Marius and Kenter, Tobias and Plessl, Christian}, year={2023} }","mla":"Meyer, Marius, et al. “Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks.” ACM Transactions on Reconfigurable Technology and Systems, Association for Computing Machinery (ACM), 2023, doi:10.1145/3576200.","short":"M. Meyer, T. Kenter, C. Plessl, ACM Transactions on Reconfigurable Technology and Systems (2023).","ieee":"M. Meyer, T. Kenter, and C. Plessl, “Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks,” ACM Transactions on Reconfigurable Technology and Systems, 2023, doi: 10.1145/3576200."},"year":"2023","type":"journal_article","title":"Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks","department":[{"_id":"27"},{"_id":"518"}],"project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"},{"name":"SFB 901 - C: SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901: SFB 901","grant_number":"160364472","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - C2: SFB 901 - Subproject C2","_id":"14"}],"publication_identifier":{"issn":["1936-7406","1936-7414"]},"publication_status":"published","date_updated":"2023-07-28T08:02:05Z","oa":"1","doi":"10.1145/3576200","language":[{"iso":"eng"}]},{"ddc":["004"],"user_id":"3145","publisher":"Heinz Nixdorf Institut, Universität Paderborn","author":[{"last_name":"Hansmeier","id":"49992","first_name":"Tim","full_name":"Hansmeier, Tim","orcid":"0000-0003-1377-3339"},{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"full_name":"Meyer, Marius","first_name":"Marius","id":"40778","last_name":"Meyer"},{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"publication":"On-The-Fly Computing -- Individualized IT-services in dynamic markets","file_date_updated":"2023-07-07T11:17:33Z","file":[{"access_level":"open_access","file_name":"C2-Chapter-SFB-Buch-Final.pdf","date_created":"2023-07-07T08:15:35Z","relation":"main_file","content_type":"application/pdf","date_updated":"2023-07-07T11:17:33Z","file_id":"45894","creator":"florida","file_size":2288788}],"volume":412,"status":"public","has_accepted_license":"1","date_created":"2023-07-07T08:15:45Z","_id":"45893","intvolume":" 412","citation":{"ieee":"T. Hansmeier, T. Kenter, M. Meyer, H. Riebler, M. Platzner, and C. Plessl, “Compute Centers I: Heterogeneous Execution Environments,” in On-The-Fly Computing -- Individualized IT-services in dynamic markets, vol. 412, C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, and H. Wehrheim, Eds. Paderborn: Heinz Nixdorf Institut, Universität Paderborn, 2023, pp. 165–182.","short":"T. Hansmeier, T. Kenter, M. Meyer, H. Riebler, M. Platzner, C. Plessl, in: C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, H. Wehrheim (Eds.), On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets, Heinz Nixdorf Institut, Universität Paderborn, Paderborn, 2023, pp. 165–182.","bibtex":"@inbook{Hansmeier_Kenter_Meyer_Riebler_Platzner_Plessl_2023, place={Paderborn}, series={Verlagsschriftenreihe des Heinz Nixdorf Instituts}, title={Compute Centers I: Heterogeneous Execution Environments}, volume={412}, DOI={10.5281/zenodo.8068642}, booktitle={On-The-Fly Computing -- Individualized IT-services in dynamic markets}, publisher={Heinz Nixdorf Institut, Universität Paderborn}, author={Hansmeier, Tim and Kenter, Tobias and Meyer, Marius and Riebler, Heinrich and Platzner, Marco and Plessl, Christian}, editor={Haake, Claus-Jochen and Meyer auf der Heide, Friedhelm and Platzner, Marco and Wachsmuth, Henning and Wehrheim, Heike}, year={2023}, pages={165–182}, collection={Verlagsschriftenreihe des Heinz Nixdorf Instituts} }","mla":"Hansmeier, Tim, et al. “Compute Centers I: Heterogeneous Execution Environments.” On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets, edited by Claus-Jochen Haake et al., vol. 412, Heinz Nixdorf Institut, Universität Paderborn, 2023, pp. 165–82, doi:10.5281/zenodo.8068642.","ama":"Hansmeier T, Kenter T, Meyer M, Riebler H, Platzner M, Plessl C. Compute Centers I: Heterogeneous Execution Environments. In: Haake C-J, Meyer auf der Heide F, Platzner M, Wachsmuth H, Wehrheim H, eds. On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets. Vol 412. Verlagsschriftenreihe des Heinz Nixdorf Instituts. Heinz Nixdorf Institut, Universität Paderborn; 2023:165-182. doi:10.5281/zenodo.8068642","apa":"Hansmeier, T., Kenter, T., Meyer, M., Riebler, H., Platzner, M., & Plessl, C. (2023). Compute Centers I: Heterogeneous Execution Environments. In C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, & H. Wehrheim (Eds.), On-The-Fly Computing -- Individualized IT-services in dynamic markets (Vol. 412, pp. 165–182). Heinz Nixdorf Institut, Universität Paderborn. https://doi.org/10.5281/zenodo.8068642","chicago":"Hansmeier, Tim, Tobias Kenter, Marius Meyer, Heinrich Riebler, Marco Platzner, and Christian Plessl. “Compute Centers I: Heterogeneous Execution Environments.” In On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets, edited by Claus-Jochen Haake, Friedhelm Meyer auf der Heide, Marco Platzner, Henning Wachsmuth, and Heike Wehrheim, 412:165–82. Verlagsschriftenreihe Des Heinz Nixdorf Instituts. Paderborn: Heinz Nixdorf Institut, Universität Paderborn, 2023. https://doi.org/10.5281/zenodo.8068642."},"year":"2023","type":"book_chapter","page":"165-182","place":"Paderborn","title":"Compute Centers I: Heterogeneous Execution Environments","department":[{"_id":"7"},{"_id":"27"},{"_id":"518"}],"editor":[{"last_name":"Haake","first_name":"Claus-Jochen","full_name":"Haake, Claus-Jochen"},{"last_name":"Meyer auf der Heide","full_name":"Meyer auf der Heide, Friedhelm","first_name":"Friedhelm"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"},{"first_name":"Henning","full_name":"Wachsmuth, Henning","last_name":"Wachsmuth"},{"first_name":"Heike","full_name":"Wehrheim, Heike","last_name":"Wehrheim"}],"project":[{"grant_number":"160364472","name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten ","_id":"1"},{"_id":"4","name":"SFB 901 - C: SFB 901 - Project Area C"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - C2: SFB 901 - On-The-Fly Compute Centers I: Heterogene Ausführungsumgebungen (Subproject C2)"}],"date_updated":"2023-07-28T09:38:14Z","doi":"10.5281/zenodo.8068642","oa":"1","series_title":"Verlagsschriftenreihe des Heinz Nixdorf Instituts","language":[{"iso":"eng"}]},{"main_file_link":[{"open_access":"1","url":"https://dl.acm.org/doi/pdf/10.1145/3597031.3597050"}],"year":"2023","citation":{"mla":"Opdenhövel, Jan-Oliver, et al. “Mutation Tree Reconstruction of Tumor Cells on FPGAs Using a Bit-Level Matrix Representation.” Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, ACM, 2023, doi:10.1145/3597031.3597050.","bibtex":"@inproceedings{Opdenhövel_Plessl_Kenter_2023, title={Mutation Tree Reconstruction of Tumor Cells on FPGAs Using a Bit-Level Matrix Representation}, DOI={10.1145/3597031.3597050}, booktitle={Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies}, publisher={ACM}, author={Opdenhövel, Jan-Oliver and Plessl, Christian and Kenter, Tobias}, year={2023} }","chicago":"Opdenhövel, Jan-Oliver, Christian Plessl, and Tobias Kenter. “Mutation Tree Reconstruction of Tumor Cells on FPGAs Using a Bit-Level Matrix Representation.” In Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. ACM, 2023. https://doi.org/10.1145/3597031.3597050.","apa":"Opdenhövel, J.-O., Plessl, C., & Kenter, T. (2023). Mutation Tree Reconstruction of Tumor Cells on FPGAs Using a Bit-Level Matrix Representation. Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. https://doi.org/10.1145/3597031.3597050","ama":"Opdenhövel J-O, Plessl C, Kenter T. Mutation Tree Reconstruction of Tumor Cells on FPGAs Using a Bit-Level Matrix Representation. In: Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. ACM; 2023. doi:10.1145/3597031.3597050","ieee":"J.-O. Opdenhövel, C. Plessl, and T. Kenter, “Mutation Tree Reconstruction of Tumor Cells on FPGAs Using a Bit-Level Matrix Representation,” 2023, doi: 10.1145/3597031.3597050.","short":"J.-O. Opdenhövel, C. Plessl, T. Kenter, in: Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, ACM, 2023."},"type":"conference","language":[{"iso":"eng"}],"_id":"46190","date_updated":"2023-07-28T09:58:06Z","doi":"10.1145/3597031.3597050","oa":"1","department":[{"_id":"27"},{"_id":"518"}],"publication":"Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies","quality_controlled":"1","publisher":"ACM","author":[{"last_name":"Opdenhövel","full_name":"Opdenhövel, Jan-Oliver","first_name":"Jan-Oliver"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"}],"publication_status":"published","date_created":"2023-07-28T09:49:23Z","project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"status":"public","title":"Mutation Tree Reconstruction of Tumor Cells on FPGAs Using a Bit-Level Matrix Representation","user_id":"3145"},{"main_file_link":[{"url":"https://dl.acm.org/doi/pdf/10.1145/3592979.3593407","open_access":"1"}],"language":[{"iso":"eng"}],"type":"conference","year":"2023","citation":{"ieee":"J. Faj, T. Kenter, S. Faghih-Naini, C. Plessl, and V. Aizinger, “Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured Meshes,” 2023, doi: 10.1145/3592979.3593407.","short":"J. Faj, T. Kenter, S. Faghih-Naini, C. Plessl, V. Aizinger, in: Proceedings of the Platform for Advanced Scientific Computing Conference, ACM, 2023.","bibtex":"@inproceedings{Faj_Kenter_Faghih-Naini_Plessl_Aizinger_2023, title={Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured Meshes}, DOI={10.1145/3592979.3593407}, booktitle={Proceedings of the Platform for Advanced Scientific Computing Conference}, publisher={ACM}, author={Faj, Jennifer and Kenter, Tobias and Faghih-Naini, Sara and Plessl, Christian and Aizinger, Vadym}, year={2023} }","mla":"Faj, Jennifer, et al. “Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured Meshes.” Proceedings of the Platform for Advanced Scientific Computing Conference, ACM, 2023, doi:10.1145/3592979.3593407.","chicago":"Faj, Jennifer, Tobias Kenter, Sara Faghih-Naini, Christian Plessl, and Vadym Aizinger. “Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured Meshes.” In Proceedings of the Platform for Advanced Scientific Computing Conference. ACM, 2023. https://doi.org/10.1145/3592979.3593407.","ama":"Faj J, Kenter T, Faghih-Naini S, Plessl C, Aizinger V. Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured Meshes. In: Proceedings of the Platform for Advanced Scientific Computing Conference. ACM; 2023. doi:10.1145/3592979.3593407","apa":"Faj, J., Kenter, T., Faghih-Naini, S., Plessl, C., & Aizinger, V. (2023). Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured Meshes. Proceedings of the Platform for Advanced Scientific Computing Conference. https://doi.org/10.1145/3592979.3593407"},"date_updated":"2023-07-28T09:48:19Z","_id":"46188","oa":"1","doi":"10.1145/3592979.3593407","publication":"Proceedings of the Platform for Advanced Scientific Computing Conference","department":[{"_id":"27"},{"_id":"518"}],"quality_controlled":"1","author":[{"id":"78722","last_name":"Faj","full_name":"Faj, Jennifer","first_name":"Jennifer"},{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"full_name":"Faghih-Naini, Sara","first_name":"Sara","last_name":"Faghih-Naini"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"full_name":"Aizinger, Vadym","first_name":"Vadym","last_name":"Aizinger"}],"publisher":"ACM","project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"date_created":"2023-07-28T09:42:14Z","status":"public","publication_status":"published","user_id":"3145","title":"Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured Meshes"},{"publication_status":"published","status":"public","project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"date_created":"2023-07-28T09:46:25Z","publisher":"ACM","quality_controlled":"1","author":[{"full_name":"Prouveur, Charles","first_name":"Charles","last_name":"Prouveur"},{"first_name":"Matthieu","full_name":"Haefele, Matthieu","last_name":"Haefele"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"last_name":"Voss","first_name":"Nils","full_name":"Voss, Nils"}],"department":[{"_id":"27"},{"_id":"518"}],"publication":"Proceedings of the Platform for Advanced Scientific Computing Conference","title":"FPGA Acceleration for HPC Supercapacitor Simulations","user_id":"3145","year":"2023","type":"conference","citation":{"apa":"Prouveur, C., Haefele, M., Kenter, T., & Voss, N. (2023). FPGA Acceleration for HPC Supercapacitor Simulations. Proceedings of the Platform for Advanced Scientific Computing Conference. https://doi.org/10.1145/3592979.3593419","ama":"Prouveur C, Haefele M, Kenter T, Voss N. FPGA Acceleration for HPC Supercapacitor Simulations. In: Proceedings of the Platform for Advanced Scientific Computing Conference. ACM; 2023. doi:10.1145/3592979.3593419","chicago":"Prouveur, Charles, Matthieu Haefele, Tobias Kenter, and Nils Voss. “FPGA Acceleration for HPC Supercapacitor Simulations.” In Proceedings of the Platform for Advanced Scientific Computing Conference. ACM, 2023. https://doi.org/10.1145/3592979.3593419.","mla":"Prouveur, Charles, et al. “FPGA Acceleration for HPC Supercapacitor Simulations.” Proceedings of the Platform for Advanced Scientific Computing Conference, ACM, 2023, doi:10.1145/3592979.3593419.","bibtex":"@inproceedings{Prouveur_Haefele_Kenter_Voss_2023, title={FPGA Acceleration for HPC Supercapacitor Simulations}, DOI={10.1145/3592979.3593419}, booktitle={Proceedings of the Platform for Advanced Scientific Computing Conference}, publisher={ACM}, author={Prouveur, Charles and Haefele, Matthieu and Kenter, Tobias and Voss, Nils}, year={2023} }","short":"C. Prouveur, M. Haefele, T. Kenter, N. Voss, in: Proceedings of the Platform for Advanced Scientific Computing Conference, ACM, 2023.","ieee":"C. Prouveur, M. Haefele, T. Kenter, and N. Voss, “FPGA Acceleration for HPC Supercapacitor Simulations,” 2023, doi: 10.1145/3592979.3593419."},"language":[{"iso":"eng"}],"main_file_link":[{"url":"https://dl.acm.org/doi/pdf/10.1145/3592979.3593419","open_access":"1"}],"doi":"10.1145/3592979.3593419","oa":"1","_id":"46189","date_updated":"2023-07-28T09:58:16Z"},{"title":"Computing and Compressing Electron Repulsion Integrals on FPGAs","user_id":"75963","external_id":{"arxiv":["2303.13632"]},"abstract":[{"text":"The computation of electron repulsion integrals (ERIs) over Gaussian-type orbitals (GTOs) is a challenging problem in quantum-mechanics-based atomistic simulations. In practical simulations, several trillions of ERIs may have to be\r\ncomputed for every time step.\r\nIn this work, we investigate FPGAs as accelerators for the ERI computation. We use template parameters, here within the Intel oneAPI tool flow, to create customized designs for 256 different ERI quartet classes, based on their orbitals. To maximize data reuse, all intermediates are buffered in FPGA on-chip memory with customized layout. The pre-calculation of intermediates also helps to overcome data dependencies caused by multi-dimensional recurrence\r\nrelations. The involved loop structures are partially or even fully unrolled for high throughput of FPGA kernels. Furthermore, a lossy compression algorithm utilizing arbitrary bitwidth integers is integrated in the FPGA kernels. To our\r\nbest knowledge, this is the first work on ERI computation on FPGAs that supports more than just the single most basic quartet class. Also, the integration of ERI computation and compression it a novelty that is not even covered by CPU or GPU libraries so far.\r\nOur evaluation shows that using 16-bit integer for the ERI compression, the fastest FPGA kernels exceed the performance of 10 GERIS ($10 \\times 10^9$ ERIs per second) on one Intel Stratix 10 GX 2800 FPGA, with maximum absolute errors around $10^{-7}$ - $10^{-5}$ Hartree. The measured throughput can be accurately explained by a performance model. The FPGA kernels deployed on 2 FPGAs outperform similar computations using the widely used libint reference on a two-socket server with 40 Xeon Gold 6148 CPU cores of the same process technology by factors up to 6.0x and on a new two-socket server with 128 EPYC 7713 CPU cores by up to 1.9x.","lang":"eng"}],"project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"date_created":"2023-03-30T11:15:40Z","status":"public","department":[{"_id":"27"},{"_id":"518"}],"publication":"2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","quality_controlled":"1","author":[{"last_name":"Wu","id":"77439","first_name":"Xin","full_name":"Wu, Xin"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"first_name":"Robert","orcid":"0000-0002-6268-539","full_name":"Schade, Robert","last_name":"Schade","id":"75963"},{"last_name":"Kühne","id":"49079","first_name":"Thomas","full_name":"Kühne, Thomas"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"doi":"10.1109/FCCM57271.2023.00026","date_updated":"2023-08-02T15:05:42Z","_id":"43228","page":"162-173","type":"conference","year":"2023","citation":{"ieee":"X. Wu, T. Kenter, R. Schade, T. Kühne, and C. Plessl, “Computing and Compressing Electron Repulsion Integrals on FPGAs,” in 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2023, pp. 162–173, doi: 10.1109/FCCM57271.2023.00026.","mla":"Wu, Xin, et al. “Computing and Compressing Electron Repulsion Integrals on FPGAs.” 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2023, pp. 162–73, doi:10.1109/FCCM57271.2023.00026.","bibtex":"@inproceedings{Wu_Kenter_Schade_Kühne_Plessl_2023, title={Computing and Compressing Electron Repulsion Integrals on FPGAs}, DOI={10.1109/FCCM57271.2023.00026}, booktitle={2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)}, author={Wu, Xin and Kenter, Tobias and Schade, Robert and Kühne, Thomas and Plessl, Christian}, year={2023}, pages={162–173} }","ama":"Wu X, Kenter T, Schade R, Kühne T, Plessl C. Computing and Compressing Electron Repulsion Integrals on FPGAs. In: 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). ; 2023:162-173. doi:10.1109/FCCM57271.2023.00026","short":"X. Wu, T. Kenter, R. Schade, T. Kühne, C. Plessl, in: 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2023, pp. 162–173.","apa":"Wu, X., Kenter, T., Schade, R., Kühne, T., & Plessl, C. (2023). Computing and Compressing Electron Repulsion Integrals on FPGAs. 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 162–173. https://doi.org/10.1109/FCCM57271.2023.00026","chicago":"Wu, Xin, Tobias Kenter, Robert Schade, Thomas Kühne, and Christian Plessl. “Computing and Compressing Electron Repulsion Integrals on FPGAs.” In 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 162–73, 2023. https://doi.org/10.1109/FCCM57271.2023.00026."},"language":[{"iso":"eng"}],"main_file_link":[{"url":"https://ieeexplore.ieee.org/document/10171537"}]},{"year":"2023","citation":{"chicago":"Schade, Robert, Tobias Kenter, Hossam Elgabarty, Michael Lass, Thomas Kühne, and Christian Plessl. “Breaking the Exascale Barrier for the Electronic Structure Problem in Ab-Initio Molecular Dynamics.” The International Journal of High Performance Computing Applications, 2023. https://doi.org/10.1177/10943420231177631.","ama":"Schade R, Kenter T, Elgabarty H, Lass M, Kühne T, Plessl C. Breaking the exascale barrier for the electronic structure problem in ab-initio molecular dynamics. The International Journal of High Performance Computing Applications. Published online 2023. doi:10.1177/10943420231177631","apa":"Schade, R., Kenter, T., Elgabarty, H., Lass, M., Kühne, T., & Plessl, C. (2023). Breaking the exascale barrier for the electronic structure problem in ab-initio molecular dynamics. The International Journal of High Performance Computing Applications, Article 109434202311776. https://doi.org/10.1177/10943420231177631","short":"R. Schade, T. Kenter, H. Elgabarty, M. Lass, T. Kühne, C. Plessl, The International Journal of High Performance Computing Applications (2023).","bibtex":"@article{Schade_Kenter_Elgabarty_Lass_Kühne_Plessl_2023, title={Breaking the exascale barrier for the electronic structure problem in ab-initio molecular dynamics}, DOI={10.1177/10943420231177631}, number={109434202311776}, journal={The International Journal of High Performance Computing Applications}, publisher={SAGE Publications}, author={Schade, Robert and Kenter, Tobias and Elgabarty, Hossam and Lass, Michael and Kühne, Thomas and Plessl, Christian}, year={2023} }","mla":"Schade, Robert, et al. “Breaking the Exascale Barrier for the Electronic Structure Problem in Ab-Initio Molecular Dynamics.” The International Journal of High Performance Computing Applications, 109434202311776, SAGE Publications, 2023, doi:10.1177/10943420231177631.","ieee":"R. Schade, T. Kenter, H. Elgabarty, M. Lass, T. Kühne, and C. Plessl, “Breaking the exascale barrier for the electronic structure problem in ab-initio molecular dynamics,” The International Journal of High Performance Computing Applications, Art. no. 109434202311776, 2023, doi: 10.1177/10943420231177631."},"type":"journal_article","main_file_link":[{"url":"https://journals.sagepub.com/doi/10.1177/10943420231177631","open_access":"1"}],"article_number":"109434202311776","_id":"45361","status":"public","date_created":"2023-05-30T09:19:09Z","quality_controlled":"1","publisher":"SAGE Publications","author":[{"id":"75963","last_name":"Schade","full_name":"Schade, Robert","orcid":"0000-0002-6268-539","first_name":"Robert"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"id":"60250","last_name":"Elgabarty","orcid":"0000-0002-4945-1481","full_name":"Elgabarty, Hossam","first_name":"Hossam"},{"orcid":"0000-0002-5708-7632","full_name":"Lass, Michael","first_name":"Michael","id":"24135","last_name":"Lass"},{"id":"49079","last_name":"Kühne","full_name":"Kühne, Thomas","first_name":"Thomas"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"keyword":["Hardware and Architecture","Theoretical Computer Science","Software"],"publication":"The International Journal of High Performance Computing Applications","user_id":"75963","article_type":"original","abstract":[{"text":" The non-orthogonal local submatrix method applied to electronic structure–based molecular dynamics simulations is shown to exceed 1.1 EFLOP/s in FP16/FP32-mixed floating-point arithmetic when using 4400 NVIDIA A100 GPUs of the Perlmutter system. This is enabled by a modification of the original method that pushes the sustained fraction of the peak performance to about 80%. Example calculations are performed for SARS-CoV-2 spike proteins with up to 83 million atoms. ","lang":"eng"}],"language":[{"iso":"eng"}],"doi":"10.1177/10943420231177631","oa":"1","date_updated":"2023-08-02T15:04:53Z","publication_identifier":{"issn":["1094-3420","1741-2846"]},"publication_status":"published","project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"department":[{"_id":"27"},{"_id":"518"}],"title":"Breaking the exascale barrier for the electronic structure problem in ab-initio molecular dynamics"},{"doi":"10.1007/978-3-031-32041-5_5","_id":"46191","date_updated":"2024-01-22T09:58:49Z","language":[{"iso":"eng"}],"type":"book_chapter","year":"2023","citation":{"apa":"Alt, C., Kenter, T., Faghih-Naini, S., Faj, J., Opdenhövel, J.-O., Plessl, C., Aizinger, V., Hönig, J., & Köstler, H. (2023). Shallow Water DG Simulations on FPGAs: Design and Comparison of a Novel Code Generation Pipeline. In Lecture Notes in Computer Science. Springer Nature Switzerland. https://doi.org/10.1007/978-3-031-32041-5_5","short":"C. Alt, T. Kenter, S. Faghih-Naini, J. Faj, J.-O. Opdenhövel, C. Plessl, V. Aizinger, J. Hönig, H. Köstler, in: Lecture Notes in Computer Science, Springer Nature Switzerland, Cham, 2023.","ama":"Alt C, Kenter T, Faghih-Naini S, et al. Shallow Water DG Simulations on FPGAs: Design and Comparison of a Novel Code Generation Pipeline. In: Lecture Notes in Computer Science. Springer Nature Switzerland; 2023. doi:10.1007/978-3-031-32041-5_5","chicago":"Alt, Christoph, Tobias Kenter, Sara Faghih-Naini, Jennifer Faj, Jan-Oliver Opdenhövel, Christian Plessl, Vadym Aizinger, Jan Hönig, and Harald Köstler. “Shallow Water DG Simulations on FPGAs: Design and Comparison of a Novel Code Generation Pipeline.” In Lecture Notes in Computer Science. Cham: Springer Nature Switzerland, 2023. https://doi.org/10.1007/978-3-031-32041-5_5.","ieee":"C. Alt et al., “Shallow Water DG Simulations on FPGAs: Design and Comparison of a Novel Code Generation Pipeline,” in Lecture Notes in Computer Science, Cham: Springer Nature Switzerland, 2023.","mla":"Alt, Christoph, et al. “Shallow Water DG Simulations on FPGAs: Design and Comparison of a Novel Code Generation Pipeline.” Lecture Notes in Computer Science, Springer Nature Switzerland, 2023, doi:10.1007/978-3-031-32041-5_5.","bibtex":"@inbook{Alt_Kenter_Faghih-Naini_Faj_Opdenhövel_Plessl_Aizinger_Hönig_Köstler_2023, place={Cham}, title={Shallow Water DG Simulations on FPGAs: Design and Comparison of a Novel Code Generation Pipeline}, DOI={10.1007/978-3-031-32041-5_5}, booktitle={Lecture Notes in Computer Science}, publisher={Springer Nature Switzerland}, author={Alt, Christoph and Kenter, Tobias and Faghih-Naini, Sara and Faj, Jennifer and Opdenhövel, Jan-Oliver and Plessl, Christian and Aizinger, Vadym and Hönig, Jan and Köstler, Harald}, year={2023} }"},"user_id":"3145","title":"Shallow Water DG Simulations on FPGAs: Design and Comparison of a Novel Code Generation Pipeline","place":"Cham","date_created":"2023-07-28T09:53:21Z","project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"status":"public","publication_identifier":{"isbn":["9783031320408","9783031320415"],"issn":["0302-9743","1611-3349"]},"publication_status":"published","department":[{"_id":"27"},{"_id":"518"}],"publication":"Lecture Notes in Computer Science","quality_controlled":"1","author":[{"full_name":"Alt, Christoph","first_name":"Christoph","id":"100625","last_name":"Alt"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"last_name":"Faghih-Naini","first_name":"Sara","full_name":"Faghih-Naini, Sara"},{"first_name":"Jennifer","full_name":"Faj, Jennifer","last_name":"Faj","id":"78722"},{"full_name":"Opdenhövel, Jan-Oliver","first_name":"Jan-Oliver","last_name":"Opdenhövel"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"full_name":"Aizinger, Vadym","first_name":"Vadym","last_name":"Aizinger"},{"first_name":"Jan","full_name":"Hönig, Jan","last_name":"Hönig"},{"first_name":"Harald","full_name":"Köstler, Harald","last_name":"Köstler"}],"publisher":"Springer Nature Switzerland"},{"_id":"43439","date_updated":"2024-01-22T09:56:42Z","year":"2023","type":"preprint","citation":{"short":"L. Van Hirtum, P. De Causmaecker, J. Goemaere, T. Kenter, H. Riebler, M. Lass, C. Plessl, ArXiv:2304.03039 (2023).","ieee":"L. Van Hirtum et al., “A computation of D(9) using FPGA Supercomputing,” arXiv:2304.03039. 2023.","ama":"Van Hirtum L, De Causmaecker P, Goemaere J, et al. A computation of D(9) using FPGA Supercomputing. arXiv:230403039. Published online 2023.","apa":"Van Hirtum, L., De Causmaecker, P., Goemaere, J., Kenter, T., Riebler, H., Lass, M., & Plessl, C. (2023). A computation of D(9) using FPGA Supercomputing. In arXiv:2304.03039.","chicago":"Van Hirtum, Lennart, Patrick De Causmaecker, Jens Goemaere, Tobias Kenter, Heinrich Riebler, Michael Lass, and Christian Plessl. “A Computation of D(9) Using FPGA Supercomputing.” ArXiv:2304.03039, 2023.","mla":"Van Hirtum, Lennart, et al. “A Computation of D(9) Using FPGA Supercomputing.” ArXiv:2304.03039, 2023.","bibtex":"@article{Van Hirtum_De Causmaecker_Goemaere_Kenter_Riebler_Lass_Plessl_2023, title={A computation of D(9) using FPGA Supercomputing}, journal={arXiv:2304.03039}, author={Van Hirtum, Lennart and De Causmaecker, Patrick and Goemaere, Jens and Kenter, Tobias and Riebler, Heinrich and Lass, Michael and Plessl, Christian}, year={2023} }"},"language":[{"iso":"eng"}],"external_id":{"arxiv":["2304.03039"]},"abstract":[{"lang":"eng","text":"This preprint makes the claim of having computed the $9^{th}$ Dedekind\r\nNumber. This was done by building an efficient FPGA Accelerator for the core\r\noperation of the process, and parallelizing it on the Noctua 2 Supercluster at\r\nPaderborn University. The resulting value is\r\n286386577668298411128469151667598498812366. This value can be verified in two\r\nsteps. We have made the data file containing the 490M results available, each\r\nof which can be verified separately on CPU, and the whole file sums to our\r\nproposed value."}],"title":"A computation of D(9) using FPGA Supercomputing","user_id":"3145","publication":"arXiv:2304.03039","department":[{"_id":"27"},{"_id":"518"}],"author":[{"last_name":"Van Hirtum","first_name":"Lennart","full_name":"Van Hirtum, Lennart"},{"last_name":"De Causmaecker","full_name":"De Causmaecker, Patrick","first_name":"Patrick"},{"full_name":"Goemaere, Jens","first_name":"Jens","last_name":"Goemaere"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"last_name":"Riebler","id":"8961","first_name":"Heinrich","full_name":"Riebler, Heinrich"},{"first_name":"Michael","full_name":"Lass, Michael","orcid":"0000-0002-5708-7632","last_name":"Lass","id":"24135"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"date_created":"2023-04-08T11:05:29Z","status":"public"},{"title":"Bringing Massive Parallelism and Hardware Acceleration to Linear Scaling Density Functional Theory Through Targeted Approximations","user_id":"24135","place":"Paderborn","status":"public","date_created":"2022-07-25T18:13:51Z","publisher":"Universität Paderborn","author":[{"first_name":"Michael","orcid":"0000-0002-5708-7632","full_name":"Lass, Michael","last_name":"Lass","id":"24135"}],"department":[{"_id":"27"},{"_id":"518"}],"doi":"10.17619/UNIPB/1-1281","date_updated":"2022-07-25T18:14:23Z","_id":"32414","type":"dissertation","year":"2022","citation":{"short":"M. Lass, Bringing Massive Parallelism and Hardware Acceleration to Linear Scaling Density Functional Theory Through Targeted Approximations, Universität Paderborn, Paderborn, 2022.","ieee":"M. Lass, Bringing Massive Parallelism and Hardware Acceleration to Linear Scaling Density Functional Theory Through Targeted Approximations. Paderborn: Universität Paderborn, 2022.","apa":"Lass, M. (2022). Bringing Massive Parallelism and Hardware Acceleration to Linear Scaling Density Functional Theory Through Targeted Approximations. Universität Paderborn. https://doi.org/10.17619/UNIPB/1-1281","ama":"Lass M. Bringing Massive Parallelism and Hardware Acceleration to Linear Scaling Density Functional Theory Through Targeted Approximations. Universität Paderborn; 2022. doi:10.17619/UNIPB/1-1281","chicago":"Lass, Michael. Bringing Massive Parallelism and Hardware Acceleration to Linear Scaling Density Functional Theory Through Targeted Approximations. Paderborn: Universität Paderborn, 2022. https://doi.org/10.17619/UNIPB/1-1281.","mla":"Lass, Michael. Bringing Massive Parallelism and Hardware Acceleration to Linear Scaling Density Functional Theory Through Targeted Approximations. Universität Paderborn, 2022, doi:10.17619/UNIPB/1-1281.","bibtex":"@book{Lass_2022, place={Paderborn}, title={Bringing Massive Parallelism and Hardware Acceleration to Linear Scaling Density Functional Theory Through Targeted Approximations}, DOI={10.17619/UNIPB/1-1281}, publisher={Universität Paderborn}, author={Lass, Michael}, year={2022} }"},"language":[{"iso":"eng"}],"supervisor":[{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}]},{"date_updated":"2023-07-28T08:03:41Z","_id":"33493","type":"preprint","year":"2022","citation":{"ieee":"V. Gavini et al., “Roadmap on Electronic Structure Codes in the Exascale Era,” arXiv:2209.12747. 2022.","short":"V. Gavini, S. Baroni, V. Blum, D.R. Bowler, A. Buccheri, J.R. Chelikowsky, S. Das, W. Dawson, P. Delugas, M. Dogan, C. Draxl, G. Galli, L. Genovese, P. Giannozzi, M. Giantomassi, X. Gonze, M. Govoni, A. Gulans, F. Gygi, J.M. Herbert, S. Kokott, T. Kühne, K.-H. Liou, T. Miyazaki, P. Motamarri, A. Nakata, J.E. Pask, C. Plessl, L.E. Ratcliff, R.M. Richard, M. Rossi, R. Schade, M. Scheffler, O. Schütt, P. Suryanarayana, M. Torrent, L. Truflandier, T.L. Windus, Q. Xu, V.W.-Z. Yu, D. Perez, ArXiv:2209.12747 (2022).","mla":"Gavini, Vikram, et al. “Roadmap on Electronic Structure Codes in the Exascale Era.” ArXiv:2209.12747, 2022.","bibtex":"@article{Gavini_Baroni_Blum_Bowler_Buccheri_Chelikowsky_Das_Dawson_Delugas_Dogan_et al._2022, title={Roadmap on Electronic Structure Codes in the Exascale Era}, journal={arXiv:2209.12747}, author={Gavini, Vikram and Baroni, Stefano and Blum, Volker and Bowler, David R. and Buccheri, Alexander and Chelikowsky, James R. and Das, Sambit and Dawson, William and Delugas, Pietro and Dogan, Mehmet and et al.}, year={2022} }","chicago":"Gavini, Vikram, Stefano Baroni, Volker Blum, David R. Bowler, Alexander Buccheri, James R. Chelikowsky, Sambit Das, et al. “Roadmap on Electronic Structure Codes in the Exascale Era.” ArXiv:2209.12747, 2022.","ama":"Gavini V, Baroni S, Blum V, et al. Roadmap on Electronic Structure Codes in the Exascale Era. arXiv:220912747. Published online 2022.","apa":"Gavini, V., Baroni, S., Blum, V., Bowler, D. R., Buccheri, A., Chelikowsky, J. R., Das, S., Dawson, W., Delugas, P., Dogan, M., Draxl, C., Galli, G., Genovese, L., Giannozzi, P., Giantomassi, M., Gonze, X., Govoni, M., Gulans, A., Gygi, F., … Perez, D. (2022). Roadmap on Electronic Structure Codes in the Exascale Era. In arXiv:2209.12747."},"language":[{"iso":"eng"}],"external_id":{"arxiv":["2209.12747"]},"abstract":[{"text":"Electronic structure calculations have been instrumental in providing many\r\nimportant insights into a range of physical and chemical properties of various\r\nmolecular and solid-state systems. Their importance to various fields,\r\nincluding materials science, chemical sciences, computational chemistry and\r\ndevice physics, is underscored by the large fraction of available public\r\nsupercomputing resources devoted to these calculations. As we enter the\r\nexascale era, exciting new opportunities to increase simulation numbers, sizes,\r\nand accuracies present themselves. In order to realize these promises, the\r\ncommunity of electronic structure software developers will however first have\r\nto tackle a number of challenges pertaining to the efficient use of new\r\narchitectures that will rely heavily on massive parallelism and hardware\r\naccelerators. This roadmap provides a broad overview of the state-of-the-art in\r\nelectronic structure calculations and of the various new directions being\r\npursued by the community. It covers 14 electronic structure codes, presenting\r\ntheir current status, their development priorities over the next five years,\r\nand their plans towards tackling the challenges and leveraging the\r\nopportunities presented by the advent of exascale computing.","lang":"eng"}],"title":"Roadmap on Electronic Structure Codes in the Exascale Era","user_id":"24135","department":[{"_id":"27"},{"_id":"518"}],"publication":"arXiv:2209.12747","author":[{"last_name":"Gavini","full_name":"Gavini, Vikram","first_name":"Vikram"},{"first_name":"Stefano","full_name":"Baroni, Stefano","last_name":"Baroni"},{"full_name":"Blum, Volker","first_name":"Volker","last_name":"Blum"},{"first_name":"David R.","full_name":"Bowler, David R.","last_name":"Bowler"},{"first_name":"Alexander","full_name":"Buccheri, Alexander","last_name":"Buccheri"},{"last_name":"Chelikowsky","full_name":"Chelikowsky, James R.","first_name":"James R."},{"last_name":"Das","first_name":"Sambit","full_name":"Das, Sambit"},{"last_name":"Dawson","first_name":"William","full_name":"Dawson, William"},{"first_name":"Pietro","full_name":"Delugas, Pietro","last_name":"Delugas"},{"last_name":"Dogan","full_name":"Dogan, Mehmet","first_name":"Mehmet"},{"first_name":"Claudia","full_name":"Draxl, Claudia","last_name":"Draxl"},{"full_name":"Galli, Giulia","first_name":"Giulia","last_name":"Galli"},{"first_name":"Luigi","full_name":"Genovese, Luigi","last_name":"Genovese"},{"full_name":"Giannozzi, Paolo","first_name":"Paolo","last_name":"Giannozzi"},{"first_name":"Matteo","full_name":"Giantomassi, Matteo","last_name":"Giantomassi"},{"last_name":"Gonze","full_name":"Gonze, Xavier","first_name":"Xavier"},{"last_name":"Govoni","full_name":"Govoni, Marco","first_name":"Marco"},{"first_name":"Andris","full_name":"Gulans, Andris","last_name":"Gulans"},{"last_name":"Gygi","full_name":"Gygi, François","first_name":"François"},{"last_name":"Herbert","first_name":"John M.","full_name":"Herbert, John M."},{"full_name":"Kokott, Sebastian","first_name":"Sebastian","last_name":"Kokott"},{"last_name":"Kühne","id":"49079","first_name":"Thomas","full_name":"Kühne, Thomas"},{"full_name":"Liou, Kai-Hsin","first_name":"Kai-Hsin","last_name":"Liou"},{"full_name":"Miyazaki, Tsuyoshi","first_name":"Tsuyoshi","last_name":"Miyazaki"},{"last_name":"Motamarri","first_name":"Phani","full_name":"Motamarri, Phani"},{"last_name":"Nakata","full_name":"Nakata, Ayako","first_name":"Ayako"},{"last_name":"Pask","full_name":"Pask, John E.","first_name":"John E."},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"last_name":"Ratcliff","first_name":"Laura E.","full_name":"Ratcliff, Laura E."},{"last_name":"Richard","full_name":"Richard, Ryan M.","first_name":"Ryan M."},{"last_name":"Rossi","first_name":"Mariana","full_name":"Rossi, Mariana"},{"id":"75963","last_name":"Schade","orcid":"0000-0002-6268-539","full_name":"Schade, Robert","first_name":"Robert"},{"first_name":"Matthias","full_name":"Scheffler, Matthias","last_name":"Scheffler"},{"first_name":"Ole","full_name":"Schütt, Ole","last_name":"Schütt"},{"last_name":"Suryanarayana","full_name":"Suryanarayana, Phanish","first_name":"Phanish"},{"last_name":"Torrent","first_name":"Marc","full_name":"Torrent, Marc"},{"first_name":"Lionel","full_name":"Truflandier, Lionel","last_name":"Truflandier"},{"last_name":"Windus","first_name":"Theresa L.","full_name":"Windus, Theresa L."},{"first_name":"Qimen","full_name":"Xu, Qimen","last_name":"Xu"},{"full_name":"Yu, Victor W. -Z.","first_name":"Victor W. -Z.","last_name":"Yu"},{"first_name":"Danny","full_name":"Perez, Danny","last_name":"Perez"}],"date_created":"2022-09-28T05:25:10Z","project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"status":"public"},{"_id":"46193","date_updated":"2023-07-28T11:53:15Z","doi":"10.1145/3492805.3492808","oa":"1","main_file_link":[{"url":"https://dl.acm.org/doi/pdf/10.1145/3492805.3492808","open_access":"1"}],"type":"conference","year":"2022","citation":{"ieee":"M. Karp et al., “A High-Fidelity Flow Solver for Unstructured Meshes on Field-Programmable Gate Arrays: Design, Evaluation, and Future Challenges,” 2022, doi: 10.1145/3492805.3492808.","short":"M. Karp, A. Podobas, T. Kenter, N. Jansson, C. Plessl, P. Schlatter, S. Markidis, in: International Conference on High Performance Computing in Asia-Pacific Region, ACM, 2022.","bibtex":"@inproceedings{Karp_Podobas_Kenter_Jansson_Plessl_Schlatter_Markidis_2022, title={A High-Fidelity Flow Solver for Unstructured Meshes on Field-Programmable Gate Arrays: Design, Evaluation, and Future Challenges}, DOI={10.1145/3492805.3492808}, booktitle={International Conference on High Performance Computing in Asia-Pacific Region}, publisher={ACM}, author={Karp, Martin and Podobas, Artur and Kenter, Tobias and Jansson, Niclas and Plessl, Christian and Schlatter, Philipp and Markidis, Stefano}, year={2022} }","mla":"Karp, Martin, et al. “A High-Fidelity Flow Solver for Unstructured Meshes on Field-Programmable Gate Arrays: Design, Evaluation, and Future Challenges.” International Conference on High Performance Computing in Asia-Pacific Region, ACM, 2022, doi:10.1145/3492805.3492808.","chicago":"Karp, Martin, Artur Podobas, Tobias Kenter, Niclas Jansson, Christian Plessl, Philipp Schlatter, and Stefano Markidis. “A High-Fidelity Flow Solver for Unstructured Meshes on Field-Programmable Gate Arrays: Design, Evaluation, and Future Challenges.” In International Conference on High Performance Computing in Asia-Pacific Region. ACM, 2022. https://doi.org/10.1145/3492805.3492808.","ama":"Karp M, Podobas A, Kenter T, et al. A High-Fidelity Flow Solver for Unstructured Meshes on Field-Programmable Gate Arrays: Design, Evaluation, and Future Challenges. In: International Conference on High Performance Computing in Asia-Pacific Region. ACM; 2022. doi:10.1145/3492805.3492808","apa":"Karp, M., Podobas, A., Kenter, T., Jansson, N., Plessl, C., Schlatter, P., & Markidis, S. (2022). A High-Fidelity Flow Solver for Unstructured Meshes on Field-Programmable Gate Arrays: Design, Evaluation, and Future Challenges. International Conference on High Performance Computing in Asia-Pacific Region. https://doi.org/10.1145/3492805.3492808"},"language":[{"iso":"eng"}],"title":"A High-Fidelity Flow Solver for Unstructured Meshes on Field-Programmable Gate Arrays: Design, Evaluation, and Future Challenges","user_id":"3145","department":[{"_id":"27"},{"_id":"518"}],"publication":"International Conference on High Performance Computing in Asia-Pacific Region","author":[{"full_name":"Karp, Martin","first_name":"Martin","last_name":"Karp"},{"first_name":"Artur","full_name":"Podobas, Artur","last_name":"Podobas"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"last_name":"Jansson","first_name":"Niclas","full_name":"Jansson, Niclas"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"last_name":"Schlatter","first_name":"Philipp","full_name":"Schlatter, Philipp"},{"last_name":"Markidis","full_name":"Markidis, Stefano","first_name":"Stefano"}],"quality_controlled":"1","publisher":"ACM","publication_status":"published","project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"date_created":"2023-07-28T11:51:55Z","status":"public"},{"language":[{"iso":"eng"}],"type":"preprint","citation":{"short":"T. Kühne, C. Plessl, R. Schade, O. Schütt, ArXiv:2205.14741 (2022).","ieee":"T. Kühne, C. Plessl, R. Schade, and O. Schütt, “CP2K on the road to exascale,” arXiv:2205.14741. 2022.","ama":"Kühne T, Plessl C, Schade R, Schütt O. CP2K on the road to exascale. arXiv:220514741. Published online 2022.","apa":"Kühne, T., Plessl, C., Schade, R., & Schütt, O. (2022). CP2K on the road to exascale. In arXiv:2205.14741.","chicago":"Kühne, Thomas, Christian Plessl, Robert Schade, and Ole Schütt. “CP2K on the Road to Exascale.” ArXiv:2205.14741, 2022.","mla":"Kühne, Thomas, et al. “CP2K on the Road to Exascale.” ArXiv:2205.14741, 2022.","bibtex":"@article{Kühne_Plessl_Schade_Schütt_2022, title={CP2K on the road to exascale}, journal={arXiv:2205.14741}, author={Kühne, Thomas and Plessl, Christian and Schade, Robert and Schütt, Ole}, year={2022} }"},"year":"2022","main_file_link":[{"url":"https://arxiv.org/abs/2205.14741"}],"_id":"32404","date_updated":"2023-08-02T14:55:35Z","project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"date_created":"2022-07-22T08:14:08Z","status":"public","publication":"arXiv:2205.14741","department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"author":[{"full_name":"Kühne, Thomas","first_name":"Thomas","id":"49079","last_name":"Kühne"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"orcid":"0000-0002-6268-539","full_name":"Schade, Robert","first_name":"Robert","id":"75963","last_name":"Schade"},{"first_name":"Ole","full_name":"Schütt, Ole","last_name":"Schütt"}],"user_id":"75963","title":"CP2K on the road to exascale","external_id":{"arxiv":["2205.14741"]},"abstract":[{"text":"The CP2K program package, which can be considered as the swiss army knife of\r\natomistic simulations, is presented with a special emphasis on ab-initio\r\nmolecular dynamics using the second-generation Car-Parrinello method. After\r\noutlining current and near-term development efforts with regards to massively\r\nparallel low-scaling post-Hartree-Fock and eigenvalue solvers, novel approaches\r\non how we plan to take full advantage of future low-precision hardware\r\narchitectures are introduced. Our focus here is on combining our submatrix\r\nmethod with the approximate computing paradigm to address the immanent exascale\r\nera.","lang":"eng"}]},{"main_file_link":[{"open_access":"1","url":"https://journals.aps.org/prresearch/abstract/10.1103/PhysRevResearch.4.033160"}],"year":"2022","type":"journal_article","citation":{"chicago":"Schade, Robert, Carsten Bauer, Konstantin Tamoev, Lukas Mazur, Christian Plessl, and Thomas Kühne. “Parallel Quantum Chemistry on Noisy Intermediate-Scale Quantum Computers.” Phys. Rev. Research 4 (2022): 033160. https://doi.org/10.1103/PhysRevResearch.4.033160.","ama":"Schade R, Bauer C, Tamoev K, Mazur L, Plessl C, Kühne T. Parallel quantum chemistry on noisy intermediate-scale quantum computers. Phys Rev Research. 2022;4:033160. doi:10.1103/PhysRevResearch.4.033160","apa":"Schade, R., Bauer, C., Tamoev, K., Mazur, L., Plessl, C., & Kühne, T. (2022). Parallel quantum chemistry on noisy intermediate-scale quantum computers. Phys. Rev. Research, 4, 033160. https://doi.org/10.1103/PhysRevResearch.4.033160","short":"R. Schade, C. Bauer, K. Tamoev, L. Mazur, C. Plessl, T. Kühne, Phys. Rev. Research 4 (2022) 033160.","mla":"Schade, Robert, et al. “Parallel Quantum Chemistry on Noisy Intermediate-Scale Quantum Computers.” Phys. Rev. Research, vol. 4, American Physical Society, 2022, p. 033160, doi:10.1103/PhysRevResearch.4.033160.","bibtex":"@article{Schade_Bauer_Tamoev_Mazur_Plessl_Kühne_2022, title={Parallel quantum chemistry on noisy intermediate-scale quantum computers}, volume={4}, DOI={10.1103/PhysRevResearch.4.033160}, journal={Phys. Rev. Research}, publisher={American Physical Society}, author={Schade, Robert and Bauer, Carsten and Tamoev, Konstantin and Mazur, Lukas and Plessl, Christian and Kühne, Thomas}, year={2022}, pages={033160} }","ieee":"R. Schade, C. Bauer, K. Tamoev, L. Mazur, C. Plessl, and T. Kühne, “Parallel quantum chemistry on noisy intermediate-scale quantum computers,” Phys. Rev. Research, vol. 4, p. 033160, 2022, doi: 10.1103/PhysRevResearch.4.033160."},"page":"033160","intvolume":" 4","_id":"33226","quality_controlled":"1","author":[{"last_name":"Schade","id":"75963","first_name":"Robert","full_name":"Schade, Robert","orcid":"0000-0002-6268-539"},{"first_name":"Carsten","full_name":"Bauer, Carsten","last_name":"Bauer","id":"90082"},{"last_name":"Tamoev","id":"50177","first_name":"Konstantin","full_name":"Tamoev, Konstantin"},{"first_name":"Lukas","orcid":" 0000-0001-6304-7082","full_name":"Mazur, Lukas","last_name":"Mazur","id":"90492"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"first_name":"Thomas","full_name":"Kühne, Thomas","last_name":"Kühne","id":"49079"}],"publisher":"American Physical Society","publication":"Phys. Rev. Research","volume":4,"status":"public","date_created":"2022-08-29T14:07:01Z","article_type":"original","abstract":[{"lang":"eng","text":"A parallel hybrid quantum-classical algorithm for the solution of the quantum-chemical ground-state energy problem on gate-based quantum computers is presented. This approach is based on the reduced density-matrix functional theory (RDMFT) formulation of the electronic structure problem. For that purpose, the density-matrix functional of the full system is decomposed into an indirectly coupled sum of density-matrix functionals for all its subsystems using the adaptive cluster approximation to RDMFT. The approximations involved in the decomposition and the adaptive cluster approximation itself can be systematically converged to the exact result. The solutions for the density-matrix functionals of the effective subsystems involves a constrained minimization over many-particle states that are approximated by parametrized trial states on the quantum computer similarly to the variational quantum eigensolver. The independence of the density-matrix functionals of the effective subsystems introduces a new level of parallelization and allows for the computational treatment of much larger molecules on a quantum computer with a given qubit count. In addition, for the proposed algorithm techniques are presented to reduce the qubit count, the number of quantum programs, as well as its depth. The evaluation of a density-matrix functional as the essential part of our approach is demonstrated for Hubbard-like systems on IBM quantum computers based on superconducting transmon qubits."}],"user_id":"75963","language":[{"iso":"eng"}],"date_updated":"2023-08-02T15:04:22Z","doi":"10.1103/PhysRevResearch.4.033160","oa":"1","department":[{"_id":"27"},{"_id":"518"}],"publication_status":"published","project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"title":"Parallel quantum chemistry on noisy intermediate-scale quantum computers"},{"main_file_link":[{"url":"https://www.sciencedirect.com/science/article/pii/S0167819122000242","open_access":"1"}],"type":"journal_article","year":"2022","citation":{"chicago":"Schade, Robert, Tobias Kenter, Hossam Elgabarty, Michael Lass, Ole Schütt, Alfio Lazzaro, Hans Pabst, et al. “Towards Electronic Structure-Based Ab-Initio Molecular Dynamics Simulations with Hundreds of Millions of Atoms.” Parallel Computing 111 (2022). https://doi.org/10.1016/j.parco.2022.102920.","ama":"Schade R, Kenter T, Elgabarty H, et al. Towards electronic structure-based ab-initio molecular dynamics simulations with hundreds of millions of atoms. Parallel Computing. 2022;111. doi:10.1016/j.parco.2022.102920","apa":"Schade, R., Kenter, T., Elgabarty, H., Lass, M., Schütt, O., Lazzaro, A., Pabst, H., Mohr, S., Hutter, J., Kühne, T., & Plessl, C. (2022). Towards electronic structure-based ab-initio molecular dynamics simulations with hundreds of millions of atoms. Parallel Computing, 111, Article 102920. https://doi.org/10.1016/j.parco.2022.102920","bibtex":"@article{Schade_Kenter_Elgabarty_Lass_Schütt_Lazzaro_Pabst_Mohr_Hutter_Kühne_et al._2022, title={Towards electronic structure-based ab-initio molecular dynamics simulations with hundreds of millions of atoms}, volume={111}, DOI={10.1016/j.parco.2022.102920}, number={102920}, journal={Parallel Computing}, publisher={Elsevier BV}, author={Schade, Robert and Kenter, Tobias and Elgabarty, Hossam and Lass, Michael and Schütt, Ole and Lazzaro, Alfio and Pabst, Hans and Mohr, Stephan and Hutter, Jürg and Kühne, Thomas and et al.}, year={2022} }","mla":"Schade, Robert, et al. “Towards Electronic Structure-Based Ab-Initio Molecular Dynamics Simulations with Hundreds of Millions of Atoms.” Parallel Computing, vol. 111, 102920, Elsevier BV, 2022, doi:10.1016/j.parco.2022.102920.","short":"R. Schade, T. Kenter, H. Elgabarty, M. Lass, O. Schütt, A. Lazzaro, H. Pabst, S. Mohr, J. Hutter, T. Kühne, C. Plessl, Parallel Computing 111 (2022).","ieee":"R. Schade et al., “Towards electronic structure-based ab-initio molecular dynamics simulations with hundreds of millions of atoms,” Parallel Computing, vol. 111, Art. no. 102920, 2022, doi: 10.1016/j.parco.2022.102920."},"intvolume":" 111","_id":"33684","article_number":"102920","publisher":"Elsevier BV","author":[{"orcid":"0000-0002-6268-539","full_name":"Schade, Robert","first_name":"Robert","id":"75963","last_name":"Schade"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"last_name":"Elgabarty","id":"60250","first_name":"Hossam","orcid":"0000-0002-4945-1481","full_name":"Elgabarty, Hossam"},{"full_name":"Lass, Michael","orcid":"0000-0002-5708-7632","first_name":"Michael","id":"24135","last_name":"Lass"},{"last_name":"Schütt","first_name":"Ole","full_name":"Schütt, Ole"},{"first_name":"Alfio","full_name":"Lazzaro, Alfio","last_name":"Lazzaro"},{"first_name":"Hans","full_name":"Pabst, Hans","last_name":"Pabst"},{"last_name":"Mohr","full_name":"Mohr, Stephan","first_name":"Stephan"},{"last_name":"Hutter","first_name":"Jürg","full_name":"Hutter, Jürg"},{"last_name":"Kühne","id":"49079","first_name":"Thomas","full_name":"Kühne, Thomas"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","publication":"Parallel Computing","keyword":["Artificial Intelligence","Computer Graphics and Computer-Aided Design","Computer Networks and Communications","Hardware and Architecture","Theoretical Computer Science","Software"],"volume":111,"status":"public","date_created":"2022-10-11T08:17:02Z","user_id":"75963","language":[{"iso":"eng"}],"date_updated":"2023-08-02T15:03:55Z","doi":"10.1016/j.parco.2022.102920","oa":"1","department":[{"_id":"613"},{"_id":"27"},{"_id":"518"}],"publication_identifier":{"issn":["0167-8191"]},"publication_status":"published","project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"title":"Towards electronic structure-based ab-initio molecular dynamics simulations with hundreds of millions of atoms"},{"title":"In-depth FPGA Accelerator Performance Evaluation with Single Node Benchmarks from the HPC Challenge Benchmark Suite for Intel and Xilinx FPGAs using OpenCL","user_id":"15278","publication_identifier":{"issn":["0743-7315"]},"publication_status":"published","status":"public","date_created":"2021-11-10T14:36:27Z","project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"quality_controlled":"1","author":[{"id":"40778","last_name":"Meyer","full_name":"Meyer, Marius","first_name":"Marius"},{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"department":[{"_id":"27"},{"_id":"518"}],"publication":"Journal of Parallel and Distributed Computing","doi":"10.1016/j.jpdc.2021.10.007","_id":"27364","date_updated":"2023-09-26T10:26:56Z","citation":{"mla":"Meyer, Marius, et al. “In-Depth FPGA Accelerator Performance Evaluation with Single Node Benchmarks from the HPC Challenge Benchmark Suite for Intel and Xilinx FPGAs Using OpenCL.” Journal of Parallel and Distributed Computing, 2022, doi:10.1016/j.jpdc.2021.10.007.","bibtex":"@article{Meyer_Kenter_Plessl_2022, title={In-depth FPGA Accelerator Performance Evaluation with Single Node Benchmarks from the HPC Challenge Benchmark Suite for Intel and Xilinx FPGAs using OpenCL}, DOI={10.1016/j.jpdc.2021.10.007}, journal={Journal of Parallel and Distributed Computing}, author={Meyer, Marius and Kenter, Tobias and Plessl, Christian}, year={2022} }","chicago":"Meyer, Marius, Tobias Kenter, and Christian Plessl. “In-Depth FPGA Accelerator Performance Evaluation with Single Node Benchmarks from the HPC Challenge Benchmark Suite for Intel and Xilinx FPGAs Using OpenCL.” Journal of Parallel and Distributed Computing, 2022. https://doi.org/10.1016/j.jpdc.2021.10.007.","ama":"Meyer M, Kenter T, Plessl C. In-depth FPGA Accelerator Performance Evaluation with Single Node Benchmarks from the HPC Challenge Benchmark Suite for Intel and Xilinx FPGAs using OpenCL. Journal of Parallel and Distributed Computing. Published online 2022. doi:10.1016/j.jpdc.2021.10.007","apa":"Meyer, M., Kenter, T., & Plessl, C. (2022). In-depth FPGA Accelerator Performance Evaluation with Single Node Benchmarks from the HPC Challenge Benchmark Suite for Intel and Xilinx FPGAs using OpenCL. Journal of Parallel and Distributed Computing. https://doi.org/10.1016/j.jpdc.2021.10.007","ieee":"M. Meyer, T. Kenter, and C. Plessl, “In-depth FPGA Accelerator Performance Evaluation with Single Node Benchmarks from the HPC Challenge Benchmark Suite for Intel and Xilinx FPGAs using OpenCL,” Journal of Parallel and Distributed Computing, 2022, doi: 10.1016/j.jpdc.2021.10.007.","short":"M. Meyer, T. Kenter, C. Plessl, Journal of Parallel and Distributed Computing (2022)."},"year":"2022","type":"journal_article","language":[{"iso":"eng"}]},{"department":[{"_id":"27"},{"_id":"518"}],"publication_identifier":{"issn":["1936-7406","1936-7414"]},"publication_status":"published","title":"The Strong Scaling Advantage of FPGAs in HPC for N-body Simulations","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:57:51Z","doi":"10.1145/3491235","oa":"1","author":[{"first_name":"Johannes","full_name":"Menzel, Johannes","last_name":"Menzel"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"}],"quality_controlled":"1","publication":"ACM Transactions on Reconfigurable Technology and Systems","volume":15,"status":"public","date_created":"2021-11-30T10:00:31Z","article_type":"original","abstract":[{"lang":"eng","text":"N-body methods are one of the essential algorithmic building blocks of high-performance and parallel computing. Previous research has shown promising performance for implementing n-body simulations with pairwise force calculations on FPGAs. However, to avoid challenges with accumulation and memory access patterns, the presented designs calculate each pair of forces twice, along with both force sums of the involved particles. Also, they require large problem instances with hundreds of thousands of particles to reach their respective peak performance, limiting the applicability for strong scaling scenarios. This work addresses both issues by presenting a novel FPGA design that uses each calculated force twice and overlaps data transfers and computations in a way that allows to reach peak performance even for small problem instances, outperforming previous single precision results even in double precision, and scaling linearly over multiple interconnected FPGAs. For a comparison across architectures, we provide an equally optimized CPU reference, which for large problems actually achieves higher peak performance per device, however, given the strong scaling advantages of the FPGA design, in parallel setups with few thousand particles per device, the FPGA platform achieves highest performance and power efficiency."}],"user_id":"3145","main_file_link":[{"url":"https://dl.acm.org/doi/10.1145/3491235","open_access":"1"}],"year":"2021","type":"journal_article","citation":{"ieee":"J. Menzel, C. Plessl, and T. Kenter, “The Strong Scaling Advantage of FPGAs in HPC for N-body Simulations,” ACM Transactions on Reconfigurable Technology and Systems, vol. 15, no. 1, pp. 1–30, 2021, doi: 10.1145/3491235.","short":"J. Menzel, C. Plessl, T. Kenter, ACM Transactions on Reconfigurable Technology and Systems 15 (2021) 1–30.","mla":"Menzel, Johannes, et al. “The Strong Scaling Advantage of FPGAs in HPC for N-Body Simulations.” ACM Transactions on Reconfigurable Technology and Systems, vol. 15, no. 1, 2021, pp. 1–30, doi:10.1145/3491235.","bibtex":"@article{Menzel_Plessl_Kenter_2021, title={The Strong Scaling Advantage of FPGAs in HPC for N-body Simulations}, volume={15}, DOI={10.1145/3491235}, number={1}, journal={ACM Transactions on Reconfigurable Technology and Systems}, author={Menzel, Johannes and Plessl, Christian and Kenter, Tobias}, year={2021}, pages={1–30} }","chicago":"Menzel, Johannes, Christian Plessl, and Tobias Kenter. “The Strong Scaling Advantage of FPGAs in HPC for N-Body Simulations.” ACM Transactions on Reconfigurable Technology and Systems 15, no. 1 (2021): 1–30. https://doi.org/10.1145/3491235.","ama":"Menzel J, Plessl C, Kenter T. The Strong Scaling Advantage of FPGAs in HPC for N-body Simulations. ACM Transactions on Reconfigurable Technology and Systems. 2021;15(1):1-30. doi:10.1145/3491235","apa":"Menzel, J., Plessl, C., & Kenter, T. (2021). The Strong Scaling Advantage of FPGAs in HPC for N-body Simulations. ACM Transactions on Reconfigurable Technology and Systems, 15(1), 1–30. https://doi.org/10.1145/3491235"},"page":"1-30","_id":"28099","intvolume":" 15","issue":"1"},{"oa":"1","doi":"10.1145/3468267.3470617","date_updated":"2023-07-28T12:03:19Z","_id":"46194","language":[{"iso":"eng"}],"year":"2021","type":"conference","citation":{"ama":"Kenter T, Shambhu A, Faghih-Naini S, Aizinger V. Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA. In: Proceedings of the Platform for Advanced Scientific Computing Conference. ACM; 2021. doi:10.1145/3468267.3470617","apa":"Kenter, T., Shambhu, A., Faghih-Naini, S., & Aizinger, V. (2021). Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA. Proceedings of the Platform for Advanced Scientific Computing Conference. https://doi.org/10.1145/3468267.3470617","chicago":"Kenter, Tobias, Adesh Shambhu, Sara Faghih-Naini, and Vadym Aizinger. “Algorithm-Hardware Co-Design of a Discontinuous Galerkin Shallow-Water Model for a Dataflow Architecture on FPGA.” In Proceedings of the Platform for Advanced Scientific Computing Conference. ACM, 2021. https://doi.org/10.1145/3468267.3470617.","mla":"Kenter, Tobias, et al. “Algorithm-Hardware Co-Design of a Discontinuous Galerkin Shallow-Water Model for a Dataflow Architecture on FPGA.” Proceedings of the Platform for Advanced Scientific Computing Conference, ACM, 2021, doi:10.1145/3468267.3470617.","bibtex":"@inproceedings{Kenter_Shambhu_Faghih-Naini_Aizinger_2021, title={Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA}, DOI={10.1145/3468267.3470617}, booktitle={Proceedings of the Platform for Advanced Scientific Computing Conference}, publisher={ACM}, author={Kenter, Tobias and Shambhu, Adesh and Faghih-Naini, Sara and Aizinger, Vadym}, year={2021} }","short":"T. Kenter, A. Shambhu, S. Faghih-Naini, V. Aizinger, in: Proceedings of the Platform for Advanced Scientific Computing Conference, ACM, 2021.","ieee":"T. Kenter, A. Shambhu, S. Faghih-Naini, and V. Aizinger, “Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA,” 2021, doi: 10.1145/3468267.3470617."},"main_file_link":[{"url":"https://dl.acm.org/doi/pdf/10.1145/3468267.3470617","open_access":"1"}],"user_id":"3145","title":"Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA","status":"public","date_created":"2023-07-28T11:58:14Z","project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"publication_status":"published","author":[{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"last_name":"Shambhu","first_name":"Adesh","full_name":"Shambhu, Adesh"},{"full_name":"Faghih-Naini, Sara","first_name":"Sara","last_name":"Faghih-Naini"},{"last_name":"Aizinger","first_name":"Vadym","full_name":"Aizinger, Vadym"}],"publisher":"ACM","quality_controlled":"1","publication":"Proceedings of the Platform for Advanced Scientific Computing Conference","department":[{"_id":"27"},{"_id":"518"}]},{"date_updated":"2023-07-28T12:05:15Z","_id":"46195","doi":"10.1109/ipdps49936.2021.00116","language":[{"iso":"eng"}],"year":"2021","citation":{"bibtex":"@inproceedings{Karp_Podobas_Jansson_Kenter_Plessl_Schlatter_Markidis_2021, title={High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection}, DOI={10.1109/ipdps49936.2021.00116}, booktitle={2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS)}, publisher={IEEE}, author={Karp, Martin and Podobas, Artur and Jansson, Niclas and Kenter, Tobias and Plessl, Christian and Schlatter, Philipp and Markidis, Stefano}, year={2021} }","mla":"Karp, Martin, et al. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021, doi:10.1109/ipdps49936.2021.00116.","chicago":"Karp, Martin, Artur Podobas, Niclas Jansson, Tobias Kenter, Christian Plessl, Philipp Schlatter, and Stefano Markidis. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” In 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE, 2021. https://doi.org/10.1109/ipdps49936.2021.00116.","apa":"Karp, M., Podobas, A., Jansson, N., Kenter, T., Plessl, C., Schlatter, P., & Markidis, S. (2021). High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). https://doi.org/10.1109/ipdps49936.2021.00116","ama":"Karp M, Podobas A, Jansson N, et al. High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. In: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE; 2021. doi:10.1109/ipdps49936.2021.00116","ieee":"M. Karp et al., “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection,” 2021, doi: 10.1109/ipdps49936.2021.00116.","short":"M. Karp, A. Podobas, N. Jansson, T. Kenter, C. Plessl, P. Schlatter, S. Markidis, in: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021."},"type":"conference","user_id":"3145","title":"High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection","department":[{"_id":"27"},{"_id":"518"}],"publication":"2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS)","author":[{"last_name":"Karp","full_name":"Karp, Martin","first_name":"Martin"},{"last_name":"Podobas","full_name":"Podobas, Artur","first_name":"Artur"},{"last_name":"Jansson","first_name":"Niclas","full_name":"Jansson, Niclas"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Schlatter","full_name":"Schlatter, Philipp","first_name":"Philipp"},{"full_name":"Markidis, Stefano","first_name":"Stefano","last_name":"Markidis"}],"quality_controlled":"1","publisher":"IEEE","date_created":"2023-07-28T12:04:27Z","status":"public","publication_status":"published"},{"abstract":[{"text":"Solving partial differential equations on unstructured grids is a cornerstone of engineering and scientific computing. Nowadays, heterogeneous parallel platforms with CPUs, GPUs, and FPGAs enable energy-efficient and computationally demanding simulations. We developed the HighPerMeshes C++-embedded Domain-Specific Language (DSL) for bridging the abstraction gap between the mathematical and algorithmic formulation of mesh-based algorithms for PDE problems on the one hand and an increasing number of heterogeneous platforms with their different parallel programming and runtime models on the other hand. Thus, the HighPerMeshes DSL aims at higher productivity in the code development process for multiple target platforms. We introduce the concepts as well as the basic structure of the HighPerMeshes DSL, and demonstrate its usage with three examples, a Poisson and monodomain problem, respectively, solved by the continuous finite element method, and the discontinuous Galerkin method for Maxwell’s equation. The mapping of the abstract algorithmic description onto parallel hardware, including distributed memory compute clusters, is presented. Finally, the achievable performance and scalability are demonstrated for a typical example problem on a multi-core CPU cluster.","lang":"eng"}],"ddc":["004"],"user_id":"15278","author":[{"id":"42456","last_name":"Alhaddad","full_name":"Alhaddad, Samer","first_name":"Samer"},{"first_name":"Jens","orcid":"0000-0001-7059-9862","full_name":"Förstner, Jens","last_name":"Förstner","id":"158"},{"full_name":"Groth, Stefan","first_name":"Stefan","last_name":"Groth"},{"last_name":"Grünewald","first_name":"Daniel","full_name":"Grünewald, Daniel"},{"first_name":"Yevgen","full_name":"Grynko, Yevgen","last_name":"Grynko","id":"26059"},{"full_name":"Hannig, Frank","first_name":"Frank","last_name":"Hannig"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"first_name":"Franz-Josef","full_name":"Pfreundt, Franz-Josef","last_name":"Pfreundt"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"last_name":"Schotte","first_name":"Merlind","full_name":"Schotte, Merlind"},{"full_name":"Steinke, Thomas","first_name":"Thomas","last_name":"Steinke"},{"full_name":"Teich, Jürgen","first_name":"Jürgen","last_name":"Teich"},{"last_name":"Weiser","first_name":"Martin","full_name":"Weiser, Martin"},{"full_name":"Wende, Florian","first_name":"Florian","last_name":"Wende"}],"quality_controlled":"1","publication":"Euro-Par 2020: Parallel Processing Workshops","keyword":["tet_topic_hpc"],"file_date_updated":"2021-03-31T19:42:52Z","file":[{"date_updated":"2021-03-31T19:42:52Z","content_type":"application/pdf","relation":"main_file","success":1,"file_size":564398,"creator":"fossie","file_id":"21588","access_level":"closed","date_created":"2021-03-31T19:42:52Z","file_name":"2021-03 Alhaddad2021_Chapter_HighPerMeshesADomain-SpecificL.pdf"}],"has_accepted_license":"1","status":"public","date_created":"2021-03-31T19:39:42Z","_id":"21587","year":"2021","type":"book_chapter","citation":{"ieee":"S. Alhaddad et al., “HighPerMeshes – A Domain-Specific Language for Numerical Algorithms on Unstructured Grids,” in Euro-Par 2020: Parallel Processing Workshops, Cham, 2021.","short":"S. Alhaddad, J. Förstner, S. Groth, D. Grünewald, Y. Grynko, F. Hannig, T. Kenter, F.-J. Pfreundt, C. Plessl, M. Schotte, T. Steinke, J. Teich, M. Weiser, F. Wende, in: Euro-Par 2020: Parallel Processing Workshops, Cham, 2021.","mla":"Alhaddad, Samer, et al. “HighPerMeshes – A Domain-Specific Language for Numerical Algorithms on Unstructured Grids.” Euro-Par 2020: Parallel Processing Workshops, 2021, doi:10.1007/978-3-030-71593-9_15.","bibtex":"@inbook{Alhaddad_Förstner_Groth_Grünewald_Grynko_Hannig_Kenter_Pfreundt_Plessl_Schotte_et al._2021, place={Cham}, title={HighPerMeshes – A Domain-Specific Language for Numerical Algorithms on Unstructured Grids}, DOI={10.1007/978-3-030-71593-9_15}, booktitle={Euro-Par 2020: Parallel Processing Workshops}, author={Alhaddad, Samer and Förstner, Jens and Groth, Stefan and Grünewald, Daniel and Grynko, Yevgen and Hannig, Frank and Kenter, Tobias and Pfreundt, Franz-Josef and Plessl, Christian and Schotte, Merlind and et al.}, year={2021} }","chicago":"Alhaddad, Samer, Jens Förstner, Stefan Groth, Daniel Grünewald, Yevgen Grynko, Frank Hannig, Tobias Kenter, et al. “HighPerMeshes – A Domain-Specific Language for Numerical Algorithms on Unstructured Grids.” In Euro-Par 2020: Parallel Processing Workshops. Cham, 2021. https://doi.org/10.1007/978-3-030-71593-9_15.","ama":"Alhaddad S, Förstner J, Groth S, et al. HighPerMeshes – A Domain-Specific Language for Numerical Algorithms on Unstructured Grids. In: Euro-Par 2020: Parallel Processing Workshops. ; 2021. doi:10.1007/978-3-030-71593-9_15","apa":"Alhaddad, S., Förstner, J., Groth, S., Grünewald, D., Grynko, Y., Hannig, F., Kenter, T., Pfreundt, F.-J., Plessl, C., Schotte, M., Steinke, T., Teich, J., Weiser, M., & Wende, F. (2021). HighPerMeshes – A Domain-Specific Language for Numerical Algorithms on Unstructured Grids. In Euro-Par 2020: Parallel Processing Workshops. https://doi.org/10.1007/978-3-030-71593-9_15"},"place":"Cham","title":"HighPerMeshes – A Domain-Specific Language for Numerical Algorithms on Unstructured Grids","department":[{"_id":"61"},{"_id":"230"},{"_id":"429"},{"_id":"27"},{"_id":"518"}],"publication_identifier":{"isbn":["9783030715922","9783030715939"],"issn":["0302-9743","1611-3349"]},"publication_status":"published","project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"date_updated":"2023-09-26T11:40:25Z","doi":"10.1007/978-3-030-71593-9_15","language":[{"iso":"eng"}]},{"place":"Cham","title":"Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance Computing","user_id":"15278","quality_controlled":"1","author":[{"first_name":"Arjun","orcid":"https://orcid.org/0000-0002-0909-1178","full_name":"Ramaswami, Arjun","last_name":"Ramaswami","id":"49171"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"id":"49079","last_name":"Kühne","full_name":"Kühne, Thomas","first_name":"Thomas"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"publisher":"Springer International Publishing","department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"publication":"Applied Reconfigurable Computing. Architectures, Tools, and Applications","publication_status":"published","publication_identifier":{"isbn":["9783030790240","9783030790257"],"issn":["0302-9743","1611-3349"]},"status":"public","date_created":"2022-02-21T14:22:01Z","date_updated":"2023-09-26T11:40:45Z","_id":"29936","conference":{"name":"Int. Conf. on Applied Reconfigurable Computing. Architectures, Tools, and Applications"},"doi":"10.1007/978-3-030-79025-7_21","type":"book_chapter","year":"2021","citation":{"ama":"Ramaswami A, Kenter T, Kühne T, Plessl C. Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance Computing. In: Applied Reconfigurable Computing. Architectures, Tools, and Applications. Springer International Publishing; 2021. doi:10.1007/978-3-030-79025-7_21","apa":"Ramaswami, A., Kenter, T., Kühne, T., & Plessl, C. (2021). Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance Computing. In Applied Reconfigurable Computing. Architectures, Tools, and Applications. Int. Conf. on Applied Reconfigurable Computing. Architectures, Tools, and Applications. Springer International Publishing. https://doi.org/10.1007/978-3-030-79025-7_21","chicago":"Ramaswami, Arjun, Tobias Kenter, Thomas Kühne, and Christian Plessl. “Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance Computing.” In Applied Reconfigurable Computing. Architectures, Tools, and Applications. Cham: Springer International Publishing, 2021. https://doi.org/10.1007/978-3-030-79025-7_21.","bibtex":"@inbook{Ramaswami_Kenter_Kühne_Plessl_2021, place={Cham}, title={Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance Computing}, DOI={10.1007/978-3-030-79025-7_21}, booktitle={Applied Reconfigurable Computing. Architectures, Tools, and Applications}, publisher={Springer International Publishing}, author={Ramaswami, Arjun and Kenter, Tobias and Kühne, Thomas and Plessl, Christian}, year={2021} }","mla":"Ramaswami, Arjun, et al. “Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance Computing.” Applied Reconfigurable Computing. Architectures, Tools, and Applications, Springer International Publishing, 2021, doi:10.1007/978-3-030-79025-7_21.","short":"A. Ramaswami, T. Kenter, T. Kühne, C. Plessl, in: Applied Reconfigurable Computing. Architectures, Tools, and Applications, Springer International Publishing, Cham, 2021.","ieee":"A. Ramaswami, T. Kenter, T. Kühne, and C. Plessl, “Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance Computing,” in Applied Reconfigurable Computing. Architectures, Tools, and Applications, Cham: Springer International Publishing, 2021."},"language":[{"iso":"eng"}]},{"has_accepted_license":"1","status":"public","date_created":"2021-09-22T06:15:50Z","file":[{"date_created":"2021-09-22T06:19:29Z","file_name":"2021-09 Alhaddad - Concurrency... - The HighPerMeshes framework for numerical algorithms on unstructured grids.pdf","access_level":"open_access","file_size":2300152,"creator":"fossie","file_id":"24789","date_updated":"2021-09-22T06:19:29Z","content_type":"application/pdf","relation":"main_file"}],"quality_controlled":"1","author":[{"last_name":"Alhaddad","id":"42456","first_name":"Samer","full_name":"Alhaddad, Samer"},{"last_name":"Förstner","id":"158","first_name":"Jens","orcid":"0000-0001-7059-9862","full_name":"Förstner, Jens"},{"last_name":"Groth","first_name":"Stefan","full_name":"Groth, Stefan"},{"last_name":"Grünewald","full_name":"Grünewald, Daniel","first_name":"Daniel"},{"first_name":"Yevgen","full_name":"Grynko, Yevgen","last_name":"Grynko","id":"26059"},{"full_name":"Hannig, Frank","first_name":"Frank","last_name":"Hannig"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"last_name":"Pfreundt","first_name":"Franz‐Josef","full_name":"Pfreundt, Franz‐Josef"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"full_name":"Schotte, Merlind","first_name":"Merlind","last_name":"Schotte"},{"full_name":"Steinke, Thomas","first_name":"Thomas","last_name":"Steinke"},{"first_name":"Jürgen","full_name":"Teich, Jürgen","last_name":"Teich"},{"last_name":"Weiser","first_name":"Martin","full_name":"Weiser, Martin"},{"last_name":"Wende","first_name":"Florian","full_name":"Wende, Florian"}],"keyword":["tet_topic_hpc"],"publication":"Concurrency and Computation: Practice and Experience","file_date_updated":"2021-09-22T06:19:29Z","user_id":"15278","ddc":["004"],"year":"2021","citation":{"ieee":"S. Alhaddad et al., “The HighPerMeshes framework for numerical algorithms on unstructured grids,” Concurrency and Computation: Practice and Experience, p. e6616, 2021, doi: 10.1002/cpe.6616.","short":"S. Alhaddad, J. Förstner, S. Groth, D. Grünewald, Y. Grynko, F. Hannig, T. Kenter, F. Pfreundt, C. Plessl, M. Schotte, T. Steinke, J. Teich, M. Weiser, F. Wende, Concurrency and Computation: Practice and Experience (2021) e6616.","bibtex":"@article{Alhaddad_Förstner_Groth_Grünewald_Grynko_Hannig_Kenter_Pfreundt_Plessl_Schotte_et al._2021, title={The HighPerMeshes framework for numerical algorithms on unstructured grids}, DOI={10.1002/cpe.6616}, journal={Concurrency and Computation: Practice and Experience}, author={Alhaddad, Samer and Förstner, Jens and Groth, Stefan and Grünewald, Daniel and Grynko, Yevgen and Hannig, Frank and Kenter, Tobias and Pfreundt, Franz‐Josef and Plessl, Christian and Schotte, Merlind and et al.}, year={2021}, pages={e6616} }","mla":"Alhaddad, Samer, et al. “The HighPerMeshes Framework for Numerical Algorithms on Unstructured Grids.” Concurrency and Computation: Practice and Experience, 2021, p. e6616, doi:10.1002/cpe.6616.","ama":"Alhaddad S, Förstner J, Groth S, et al. The HighPerMeshes framework for numerical algorithms on unstructured grids. Concurrency and Computation: Practice and Experience. Published online 2021:e6616. doi:10.1002/cpe.6616","apa":"Alhaddad, S., Förstner, J., Groth, S., Grünewald, D., Grynko, Y., Hannig, F., Kenter, T., Pfreundt, F., Plessl, C., Schotte, M., Steinke, T., Teich, J., Weiser, M., & Wende, F. (2021). The HighPerMeshes framework for numerical algorithms on unstructured grids. Concurrency and Computation: Practice and Experience, e6616. https://doi.org/10.1002/cpe.6616","chicago":"Alhaddad, Samer, Jens Förstner, Stefan Groth, Daniel Grünewald, Yevgen Grynko, Frank Hannig, Tobias Kenter, et al. “The HighPerMeshes Framework for Numerical Algorithms on Unstructured Grids.” Concurrency and Computation: Practice and Experience, 2021, e6616. https://doi.org/10.1002/cpe.6616."},"type":"journal_article","page":"e6616","_id":"24788","project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"},{"name":"HighPerMeshes","grant_number":"01|H16005A","_id":"33"}],"publication_identifier":{"issn":["1532-0626","1532-0634"]},"publication_status":"published","department":[{"_id":"61"},{"_id":"230"},{"_id":"27"},{"_id":"518"}],"title":"The HighPerMeshes framework for numerical algorithms on unstructured grids","language":[{"iso":"eng"}],"oa":"1","doi":"10.1002/cpe.6616","date_updated":"2023-09-26T11:42:19Z"},{"title":"High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection","user_id":"3145","publisher":"IEEE","quality_controlled":"1","author":[{"last_name":"Karp","first_name":"Martin","full_name":"Karp, Martin"},{"full_name":"Podobas, Artur","first_name":"Artur","last_name":"Podobas"},{"full_name":"Jansson, Niclas","first_name":"Niclas","last_name":"Jansson"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"full_name":"Schlatter, Philipp","first_name":"Philipp","last_name":"Schlatter"},{"full_name":"Markidis, Stefano","first_name":"Stefano","last_name":"Markidis"}],"publication":"2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS)","department":[{"_id":"27"},{"_id":"518"}],"publication_status":"published","status":"public","date_created":"2022-02-21T14:26:37Z","project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"date_updated":"2024-01-22T09:59:13Z","_id":"29937","doi":"10.1109/ipdps49936.2021.00116","type":"conference","citation":{"ieee":"M. Karp et al., “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection,” 2021, doi: 10.1109/ipdps49936.2021.00116.","short":"M. Karp, A. Podobas, N. Jansson, T. Kenter, C. Plessl, P. Schlatter, S. Markidis, in: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021.","bibtex":"@inproceedings{Karp_Podobas_Jansson_Kenter_Plessl_Schlatter_Markidis_2021, title={High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection}, DOI={10.1109/ipdps49936.2021.00116}, booktitle={2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS)}, publisher={IEEE}, author={Karp, Martin and Podobas, Artur and Jansson, Niclas and Kenter, Tobias and Plessl, Christian and Schlatter, Philipp and Markidis, Stefano}, year={2021} }","mla":"Karp, Martin, et al. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021, doi:10.1109/ipdps49936.2021.00116.","chicago":"Karp, Martin, Artur Podobas, Niclas Jansson, Tobias Kenter, Christian Plessl, Philipp Schlatter, and Stefano Markidis. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” In 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE, 2021. https://doi.org/10.1109/ipdps49936.2021.00116.","apa":"Karp, M., Podobas, A., Jansson, N., Kenter, T., Plessl, C., Schlatter, P., & Markidis, S. (2021). High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). https://doi.org/10.1109/ipdps49936.2021.00116","ama":"Karp M, Podobas A, Jansson N, et al. High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. In: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE; 2021. doi:10.1109/ipdps49936.2021.00116"},"year":"2021","language":[{"iso":"eng"}]},{"main_file_link":[{"open_access":"1","url":"https://aip.scitation.org/doi/pdf/10.1063/5.0007045?download=true"}],"type":"journal_article","citation":{"ieee":"T. Kühne et al., “CP2K: An electronic structure and molecular dynamics software package - Quickstep: Efficient and accurate electronic structure calculations,” The Journal of Chemical Physics, vol. 152, no. 19, Art. no. 194103, 2020, doi: 10.1063/5.0007045.","mla":"Kühne, Thomas, et al. “CP2K: An Electronic Structure and Molecular Dynamics Software Package - Quickstep: Efficient and Accurate Electronic Structure Calculations.” The Journal of Chemical Physics, vol. 152, no. 19, 194103, 2020, doi:10.1063/5.0007045.","bibtex":"@article{Kühne_Iannuzzi_Ben_Rybkin_Seewald_Stein_Laino_Khaliullin_Schütt_Schiffmann_et al._2020, title={CP2K: An electronic structure and molecular dynamics software package - Quickstep: Efficient and accurate electronic structure calculations}, volume={152}, DOI={10.1063/5.0007045}, number={19194103}, journal={The Journal of Chemical Physics}, author={Kühne, Thomas and Iannuzzi, Marcella and Ben, Mauro Del and Rybkin, Vladimir V. and Seewald, Patrick and Stein, Frederick and Laino, Teodoro and Khaliullin, Rustam Z. and Schütt, Ole and Schiffmann, Florian and et al.}, year={2020} }","short":"T. Kühne, M. Iannuzzi, M.D. Ben, V.V. Rybkin, P. Seewald, F. Stein, T. Laino, R.Z. Khaliullin, O. Schütt, F. Schiffmann, D. Golze, J. Wilhelm, S. Chulkov, M.H.B.-H. Mohammad Hossein Bani-Hashemian, V. Weber, U. Borstnik, M. Taillefumier, A.S. Jakobovits, A. Lazzaro, H. Pabst, T. Müller, R. Schade, M. Guidon, S. Andermatt, N. Holmberg, G.K. Schenter, A. Hehn, A. Bussy, F. Belleflamme, G. Tabacchi, A. Glöß, M. Lass, I. Bethune, C.J. Mundy, C. Plessl, M. Watkins, J. VandeVondele, M. Krack, J. Hutter, The Journal of Chemical Physics 152 (2020).","ama":"Kühne T, Iannuzzi M, Ben MD, et al. CP2K: An electronic structure and molecular dynamics software package - Quickstep: Efficient and accurate electronic structure calculations. The Journal of Chemical Physics. 2020;152(19). doi:10.1063/5.0007045","apa":"Kühne, T., Iannuzzi, M., Ben, M. D., Rybkin, V. V., Seewald, P., Stein, F., Laino, T., Khaliullin, R. Z., Schütt, O., Schiffmann, F., Golze, D., Wilhelm, J., Chulkov, S., Mohammad Hossein Bani-Hashemian, M. H. B.-H., Weber, V., Borstnik, U., Taillefumier, M., Jakobovits, A. S., Lazzaro, A., … Hutter, J. (2020). CP2K: An electronic structure and molecular dynamics software package - Quickstep: Efficient and accurate electronic structure calculations. The Journal of Chemical Physics, 152(19), Article 194103. https://doi.org/10.1063/5.0007045","chicago":"Kühne, Thomas, Marcella Iannuzzi, Mauro Del Ben, Vladimir V. Rybkin, Patrick Seewald, Frederick Stein, Teodoro Laino, et al. “CP2K: An Electronic Structure and Molecular Dynamics Software Package - Quickstep: Efficient and Accurate Electronic Structure Calculations.” The Journal of Chemical Physics 152, no. 19 (2020). https://doi.org/10.1063/5.0007045."},"year":"2020","intvolume":" 152","_id":"16277","issue":"19","article_number":"194103","file":[{"access_level":"closed","date_created":"2020-05-25T15:21:56Z","file_name":"5.0007045.pdf","relation":"main_file","success":1,"date_updated":"2020-05-25T15:21:56Z","content_type":"application/pdf","creator":"lass","file_id":"17061","file_size":4887650}],"author":[{"full_name":"Kühne, Thomas","first_name":"Thomas","id":"49079","last_name":"Kühne"},{"last_name":"Iannuzzi","full_name":"Iannuzzi, Marcella","first_name":"Marcella"},{"last_name":"Ben","first_name":"Mauro Del","full_name":"Ben, Mauro Del"},{"first_name":"Vladimir V.","full_name":"Rybkin, Vladimir V.","last_name":"Rybkin"},{"last_name":"Seewald","first_name":"Patrick","full_name":"Seewald, Patrick"},{"full_name":"Stein, Frederick","first_name":"Frederick","last_name":"Stein"},{"last_name":"Laino","first_name":"Teodoro","full_name":"Laino, Teodoro"},{"first_name":"Rustam Z.","full_name":"Khaliullin, Rustam Z.","last_name":"Khaliullin"},{"last_name":"Schütt","first_name":"Ole","full_name":"Schütt, Ole"},{"last_name":"Schiffmann","first_name":"Florian","full_name":"Schiffmann, Florian"},{"first_name":"Dorothea","full_name":"Golze, Dorothea","last_name":"Golze"},{"last_name":"Wilhelm","first_name":"Jan","full_name":"Wilhelm, Jan"},{"last_name":"Chulkov","first_name":"Sergey","full_name":"Chulkov, Sergey"},{"first_name":"Mohammad Hossein Bani-Hashemian","full_name":"Mohammad Hossein Bani-Hashemian, Mohammad Hossein Bani-Hashemian","last_name":"Mohammad Hossein Bani-Hashemian"},{"first_name":"Valéry","full_name":"Weber, Valéry","last_name":"Weber"},{"last_name":"Borstnik","first_name":"Urban","full_name":"Borstnik, Urban"},{"full_name":"Taillefumier, Mathieu","first_name":"Mathieu","last_name":"Taillefumier"},{"last_name":"Jakobovits","full_name":"Jakobovits, Alice Shoshana","first_name":"Alice Shoshana"},{"last_name":"Lazzaro","full_name":"Lazzaro, Alfio","first_name":"Alfio"},{"full_name":"Pabst, Hans","first_name":"Hans","last_name":"Pabst"},{"last_name":"Müller","first_name":"Tiziano","full_name":"Müller, Tiziano"},{"orcid":"0000-0002-6268-539","full_name":"Schade, Robert","first_name":"Robert","id":"75963","last_name":"Schade"},{"first_name":"Manuel","full_name":"Guidon, Manuel","last_name":"Guidon"},{"last_name":"Andermatt","first_name":"Samuel","full_name":"Andermatt, Samuel"},{"last_name":"Holmberg","first_name":"Nico","full_name":"Holmberg, Nico"},{"last_name":"Schenter","full_name":"Schenter, Gregory K.","first_name":"Gregory K."},{"last_name":"Hehn","full_name":"Hehn, Anna","first_name":"Anna"},{"last_name":"Bussy","first_name":"Augustin","full_name":"Bussy, Augustin"},{"last_name":"Belleflamme","first_name":"Fabian","full_name":"Belleflamme, Fabian"},{"full_name":"Tabacchi, Gloria","first_name":"Gloria","last_name":"Tabacchi"},{"last_name":"Glöß","first_name":"Andreas","full_name":"Glöß, Andreas"},{"last_name":"Lass","id":"24135","first_name":"Michael","full_name":"Lass, Michael","orcid":"0000-0002-5708-7632"},{"last_name":"Bethune","full_name":"Bethune, Iain","first_name":"Iain"},{"last_name":"Mundy","full_name":"Mundy, Christopher J.","first_name":"Christopher J."},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"last_name":"Watkins","full_name":"Watkins, Matt","first_name":"Matt"},{"last_name":"VandeVondele","first_name":"Joost","full_name":"VandeVondele, Joost"},{"last_name":"Krack","first_name":"Matthias","full_name":"Krack, Matthias"},{"full_name":"Hutter, Jürg","first_name":"Jürg","last_name":"Hutter"}],"quality_controlled":"1","file_date_updated":"2020-05-25T15:21:56Z","publication":"The Journal of Chemical Physics","has_accepted_license":"1","status":"public","date_created":"2020-03-10T15:12:31Z","volume":152,"abstract":[{"lang":"eng","text":"CP2K is an open source electronic structure and molecular dynamics software package to perform atomistic simulations of solid-state, liquid, molecular, and biological systems. It is especially aimed at massively parallel and linear-scaling electronic structure methods and state-of-theart ab initio molecular dynamics simulations. Excellent performance for electronic structure calculations is achieved using novel algorithms implemented for modern high-performance computing systems. This review revisits the main capabilities of CP2K to perform efficient and accurate electronic structure simulations. The emphasis is put on density functional theory and multiple post–Hartree–Fock methods using the Gaussian and plane wave approach and its augmented all-electron extension."}],"user_id":"75963","ddc":["540"],"language":[{"iso":"eng"}],"date_updated":"2023-08-02T14:56:21Z","oa":"1","doi":"10.1063/5.0007045","department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"},{"_id":"32","name":"Performance and Efficiency in HPC with Custom Computing","grant_number":"PL 595/2-1 / 320898746"},{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"publication_status":"published","external_id":{"arxiv":["2003.03868"]},"title":"CP2K: An electronic structure and molecular dynamics software package - Quickstep: Efficient and accurate electronic structure calculations"},{"user_id":"75963","abstract":[{"text":"Electronic structure calculations based on density-functional theory (DFT)\r\nrepresent a significant part of today's HPC workloads and pose high demands on\r\nhigh-performance computing resources. To perform these quantum-mechanical DFT\r\ncalculations on complex large-scale systems, so-called linear scaling methods\r\ninstead of conventional cubic scaling methods are required. In this work, we\r\ntake up the idea of the submatrix method and apply it to the DFT computations\r\nin the software package CP2K. For that purpose, we transform the underlying\r\nnumeric operations on distributed, large, sparse matrices into computations on\r\nlocal, much smaller and nearly dense matrices. This allows us to exploit the\r\nfull floating-point performance of modern CPUs and to make use of dedicated\r\naccelerator hardware, where performance has been limited by memory bandwidth\r\nbefore. We demonstrate both functionality and performance of our implementation\r\nand show how it can be accelerated with GPUs and FPGAs.","lang":"eng"}],"date_created":"2020-04-28T14:44:21Z","status":"public","publication":"Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC)","quality_controlled":"1","author":[{"full_name":"Lass, Michael","orcid":"0000-0002-5708-7632","first_name":"Michael","id":"24135","last_name":"Lass"},{"orcid":"0000-0002-6268-539","full_name":"Schade, Robert","first_name":"Robert","id":"75963","last_name":"Schade"},{"first_name":"Thomas","full_name":"Kühne, Thomas","last_name":"Kühne","id":"49079"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"publisher":"IEEE Computer Society","conference":{"name":"SC20: International Conference for High Performance Computing, Networking, Storage and Analysis (SC)","location":"Atlanta, GA, US"},"_id":"16898","page":"1127-1140","year":"2020","citation":{"bibtex":"@inproceedings{Lass_Schade_Kühne_Plessl_2020, place={Los Alamitos, CA, USA}, title={A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K}, DOI={10.1109/SC41405.2020.00084}, booktitle={Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC)}, publisher={IEEE Computer Society}, author={Lass, Michael and Schade, Robert and Kühne, Thomas and Plessl, Christian}, year={2020}, pages={1127–1140} }","mla":"Lass, Michael, et al. “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K.” Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), IEEE Computer Society, 2020, pp. 1127–40, doi:10.1109/SC41405.2020.00084.","ama":"Lass M, Schade R, Kühne T, Plessl C. A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K. In: Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC). IEEE Computer Society; 2020:1127-1140. doi:10.1109/SC41405.2020.00084","apa":"Lass, M., Schade, R., Kühne, T., & Plessl, C. (2020). A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K. Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 1127–1140. https://doi.org/10.1109/SC41405.2020.00084","chicago":"Lass, Michael, Robert Schade, Thomas Kühne, and Christian Plessl. “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K.” In Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 1127–40. Los Alamitos, CA, USA: IEEE Computer Society, 2020. https://doi.org/10.1109/SC41405.2020.00084.","ieee":"M. Lass, R. Schade, T. Kühne, and C. Plessl, “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K,” in Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Atlanta, GA, US, 2020, pp. 1127–1140, doi: 10.1109/SC41405.2020.00084.","short":"M. Lass, R. Schade, T. Kühne, C. Plessl, in: Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), IEEE Computer Society, Los Alamitos, CA, USA, 2020, pp. 1127–1140."},"type":"conference","main_file_link":[{"url":"https://ieeexplore.ieee.org/document/9355245"}],"title":"A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K","external_id":{"arxiv":["2004.10811"]},"place":"Los Alamitos, CA, USA","project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"},{"_id":"32","grant_number":"PL 595/2-1 / 320898746","name":"Performance and Efficiency in HPC with Custom Computing"},{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"doi":"10.1109/SC41405.2020.00084","date_updated":"2023-08-02T14:55:59Z","language":[{"iso":"eng"}]},{"title":"Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite","related_material":{"link":[{"url":"https://github.com/pc2/HPCC_FPGA","relation":"supplementary_material","description":"Official repository of the benchmark suite on GitHub"}]},"department":[{"_id":"27"},{"_id":"518"}],"publication_status":"published","publication_identifier":{"isbn":["9781665415927"]},"project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"date_updated":"2023-09-26T11:42:53Z","doi":"10.1109/h2rc51942.2020.00007","language":[{"iso":"eng"}],"abstract":[{"text":"FPGAs have found increasing adoption in data center applications since a new generation of high-level tools have become available which noticeably reduce development time for FPGA accelerators and still provide high-quality results. There is, however, no high-level benchmark suite available, which specifically enables a comparison of FPGA architectures, programming tools, and libraries for HPC applications. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community.","lang":"eng"}],"user_id":"15278","author":[{"first_name":"Marius","full_name":"Meyer, Marius","last_name":"Meyer","id":"40778"},{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"quality_controlled":"1","publication":"2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)","keyword":["FPGA","OpenCL","High Level Synthesis","HPC benchmarking"],"status":"public","date_created":"2021-04-16T10:17:22Z","_id":"21632","main_file_link":[{"url":"https://ieeexplore.ieee.org/document/9306963"}],"year":"2020","type":"conference","citation":{"bibtex":"@inproceedings{Meyer_Kenter_Plessl_2020, title={Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite}, DOI={10.1109/h2rc51942.2020.00007}, booktitle={2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, author={Meyer, Marius and Kenter, Tobias and Plessl, Christian}, year={2020} }","mla":"Meyer, Marius, et al. “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.” 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020, doi:10.1109/h2rc51942.2020.00007.","chicago":"Meyer, Marius, Tobias Kenter, and Christian Plessl. “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.” In 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020. https://doi.org/10.1109/h2rc51942.2020.00007.","apa":"Meyer, M., Kenter, T., & Plessl, C. (2020). Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite. 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). https://doi.org/10.1109/h2rc51942.2020.00007","ama":"Meyer M, Kenter T, Plessl C. Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite. In: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). ; 2020. doi:10.1109/h2rc51942.2020.00007","ieee":"M. Meyer, T. Kenter, and C. Plessl, “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite,” 2020, doi: 10.1109/h2rc51942.2020.00007.","short":"M. Meyer, T. Kenter, C. Plessl, in: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020."}},{"language":[{"iso":"eng"}],"doi":"10.3390/computation8020039","oa":"1","date_updated":"2023-09-26T11:43:52Z","project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"},{"_id":"32","grant_number":"PL 595/2-1 / 320898746","name":"Performance and Efficiency in HPC with Custom Computing"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"title":"Accurate Sampling with Noisy Forces from Approximate Computing","external_id":{"arxiv":["1907.08497"]},"citation":{"ieee":"V. Rengaraj, M. Lass, C. Plessl, and T. Kühne, “Accurate Sampling with Noisy Forces from Approximate Computing,” Computation, vol. 8, no. 2, Art. no. 39, 2020, doi: 10.3390/computation8020039.","short":"V. Rengaraj, M. Lass, C. Plessl, T. Kühne, Computation 8 (2020).","mla":"Rengaraj, Varadarajan, et al. “Accurate Sampling with Noisy Forces from Approximate Computing.” Computation, vol. 8, no. 2, 39, MDPI, 2020, doi:10.3390/computation8020039.","bibtex":"@article{Rengaraj_Lass_Plessl_Kühne_2020, title={Accurate Sampling with Noisy Forces from Approximate Computing}, volume={8}, DOI={10.3390/computation8020039}, number={239}, journal={Computation}, publisher={MDPI}, author={Rengaraj, Varadarajan and Lass, Michael and Plessl, Christian and Kühne, Thomas}, year={2020} }","ama":"Rengaraj V, Lass M, Plessl C, Kühne T. Accurate Sampling with Noisy Forces from Approximate Computing. Computation. 2020;8(2). doi:10.3390/computation8020039","apa":"Rengaraj, V., Lass, M., Plessl, C., & Kühne, T. (2020). Accurate Sampling with Noisy Forces from Approximate Computing. Computation, 8(2), Article 39. https://doi.org/10.3390/computation8020039","chicago":"Rengaraj, Varadarajan, Michael Lass, Christian Plessl, and Thomas Kühne. “Accurate Sampling with Noisy Forces from Approximate Computing.” Computation 8, no. 2 (2020). https://doi.org/10.3390/computation8020039."},"type":"journal_article","year":"2020","main_file_link":[{"open_access":"1","url":"https://www.mdpi.com/2079-3197/8/2/39/pdf"}],"article_number":"39","issue":"2","_id":"12878","intvolume":" 8","volume":8,"date_created":"2019-07-23T12:03:07Z","status":"public","publication":"Computation","author":[{"full_name":"Rengaraj, Varadarajan","first_name":"Varadarajan","last_name":"Rengaraj"},{"orcid":"0000-0002-5708-7632","full_name":"Lass, Michael","first_name":"Michael","id":"24135","last_name":"Lass"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"id":"49079","last_name":"Kühne","full_name":"Kühne, Thomas","first_name":"Thomas"}],"publisher":"MDPI","quality_controlled":"1","user_id":"15278","abstract":[{"text":"In scientific computing, the acceleration of atomistic computer simulations by means of custom hardware is finding ever-growing application. A major limitation, however, is that the high efficiency in terms of performance and low power consumption entails the massive usage of low precision computing units. Here, based on the approximate computing paradigm, we present an algorithmic method to compensate for numerical inaccuracies due to low accuracy arithmetic operations rigorously, yet still obtaining exact expectation values using a properly modified Langevin-type equation.","lang":"eng"}]},{"language":[{"iso":"eng"}],"doi":"10.1145/3319423","date_updated":"2022-01-06T07:03:44Z","publication_status":"published","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901 - Subproject C2","_id":"14"}],"department":[{"_id":"27"},{"_id":"518"}],"title":"Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL","page":"14:1–14:26","type":"journal_article","year":"2019","citation":{"short":"H. Riebler, G.F. Vaz, T. Kenter, C. Plessl, ACM Trans. Archit. Code Optim. (TACO) 16 (2019) 14:1–14:26.","ieee":"H. Riebler, G. F. Vaz, T. Kenter, and C. Plessl, “Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL,” ACM Trans. Archit. Code Optim. (TACO), vol. 16, no. 2, pp. 14:1–14:26, 2019.","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Tobias Kenter, and Christian Plessl. “Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL.” ACM Trans. Archit. Code Optim. (TACO) 16, no. 2 (2019): 14:1–14:26. https://doi.org/10.1145/3319423.","ama":"Riebler H, Vaz GF, Kenter T, Plessl C. Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL. ACM Trans Archit Code Optim (TACO). 2019;16(2):14:1–14:26. doi:10.1145/3319423","apa":"Riebler, H., Vaz, G. F., Kenter, T., & Plessl, C. (2019). Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL. ACM Trans. Archit. Code Optim. (TACO), 16(2), 14:1–14:26. https://doi.org/10.1145/3319423","bibtex":"@article{Riebler_Vaz_Kenter_Plessl_2019, title={Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL}, volume={16}, DOI={10.1145/3319423}, number={2}, journal={ACM Trans. Archit. Code Optim. (TACO)}, publisher={ACM}, author={Riebler, Heinrich and Vaz, Gavin Francis and Kenter, Tobias and Plessl, Christian}, year={2019}, pages={14:1–14:26} }","mla":"Riebler, Heinrich, et al. “Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL.” ACM Trans. Archit. Code Optim. (TACO), vol. 16, no. 2, ACM, 2019, pp. 14:1–14:26, doi:10.1145/3319423."},"issue":"2","intvolume":" 16","_id":"7689","volume":16,"date_created":"2019-02-13T15:01:43Z","has_accepted_license":"1","status":"public","keyword":["htrop"],"file_date_updated":"2019-02-13T14:59:07Z","publication":"ACM Trans. Archit. Code Optim. (TACO)","author":[{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","id":"30332","last_name":"Vaz"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","publisher":"ACM","file":[{"relation":"main_file","date_updated":"2019-02-13T14:59:07Z","content_type":"application/pdf","creator":"deffel","file_id":"7695","file_size":872822,"access_level":"closed","file_name":"htrop19_taco.pdf","date_created":"2019-02-13T14:59:07Z"}],"ddc":["000"],"user_id":"16153","article_type":"original"},{"user_id":"3145","ddc":["004"],"abstract":[{"lang":"eng","text":"Stratix 10 FPGA cards have a good potential for the acceleration of HPC workloads since the Stratix 10 product line introduces devices with a large number of DSP and memory blocks. The high level synthesis of OpenCL codes can play a fundamental role for FPGAs in HPC, because it allows to implement different designs with lower development effort compared to hand optimized HDL. However, Stratix 10 cards are still hard to fully exploit using the Intel FPGA SDK for OpenCL. The implementation of designs with thousands of concurrent arithmetic operations often suffers from place and route problems that limit the maximum frequency or entirely prevent a successful synthesis. In order to overcome these issues for the implementation of the matrix multiplication, we formulate Cannon's matrix multiplication algorithm with regard to its efficient synthesis within the FPGA logic. We obtain a two-level block algorithm, where the lower level sub-matrices are multiplied using our Cannon's algorithm implementation. Following this design approach with multiple compute units, we are able to get maximum frequencies close to and above 300 MHz with high utilization of DSP and memory blocks. This allows for performance results above 1 TeraFLOPS."}],"has_accepted_license":"1","status":"public","date_created":"2020-01-09T12:54:48Z","file":[{"date_created":"2020-01-09T12:53:57Z","file_name":"gorlani19_fpt.pdf","access_level":"closed","file_size":250559,"creator":"plessl","file_id":"15479","date_updated":"2020-01-09T12:53:57Z","content_type":"application/pdf","success":1,"relation":"main_file"}],"quality_controlled":"1","publisher":"IEEE","author":[{"first_name":"Paolo","full_name":"Gorlani, Paolo","last_name":"Gorlani","id":"72045"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","file_date_updated":"2020-01-09T12:53:57Z","_id":"15478","conference":{"name":"International Conference on Field-Programmable Technology (FPT)"},"type":"conference","year":"2019","citation":{"mla":"Gorlani, Paolo, et al. “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs.” Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2019, doi:10.1109/ICFPT47387.2019.00020.","bibtex":"@inproceedings{Gorlani_Kenter_Plessl_2019, title={OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs}, DOI={10.1109/ICFPT47387.2019.00020}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Gorlani, Paolo and Kenter, Tobias and Plessl, Christian}, year={2019} }","chicago":"Gorlani, Paolo, Tobias Kenter, and Christian Plessl. “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs.” In Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE, 2019. https://doi.org/10.1109/ICFPT47387.2019.00020.","apa":"Gorlani, P., Kenter, T., & Plessl, C. (2019). OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs. In Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE. https://doi.org/10.1109/ICFPT47387.2019.00020","ama":"Gorlani P, Kenter T, Plessl C. OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2019. doi:10.1109/ICFPT47387.2019.00020","ieee":"P. Gorlani, T. Kenter, and C. Plessl, “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2019.","short":"P. Gorlani, T. Kenter, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2019."},"title":"OpenCL Implementation of Cannon's Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs","project":[{"name":"HighPerMeshes","grant_number":"01|H16005","_id":"33"},{"_id":"32","name":"Performance and Efficiency in HPC with Custom Computing","grant_number":"PL 595/2-1"}],"department":[{"_id":"27"},{"_id":"518"}],"doi":"10.1109/ICFPT47387.2019.00020","date_updated":"2022-01-06T06:52:26Z","language":[{"iso":"eng"}]},{"language":[{"iso":"eng"}],"supervisor":[{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"citation":{"bibtex":"@book{Vaz_2019, title={Using Just-in-Time Code Generation to Transparently Accelerate Applications in Heterogeneous Systems}, publisher={Universität Paderborn}, author={Vaz, Gavin Francis}, year={2019} }","mla":"Vaz, Gavin Francis. Using Just-in-Time Code Generation to Transparently Accelerate Applications in Heterogeneous Systems. Universität Paderborn, 2019.","chicago":"Vaz, Gavin Francis. Using Just-in-Time Code Generation to Transparently Accelerate Applications in Heterogeneous Systems. Universität Paderborn, 2019.","ama":"Vaz GF. Using Just-in-Time Code Generation to Transparently Accelerate Applications in Heterogeneous Systems. Universität Paderborn; 2019.","apa":"Vaz, G. F. (2019). Using Just-in-Time Code Generation to Transparently Accelerate Applications in Heterogeneous Systems. Universität Paderborn.","ieee":"G. F. Vaz, Using Just-in-Time Code Generation to Transparently Accelerate Applications in Heterogeneous Systems. Universität Paderborn, 2019.","short":"G.F. Vaz, Using Just-in-Time Code Generation to Transparently Accelerate Applications in Heterogeneous Systems, Universität Paderborn, 2019."},"year":"2019","type":"dissertation","_id":"14849","date_updated":"2022-01-06T06:52:08Z","has_accepted_license":"1","status":"public","project":[{"_id":"1","name":"SFB 901"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"date_created":"2019-11-07T14:13:54Z","file":[{"access_level":"closed","file_name":"PhDThesis_GavinVaz_2019-07-11.pdf","date_created":"2019-11-07T14:13:14Z","date_updated":"2019-11-07T14:13:14Z","content_type":"application/pdf","success":1,"relation":"main_file","file_size":1462659,"file_id":"14850","creator":"florida"}],"author":[{"id":"30332","last_name":"Vaz","full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis"}],"publisher":"Universität Paderborn","file_date_updated":"2019-11-07T14:13:14Z","department":[{"_id":"518"}],"user_id":"477","ddc":["040"],"title":"Using Just-in-Time Code Generation to Transparently Accelerate Applications in Heterogeneous Systems"},{"department":[{"_id":"27"},{"_id":"518"},{"_id":"304"},{"_id":"104"}],"project":[{"_id":"32","grant_number":"PL 595/2-1 / 320898746","name":"Performance and Efficiency in HPC with Custom Computing"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"external_id":{"arxiv":["1703.02456"]},"title":"A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices","language":[{"iso":"eng"}],"date_updated":"2023-09-26T11:45:02Z","doi":"10.4208/cicp.OA-2018-0053","quality_controlled":"1","publisher":"Global Science Press","author":[{"last_name":"Richters","full_name":"Richters, Dorothee","first_name":"Dorothee"},{"first_name":"Michael","full_name":"Lass, Michael","orcid":"0000-0002-5708-7632","last_name":"Lass","id":"24135"},{"first_name":"Andrea","full_name":"Walther, Andrea","last_name":"Walther"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"id":"49079","last_name":"Kühne","full_name":"Kühne, Thomas","first_name":"Thomas"}],"publication":"Communications in Computational Physics","volume":25,"status":"public","date_created":"2017-07-25T14:48:26Z","abstract":[{"lang":"eng","text":"We address the general mathematical problem of computing the inverse p-th\r\nroot of a given matrix in an efficient way. A new method to construct iteration\r\nfunctions that allow calculating arbitrary p-th roots and their inverses of\r\nsymmetric positive definite matrices is presented. We show that the order of\r\nconvergence is at least quadratic and that adaptively adjusting a parameter q\r\nalways leads to an even faster convergence. In this way, a better performance\r\nthan with previously known iteration schemes is achieved. The efficiency of the\r\niterative functions is demonstrated for various matrices with different\r\ndensities, condition numbers and spectral radii."}],"user_id":"15278","type":"journal_article","citation":{"mla":"Richters, Dorothee, et al. “A General Algorithm to Calculate the Inverse Principal P-Th Root of Symmetric Positive Definite Matrices.” Communications in Computational Physics, vol. 25, no. 2, Global Science Press, 2019, pp. 564–85, doi:10.4208/cicp.OA-2018-0053.","bibtex":"@article{Richters_Lass_Walther_Plessl_Kühne_2019, title={A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices}, volume={25}, DOI={10.4208/cicp.OA-2018-0053}, number={2}, journal={Communications in Computational Physics}, publisher={Global Science Press}, author={Richters, Dorothee and Lass, Michael and Walther, Andrea and Plessl, Christian and Kühne, Thomas}, year={2019}, pages={564–585} }","apa":"Richters, D., Lass, M., Walther, A., Plessl, C., & Kühne, T. (2019). A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices. Communications in Computational Physics, 25(2), 564–585. https://doi.org/10.4208/cicp.OA-2018-0053","ama":"Richters D, Lass M, Walther A, Plessl C, Kühne T. A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices. Communications in Computational Physics. 2019;25(2):564-585. doi:10.4208/cicp.OA-2018-0053","chicago":"Richters, Dorothee, Michael Lass, Andrea Walther, Christian Plessl, and Thomas Kühne. “A General Algorithm to Calculate the Inverse Principal P-Th Root of Symmetric Positive Definite Matrices.” Communications in Computational Physics 25, no. 2 (2019): 564–85. https://doi.org/10.4208/cicp.OA-2018-0053.","ieee":"D. Richters, M. Lass, A. Walther, C. Plessl, and T. Kühne, “A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices,” Communications in Computational Physics, vol. 25, no. 2, pp. 564–585, 2019, doi: 10.4208/cicp.OA-2018-0053.","short":"D. Richters, M. Lass, A. Walther, C. Plessl, T. Kühne, Communications in Computational Physics 25 (2019) 564–585."},"year":"2019","page":"564-585","intvolume":" 25","_id":"21","issue":"2"},{"file":[{"file_name":"plessl19_informatik_spektrum.pdf","date_created":"2019-07-22T12:45:02Z","access_level":"open_access","file_size":248360,"creator":"plessl","file_id":"12872","content_type":"application/pdf","date_updated":"2019-07-22T12:45:02Z","relation":"main_file"}],"publication":"Informatik Spektrum","file_date_updated":"2019-07-22T12:45:02Z","author":[{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"quality_controlled":"1","date_created":"2019-07-22T12:42:44Z","status":"public","has_accepted_license":"1","user_id":"15278","ddc":["004"],"citation":{"chicago":"Platzner, Marco, and Christian Plessl. “FPGAs im Rechenzentrum.” Informatik Spektrum, 2019. https://doi.org/10.1007/s00287-019-01187-w.","apa":"Platzner, M., & Plessl, C. (2019). FPGAs im Rechenzentrum. Informatik Spektrum. https://doi.org/10.1007/s00287-019-01187-w","ama":"Platzner M, Plessl C. FPGAs im Rechenzentrum. Informatik Spektrum. Published online 2019. doi:10.1007/s00287-019-01187-w","bibtex":"@article{Platzner_Plessl_2019, title={FPGAs im Rechenzentrum}, DOI={10.1007/s00287-019-01187-w}, journal={Informatik Spektrum}, author={Platzner, Marco and Plessl, Christian}, year={2019} }","mla":"Platzner, Marco, and Christian Plessl. “FPGAs im Rechenzentrum.” Informatik Spektrum, 2019, doi:10.1007/s00287-019-01187-w.","short":"M. Platzner, C. Plessl, Informatik Spektrum (2019).","ieee":"M. Platzner and C. Plessl, “FPGAs im Rechenzentrum,” Informatik Spektrum, 2019, doi: 10.1007/s00287-019-01187-w."},"type":"journal_article","year":"2019","_id":"12871","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication_identifier":{"issn":["0170-6012","1432-122X"]},"publication_status":"published","title":"FPGAs im Rechenzentrum","language":[{"iso":"ger"}],"date_updated":"2023-09-26T11:45:57Z","oa":"1","doi":"10.1007/s00287-019-01187-w"},{"language":[{"iso":"eng"}],"doi":"10.1109/LES.2017.2760923","date_updated":"2022-01-06T06:54:18Z","publication_status":"published","publication_identifier":{"eissn":["1943-0671"],"issn":["1943-0663"]},"project":[{"_id":"32","name":"Performance and Efficiency in HPC with Custom Computing","grant_number":"PL 595/2-1"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"title":"Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots","external_id":{"arxiv":["1703.02283"]},"type":"journal_article","year":"2018","citation":{"ama":"Lass M, Kühne T, Plessl C. Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots. Embedded Systems Letters. 2018;10(2):33-36. doi:10.1109/LES.2017.2760923","apa":"Lass, M., Kühne, T., & Plessl, C. (2018). Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots. Embedded Systems Letters, 10(2), 33–36. https://doi.org/10.1109/LES.2017.2760923","chicago":"Lass, Michael, Thomas Kühne, and Christian Plessl. “Using Approximate Computing for the Calculation of Inverse Matrix P-Th Roots.” Embedded Systems Letters 10, no. 2 (2018): 33–36. https://doi.org/10.1109/LES.2017.2760923.","mla":"Lass, Michael, et al. “Using Approximate Computing for the Calculation of Inverse Matrix P-Th Roots.” Embedded Systems Letters, vol. 10, no. 2, IEEE, 2018, pp. 33–36, doi:10.1109/LES.2017.2760923.","bibtex":"@article{Lass_Kühne_Plessl_2018, title={Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots}, volume={10}, DOI={10.1109/LES.2017.2760923}, number={2}, journal={Embedded Systems Letters}, publisher={IEEE}, author={Lass, Michael and Kühne, Thomas and Plessl, Christian}, year={2018}, pages={33–36} }","short":"M. Lass, T. Kühne, C. Plessl, Embedded Systems Letters 10 (2018) 33–36.","ieee":"M. Lass, T. Kühne, and C. Plessl, “Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots,” Embedded Systems Letters, vol. 10, no. 2, pp. 33–36, 2018."},"page":" 33-36","issue":"2","intvolume":" 10","_id":"20","volume":10,"status":"public","date_created":"2017-07-25T14:41:08Z","publisher":"IEEE","author":[{"id":"24135","last_name":"Lass","orcid":"0000-0002-5708-7632","full_name":"Lass, Michael","first_name":"Michael"},{"full_name":"Kühne, Thomas","first_name":"Thomas","id":"49079","last_name":"Kühne"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"publication":"Embedded Systems Letters","user_id":"16153","abstract":[{"lang":"eng","text":"Approximate computing has shown to provide new ways to improve performance\r\nand power consumption of error-resilient applications. While many of these\r\napplications can be found in image processing, data classification or machine\r\nlearning, we demonstrate its suitability to a problem from scientific\r\ncomputing. Utilizing the self-correcting behavior of iterative algorithms, we\r\nshow that approximate computing can be applied to the calculation of inverse\r\nmatrix p-th roots which are required in many applications in scientific\r\ncomputing. Results show great opportunities to reduce the computational effort\r\nand bandwidth required for the execution of the discussed algorithm, especially\r\nwhen targeting special accelerator hardware."}]},{"_id":"5414","date_updated":"2022-01-06T07:01:52Z","year":"2018","citation":{"bibtex":"@book{Filmwala_2018, title={Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate it on FPGA Platform}, publisher={Universität Paderborn}, author={Filmwala, Tasneem}, year={2018} }","mla":"Filmwala, Tasneem. Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate It on FPGA Platform. Universität Paderborn, 2018.","chicago":"Filmwala, Tasneem. Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate It on FPGA Platform. Universität Paderborn, 2018.","ama":"Filmwala T. Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate It on FPGA Platform. Universität Paderborn; 2018.","apa":"Filmwala, T. (2018). Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate it on FPGA Platform. Universität Paderborn.","ieee":"T. Filmwala, Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate it on FPGA Platform. Universität Paderborn, 2018.","short":"T. Filmwala, Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate It on FPGA Platform, Universität Paderborn, 2018."},"type":"mastersthesis","language":[{"iso":"eng"}],"supervisor":[{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"title":"Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate it on FPGA Platform","user_id":"477","author":[{"last_name":"Filmwala","first_name":"Tasneem","full_name":"Filmwala, Tasneem"}],"publisher":"Universität Paderborn","department":[{"_id":"27"},{"_id":"518"}],"status":"public","date_created":"2018-11-07T15:14:26Z","project":[{"_id":"1","name":"SFB 901"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"SFB 901 - Subproject C2","_id":"14"}]},{"supervisor":[{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"language":[{"iso":"eng"}],"citation":{"apa":"Gadewar, O. (2018). Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL. Universität Paderborn.","ama":"Gadewar O. Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL. Universität Paderborn; 2018.","chicago":"Gadewar, Onkar. Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL. Universität Paderborn, 2018.","bibtex":"@book{Gadewar_2018, title={Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL}, publisher={Universität Paderborn}, author={Gadewar, Onkar}, year={2018} }","mla":"Gadewar, Onkar. Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL. Universität Paderborn, 2018.","short":"O. Gadewar, Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL, Universität Paderborn, 2018.","ieee":"O. Gadewar, Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL. Universität Paderborn, 2018."},"year":"2018","type":"mastersthesis","_id":"5421","date_updated":"2022-01-06T07:01:53Z","project":[{"_id":"1","name":"SFB 901"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"date_created":"2018-11-07T16:16:56Z","status":"public","department":[{"_id":"27"},{"_id":"518"}],"author":[{"last_name":"Gadewar","first_name":"Onkar","full_name":"Gadewar, Onkar"}],"publisher":"Universität Paderborn","user_id":"477","title":"Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL"},{"issue":"4","_id":"6516","intvolume":" 21","type":"journal_article","citation":{"chicago":"Mertens, Jan Cedric, Alexander Boschmann, M. Schmidt, and Christian Plessl. “Sprint Diagnostic with GPS and Inertial Sensor Fusion.” Sports Engineering 21, no. 4 (2018): 441–51. https://doi.org/10.1007/s12283-018-0291-0.","apa":"Mertens, J. C., Boschmann, A., Schmidt, M., & Plessl, C. (2018). Sprint diagnostic with GPS and inertial sensor fusion. Sports Engineering, 21(4), 441–451. https://doi.org/10.1007/s12283-018-0291-0","ama":"Mertens JC, Boschmann A, Schmidt M, Plessl C. Sprint diagnostic with GPS and inertial sensor fusion. Sports Engineering. 2018;21(4):441-451. doi:10.1007/s12283-018-0291-0","mla":"Mertens, Jan Cedric, et al. “Sprint Diagnostic with GPS and Inertial Sensor Fusion.” Sports Engineering, vol. 21, no. 4, Springer Nature, 2018, pp. 441–51, doi:10.1007/s12283-018-0291-0.","bibtex":"@article{Mertens_Boschmann_Schmidt_Plessl_2018, title={Sprint diagnostic with GPS and inertial sensor fusion}, volume={21}, DOI={10.1007/s12283-018-0291-0}, number={4}, journal={Sports Engineering}, publisher={Springer Nature}, author={Mertens, Jan Cedric and Boschmann, Alexander and Schmidt, M. and Plessl, Christian}, year={2018}, pages={441–451} }","short":"J.C. Mertens, A. Boschmann, M. Schmidt, C. Plessl, Sports Engineering 21 (2018) 441–451.","ieee":"J. C. Mertens, A. Boschmann, M. Schmidt, and C. Plessl, “Sprint diagnostic with GPS and inertial sensor fusion,” Sports Engineering, vol. 21, no. 4, pp. 441–451, 2018."},"year":"2018","page":"441-451","ddc":["000"],"user_id":"16153","volume":21,"has_accepted_license":"1","status":"public","date_created":"2019-01-08T17:44:43Z","quality_controlled":"1","publisher":"Springer Nature","author":[{"last_name":"Mertens","full_name":"Mertens, Jan Cedric","first_name":"Jan Cedric"},{"full_name":"Boschmann, Alexander","first_name":"Alexander","last_name":"Boschmann"},{"last_name":"Schmidt","first_name":"M.","full_name":"Schmidt, M."},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"publication":"Sports Engineering","file_date_updated":"2019-01-08T17:47:06Z","file":[{"creator":"plessl","file_id":"6517","file_size":2141021,"relation":"main_file","content_type":"application/pdf","date_updated":"2019-01-08T17:47:06Z","file_name":"plessl18_sportseng.pdf","date_created":"2019-01-08T17:47:06Z","access_level":"closed"}],"doi":"10.1007/s12283-018-0291-0","date_updated":"2022-01-06T07:03:09Z","language":[{"iso":"eng"}],"title":"Sprint diagnostic with GPS and inertial sensor fusion","publication_identifier":{"issn":["1369-7072","1460-2687"]},"publication_status":"published","department":[{"_id":"27"},{"_id":"518"}]},{"oa":"1","date_updated":"2022-01-12T16:32:23Z","language":[{"iso":"eng"}],"title":"Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA","project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901 - Subproject C2","_id":"14"}],"department":[{"_id":"27"},{"_id":"518"}],"_id":"5417","year":"2018","citation":{"short":"A. Ramaswami, Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA, Universität Paderborn, 2018.","ieee":"A. Ramaswami, Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA. Universität Paderborn, 2018.","apa":"Ramaswami, A. (2018). Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA. Universität Paderborn.","ama":"Ramaswami A. Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA. Universität Paderborn; 2018.","chicago":"Ramaswami, Arjun. Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA. Universität Paderborn, 2018.","bibtex":"@book{Ramaswami_2018, title={Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA}, publisher={Universität Paderborn}, author={Ramaswami, Arjun}, year={2018} }","mla":"Ramaswami, Arjun. Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA. Universität Paderborn, 2018."},"type":"mastersthesis","supervisor":[{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"main_file_link":[{"open_access":"1"}],"ddc":["000"],"user_id":"49171","abstract":[{"text":"Molecular Dynamic (MD) simulations are computationally intensive and accelerating them using specialized hardware is a topic of investigation in many studies. One of the routines in the critical path of MD simulations is the three-dimensional Fast Fourier Transformation (FFT3d). The potential in accelerating FFT3d using hardware is usually bound by bandwidth and memory. Therefore, designing a high throughput solution for an FPGA that overcomes this problem is challenging.\r\nIn this thesis, the feasibility of offloading FFT3d computations to FPGA implemented using OpenCL is investigated. In order to mask the latency in memory access, an FFT3d that overlaps computation with communication is designed. The implementa- tion of this design is synthesized for the Arria 10 GX 1150 FPGA and evaluated with the FFTW benchmark. Analysis shows a better performance using FPGA over CPU for larger FFT sizes, with the 643 FFT showing a 70% improvement in runtime using FPGAs.\r\nThis FFT3d design is integrated with CP2K to explore the potential in accelerating molecular dynamic simulations. Evaluation of CP2K simulations using FPGA shows a 41% improvement in runtime in FFT3d computations over CPU for larger FFT3d designs.","lang":"eng"}],"date_created":"2018-11-07T16:08:32Z","status":"public","has_accepted_license":"1","keyword":["FFT: FPGA","CP2K","OpenCL"],"file_date_updated":"2020-06-15T11:29:38Z","author":[{"orcid":"https://orcid.org/0000-0002-0909-1178","full_name":"Ramaswami, Arjun","first_name":"Arjun","id":"49171","last_name":"Ramaswami"}],"publisher":"Universität Paderborn","file":[{"date_created":"2020-06-15T11:29:38Z","file_name":"masterthesis.pdf","access_level":"closed","file_size":1297585,"creator":"arjunr","file_id":"17093","content_type":"application/pdf","date_updated":"2020-06-15T11:29:38Z","relation":"main_file","success":1}]},{"quality_controlled":"1","publisher":"IEEE","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"first_name":"Gopinath","full_name":"Mahale, Gopinath","last_name":"Mahale"},{"last_name":"Alhaddad","id":"42456","first_name":"Samer","full_name":"Alhaddad, Samer"},{"full_name":"Grynko, Yevgen","first_name":"Yevgen","id":"26059","last_name":"Grynko"},{"first_name":"Christian","full_name":"Schmitt, Christian","last_name":"Schmitt"},{"last_name":"Afzal","first_name":"Ayesha","full_name":"Afzal, Ayesha"},{"last_name":"Hannig","first_name":"Frank","full_name":"Hannig, Frank"},{"first_name":"Jens","orcid":"0000-0001-7059-9862","full_name":"Förstner, Jens","last_name":"Förstner","id":"158"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"file_date_updated":"2018-11-02T14:45:05Z","keyword":["tet_topic_hpc"],"publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","file":[{"access_level":"closed","file_name":"08457652.pdf","date_created":"2018-11-02T14:45:05Z","content_type":"application/pdf","date_updated":"2018-11-02T14:45:05Z","success":1,"relation":"main_file","file_size":269130,"creator":"ups","file_id":"5282"}],"has_accepted_license":"1","status":"public","date_created":"2018-03-22T10:48:01Z","abstract":[{"text":"The exploration of FPGAs as accelerators for scientific simulations has so far mostly been focused on small kernels of methods working on regular data structures, for example in the form of stencil computations for finite difference methods. In computational sciences, often more advanced methods are employed that promise better stability, convergence, locality and scaling. Unstructured meshes are shown to be more effective and more accurate, compared to regular grids, in representing computation domains of various shapes. Using unstructured meshes, the discontinuous Galerkin method preserves the ability to perform explicit local update operations for simulations in the time domain. In this work, we investigate FPGAs as target platform for an implementation of the nodal discontinuous Galerkin method to find time-domain solutions of Maxwell's equations in an unstructured mesh. When maximizing data reuse and fitting constant coefficients into suitably partitioned on-chip memory, high computational intensity allows us to implement and feed wide data paths with hundreds of floating point operators. By decoupling off-chip memory accesses from the computations, high memory bandwidth can be sustained, even for the irregular access pattern required by parts of the application. Using the Intel/Altera OpenCL SDK for FPGAs, we present different implementation variants for different polynomial orders of the method. In different phases of the algorithm, either computational or bandwidth limits of the Arria 10 platform are almost reached, thus outperforming a highly multithreaded CPU implementation by around 2x.","lang":"eng"}],"ddc":["000"],"user_id":"15278","year":"2018","type":"conference","citation":{"ieee":"T. Kenter et al., “OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes,” presented at the Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2018, doi: 10.1109/FCCM.2018.00037.","short":"T. Kenter, G. Mahale, S. Alhaddad, Y. Grynko, C. Schmitt, A. Afzal, F. Hannig, J. Förstner, C. Plessl, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2018.","mla":"Kenter, Tobias, et al. “OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2018, doi:10.1109/FCCM.2018.00037.","bibtex":"@inproceedings{Kenter_Mahale_Alhaddad_Grynko_Schmitt_Afzal_Hannig_Förstner_Plessl_2018, title={OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes}, DOI={10.1109/FCCM.2018.00037}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Kenter, Tobias and Mahale, Gopinath and Alhaddad, Samer and Grynko, Yevgen and Schmitt, Christian and Afzal, Ayesha and Hannig, Frank and Förstner, Jens and Plessl, Christian}, year={2018} }","apa":"Kenter, T., Mahale, G., Alhaddad, S., Grynko, Y., Schmitt, C., Afzal, A., Hannig, F., Förstner, J., & Plessl, C. (2018). OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). https://doi.org/10.1109/FCCM.2018.00037","ama":"Kenter T, Mahale G, Alhaddad S, et al. OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE; 2018. doi:10.1109/FCCM.2018.00037","chicago":"Kenter, Tobias, Gopinath Mahale, Samer Alhaddad, Yevgen Grynko, Christian Schmitt, Ayesha Afzal, Frank Hannig, Jens Förstner, and Christian Plessl. “OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2018. https://doi.org/10.1109/FCCM.2018.00037."},"_id":"1588","conference":{"name":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)"},"department":[{"_id":"27"},{"_id":"518"},{"_id":"61"}],"project":[{"name":"HighPerMeshes","grant_number":"01|H16005A","_id":"33"},{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subproject C2"}],"title":"OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes","language":[{"iso":"eng"}],"date_updated":"2023-09-26T11:47:52Z","doi":"10.1109/FCCM.2018.00037"},{"doi":"10.1145/3218176.3218231","date_updated":"2023-09-26T11:48:12Z","language":[{"iso":"eng"}],"title":"A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices","place":"New York, NY, USA","external_id":{"arxiv":["1710.10899"]},"publication_identifier":{"isbn":["978-1-4503-5891-0/18/07"]},"project":[{"_id":"32","grant_number":"PL 595/2-1 / 320898746","name":"Performance and Efficiency in HPC with Custom Computing"},{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"_id":"1590","conference":{"end_date":"2018-07-04","location":"Basel, Switzerland","name":"Platform for Advanced Scientific Computing Conference (PASC)","start_date":"2018-07-02"},"year":"2018","type":"conference","citation":{"bibtex":"@inproceedings{Lass_Mohr_Wiebeler_Kühne_Plessl_2018, place={New York, NY, USA}, title={A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices}, DOI={10.1145/3218176.3218231}, booktitle={Proc. Platform for Advanced Scientific Computing (PASC) Conference}, publisher={ACM}, author={Lass, Michael and Mohr, Stephan and Wiebeler, Hendrik and Kühne, Thomas and Plessl, Christian}, year={2018} }","mla":"Lass, Michael, et al. “A Massively Parallel Algorithm for the Approximate Calculation of Inverse P-Th Roots of Large Sparse Matrices.” Proc. Platform for Advanced Scientific Computing (PASC) Conference, ACM, 2018, doi:10.1145/3218176.3218231.","chicago":"Lass, Michael, Stephan Mohr, Hendrik Wiebeler, Thomas Kühne, and Christian Plessl. “A Massively Parallel Algorithm for the Approximate Calculation of Inverse P-Th Roots of Large Sparse Matrices.” In Proc. Platform for Advanced Scientific Computing (PASC) Conference. New York, NY, USA: ACM, 2018. https://doi.org/10.1145/3218176.3218231.","apa":"Lass, M., Mohr, S., Wiebeler, H., Kühne, T., & Plessl, C. (2018). A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices. Proc. Platform for Advanced Scientific Computing (PASC) Conference. Platform for Advanced Scientific Computing Conference (PASC), Basel, Switzerland. https://doi.org/10.1145/3218176.3218231","ama":"Lass M, Mohr S, Wiebeler H, Kühne T, Plessl C. A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices. In: Proc. Platform for Advanced Scientific Computing (PASC) Conference. ACM; 2018. doi:10.1145/3218176.3218231","ieee":"M. Lass, S. Mohr, H. Wiebeler, T. Kühne, and C. Plessl, “A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices,” presented at the Platform for Advanced Scientific Computing Conference (PASC), Basel, Switzerland, 2018, doi: 10.1145/3218176.3218231.","short":"M. Lass, S. Mohr, H. Wiebeler, T. Kühne, C. Plessl, in: Proc. Platform for Advanced Scientific Computing (PASC) Conference, ACM, New York, NY, USA, 2018."},"user_id":"15278","abstract":[{"lang":"eng","text":"We present the submatrix method, a highly parallelizable method for the approximate calculation of inverse p-th roots of large sparse symmetric matrices which are required in different scientific applications. Following the idea of Approximate Computing, we allow imprecision in the final result in order to utilize the sparsity of the input matrix and to allow massively parallel execution. For an n x n matrix, the proposed algorithm allows to distribute the calculations over n nodes with only little communication overhead. The result matrix exhibits the same sparsity pattern as the input matrix, allowing for efficient reuse of allocated data structures.\r\n\r\nWe evaluate the algorithm with respect to the error that it introduces into calculated results, as well as its performance and scalability. We demonstrate that the error is relatively limited for well-conditioned matrices and that results are still valuable for error-resilient applications like preconditioning even for ill-conditioned matrices. We discuss the execution time and scaling of the algorithm on a theoretical level and present a distributed implementation of the algorithm using MPI and OpenMP. We demonstrate the scalability of this implementation by running it on a high-performance compute cluster comprised of 1024 CPU cores, showing a speedup of 665x compared to single-threaded execution."}],"status":"public","date_created":"2018-03-22T10:53:01Z","publisher":"ACM","author":[{"last_name":"Lass","id":"24135","first_name":"Michael","full_name":"Lass, Michael","orcid":"0000-0002-5708-7632"},{"first_name":"Stephan","full_name":"Mohr, Stephan","last_name":"Mohr"},{"last_name":"Wiebeler","full_name":"Wiebeler, Hendrik","first_name":"Hendrik"},{"first_name":"Thomas","full_name":"Kühne, Thomas","last_name":"Kühne","id":"49079"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","keyword":["approximate computing","linear algebra","matrix inversion","matrix p-th roots","numeric algorithm","parallel computing"],"publication":"Proc. Platform for Advanced Scientific Computing (PASC) Conference"},{"_id":"1204","type":"conference","citation":{"mla":"Riebler, Heinrich, et al. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018, doi:10.1145/3178487.3178534.","bibtex":"@inproceedings{Riebler_Vaz_Kenter_Plessl_2018, title={Automated Code Acceleration Targeting Heterogeneous OpenCL Devices}, DOI={10.1145/3178487.3178534}, booktitle={Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)}, publisher={ACM}, author={Riebler, Heinrich and Vaz, Gavin Francis and Kenter, Tobias and Plessl, Christian}, year={2018} }","apa":"Riebler, H., Vaz, G. F., Kenter, T., & Plessl, C. (2018). Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). https://doi.org/10.1145/3178487.3178534","ama":"Riebler H, Vaz GF, Kenter T, Plessl C. Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. In: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). ACM; 2018. doi:10.1145/3178487.3178534","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Tobias Kenter, and Christian Plessl. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” In Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). ACM, 2018. https://doi.org/10.1145/3178487.3178534.","ieee":"H. Riebler, G. F. Vaz, T. Kenter, and C. Plessl, “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices,” 2018, doi: 10.1145/3178487.3178534.","short":"H. Riebler, G.F. Vaz, T. Kenter, C. Plessl, in: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018."},"year":"2018","user_id":"15278","ddc":["000"],"file":[{"file_name":"p417-riebler.pdf","date_created":"2018-11-02T14:43:37Z","access_level":"closed","file_size":447769,"creator":"ups","file_id":"5281","content_type":"application/pdf","date_updated":"2018-11-02T14:43:37Z","relation":"main_file","success":1}],"keyword":["htrop"],"file_date_updated":"2018-11-02T14:43:37Z","publication":"Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)","author":[{"id":"8961","last_name":"Riebler","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","id":"30332","last_name":"Vaz"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"publisher":"ACM","quality_controlled":"1","date_created":"2018-03-08T14:45:18Z","has_accepted_license":"1","status":"public","date_updated":"2023-09-26T11:47:23Z","doi":"10.1145/3178487.3178534","language":[{"iso":"eng"}],"title":"Automated Code Acceleration Targeting Heterogeneous OpenCL Devices","department":[{"_id":"27"},{"_id":"518"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"14","name":"SFB 901 - Subproject C2","grant_number":"160364472"}],"publication_identifier":{"isbn":["9781450349826"]},"publication_status":"published"},{"file":[{"access_level":"closed","date_created":"2018-11-02T16:04:14Z","file_name":"a24-riebler.pdf","content_type":"application/pdf","date_updated":"2018-11-02T16:04:14Z","relation":"main_file","success":1,"file_size":2131617,"file_id":"5322","creator":"ups"}],"author":[{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"first_name":"Michael","orcid":"0000-0002-5708-7632","full_name":"Lass, Michael","last_name":"Lass","id":"24135"},{"first_name":"Robert","full_name":"Mittendorf, Robert","last_name":"Mittendorf"},{"full_name":"Löcke, Thomas","first_name":"Thomas","last_name":"Löcke"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"publisher":"Association for Computing Machinery (ACM)","quality_controlled":"1","file_date_updated":"2018-11-02T16:04:14Z","publication":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","keyword":["coldboot"],"has_accepted_license":"1","status":"public","date_created":"2017-07-25T14:17:32Z","volume":10,"abstract":[{"text":"Branch and bound (B&B) algorithms structure the search space as a tree and eliminate infeasible solutions early by pruning subtrees that cannot lead to a valid or optimal solution. Custom hardware designs significantly accelerate the execution of these algorithms. In this article, we demonstrate a high-performance B&B implementation on FPGAs. First, we identify general elements of B&B algorithms and describe their implementation as a finite state machine. Then, we introduce workers that autonomously cooperate using work stealing to allow parallel execution and full utilization of the target FPGA. Finally, we explore advantages of instance-specific designs that target a specific problem instance to improve performance.\r\n\r\nWe evaluate our concepts by applying them to a branch and bound problem, the reconstruction of corrupted AES keys obtained from cold-boot attacks. The evaluation shows that our work stealing approach is scalable with the available resources and provides speedups proportional to the number of workers. Instance-specific designs allow us to achieve an overall speedup of 47 × compared to the fastest implementation of AES key reconstruction so far. Finally, we demonstrate how instance-specific designs can be generated just-in-time such that the provided speedups outweigh the additional time required for design synthesis.","lang":"eng"}],"user_id":"15278","ddc":["000"],"type":"journal_article","citation":{"bibtex":"@article{Riebler_Lass_Mittendorf_Löcke_Plessl_2017, title={Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs}, volume={10}, DOI={10.1145/3053687}, number={3}, journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={Association for Computing Machinery (ACM)}, author={Riebler, Heinrich and Lass, Michael and Mittendorf, Robert and Löcke, Thomas and Plessl, Christian}, year={2017}, pages={24:1-24:23} }","mla":"Riebler, Heinrich, et al. “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs.” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 10, no. 3, Association for Computing Machinery (ACM), 2017, p. 24:1-24:23, doi:10.1145/3053687.","chicago":"Riebler, Heinrich, Michael Lass, Robert Mittendorf, Thomas Löcke, and Christian Plessl. “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs.” ACM Transactions on Reconfigurable Technology and Systems (TRETS) 10, no. 3 (2017): 24:1-24:23. https://doi.org/10.1145/3053687.","apa":"Riebler, H., Lass, M., Mittendorf, R., Löcke, T., & Plessl, C. (2017). Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 10(3), 24:1-24:23. https://doi.org/10.1145/3053687","ama":"Riebler H, Lass M, Mittendorf R, Löcke T, Plessl C. Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs. ACM Transactions on Reconfigurable Technology and Systems (TRETS). 2017;10(3):24:1-24:23. doi:10.1145/3053687","ieee":"H. Riebler, M. Lass, R. Mittendorf, T. Löcke, and C. Plessl, “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 10, no. 3, p. 24:1-24:23, 2017, doi: 10.1145/3053687.","short":"H. Riebler, M. Lass, R. Mittendorf, T. Löcke, C. Plessl, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 10 (2017) 24:1-24:23."},"year":"2017","page":"24:1-24:23","intvolume":" 10","_id":"18","issue":"3","department":[{"_id":"27"},{"_id":"518"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"160364472","name":"SFB 901 - Subproject C2","_id":"14"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"},{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"publication_status":"published","publication_identifier":{"issn":["1936-7406"]},"title":"Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:23:58Z","doi":"10.1145/3053687"},{"title":"Flexible FPGA design for FDTD using OpenCL","department":[{"_id":"27"},{"_id":"518"},{"_id":"61"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"160364472","name":"SFB 901 - Subproject C2","_id":"14"},{"name":"HighPerMeshes","grant_number":"01|H16005A","_id":"33"},{"grant_number":"PL 595/2-1 / 320898746","name":"Performance and Efficiency in HPC with Custom Computing","_id":"32"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"date_updated":"2023-09-26T13:24:38Z","doi":"10.23919/FPL.2017.8056844","language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"Compared to classical HDL designs, generating FPGA with high-level synthesis from an OpenCL specification promises easier exploration of different design alternatives and, through ready-to-use infrastructure and common abstractions for host and memory interfaces, easier portability between different FPGA families. In this work, we evaluate the extent of this promise. To this end, we present a parameterized FDTD implementation for photonic microcavity simulations. Our design can trade-off different forms of parallelism and works for two independent OpenCL-based FPGA design flows. Hence, we can target FPGAs from different vendors and different FPGA families. We describe how we used pre-processor macros to achieve this flexibility and to work around different shortcomings of the current tools. Choosing the right design configurations, we are able to present two extremely competitive solutions for very different FPGA targets, reaching up to 172 GFLOPS sustained performance. With the portability and flexibility demonstrated, code developers not only avoid vendor lock-in, but can even make best use of real trade-offs between different architectures."}],"ddc":["000"],"user_id":"15278","quality_controlled":"1","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"first_name":"Jens","full_name":"Förstner, Jens","orcid":"0000-0001-7059-9862","last_name":"Förstner","id":"158"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"publisher":"IEEE","keyword":["tet_topic_hpc"],"file_date_updated":"2018-11-02T15:02:28Z","publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","file":[{"content_type":"application/pdf","date_updated":"2018-11-02T15:02:28Z","success":1,"relation":"main_file","file_size":230235,"creator":"ups","file_id":"5291","access_level":"closed","date_created":"2018-11-02T15:02:28Z","file_name":"08056844.pdf"}],"status":"public","has_accepted_license":"1","date_created":"2018-03-22T11:10:23Z","_id":"1592","citation":{"apa":"Kenter, T., Förstner, J., & Plessl, C. (2017). Flexible FPGA design for FDTD using OpenCL. Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). https://doi.org/10.23919/FPL.2017.8056844","ama":"Kenter T, Förstner J, Plessl C. Flexible FPGA design for FDTD using OpenCL. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2017. doi:10.23919/FPL.2017.8056844","chicago":"Kenter, Tobias, Jens Förstner, and Christian Plessl. “Flexible FPGA Design for FDTD Using OpenCL.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE, 2017. https://doi.org/10.23919/FPL.2017.8056844.","bibtex":"@inproceedings{Kenter_Förstner_Plessl_2017, title={Flexible FPGA design for FDTD using OpenCL}, DOI={10.23919/FPL.2017.8056844}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Kenter, Tobias and Förstner, Jens and Plessl, Christian}, year={2017} }","mla":"Kenter, Tobias, et al. “Flexible FPGA Design for FDTD Using OpenCL.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2017, doi:10.23919/FPL.2017.8056844.","short":"T. Kenter, J. Förstner, C. Plessl, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2017.","ieee":"T. Kenter, J. Förstner, and C. Plessl, “Flexible FPGA design for FDTD using OpenCL,” 2017, doi: 10.23919/FPL.2017.8056844."},"type":"conference","year":"2017"},{"doi":"10.1088/1742-6596/898/8/082003","article_number":"082003","intvolume":" 898","_id":"1589","date_updated":"2023-09-26T13:24:19Z","language":[{"iso":"eng"}],"type":"journal_article","citation":{"bibtex":"@article{Schumacher_Plessl_Vandelli_2017, title={High-Throughput and Low-Latency Network Communication with NetIO}, volume={898}, DOI={10.1088/1742-6596/898/8/082003}, number={082003}, journal={Journal of Physics: Conference Series}, publisher={IOP Publishing}, author={Schumacher, Jörn and Plessl, Christian and Vandelli, Wainer}, year={2017} }","mla":"Schumacher, Jörn, et al. “High-Throughput and Low-Latency Network Communication with NetIO.” Journal of Physics: Conference Series, vol. 898, 082003, IOP Publishing, 2017, doi:10.1088/1742-6596/898/8/082003.","chicago":"Schumacher, Jörn, Christian Plessl, and Wainer Vandelli. “High-Throughput and Low-Latency Network Communication with NetIO.” Journal of Physics: Conference Series 898 (2017). https://doi.org/10.1088/1742-6596/898/8/082003.","apa":"Schumacher, J., Plessl, C., & Vandelli, W. (2017). High-Throughput and Low-Latency Network Communication with NetIO. Journal of Physics: Conference Series, 898, Article 082003. https://doi.org/10.1088/1742-6596/898/8/082003","ama":"Schumacher J, Plessl C, Vandelli W. High-Throughput and Low-Latency Network Communication with NetIO. Journal of Physics: Conference Series. 2017;898. doi:10.1088/1742-6596/898/8/082003","ieee":"J. Schumacher, C. Plessl, and W. Vandelli, “High-Throughput and Low-Latency Network Communication with NetIO,” Journal of Physics: Conference Series, vol. 898, Art. no. 082003, 2017, doi: 10.1088/1742-6596/898/8/082003.","short":"J. Schumacher, C. Plessl, W. Vandelli, Journal of Physics: Conference Series 898 (2017)."},"year":"2017","user_id":"15278","title":"High-Throughput and Low-Latency Network Communication with NetIO","date_created":"2018-03-22T10:51:20Z","status":"public","volume":898,"department":[{"_id":"27"},{"_id":"518"}],"publication":"Journal of Physics: Conference Series","quality_controlled":"1","author":[{"last_name":"Schumacher","full_name":"Schumacher, Jörn","first_name":"Jörn"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"last_name":"Vandelli","first_name":"Wainer","full_name":"Vandelli, Wainer"}],"publisher":"IOP Publishing"},{"language":[{"iso":"eng"}],"type":"conference","year":"2016","citation":{"ama":"Lass M, Leibenger D, Sorge C. Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension. In: Proc. 41st Conference on Local Computer Networks (LCN). IEEE; 2016. doi:10.1109/lcn.2016.11","apa":"Lass, M., Leibenger, D., & Sorge, C. (2016). Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension. In Proc. 41st Conference on Local Computer Networks (LCN). IEEE. https://doi.org/10.1109/lcn.2016.11","chicago":"Lass, Michael, Dominik Leibenger, and Christoph Sorge. “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension.” In Proc. 41st Conference on Local Computer Networks (LCN). IEEE, 2016. https://doi.org/10.1109/lcn.2016.11.","mla":"Lass, Michael, et al. “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension.” Proc. 41st Conference on Local Computer Networks (LCN), IEEE, 2016, doi:10.1109/lcn.2016.11.","bibtex":"@inproceedings{Lass_Leibenger_Sorge_2016, title={Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension}, DOI={10.1109/lcn.2016.11}, booktitle={Proc. 41st Conference on Local Computer Networks (LCN)}, publisher={IEEE}, author={Lass, Michael and Leibenger, Dominik and Sorge, Christoph}, year={2016} }","short":"M. Lass, D. Leibenger, C. Sorge, in: Proc. 41st Conference on Local Computer Networks (LCN), IEEE, 2016.","ieee":"M. Lass, D. Leibenger, and C. Sorge, “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension,” in Proc. 41st Conference on Local Computer Networks (LCN), 2016."},"doi":"10.1109/lcn.2016.11","date_updated":"2022-01-06T06:53:56Z","_id":"19","date_created":"2017-07-25T14:36:16Z","status":"public","publication_identifier":{"isbn":["978-1-5090-2054-6"]},"publication_status":"published","keyword":["access control","distributed version control systems","mercurial","peer-to-peer","convergent encryption","confidentiality","authenticity"],"department":[{"_id":"27"},{"_id":"518"}],"publication":"Proc. 41st Conference on Local Computer Networks (LCN)","publisher":"IEEE","author":[{"first_name":"Michael","full_name":"Lass, Michael","orcid":"0000-0002-5708-7632","last_name":"Lass","id":"24135"},{"last_name":"Leibenger","first_name":"Dominik","full_name":"Leibenger, Dominik"},{"last_name":"Sorge","full_name":"Sorge, Christoph","first_name":"Christoph"}],"user_id":"24135","title":"Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension","abstract":[{"text":"Version Control Systems (VCS) are a valuable tool for software development\r\nand document management. Both client/server and distributed (Peer-to-Peer)\r\nmodels exist, with the latter (e.g., Git and Mercurial) becoming\r\nincreasingly popular. Their distributed nature introduces complications,\r\nespecially concerning security: it is hard to control the dissemination of\r\ncontents stored in distributed VCS as they rely on replication of complete\r\nrepositories to any involved user.\r\n\r\nWe overcome this issue by designing and implementing a concept for\r\ncryptography-enforced access control which is transparent to the user. Use\r\nof field-tested schemes (end-to-end encryption, digital signatures) allows\r\nfor strong security, while adoption of convergent encryption and\r\ncontent-defined chunking retains storage efficiency. The concept is\r\nseamlessly integrated into Mercurial---respecting its distributed storage\r\nconcept---to ensure practical usability and compatibility to existing\r\ndeployments.","lang":"eng"}]},{"_id":"5418","date_updated":"2022-01-06T07:01:52Z","year":"2016","citation":{"ieee":"C. Tölke, Sicherheit von hybriden FPGA-Systemen in der industriellen Automatisierungstechnik -- Anforderungen und Umsetzung. Universität Paderborn, 2016.","short":"C. Tölke, Sicherheit von Hybriden FPGA-Systemen in Der Industriellen Automatisierungstechnik -- Anforderungen Und Umsetzung, Universität Paderborn, 2016.","mla":"Tölke, Christian. Sicherheit von Hybriden FPGA-Systemen in Der Industriellen Automatisierungstechnik -- Anforderungen Und Umsetzung. Universität Paderborn, 2016.","bibtex":"@book{Tölke_2016, title={Sicherheit von hybriden FPGA-Systemen in der industriellen Automatisierungstechnik -- Anforderungen und Umsetzung}, publisher={Universität Paderborn}, author={Tölke, Christian}, year={2016} }","chicago":"Tölke, Christian. Sicherheit von Hybriden FPGA-Systemen in Der Industriellen Automatisierungstechnik -- Anforderungen Und Umsetzung. Universität Paderborn, 2016.","apa":"Tölke, C. (2016). Sicherheit von hybriden FPGA-Systemen in der industriellen Automatisierungstechnik -- Anforderungen und Umsetzung. Universität Paderborn.","ama":"Tölke C. Sicherheit von Hybriden FPGA-Systemen in Der Industriellen Automatisierungstechnik -- Anforderungen Und Umsetzung. Universität Paderborn; 2016."},"type":"mastersthesis","supervisor":[{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"language":[{"iso":"eng"}],"title":"Sicherheit von hybriden FPGA-Systemen in der industriellen Automatisierungstechnik -- Anforderungen und Umsetzung","user_id":"477","department":[{"_id":"27"},{"_id":"518"}],"author":[{"last_name":"Tölke","first_name":"Christian","full_name":"Tölke, Christian"}],"publisher":"Universität Paderborn","date_created":"2018-11-07T16:10:00Z","project":[{"name":"SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"status":"public"},{"title":"Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment","user_id":"477","publisher":"Universität Paderborn","author":[{"last_name":"Wüllrich","full_name":"Wüllrich, Gunnar","first_name":"Gunnar"}],"department":[{"_id":"27"},{"_id":"518"}],"status":"public","project":[{"_id":"1","name":"SFB 901"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"date_created":"2018-11-07T16:15:51Z","_id":"5420","date_updated":"2022-01-06T07:01:53Z","citation":{"short":"G. Wüllrich, Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment, Universität Paderborn, 2016.","ieee":"G. Wüllrich, Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment. Universität Paderborn, 2016.","ama":"Wüllrich G. Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment. Universität Paderborn; 2016.","apa":"Wüllrich, G. (2016). Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment. Universität Paderborn.","chicago":"Wüllrich, Gunnar. Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment. Universität Paderborn, 2016.","bibtex":"@book{Wüllrich_2016, title={Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment}, publisher={Universität Paderborn}, author={Wüllrich, Gunnar}, year={2016} }","mla":"Wüllrich, Gunnar. Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment. Universität Paderborn, 2016."},"type":"mastersthesis","year":"2016","language":[{"iso":"eng"}],"supervisor":[{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}]},{"type":"dissertation","year":"2016","citation":{"ieee":"T. Kenter, Reconfigurable Accelerators in the World of General-Purpose Computing. Universität Paderborn, 2016.","short":"T. Kenter, Reconfigurable Accelerators in the World of General-Purpose Computing, Universität Paderborn, 2016.","mla":"Kenter, Tobias. Reconfigurable Accelerators in the World of General-Purpose Computing. Universität Paderborn, 2016.","bibtex":"@book{Kenter_2016, title={Reconfigurable Accelerators in the World of General-Purpose Computing}, publisher={Universität Paderborn}, author={Kenter, Tobias}, year={2016} }","apa":"Kenter, T. (2016). Reconfigurable Accelerators in the World of General-Purpose Computing. Universität Paderborn.","ama":"Kenter T. Reconfigurable Accelerators in the World of General-Purpose Computing. Universität Paderborn; 2016.","chicago":"Kenter, Tobias. Reconfigurable Accelerators in the World of General-Purpose Computing. Universität Paderborn, 2016."},"supervisor":[{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"date_updated":"2022-01-06T06:52:43Z","_id":"161","file_date_updated":"2018-03-21T12:46:48Z","department":[{"_id":"27"},{"_id":"518"}],"author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"}],"publisher":"Universität Paderborn","file":[{"access_level":"closed","file_name":"161kenter16_diss_submission_print_16-08-26.pdf","date_created":"2018-03-21T12:46:48Z","relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-03-21T12:46:48Z","creator":"florida","file_id":"1545","file_size":5039555}],"date_created":"2017-10-17T12:41:23Z","project":[{"name":"SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"}],"status":"public","has_accepted_license":"1","title":"Reconfigurable Accelerators in the World of General-Purpose Computing","ddc":["040"],"user_id":"3145"},{"abstract":[{"lang":"eng","text":"In this chapter, we present an introduction to the ReconOS operating system for reconfigurable computing. ReconOS offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. By supporting standard POSIX operating system functions for both software and hardware threads, ReconOS particularly caters to developers with a software background, because developers can use well-known mechanisms such as semaphores, mutexes, condition variables, and message queues for developing hybrid applications with threads running on the CPU and FPGA concurrently. Through the semantic integration of hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications between different reconfigurable computing systems."}],"user_id":"15278","publisher":"Springer International Publishing","quality_controlled":"1","author":[{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"first_name":"Enno","full_name":"Lübbers, Enno","last_name":"Lübbers"}],"publication":"FPGAs for Software Programmers","status":"public","date_created":"2017-07-26T15:07:06Z","_id":"29","citation":{"bibtex":"@inbook{Agne_Platzner_Plessl_Happe_Lübbers_2016, place={Cham}, title={ReconOS}, DOI={10.1007/978-3-319-26408-0_13}, booktitle={FPGAs for Software Programmers}, publisher={Springer International Publishing}, author={Agne, Andreas and Platzner, Marco and Plessl, Christian and Happe, Markus and Lübbers, Enno}, editor={Koch, Dirk and Hannig, Frank and Ziener, Daniel}, year={2016}, pages={227–244} }","mla":"Agne, Andreas, et al. “ReconOS.” FPGAs for Software Programmers, edited by Dirk Koch et al., Springer International Publishing, 2016, pp. 227–44, doi:10.1007/978-3-319-26408-0_13.","chicago":"Agne, Andreas, Marco Platzner, Christian Plessl, Markus Happe, and Enno Lübbers. “ReconOS.” In FPGAs for Software Programmers, edited by Dirk Koch, Frank Hannig, and Daniel Ziener, 227–44. Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-26408-0_13.","apa":"Agne, A., Platzner, M., Plessl, C., Happe, M., & Lübbers, E. (2016). ReconOS. In D. Koch, F. Hannig, & D. Ziener (Eds.), FPGAs for Software Programmers (pp. 227–244). Springer International Publishing. https://doi.org/10.1007/978-3-319-26408-0_13","ama":"Agne A, Platzner M, Plessl C, Happe M, Lübbers E. ReconOS. In: Koch D, Hannig F, Ziener D, eds. FPGAs for Software Programmers. Springer International Publishing; 2016:227-244. doi:10.1007/978-3-319-26408-0_13","ieee":"A. Agne, M. Platzner, C. Plessl, M. Happe, and E. Lübbers, “ReconOS,” in FPGAs for Software Programmers, D. Koch, F. Hannig, and D. Ziener, Eds. Cham: Springer International Publishing, 2016, pp. 227–244.","short":"A. Agne, M. Platzner, C. Plessl, M. Happe, E. Lübbers, in: D. Koch, F. Hannig, D. Ziener (Eds.), FPGAs for Software Programmers, Springer International Publishing, Cham, 2016, pp. 227–244."},"type":"book_chapter","year":"2016","page":"227-244","place":"Cham","title":"ReconOS","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"editor":[{"last_name":"Koch","full_name":"Koch, Dirk","first_name":"Dirk"},{"full_name":"Hannig, Frank","first_name":"Frank","last_name":"Hannig"},{"last_name":"Ziener","first_name":"Daniel","full_name":"Ziener, Daniel"}],"publication_identifier":{"isbn":["978-3-319-26406-6","978-3-319-26408-0"]},"publication_status":"published","project":[{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"date_updated":"2023-09-26T13:25:38Z","doi":"10.1007/978-3-319-26408-0_13","language":[{"iso":"eng"}]},{"date_updated":"2023-09-26T13:25:59Z","_id":"31","type":"conference","year":"2016","citation":{"ieee":"H. Riebler, G. F. Vaz, C. Plessl, E. M. G. Trainiti, G. C. Durelli, and C. Bolchini, “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” 2016.","short":"H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, C. Bolchini, in: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.","mla":"Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.","bibtex":"@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, booktitle={Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Bolchini, Cristiana}, year={2016} }","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, and Cristiana Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.","apa":"Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., & Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. Proc. HiPEAC Workshop on Reonfigurable Computing (WRC).","ama":"Riebler H, Vaz GF, Plessl C, Trainiti EMG, Durelli GC, Bolchini C. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC). ; 2016."},"language":[{"iso":"eng"}],"ddc":["040"],"title":"Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems","user_id":"15278","department":[{"_id":"27"},{"_id":"518"}],"file_date_updated":"2019-01-11T11:56:55Z","publication":"Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)","quality_controlled":"1","author":[{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","last_name":"Vaz","id":"30332"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"first_name":"Ettore M. G.","full_name":"Trainiti, Ettore M. G.","last_name":"Trainiti"},{"full_name":"Durelli, Gianluca C.","first_name":"Gianluca C.","last_name":"Durelli"},{"full_name":"Bolchini, Cristiana","first_name":"Cristiana","last_name":"Bolchini"}],"file":[{"date_updated":"2019-01-11T11:56:55Z","content_type":"application/pdf","success":1,"relation":"main_file","file_size":394563,"creator":"deffel","file_id":"6626","access_level":"closed","date_created":"2019-01-11T11:56:55Z","file_name":"wrc_upb_polimi_final.pdf"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"160364472","name":"SFB 901 - Subproject C2","_id":"14"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"date_created":"2017-07-26T15:16:31Z","status":"public","has_accepted_license":"1"},{"title":"Microdisk Cavity FDTD Simulation on FPGA using OpenCL","ddc":["004"],"user_id":"15278","author":[{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"quality_controlled":"1","publication":"Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)","department":[{"_id":"27"},{"_id":"518"}],"file_date_updated":"2018-11-14T12:38:45Z","file":[{"access_level":"closed","file_name":"paper_26.pdf","date_created":"2018-11-14T12:38:45Z","relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-11-14T12:38:45Z","creator":"kenter","file_id":"5602","file_size":129552}],"has_accepted_license":"1","status":"public","date_created":"2017-07-26T15:00:43Z","project":[{"_id":"32","grant_number":"PL 595/2-1 / 320898746","name":"Performance and Efficiency in HPC with Custom Computing"},{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901 - Subproject C2","grant_number":"160364472","_id":"14"}],"_id":"24","date_updated":"2023-09-26T13:26:17Z","citation":{"chicago":"Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” In Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016.","apa":"Kenter, T., & Plessl, C. (2016). Microdisk Cavity FDTD Simulation on FPGA using OpenCL. Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC).","ama":"Kenter T, Plessl C. Microdisk Cavity FDTD Simulation on FPGA using OpenCL. In: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). ; 2016.","mla":"Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016.","bibtex":"@inproceedings{Kenter_Plessl_2016, title={Microdisk Cavity FDTD Simulation on FPGA using OpenCL}, booktitle={Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, author={Kenter, Tobias and Plessl, Christian}, year={2016} }","short":"T. Kenter, C. Plessl, in: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016.","ieee":"T. Kenter and C. Plessl, “Microdisk Cavity FDTD Simulation on FPGA using OpenCL,” 2016."},"year":"2016","type":"conference","language":[{"iso":"eng"}]},{"author":[{"orcid":"0000-0002-5708-7632","full_name":"Lass, Michael","first_name":"Michael","id":"24135","last_name":"Lass"},{"full_name":"Kühne, Thomas","first_name":"Thomas","id":"49079","last_name":"Kühne"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","publication":"Workshop on Approximate Computing (AC)","department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"status":"public","date_created":"2017-07-26T15:02:20Z","project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"user_id":"15278","title":"Using Approximate Computing in Scientific Codes","language":[{"iso":"eng"}],"citation":{"short":"M. Lass, T. Kühne, C. Plessl, in: Workshop on Approximate Computing (AC), 2016.","ieee":"M. Lass, T. Kühne, and C. Plessl, “Using Approximate Computing in Scientific Codes,” 2016.","chicago":"Lass, Michael, Thomas Kühne, and Christian Plessl. “Using Approximate Computing in Scientific Codes.” In Workshop on Approximate Computing (AC), 2016.","apa":"Lass, M., Kühne, T., & Plessl, C. (2016). Using Approximate Computing in Scientific Codes. Workshop on Approximate Computing (AC).","ama":"Lass M, Kühne T, Plessl C. Using Approximate Computing in Scientific Codes. In: Workshop on Approximate Computing (AC). ; 2016.","mla":"Lass, Michael, et al. “Using Approximate Computing in Scientific Codes.” Workshop on Approximate Computing (AC), 2016.","bibtex":"@inproceedings{Lass_Kühne_Plessl_2016, title={Using Approximate Computing in Scientific Codes}, booktitle={Workshop on Approximate Computing (AC)}, author={Lass, Michael and Kühne, Thomas and Plessl, Christian}, year={2016} }"},"year":"2016","type":"conference","date_updated":"2023-09-26T13:25:17Z","_id":"25"},{"department":[{"_id":"27"},{"_id":"518"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"title":"Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:28:11Z","doi":"10.1109/RTSI.2016.7740545","file":[{"file_name":"138-07740545.pdf","date_created":"2018-03-21T13:01:09Z","access_level":"closed","file_size":184334,"file_id":"1560","creator":"florida","date_updated":"2018-03-21T13:01:09Z","content_type":"application/pdf","success":1,"relation":"main_file"}],"author":[{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","id":"30332","last_name":"Vaz"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"first_name":"Ettore M. G. ","full_name":"Trainiti, Ettore M. G. ","last_name":"Trainiti"},{"last_name":"Durelli","first_name":"Gianluca C.","full_name":"Durelli, Gianluca C."},{"first_name":"Emanuele","full_name":"Del Sozzo, Emanuele","last_name":"Del Sozzo"},{"last_name":"Santambrogio","first_name":"Marco D. ","full_name":"Santambrogio, Marco D. "},{"last_name":"Bolchini","full_name":"Bolchini, Christina","first_name":"Christina"}],"quality_controlled":"1","publisher":"IEEE","publication":"Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)","file_date_updated":"2018-03-21T13:01:09Z","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:41:18Z","abstract":[{"text":"Hardware accelerators are becoming popular in academia and industry. To move one step further from the state-of-the-art multicore plus accelerator approaches, we present in this paper our innovative SAVEHSA architecture. It comprises of a heterogeneous hardware platform with three different high-end accelerators attached over PCIe (GPGPU, FPGA and Intel MIC). Such systems can process parallel workloads very efficiently whilst being more energy efficient than regular CPU systems. To leverage the heterogeneity, the workload has to be distributed among the computing units in a way that each unit is well-suited for the assigned task and executable code must be available. To tackle this problem we present two software components; the first can perform resource allocation at runtime while respecting system and application goals (in terms of throughput, energy, latency, etc.) and the second is able to analyze an application and generate executable code for an accelerator at runtime. We demonstrate the first proof-of-concept implementation of our framework on the heterogeneous platform, discuss different runtime policies and measure the introduced overheads.","lang":"eng"}],"user_id":"15278","ddc":["040"],"type":"conference","citation":{"ama":"Riebler H, Vaz GF, Plessl C, et al. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI). IEEE; 2016:1-5. doi:10.1109/RTSI.2016.7740545","apa":"Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., Del Sozzo, E., Santambrogio, M. D., & Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 1–5. https://doi.org/10.1109/RTSI.2016.7740545","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, Emanuele Del Sozzo, Marco D. Santambrogio, and Christina Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 1–5. IEEE, 2016. https://doi.org/10.1109/RTSI.2016.7740545.","mla":"Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5, doi:10.1109/RTSI.2016.7740545.","bibtex":"@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Del Sozzo_Santambrogio_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, DOI={10.1109/RTSI.2016.7740545}, booktitle={Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)}, publisher={IEEE}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Del Sozzo, Emanuele and Santambrogio, Marco D. and Bolchini, Christina}, year={2016}, pages={1–5} }","short":"H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, E. Del Sozzo, M.D. Santambrogio, C. Bolchini, in: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5.","ieee":"H. Riebler et al., “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” in Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 2016, pp. 1–5, doi: 10.1109/RTSI.2016.7740545."},"year":"2016","page":"1-5","_id":"138"},{"_id":"156","page":"145-165","type":"book_chapter","year":"2016","citation":{"ieee":"A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-aware Compute Nodes,” in Self-aware Computing Systems, Cham: Springer International Publishing, 2016, pp. 145–165.","short":"A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, in: Self-Aware Computing Systems, Springer International Publishing, Cham, 2016, pp. 145–165.","bibtex":"@inbook{Agne_Happe_Lösch_Plessl_Platzner_2016, place={Cham}, series={Natural Computing Series (NCS)}, title={Self-aware Compute Nodes}, DOI={10.1007/978-3-319-39675-0_8}, booktitle={Self-aware Computing Systems}, publisher={Springer International Publishing}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2016}, pages={145–165}, collection={Natural Computing Series (NCS)} }","mla":"Agne, Andreas, et al. “Self-Aware Compute Nodes.” Self-Aware Computing Systems, Springer International Publishing, 2016, pp. 145–65, doi:10.1007/978-3-319-39675-0_8.","chicago":"Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Aware Compute Nodes.” In Self-Aware Computing Systems, 145–65. Natural Computing Series (NCS). Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-39675-0_8.","ama":"Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-aware Compute Nodes. In: Self-Aware Computing Systems. Natural Computing Series (NCS). Springer International Publishing; 2016:145-165. doi:10.1007/978-3-319-39675-0_8","apa":"Agne, A., Happe, M., Lösch, A., Plessl, C., & Platzner, M. (2016). Self-aware Compute Nodes. In Self-aware Computing Systems (pp. 145–165). Springer International Publishing. https://doi.org/10.1007/978-3-319-39675-0_8"},"ddc":["040"],"user_id":"15278","abstract":[{"lang":"eng","text":"Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level."}],"date_created":"2017-10-17T12:41:22Z","has_accepted_license":"1","status":"public","publication":"Self-aware Computing Systems","file_date_updated":"2018-11-14T13:20:32Z","author":[{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"last_name":"Lösch","id":"43646","first_name":"Achim","full_name":"Lösch, Achim"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"quality_controlled":"1","publisher":"Springer International Publishing","file":[{"creator":"aloesch","file_id":"5613","file_size":833054,"success":1,"relation":"main_file","date_updated":"2018-11-14T13:20:32Z","content_type":"application/pdf","date_created":"2018-11-14T13:20:32Z","file_name":"chapter8.pdf","access_level":"closed"}],"doi":"10.1007/978-3-319-39675-0_8","date_updated":"2023-09-26T13:27:44Z","language":[{"iso":"eng"}],"series_title":"Natural Computing Series (NCS)","title":"Self-aware Compute Nodes","place":"Cham","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"department":[{"_id":"518"},{"_id":"27"},{"_id":"78"}]},{"page":"91-111","citation":{"ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code,” Computers and Electrical Engineering, vol. 55, pp. 91–111, 2016, doi: 10.1016/j.compeleceng.2016.04.021.","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, Computers and Electrical Engineering 55 (2016) 91–111.","bibtex":"@article{Vaz_Riebler_Kenter_Plessl_2016, title={Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code}, volume={55}, DOI={10.1016/j.compeleceng.2016.04.021}, journal={Computers and Electrical Engineering}, publisher={Elsevier}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2016}, pages={91–111} }","mla":"Vaz, Gavin Francis, et al. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” Computers and Electrical Engineering, vol. 55, Elsevier, 2016, pp. 91–111, doi:10.1016/j.compeleceng.2016.04.021.","chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” Computers and Electrical Engineering 55 (2016): 91–111. https://doi.org/10.1016/j.compeleceng.2016.04.021.","apa":"Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2016). Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. Computers and Electrical Engineering, 55, 91–111. https://doi.org/10.1016/j.compeleceng.2016.04.021","ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. Computers and Electrical Engineering. 2016;55:91-111. doi:10.1016/j.compeleceng.2016.04.021"},"type":"journal_article","year":"2016","intvolume":" 55","_id":"165","publication":"Computers and Electrical Engineering","file_date_updated":"2018-03-21T12:45:47Z","author":[{"id":"30332","last_name":"Vaz","full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis"},{"first_name":"Heinrich","full_name":"Riebler, Heinrich","last_name":"Riebler","id":"8961"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"publisher":"Elsevier","quality_controlled":"1","file":[{"access_level":"closed","file_name":"165-1-s2.0-S0045790616301021-main.pdf","date_created":"2018-03-21T12:45:47Z","success":1,"relation":"main_file","date_updated":"2018-03-21T12:45:47Z","content_type":"application/pdf","file_id":"1544","creator":"florida","file_size":3037854}],"volume":55,"date_created":"2017-10-17T12:41:24Z","status":"public","has_accepted_license":"1","abstract":[{"text":"A broad spectrum of applications can be accelerated by offloading computation intensive parts to reconfigurable hardware. However, to achieve speedups, the number of loop it- erations (trip count) needs to be sufficiently large to amortize offloading overheads. Trip counts are frequently not known at compile time, but only at runtime just before entering a loop. Therefore, we propose to generate code for both the CPU and the coprocessor, and defer the offloading decision to the application runtime. We demonstrate how a toolflow, based on the LLVM compiler framework, can automatically embed dynamic offloading de- cisions into the application code. We perform in-depth static and dynamic analysis of pop- ular benchmarks, which confirm the general potential of such an approach. We also pro- pose to optimize the offloading process by decoupling the runtime decision from the loop execution (decision slack). The feasibility of our approach is demonstrated by a toolflow that automatically identifies suitable data-parallel loops and generates code for the FPGA coprocessor of a Convey HC-1. We evaluate the integrated toolflow with representative loops executed for different input data sizes.","lang":"eng"}],"ddc":["040"],"user_id":"15278","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:26:38Z","doi":"10.1016/j.compeleceng.2016.04.021","department":[{"_id":"27"},{"_id":"518"}],"publication_identifier":{"issn":["0045-7906"]},"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"title":"Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code"},{"abstract":[{"lang":"eng","text":"The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative."}],"user_id":"15278","ddc":["040"],"file":[{"file_size":261356,"file_id":"1541","creator":"florida","content_type":"application/pdf","date_updated":"2018-03-21T12:41:55Z","relation":"main_file","success":1,"file_name":"168-07459438.pdf","date_created":"2018-03-21T12:41:55Z","access_level":"closed"}],"quality_controlled":"1","publisher":"EDA Consortium / IEEE","author":[{"last_name":"Lösch","id":"43646","first_name":"Achim","full_name":"Lösch, Achim"},{"full_name":"Beisel, Tobias","first_name":"Tobias","last_name":"Beisel"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"file_date_updated":"2018-03-21T12:41:55Z","publication":"Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:41:24Z","_id":"168","citation":{"short":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–917.","ieee":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric scheduling with task migration for a heterogeneous compute node in the data center,” in Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, pp. 912–917.","apa":"Lösch, A., Beisel, T., Kenter, T., Plessl, C., & Platzner, M. (2016). Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–917.","ama":"Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. In: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE). EDA Consortium / IEEE; 2016:912-917.","chicago":"Lösch, Achim, Tobias Beisel, Tobias Kenter, Christian Plessl, and Marco Platzner. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” In Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–17. EDA Consortium / IEEE, 2016.","mla":"Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–17.","bibtex":"@inproceedings{Lösch_Beisel_Kenter_Plessl_Platzner_2016, title={Performance-centric scheduling with task migration for a heterogeneous compute node in the data center}, booktitle={Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, publisher={EDA Consortium / IEEE}, author={Lösch, Achim and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco}, year={2016}, pages={912–917} }"},"year":"2016","type":"conference","page":"912-917","title":"Performance-centric scheduling with task migration for a heterogeneous compute node in the data center","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30"}],"date_updated":"2023-09-26T13:27:00Z","language":[{"iso":"eng"}]},{"file":[{"access_level":"closed","file_name":"171-plessl16_fpl_wrc.pdf","date_created":"2018-03-21T12:39:46Z","date_updated":"2018-03-21T12:39:46Z","content_type":"application/pdf","relation":"main_file","success":1,"file_size":54421,"file_id":"1538","creator":"florida"}],"publication":"Workshop on Reconfigurable Computing (WRC)","department":[{"_id":"27"},{"_id":"518"}],"file_date_updated":"2018-03-21T12:39:46Z","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"id":"30332","last_name":"Vaz","full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis"},{"id":"8961","last_name":"Riebler","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"quality_controlled":"1","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"date_created":"2017-10-17T12:41:25Z","status":"public","has_accepted_license":"1","user_id":"15278","title":"Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)","ddc":["040"],"language":[{"iso":"eng"}],"year":"2016","citation":{"short":"T. Kenter, G.F. Vaz, H. Riebler, C. Plessl, in: Workshop on Reconfigurable Computing (WRC), 2016.","ieee":"T. Kenter, G. F. Vaz, H. Riebler, and C. Plessl, “Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract),” 2016.","chicago":"Kenter, Tobias, Gavin Francis Vaz, Heinrich Riebler, and Christian Plessl. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” In Workshop on Reconfigurable Computing (WRC), 2016.","apa":"Kenter, T., Vaz, G. F., Riebler, H., & Plessl, C. (2016). Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). Workshop on Reconfigurable Computing (WRC).","ama":"Kenter T, Vaz GF, Riebler H, Plessl C. Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). In: Workshop on Reconfigurable Computing (WRC). ; 2016.","bibtex":"@inproceedings{Kenter_Vaz_Riebler_Plessl_2016, title={Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)}, booktitle={Workshop on Reconfigurable Computing (WRC)}, author={Kenter, Tobias and Vaz, Gavin Francis and Riebler, Heinrich and Plessl, Christian}, year={2016} }","mla":"Kenter, Tobias, et al. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” Workshop on Reconfigurable Computing (WRC), 2016."},"type":"conference","date_updated":"2023-09-26T13:27:21Z","_id":"171"},{"title":"Self-Aware and Self-Expressive Systems – Guest Editor's Introduction","project":[{"_id":"1","name":"SFB 901"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"14","name":"SFB 901 - Subproject C2"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1109/MC.2015.205","date_updated":"2022-01-06T06:53:19Z","language":[{"iso":"eng"}],"user_id":"16153","ddc":["000"],"has_accepted_license":"1","status":"public","date_created":"2018-03-23T14:06:12Z","volume":48,"file":[{"access_level":"closed","file_name":"07163237.pdf","date_created":"2018-11-02T15:47:45Z","date_updated":"2018-11-02T15:47:45Z","content_type":"application/pdf","success":1,"relation":"main_file","file_size":5605009,"file_id":"5313","creator":"ups"}],"author":[{"first_name":"Jim","full_name":"Torresen, Jim","last_name":"Torresen"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"full_name":"Yao, Xin","first_name":"Xin","last_name":"Yao"}],"publisher":"IEEE Computer Society","publication":"IEEE Computer","file_date_updated":"2018-11-02T15:47:45Z","keyword":["self-awareness","self-expression"],"issue":"7","_id":"1772","intvolume":" 48","citation":{"mla":"Torresen, Jim, et al. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” IEEE Computer, vol. 48, no. 7, IEEE Computer Society, 2015, pp. 18–20, doi:10.1109/MC.2015.205.","bibtex":"@article{Torresen_Plessl_Yao_2015, title={Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction}, volume={48}, DOI={10.1109/MC.2015.205}, number={7}, journal={IEEE Computer}, publisher={IEEE Computer Society}, author={Torresen, Jim and Plessl, Christian and Yao, Xin}, year={2015}, pages={18–20} }","chicago":"Torresen, Jim, Christian Plessl, and Xin Yao. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” IEEE Computer 48, no. 7 (2015): 18–20. https://doi.org/10.1109/MC.2015.205.","apa":"Torresen, J., Plessl, C., & Yao, X. (2015). Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer, 48(7), 18–20. https://doi.org/10.1109/MC.2015.205","ama":"Torresen J, Plessl C, Yao X. Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer. 2015;48(7):18-20. doi:10.1109/MC.2015.205","ieee":"J. Torresen, C. Plessl, and X. Yao, “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction,” IEEE Computer, vol. 48, no. 7, pp. 18–20, 2015.","short":"J. Torresen, C. Plessl, X. Yao, IEEE Computer 48 (2015) 18–20."},"type":"journal_article","year":"2015","page":"18-20"},{"department":[{"_id":"27"},{"_id":"518"}],"author":[{"last_name":"Lass","id":"24135","first_name":"Michael","full_name":"Lass, Michael","orcid":"0000-0002-5708-7632"}],"publisher":"Paderborn University","date_created":"2018-03-26T15:24:10Z","status":"public","abstract":[{"lang":"eng","text":"Demands for computational power and energy efficiency of computing devices are steadily increasing. At the same time, following classic methods to increase speed and reduce energy consumption of these devices becomes increasingly difficult, bringing alternative methods into focus. One of these methods is approximate computing which utilizes the fact that small errors in computations are acceptable in many applications in order to allow acceleration of these computations or to increase energy efficiency. This thesis develops elements of a workflow that can be followed to apply approximate computing to existing applications. It proposes a novel heuristic approach to the localization of code paths that are suitable to approximate computing based on findings in recent research. Additionally, an approach to identification of approximable instructions within these code paths is proposed and used to implement simulation of approximation. The parts of the workflow are implemented with the goal to lay the foundation for a partly automated toolflow. Evaluation of the developed techniques shows that the proposed methods can help providing a convenient workflow, facilitating the first steps into the application of approximate computing."}],"place":"Paderborn","title":"Localization and Analysis of Code Paths Suitable for Acceleration using Approximate Computing","user_id":"24135","year":"2015","citation":{"short":"M. Lass, Localization and Analysis of Code Paths Suitable for Acceleration Using Approximate Computing, Paderborn University, Paderborn, 2015.","ieee":"M. Lass, Localization and Analysis of Code Paths Suitable for Acceleration using Approximate Computing. Paderborn: Paderborn University, 2015.","ama":"Lass M. Localization and Analysis of Code Paths Suitable for Acceleration Using Approximate Computing. Paderborn: Paderborn University; 2015.","apa":"Lass, M. (2015). Localization and Analysis of Code Paths Suitable for Acceleration using Approximate Computing. Paderborn: Paderborn University.","chicago":"Lass, Michael. Localization and Analysis of Code Paths Suitable for Acceleration Using Approximate Computing. Paderborn: Paderborn University, 2015.","bibtex":"@book{Lass_2015, place={Paderborn}, title={Localization and Analysis of Code Paths Suitable for Acceleration using Approximate Computing}, publisher={Paderborn University}, author={Lass, Michael}, year={2015} }","mla":"Lass, Michael. Localization and Analysis of Code Paths Suitable for Acceleration Using Approximate Computing. Paderborn University, 2015."},"type":"mastersthesis","supervisor":[{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"date_updated":"2022-01-06T06:53:23Z","_id":"1794"},{"type":"conference","citation":{"chicago":"Jenert, Tobias, and Taiga Brahm. “How Do They Find Their Place? A Longitudinal Study of Management Students’ Attitudes and Motivations During Their First Year at Business School,” 2015.","ama":"Jenert T, Brahm T. How Do They Find Their Place? A Longitudinal Study of Management Students’ Attitudes and Motivations During Their First Year at Business School. In: ; 2015.","apa":"Jenert, T., & Brahm, T. (2015). How Do They Find Their Place? A Longitudinal Study of Management Students’ Attitudes and Motivations During Their First Year at Business School. Presented at the American Educational Research Association (AERA) Annual Meeting 2015, Chicago.","bibtex":"@inproceedings{Jenert_Brahm_2015, title={How Do They Find Their Place? A Longitudinal Study of Management Students’ Attitudes and Motivations During Their First Year at Business School}, author={Jenert, Tobias and Brahm, Taiga}, year={2015} }","mla":"Jenert, Tobias, and Taiga Brahm. How Do They Find Their Place? A Longitudinal Study of Management Students’ Attitudes and Motivations During Their First Year at Business School. 2015.","short":"T. Jenert, T. Brahm, in: 2015.","ieee":"T. Jenert and T. Brahm, “How Do They Find Their Place? A Longitudinal Study of Management Students’ Attitudes and Motivations During Their First Year at Business School,” presented at the American Educational Research Association (AERA) Annual Meeting 2015, Chicago, 2015."},"year":"2015","date_updated":"2022-01-06T07:01:05Z","_id":"4465","conference":{"start_date":"2015-04-16","name":"American Educational Research Association (AERA) Annual Meeting 2015","location":"Chicago","end_date":"2015-04-20"},"status":"public","date_created":"2018-09-18T13:00:01Z","author":[{"full_name":"Jenert, Tobias","orcid":" https://orcid.org/0000-0001-9262-5646","first_name":"Tobias","id":"71994","last_name":"Jenert"},{"first_name":"Taiga","full_name":"Brahm, Taiga","last_name":"Brahm"}],"keyword":["Enculturation","first-year students","beginning students","retention","drop-out"],"department":[{"_id":"208"},{"_id":"518"}],"user_id":"51057","title":"How Do They Find Their Place? A Longitudinal Study of Management Students' Attitudes and Motivations During Their First Year at Business School","abstract":[{"text":"The first year of studying has been extensively researched applying different theoretical lenses to better understand the transition into Higher Education (HE). It is of particular interest to investigate how students deal with frictions between themselves as individuals and what they perceive to be dominant features of the first-year culture of their studies. To tackle this question, a qualitative longitudinal study was conducted. Based on a sociocultural understanding of attitudes and motivations, its aim was to closely follow a relatively small but highly diverse sample of students throughout their first year at a business school in order to develop an in-depth understanding of each individual’s motivational and attitudinal development.","lang":"eng"}],"extern":"1"},{"_id":"5413","date_updated":"2022-01-06T07:01:52Z","language":[{"iso":"eng"}],"supervisor":[{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"citation":{"ieee":"L. Funke, An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications using FPGA Overlay Architectures. Universität Paderborn, 2015.","short":"L. Funke, An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications Using FPGA Overlay Architectures, Universität Paderborn, 2015.","bibtex":"@book{Funke_2015, title={An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications using FPGA Overlay Architectures}, publisher={Universität Paderborn}, author={Funke, Lukas}, year={2015} }","mla":"Funke, Lukas. An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications Using FPGA Overlay Architectures. Universität Paderborn, 2015.","chicago":"Funke, Lukas. An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications Using FPGA Overlay Architectures. Universität Paderborn, 2015.","ama":"Funke L. An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications Using FPGA Overlay Architectures. Universität Paderborn; 2015.","apa":"Funke, L. (2015). An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications using FPGA Overlay Architectures. Universität Paderborn."},"year":"2015","type":"mastersthesis","user_id":"477","title":"An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications using FPGA Overlay Architectures","status":"public","date_created":"2018-11-07T15:10:35Z","project":[{"name":"SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"SFB 901 - Subproject C2","_id":"14"}],"author":[{"last_name":"Funke","full_name":"Funke, Lukas","first_name":"Lukas"}],"publisher":"Universität Paderborn","department":[{"_id":"27"},{"_id":"518"}]},{"year":"2015","citation":{"short":"T. Löcke, Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems, Universität Paderborn, 2015.","ieee":"T. Löcke, Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems. Universität Paderborn, 2015.","chicago":"Löcke, Thomas. Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems. Universität Paderborn, 2015.","apa":"Löcke, T. (2015). Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems. Universität Paderborn.","ama":"Löcke T. Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems. Universität Paderborn; 2015.","mla":"Löcke, Thomas. Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems. Universität Paderborn, 2015.","bibtex":"@book{Löcke_2015, title={Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems}, publisher={Universität Paderborn}, author={Löcke, Thomas}, year={2015} }"},"type":"mastersthesis","supervisor":[{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"language":[{"iso":"eng"}],"date_updated":"2022-01-06T07:01:52Z","_id":"5416","date_created":"2018-11-07T16:06:53Z","project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"status":"public","department":[{"_id":"27"},{"_id":"518"}],"author":[{"first_name":"Thomas","full_name":"Löcke, Thomas","last_name":"Löcke"}],"publisher":"Universität Paderborn","title":"Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems","user_id":"477"},{"_id":"5419","date_updated":"2022-01-06T07:01:52Z","citation":{"mla":"Wallaschek, Felix. Accelerating Programmable Logic Controllers with the Use of FPGAs. Universität Paderborn, 2015.","bibtex":"@book{Wallaschek_2015, title={Accelerating Programmable Logic Controllers with the use of FPGAs}, publisher={Universität Paderborn}, author={Wallaschek, Felix}, year={2015} }","apa":"Wallaschek, F. (2015). Accelerating Programmable Logic Controllers with the use of FPGAs. Universität Paderborn.","ama":"Wallaschek F. Accelerating Programmable Logic Controllers with the Use of FPGAs. Universität Paderborn; 2015.","chicago":"Wallaschek, Felix. Accelerating Programmable Logic Controllers with the Use of FPGAs. Universität Paderborn, 2015.","ieee":"F. Wallaschek, Accelerating Programmable Logic Controllers with the use of FPGAs. Universität Paderborn, 2015.","short":"F. Wallaschek, Accelerating Programmable Logic Controllers with the Use of FPGAs, Universität Paderborn, 2015."},"year":"2015","type":"mastersthesis","language":[{"iso":"eng"}],"supervisor":[{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"title":"Accelerating Programmable Logic Controllers with the use of FPGAs","user_id":"477","status":"public","project":[{"name":"SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"SFB 901 - Subproject C2","_id":"14"}],"date_created":"2018-11-07T16:14:30Z","publisher":"Universität Paderborn","author":[{"first_name":"Felix","full_name":"Wallaschek, Felix","last_name":"Wallaschek"}],"department":[{"_id":"27"},{"_id":"518"}]},{"user_id":"3118","title":"Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing","abstract":[{"text":"The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types.\r\n\r\nEnabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes.\r\n\r\nThis thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies.","lang":"eng"}],"place":"Berlin","date_created":"2019-07-10T09:36:58Z","project":[{"_id":"30","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004"}],"status":"public","publication_identifier":{"isbn":["978-3-8325-4155-2"]},"department":[{"_id":"78"},{"_id":"27"},{"_id":"518"}],"publisher":"Logos Verlag Berlin GmbH","author":[{"first_name":"Tobias","full_name":"Beisel, Tobias","last_name":"Beisel"}],"_id":"10624","date_updated":"2022-01-06T06:50:48Z","language":[{"iso":"eng"}],"supervisor":[{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"page":"183","citation":{"mla":"Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Logos Verlag Berlin GmbH, 2015.","bibtex":"@book{Beisel_2015, place={Berlin}, title={Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing}, publisher={Logos Verlag Berlin GmbH}, author={Beisel, Tobias}, year={2015} }","chicago":"Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.","apa":"Beisel, T. (2015). Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH.","ama":"Beisel T. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH; 2015.","ieee":"T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.","short":"T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing, Logos Verlag Berlin GmbH, Berlin, 2015."},"type":"dissertation","year":"2015"},{"language":[{"iso":"eng"}],"doi":"10.1155/2015/859425","date_updated":"2023-09-26T13:29:08Z","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study","year":"2015","type":"journal_article","citation":{"ama":"Kenter T, Schmitz H, Plessl C. Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International Journal of Reconfigurable Computing (IJRC). 2015;2015. doi:10.1155/2015/859425","apa":"Kenter, T., Schmitz, H., & Plessl, C. (2015). Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International Journal of Reconfigurable Computing (IJRC), 2015, Article 859425. https://doi.org/10.1155/2015/859425","chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” International Journal of Reconfigurable Computing (IJRC) 2015 (2015). https://doi.org/10.1155/2015/859425.","mla":"Kenter, Tobias, et al. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” International Journal of Reconfigurable Computing (IJRC), vol. 2015, 859425, Hindawi, 2015, doi:10.1155/2015/859425.","bibtex":"@article{Kenter_Schmitz_Plessl_2015, title={Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study}, volume={2015}, DOI={10.1155/2015/859425}, number={859425}, journal={International Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2015} }","short":"T. Kenter, H. Schmitz, C. Plessl, International Journal of Reconfigurable Computing (IJRC) 2015 (2015).","ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study,” International Journal of Reconfigurable Computing (IJRC), vol. 2015, Art. no. 859425, 2015, doi: 10.1155/2015/859425."},"article_number":"859425","intvolume":" 2015","_id":"296","volume":2015,"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:41:49Z","author":[{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"last_name":"Schmitz","full_name":"Schmitz, Henning","first_name":"Henning"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","publisher":"Hindawi","publication":"International Journal of Reconfigurable Computing (IJRC)","file_date_updated":"2018-03-20T07:47:56Z","file":[{"file_name":"296-859425.pdf","date_created":"2018-03-20T07:47:56Z","access_level":"closed","file_size":2993898,"file_id":"1444","creator":"florida","date_updated":"2018-03-20T07:47:56Z","content_type":"application/pdf","success":1,"relation":"main_file"}],"ddc":["040"],"user_id":"15278","abstract":[{"lang":"eng","text":"FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x."}]},{"_id":"303","year":"2015","type":"conference","citation":{"ieee":"M. Damschen and C. Plessl, “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores,” 2015.","short":"M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.","mla":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.","bibtex":"@inproceedings{Damschen_Plessl_2015, title={Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores}, booktitle={Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}, author={Damschen, Marvin and Plessl, Christian}, year={2015} }","apa":"Damschen, M., & Plessl, C. (2015). Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT).","ama":"Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. In: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT). ; 2015.","chicago":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” In Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015."},"abstract":[{"text":"This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement.","lang":"eng"}],"user_id":"15278","ddc":["040"],"file":[{"file_size":1176620,"file_id":"1442","creator":"florida","content_type":"application/pdf","date_updated":"2019-08-01T09:10:44Z","relation":"main_file","date_created":"2018-03-20T07:46:46Z","file_name":"303-plessl15_adapt.pdf","access_level":"open_access"}],"publication":"Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)","file_date_updated":"2019-08-01T09:10:44Z","quality_controlled":"1","author":[{"first_name":"Marvin","full_name":"Damschen, Marvin","last_name":"Damschen"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"date_created":"2017-10-17T12:41:51Z","has_accepted_license":"1","status":"public","date_updated":"2023-09-26T13:29:59Z","oa":"1","language":[{"iso":"eng"}],"external_id":{"arxiv":["1412.3906"]},"title":"Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}]},{"doi":"10.1145/2675743.2771824","date_updated":"2023-09-26T13:31:01Z","_id":"1773","language":[{"iso":"eng"}],"citation":{"ieee":"J. Schumacher et al., “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm,” 2015, doi: 10.1145/2675743.2771824.","short":"J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen, J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015.","mla":"Schumacher, Jörn, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015, doi:10.1145/2675743.2771824.","bibtex":"@inproceedings{Schumacher_T. Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_et al._2015, title={Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm}, DOI={10.1145/2675743.2771824}, booktitle={Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)}, publisher={ACM}, author={Schumacher, Jörn and T. Anderson, J. and Borga, A. and Boterenbrood, H. and Chen, H. and Chen, K. and Drake, G. and Francis, D. and Gorini, B. and Lanni, F. and et al.}, year={2015} }","chicago":"Schumacher, Jörn, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” In Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM, 2015. https://doi.org/10.1145/2675743.2771824.","ama":"Schumacher J, T. Anderson J, Borga A, et al. Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. In: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM; 2015. doi:10.1145/2675743.2771824","apa":"Schumacher, J., T. Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann-Miotto, G., Levinson, L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., P. Schreuder, F., Vandelli, W., Vermeulen, J., & Zhang, J. (2015). Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). https://doi.org/10.1145/2675743.2771824"},"year":"2015","type":"conference","user_id":"15278","title":"Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm","status":"public","date_created":"2018-03-23T14:09:33Z","publisher":"ACM","author":[{"full_name":"Schumacher, Jörn","first_name":"Jörn","last_name":"Schumacher"},{"full_name":"T. Anderson, J.","first_name":"J.","last_name":"T. Anderson"},{"full_name":"Borga, A.","first_name":"A.","last_name":"Borga"},{"last_name":"Boterenbrood","first_name":"H.","full_name":"Boterenbrood, H."},{"last_name":"Chen","first_name":"H.","full_name":"Chen, H."},{"last_name":"Chen","full_name":"Chen, K.","first_name":"K."},{"last_name":"Drake","full_name":"Drake, G.","first_name":"G."},{"first_name":"D.","full_name":"Francis, D.","last_name":"Francis"},{"first_name":"B.","full_name":"Gorini, B.","last_name":"Gorini"},{"first_name":"F.","full_name":"Lanni, F.","last_name":"Lanni"},{"last_name":"Lehmann-Miotto","full_name":"Lehmann-Miotto, Giovanna","first_name":"Giovanna"},{"last_name":"Levinson","full_name":"Levinson, L.","first_name":"L."},{"last_name":"Narevicius","first_name":"J.","full_name":"Narevicius, J."},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"first_name":"A.","full_name":"Roich, A.","last_name":"Roich"},{"first_name":"S.","full_name":"Ryu, S.","last_name":"Ryu"},{"last_name":"P. Schreuder","first_name":"F.","full_name":"P. Schreuder, F."},{"last_name":"Vandelli","full_name":"Vandelli, Wainer","first_name":"Wainer"},{"last_name":"Vermeulen","first_name":"J.","full_name":"Vermeulen, J."},{"first_name":"J.","full_name":"Zhang, J.","last_name":"Zhang"}],"quality_controlled":"1","publication":"Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}]},{"language":[{"iso":"eng"}],"type":"journal_article","citation":{"short":"C. Plessl, M. Platzner, P.J. Schreier, Informatik Spektrum (2015) 396–399.","ieee":"C. Plessl, M. Platzner, and P. J. Schreier, “Aktuelles Schlagwort: Approximate Computing,” Informatik Spektrum, no. 5, pp. 396–399, 2015, doi: 10.1007/s00287-015-0911-z.","ama":"Plessl C, Platzner M, Schreier PJ. Aktuelles Schlagwort: Approximate Computing. Informatik Spektrum. 2015;(5):396-399. doi:10.1007/s00287-015-0911-z","apa":"Plessl, C., Platzner, M., & Schreier, P. J. (2015). Aktuelles Schlagwort: Approximate Computing. Informatik Spektrum, 5, 396–399. https://doi.org/10.1007/s00287-015-0911-z","chicago":"Plessl, Christian, Marco Platzner, and Peter J. Schreier. “Aktuelles Schlagwort: Approximate Computing.” Informatik Spektrum, no. 5 (2015): 396–99. https://doi.org/10.1007/s00287-015-0911-z.","mla":"Plessl, Christian, et al. “Aktuelles Schlagwort: Approximate Computing.” Informatik Spektrum, no. 5, Springer, 2015, pp. 396–99, doi:10.1007/s00287-015-0911-z.","bibtex":"@article{Plessl_Platzner_Schreier_2015, title={Aktuelles Schlagwort: Approximate Computing}, DOI={10.1007/s00287-015-0911-z}, number={5}, journal={Informatik Spektrum}, publisher={Springer}, author={Plessl, Christian and Platzner, Marco and Schreier, Peter J.}, year={2015}, pages={396–399} }"},"year":"2015","page":"396-399","date_updated":"2023-09-26T13:30:22Z","_id":"1768","issue":"5","doi":"10.1007/s00287-015-0911-z","quality_controlled":"1","author":[{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"last_name":"Schreier","full_name":"Schreier, Peter J.","first_name":"Peter J."}],"publisher":"Springer","department":[{"_id":"27"},{"_id":"518"},{"_id":"263"},{"_id":"78"}],"keyword":["approximate computing","survey"],"publication":"Informatik Spektrum","status":"public","date_created":"2018-03-23T13:58:34Z","user_id":"15278","title":"Aktuelles Schlagwort: Approximate Computing"},{"_id":"238","year":"2015","type":"conference","citation":{"mla":"Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–83, doi:10.7873/DATE.2015.1124.","bibtex":"@inproceedings{Damschen_Riebler_Vaz_Plessl_2015, title={Transparent offloading of computational hotspots from binary code to Xeon Phi}, DOI={10.7873/DATE.2015.1124}, booktitle={Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)}, publisher={EDA Consortium / IEEE}, author={Damschen, Marvin and Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}, year={2015}, pages={1078–1083} }","apa":"Damschen, M., Riebler, H., Vaz, G. F., & Plessl, C. (2015). Transparent offloading of computational hotspots from binary code to Xeon Phi. Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–1083. https://doi.org/10.7873/DATE.2015.1124","ama":"Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational hotspots from binary code to Xeon Phi. In: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE). EDA Consortium / IEEE; 2015:1078-1083. doi:10.7873/DATE.2015.1124","chicago":"Damschen, Marvin, Heinrich Riebler, Gavin Francis Vaz, and Christian Plessl. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” In Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–83. EDA Consortium / IEEE, 2015. https://doi.org/10.7873/DATE.2015.1124.","ieee":"M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading of computational hotspots from binary code to Xeon Phi,” in Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 2015, pp. 1078–1083, doi: 10.7873/DATE.2015.1124.","short":"M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–1083."},"page":"1078-1083","abstract":[{"text":"In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator.","lang":"eng"}],"user_id":"15278","ddc":["040"],"file":[{"file_name":"238-plessl15_date.pdf","date_created":"2018-03-21T10:29:49Z","access_level":"closed","file_size":380552,"creator":"florida","file_id":"1500","date_updated":"2018-03-21T10:29:49Z","content_type":"application/pdf","success":1,"relation":"main_file"}],"publisher":"EDA Consortium / IEEE","author":[{"last_name":"Damschen","full_name":"Damschen, Marvin","first_name":"Marvin"},{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","last_name":"Vaz","id":"30332"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","file_date_updated":"2018-03-21T10:29:49Z","publication":"Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:41:38Z","date_updated":"2023-09-26T13:31:44Z","doi":"10.7873/DATE.2015.1124","language":[{"iso":"eng"}],"title":"Transparent offloading of computational hotspots from binary code to Xeon Phi","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}]},{"citation":{"short":"J. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. Schreuder, J. Schumacher, W. Vandelli, J. Vermeulen, J. Zhang, Journal of Physics: Conference Series 664 (2015).","ieee":"J. Anderson et al., “FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades,” Journal of Physics: Conference Series, vol. 664, Art. no. 082050, 2015, doi: 10.1088/1742-6596/664/8/082050.","apa":"Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann Miotto, G., Levinson, L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., Schreuder, F., Schumacher, J., Vandelli, W., Vermeulen, J., & Zhang, J. (2015). FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades. Journal of Physics: Conference Series, 664, Article 082050. https://doi.org/10.1088/1742-6596/664/8/082050","ama":"Anderson J, Borga A, Boterenbrood H, et al. FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades. Journal of Physics: Conference Series. 2015;664. doi:10.1088/1742-6596/664/8/082050","chicago":"Anderson, J, A Borga, H Boterenbrood, H Chen, K Chen, G Drake, D Francis, et al. “FELIX: A High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades.” Journal of Physics: Conference Series 664 (2015). https://doi.org/10.1088/1742-6596/664/8/082050.","mla":"Anderson, J., et al. “FELIX: A High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades.” Journal of Physics: Conference Series, vol. 664, 082050, IOP Publishing, 2015, doi:10.1088/1742-6596/664/8/082050.","bibtex":"@article{Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_Lehmann Miotto_et al._2015, title={FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades}, volume={664}, DOI={10.1088/1742-6596/664/8/082050}, number={082050}, journal={Journal of Physics: Conference Series}, publisher={IOP Publishing}, author={Anderson, J and Borga, A and Boterenbrood, H and Chen, H and Chen, K and Drake, G and Francis, D and Gorini, B and Lanni, F and Lehmann Miotto, G and et al.}, year={2015} }"},"year":"2015","type":"journal_article","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:31:23Z","_id":"1775","intvolume":" 664","doi":"10.1088/1742-6596/664/8/082050","article_number":"082050","publication":"Journal of Physics: Conference Series","department":[{"_id":"27"},{"_id":"518"}],"quality_controlled":"1","author":[{"full_name":"Anderson, J","first_name":"J","last_name":"Anderson"},{"full_name":"Borga, A","first_name":"A","last_name":"Borga"},{"last_name":"Boterenbrood","first_name":"H","full_name":"Boterenbrood, H"},{"last_name":"Chen","full_name":"Chen, H","first_name":"H"},{"last_name":"Chen","first_name":"K","full_name":"Chen, K"},{"last_name":"Drake","full_name":"Drake, G","first_name":"G"},{"last_name":"Francis","first_name":"D","full_name":"Francis, D"},{"last_name":"Gorini","first_name":"B","full_name":"Gorini, B"},{"first_name":"F","full_name":"Lanni, F","last_name":"Lanni"},{"last_name":"Lehmann Miotto","first_name":"G","full_name":"Lehmann Miotto, G"},{"last_name":"Levinson","first_name":"L","full_name":"Levinson, L"},{"full_name":"Narevicius, J","first_name":"J","last_name":"Narevicius"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"full_name":"Roich, A","first_name":"A","last_name":"Roich"},{"first_name":"S","full_name":"Ryu, S","last_name":"Ryu"},{"full_name":"Schreuder, F","first_name":"F","last_name":"Schreuder"},{"full_name":"Schumacher, Jörn","first_name":"Jörn","last_name":"Schumacher"},{"full_name":"Vandelli, Wainer","first_name":"Wainer","last_name":"Vandelli"},{"last_name":"Vermeulen","first_name":"J","full_name":"Vermeulen, J"},{"last_name":"Zhang","full_name":"Zhang, J","first_name":"J"}],"publisher":"IOP Publishing","volume":664,"date_created":"2018-03-23T14:19:27Z","status":"public","abstract":[{"text":"The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. A new class of devices will be needed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper FELIX (Front End LInk eXchange) is presented, a PC-based device to route data from and to multiple GBT links via a high-performance general purpose network capable of a total throughput up to O(20 Tbps). FELIX implies architectural changes to the ATLAS data acquisition system, such as the use of industry standard COTS components early in the DAQ chain. Additionally the design and implementation of a FELIX demonstration platform is presented and hardware and software aspects will be discussed.","lang":"eng"}],"title":"FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades","user_id":"15278"},{"place":"Paderborn","title":"Verschiebungen an der Grenze zwischen Hardware und Software","department":[{"_id":"518"},{"_id":"27"},{"_id":"78"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"}],"editor":[{"full_name":"Künsemöller, Jörn","first_name":"Jörn","last_name":"Künsemöller"},{"last_name":"Eke","first_name":"Norber Otto","full_name":"Eke, Norber Otto"},{"last_name":"Foit","first_name":"Lioba","full_name":"Foit, Lioba"},{"last_name":"Kaerlein","full_name":"Kaerlein, Timo","first_name":"Timo"}],"publication_identifier":{"isbn":["978-3-7705-5730-1"]},"publication_status":"published","date_updated":"2023-09-26T13:32:49Z","series_title":"Schriftenreihe des Graduiertenkollegs \"Automatismen\"","language":[{"iso":"ger"}],"abstract":[{"text":"Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung der Ausbildung in den Computerwissenschaften beeinflusst und sogar zur Entstehung von neuen Forschungsrichtungen gef{\\\"u}hrt. In diesem Beitrag besch{\\\"a}ftigen wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der Entstehung dieser Grenze, die Hardware und Software erst als eigenst{\\\"a}ndige Produkte differenziert. Dann widmen wir uns der Frage, welche Funktionen in einem Computersystem besser in Hardware und welche besser in Software realisiert werden sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen Forschungsrichtung, dem sogenannten Hardware/Software Co-design, gef{\\\"u}hrt hat. Im Hardware/Software Co-design findet eine Verschiebung von Funktionen an der Grenze zwischen Hardware und Software w{\\\"a}hrend der Entwicklung eines Produktes statt, um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten Produkt hingegen k{\\\"o}nnen wir dann eine feste Grenze zwischen Hardware und Software beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption, dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware und Software autonom w{\\\"a}hrend der Betriebszeit vornimmt. Solche Systeme beruhen auf rekonfigurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware eines Computers w{\\\"a}hrend der Laufzeit ver{\\\"a}ndert werden kann. Diese Technologie f{\\\"u}hrt zu einer durchl{\\\"a}ssigen Grenze zwischen Hardware und Software bzw. l{\\\"o}st sie die herk{\\\"o}mmliche Vorstellung einer festen Hardware und einer flexiblen Software damit auf.","lang":"eng"}],"user_id":"15278","ddc":["040"],"file":[{"file_size":2848154,"creator":"florida","file_id":"1424","date_updated":"2018-03-20T07:29:58Z","content_type":"application/pdf","success":1,"relation":"main_file","file_name":"335-2014_plessl_automatismen.pdf","date_created":"2018-03-20T07:29:58Z","access_level":"closed"}],"publisher":"Wilhelm Fink","author":[{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","publication":"Logiken strukturbildender Prozesse: Automatismen","file_date_updated":"2018-03-20T07:29:58Z","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:41:57Z","_id":"335","citation":{"ama":"Platzner M, Plessl C. Verschiebungen an der Grenze zwischen Hardware und Software. In: Künsemöller J, Eke NO, Foit L, Kaerlein T, eds. Logiken strukturbildender Prozesse: Automatismen. Schriftenreihe des Graduiertenkollegs “Automatismen.” Wilhelm Fink; 2014:123-144.","apa":"Platzner, M., & Plessl, C. (2014). Verschiebungen an der Grenze zwischen Hardware und Software. In J. Künsemöller, N. O. Eke, L. Foit, & T. Kaerlein (Eds.), Logiken strukturbildender Prozesse: Automatismen (pp. 123–144). Wilhelm Fink.","chicago":"Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” In Logiken strukturbildender Prozesse: Automatismen, edited by Jörn Künsemöller, Norber Otto Eke, Lioba Foit, and Timo Kaerlein, 123–44. Schriftenreihe des Graduiertenkollegs “Automatismen.” Paderborn: Wilhelm Fink, 2014.","bibtex":"@inbook{Platzner_Plessl_2014, place={Paderborn}, series={Schriftenreihe des Graduiertenkollegs “Automatismen”}, title={Verschiebungen an der Grenze zwischen Hardware und Software}, booktitle={Logiken strukturbildender Prozesse: Automatismen}, publisher={Wilhelm Fink}, author={Platzner, Marco and Plessl, Christian}, editor={Künsemöller, Jörn and Eke, Norber Otto and Foit, Lioba and Kaerlein, Timo}, year={2014}, pages={123–144}, collection={Schriftenreihe des Graduiertenkollegs “Automatismen”} }","mla":"Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” Logiken strukturbildender Prozesse: Automatismen, edited by Jörn Künsemöller et al., Wilhelm Fink, 2014, pp. 123–44.","short":"M. Platzner, C. Plessl, in: J. Künsemöller, N.O. Eke, L. Foit, T. Kaerlein (Eds.), Logiken strukturbildender Prozesse: Automatismen, Wilhelm Fink, Paderborn, 2014, pp. 123–144.","ieee":"M. Platzner and C. Plessl, “Verschiebungen an der Grenze zwischen Hardware und Software,” in Logiken strukturbildender Prozesse: Automatismen, J. Künsemöller, N. O. Eke, L. Foit, and T. Kaerlein, Eds. Paderborn: Wilhelm Fink, 2014, pp. 123–144."},"type":"book_chapter","year":"2014","page":"123-144"},{"user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties."}],"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:07Z","volume":8405,"file":[{"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-20T07:02:02Z","file_id":"1387","creator":"florida","file_size":330193,"access_level":"closed","file_name":"388-plessl14_arc.pdf","date_created":"2018-03-20T07:02:02Z"}],"quality_controlled":"1","publisher":"Springer International Publishing","author":[{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"id":"30332","last_name":"Vaz","full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"publication":"Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)","file_date_updated":"2018-03-20T07:02:02Z","intvolume":" 8405","_id":"388","citation":{"short":"T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer International Publishing, Cham, 2014, pp. 144–155.","ieee":"T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer,” in Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 2014, vol. 8405, pp. 144–155, doi: 10.1007/978-3-319-05960-0_13.","chicago":"Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 8405:144–55. Lecture Notes in Computer Science (LNCS). Cham: Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-05960-0_13.","ama":"Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. In: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC). Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International Publishing; 2014:144-155. doi:10.1007/978-3-319-05960-0_13","apa":"Kenter, T., Vaz, G. F., & Plessl, C. (2014). Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 8405, 144–155. https://doi.org/10.1007/978-3-319-05960-0_13","mla":"Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:10.1007/978-3-319-05960-0_13.","bibtex":"@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer}, volume={8405}, DOI={10.1007/978-3-319-05960-0_13}, booktitle={Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)}, publisher={Springer International Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian}, year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)} }"},"type":"conference","year":"2014","page":"144-155","title":"Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer","place":"Cham","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1007/978-3-319-05960-0_13","date_updated":"2023-09-26T13:34:08Z","language":[{"iso":"eng"}],"series_title":"Lecture Notes in Computer Science (LNCS)"},{"intvolume":" 38","_id":"363","issue":"8, Part B","page":"911-919","citation":{"chicago":"Agne, Andreas, Hendrik Hangmann, Markus Happe, Marco Platzner, and Christian Plessl. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” Microprocessors and Microsystems 38, no. 8, Part B (2014): 911–19. https://doi.org/10.1016/j.micpro.2013.12.001.","apa":"Agne, A., Hangmann, H., Happe, M., Platzner, M., & Plessl, C. (2014). Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems, 38(8, Part B), 911–919. https://doi.org/10.1016/j.micpro.2013.12.001","ama":"Agne A, Hangmann H, Happe M, Platzner M, Plessl C. Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems. 2014;38(8, Part B):911-919. doi:10.1016/j.micpro.2013.12.001","bibtex":"@article{Agne_Hangmann_Happe_Platzner_Plessl_2014, title={Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators}, volume={38}, DOI={10.1016/j.micpro.2013.12.001}, number={8, Part B}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco and Plessl, Christian}, year={2014}, pages={911–919} }","mla":"Agne, Andreas, et al. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” Microprocessors and Microsystems, vol. 38, no. 8, Part B, Elsevier, 2014, pp. 911–19, doi:10.1016/j.micpro.2013.12.001.","short":"A. Agne, H. Hangmann, M. Happe, M. Platzner, C. Plessl, Microprocessors and Microsystems 38 (2014) 911–919.","ieee":"A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl, “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators,” Microprocessors and Microsystems, vol. 38, no. 8, Part B, pp. 911–919, 2014, doi: 10.1016/j.micpro.2013.12.001."},"type":"journal_article","year":"2014","abstract":[{"text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices.","lang":"eng"}],"ddc":["040"],"user_id":"15278","file_date_updated":"2018-03-20T07:20:31Z","publication":"Microprocessors and Microsystems","author":[{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"full_name":"Hangmann, Hendrik","first_name":"Hendrik","last_name":"Hangmann"},{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"publisher":"Elsevier","quality_controlled":"1","file":[{"file_size":1499996,"file_id":"1408","creator":"florida","date_updated":"2018-03-20T07:20:31Z","content_type":"application/pdf","success":1,"relation":"main_file","file_name":"363-plessl13_micpro.pdf","date_created":"2018-03-20T07:20:31Z","access_level":"closed"}],"volume":38,"date_created":"2017-10-17T12:42:02Z","status":"public","has_accepted_license":"1","date_updated":"2023-09-26T13:33:06Z","doi":"10.1016/j.micpro.2013.12.001","language":[{"iso":"eng"}],"title":"Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}]},{"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Reconstructing AES Key Schedules from Decayed Memory with FPGAs","language":[{"iso":"eng"}],"doi":"10.1109/FCCM.2014.67","date_updated":"2023-09-26T13:33:50Z","date_created":"2017-10-17T12:42:05Z","status":"public","has_accepted_license":"1","keyword":["coldboot"],"file_date_updated":"2018-03-20T07:14:20Z","publication":"Proceedings of Field-Programmable Custom Computing Machines (FCCM)","author":[{"first_name":"Heinrich","full_name":"Riebler, Heinrich","last_name":"Riebler","id":"8961"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"last_name":"Sorge","first_name":"Christoph","full_name":"Sorge, Christoph"}],"publisher":"IEEE","quality_controlled":"1","file":[{"relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-03-20T07:14:20Z","file_id":"1397","creator":"florida","file_size":1003907,"access_level":"closed","date_created":"2018-03-20T07:14:20Z","file_name":"377-FCCM14.pdf"}],"ddc":["040"],"user_id":"15278","abstract":[{"lang":"eng","text":"In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates."}],"page":"222-229","type":"conference","citation":{"bibtex":"@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing AES Key Schedules from Decayed Memory with FPGAs}, DOI={10.1109/FCCM.2014.67}, booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian and Sorge, Christoph}, year={2014}, pages={222–229} }","mla":"Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–29, doi:10.1109/FCCM.2014.67.","ama":"Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from Decayed Memory with FPGAs. In: Proceedings of Field-Programmable Custom Computing Machines (FCCM). IEEE; 2014:222-229. doi:10.1109/FCCM.2014.67","apa":"Riebler, H., Kenter, T., Plessl, C., & Sorge, C. (2014). Reconstructing AES Key Schedules from Decayed Memory with FPGAs. Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–229. https://doi.org/10.1109/FCCM.2014.67","chicago":"Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–29. IEEE, 2014. https://doi.org/10.1109/FCCM.2014.67.","ieee":"H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules from Decayed Memory with FPGAs,” in Proceedings of Field-Programmable Custom Computing Machines (FCCM), 2014, pp. 222–229, doi: 10.1109/FCCM.2014.67.","short":"H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229."},"year":"2014","_id":"377"},{"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"department":[{"_id":"27"},{"_id":"78"},{"_id":"518"}],"title":"Self-awareness as a Model for Designing and Operating Heterogeneous Multicores","language":[{"iso":"eng"}],"doi":"10.1145/2617596","date_updated":"2023-09-26T13:33:31Z","date_created":"2017-10-17T12:42:03Z","has_accepted_license":"1","status":"public","volume":7,"file":[{"date_created":"2018-03-20T07:19:19Z","file_name":"365-plessl14_trets_01.pdf","access_level":"closed","file_size":916052,"file_id":"1406","creator":"florida","date_updated":"2018-03-20T07:19:19Z","content_type":"application/pdf","success":1,"relation":"main_file"}],"file_date_updated":"2018-03-20T07:19:19Z","publication":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","author":[{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"full_name":"Lösch, Achim","first_name":"Achim","id":"43646","last_name":"Lösch"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"ACM","quality_controlled":"1","user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems."}],"type":"journal_article","citation":{"apa":"Agne, A., Happe, M., Lösch, A., Plessl, C., & Platzner, M. (2014). Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 7(2), Article 13. https://doi.org/10.1145/2617596","ama":"Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. ACM Transactions on Reconfigurable Technology and Systems (TRETS). 2014;7(2). doi:10.1145/2617596","chicago":"Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7, no. 2 (2014). https://doi.org/10.1145/2617596.","mla":"Agne, Andreas, et al. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, 13, ACM, 2014, doi:10.1145/2617596.","bibtex":"@article{Agne_Happe_Lösch_Plessl_Platzner_2014, title={Self-awareness as a Model for Designing and Operating Heterogeneous Multicores}, volume={7}, DOI={10.1145/2617596}, number={213}, journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={ACM}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2014} }","short":"A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (2014).","ieee":"A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-awareness as a Model for Designing and Operating Heterogeneous Multicores,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, Art. no. 13, 2014, doi: 10.1145/2617596."},"year":"2014","issue":"2","article_number":"13","intvolume":" 7","_id":"365"},{"publication":"IEEE Micro","file_date_updated":"2018-03-20T07:31:40Z","author":[{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"last_name":"Keller","full_name":"Keller, Ariane","first_name":"Ariane"},{"last_name":"Lübbers","first_name":"Enno","full_name":"Lübbers, Enno"},{"full_name":"Plattner, Bernhard","first_name":"Bernhard","last_name":"Plattner"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","publisher":"IEEE","file":[{"access_level":"closed","date_created":"2018-03-20T07:31:40Z","file_name":"328-plessl14_micro_01.pdf","relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-03-20T07:31:40Z","creator":"florida","file_id":"1426","file_size":1877185}],"volume":34,"date_created":"2017-10-17T12:41:55Z","has_accepted_license":"1","status":"public","abstract":[{"text":"The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications","lang":"eng"}],"ddc":["040"],"user_id":"15278","page":"60-71","type":"journal_article","year":"2014","citation":{"mla":"Agne, Andreas, et al. “ReconOS - An Operating System Approach for Reconfigurable Computing.” IEEE Micro, vol. 34, no. 1, IEEE, 2014, pp. 60–71, doi:10.1109/MM.2013.110.","bibtex":"@article{Agne_Happe_Keller_Lübbers_Plattner_Platzner_Plessl_2014, title={ReconOS - An Operating System Approach for Reconfigurable Computing}, volume={34}, DOI={10.1109/MM.2013.110}, number={1}, journal={IEEE Micro}, publisher={IEEE}, author={Agne, Andreas and Happe, Markus and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco and Plessl, Christian}, year={2014}, pages={60–71} }","ama":"Agne A, Happe M, Keller A, et al. ReconOS - An Operating System Approach for Reconfigurable Computing. IEEE Micro. 2014;34(1):60-71. doi:10.1109/MM.2013.110","apa":"Agne, A., Happe, M., Keller, A., Lübbers, E., Plattner, B., Platzner, M., & Plessl, C. (2014). ReconOS - An Operating System Approach for Reconfigurable Computing. IEEE Micro, 34(1), 60–71. https://doi.org/10.1109/MM.2013.110","chicago":"Agne, Andreas, Markus Happe, Ariane Keller, Enno Lübbers, Bernhard Plattner, Marco Platzner, and Christian Plessl. “ReconOS - An Operating System Approach for Reconfigurable Computing.” IEEE Micro 34, no. 1 (2014): 60–71. https://doi.org/10.1109/MM.2013.110.","ieee":"A. Agne et al., “ReconOS - An Operating System Approach for Reconfigurable Computing,” IEEE Micro, vol. 34, no. 1, pp. 60–71, 2014, doi: 10.1109/MM.2013.110.","short":"A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl, IEEE Micro 34 (2014) 60–71."},"intvolume":" 34","_id":"328","issue":"1","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","grant_number":"257906","name":"Engineering Proprioception in Computing Systems"}],"title":"ReconOS - An Operating System Approach for Reconfigurable Computing","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:32:31Z","doi":"10.1109/MM.2013.110"},{"author":[{"first_name":"Gianluca","full_name":"C. Durelli, Gianluca","last_name":"C. Durelli"},{"last_name":"Pogliani","first_name":"Marcello","full_name":"Pogliani, Marcello"},{"first_name":"Antonio","full_name":"Miele, Antonio","last_name":"Miele"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"last_name":"Riebler","id":"8961","first_name":"Heinrich","full_name":"Riebler, Heinrich"},{"last_name":"Vaz","id":"30332","first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis"},{"first_name":"Marco","full_name":"D. Santambrogio, Marco","last_name":"D. Santambrogio"},{"full_name":"Bolchini, Cristiana","first_name":"Cristiana","last_name":"Bolchini"}],"quality_controlled":"1","publisher":"IEEE","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)","status":"public","project":[{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"date_created":"2018-03-26T13:40:14Z","title":"Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach","user_id":"15278","year":"2014","citation":{"short":"G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–149.","ieee":"G. C. Durelli et al., “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach,” in Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 2014, pp. 142–149, doi: 10.1109/ISPA.2014.27.","ama":"C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. In: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA). IEEE; 2014:142-149. doi:10.1109/ISPA.2014.27","apa":"C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G. F., D. Santambrogio, M., & Bolchini, C. (2014). Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–149. https://doi.org/10.1109/ISPA.2014.27","chicago":"C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl, Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” In Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–49. IEEE, 2014. https://doi.org/10.1109/ISPA.2014.27.","mla":"C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–49, doi:10.1109/ISPA.2014.27.","bibtex":"@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014, title={Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach}, DOI={10.1109/ISPA.2014.27}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149} }"},"type":"conference","page":"142-149","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:35:40Z","_id":"1778","doi":"10.1109/ISPA.2014.27"},{"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:37:02Z","doi":"10.1109/ReConFig.2014.7032509","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"title":"Deferring Accelerator Offloading Decisions to Application Runtime","page":"1-8","type":"conference","citation":{"mla":"Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application Runtime.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509.","bibtex":"@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator Offloading Decisions to Application Runtime}, DOI={10.1109/ReConFig.2014.7032509}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }","chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Deferring Accelerator Offloading Decisions to Application Runtime.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032509.","apa":"Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2014). Deferring Accelerator Offloading Decisions to Application Runtime. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032509","ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions to Application Runtime. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509","ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading Decisions to Application Runtime,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032509.","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8."},"year":"2014","_id":"439","file_date_updated":"2018-03-16T11:29:52Z","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","quality_controlled":"1","publisher":"IEEE","author":[{"last_name":"Vaz","id":"30332","first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis"},{"first_name":"Heinrich","full_name":"Riebler, Heinrich","last_name":"Riebler","id":"8961"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"file":[{"relation":"main_file","success":1,"date_updated":"2018-03-16T11:29:52Z","content_type":"application/pdf","file_id":"1353","creator":"florida","file_size":557362,"access_level":"closed","date_created":"2018-03-16T11:29:52Z","file_name":"439-plessl14a_reconfig.pdf"}],"date_created":"2017-10-17T12:42:17Z","status":"public","has_accepted_license":"1","abstract":[{"lang":"eng","text":"Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes."}],"ddc":["040"],"user_id":"15278"},{"publisher":"IEEE","author":[{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"first_name":"Henning","full_name":"Schmitz, Henning","last_name":"Schmitz"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-16T11:37:42Z","file":[{"access_level":"closed","date_created":"2018-03-16T11:37:42Z","file_name":"406-ReConFig14.pdf","relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-03-16T11:37:42Z","file_id":"1366","creator":"florida","file_size":932852}],"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:11Z","abstract":[{"lang":"eng","text":"Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design."}],"ddc":["040"],"user_id":"15278","type":"conference","citation":{"ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High Accuracy Stereo-Matching,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032535.","short":"T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","bibtex":"@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration of High Accuracy Stereo-Matching}, DOI={10.1109/ReConFig.2014.7032535}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2014}, pages={1–8} }","mla":"Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535.","chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032535.","apa":"Kenter, T., Schmitz, H., & Plessl, C. (2014). Kernel-Centric Acceleration of High Accuracy Stereo-Matching. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032535","ama":"Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy Stereo-Matching. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032535"},"year":"2014","page":"1-8","_id":"406","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"title":"Kernel-Centric Acceleration of High Accuracy Stereo-Matching","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:36:40Z","doi":"10.1109/ReConFig.2014.7032535"},{"doi":"10.1007/978-3-319-05960-0_38","date_updated":"2023-09-26T13:36:20Z","_id":"1780","citation":{"ieee":"G. C. Durelli et al., “SAVE: Towards efficient resource management in heterogeneous system architectures,” 2014, doi: 10.1007/978-3-319-05960-0_38.","short":"G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino, O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014.","mla":"C. Durelli, Gianluca, et al. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014, doi:10.1007/978-3-319-05960-0_38.","bibtex":"@inproceedings{C. Durelli_Copolla_Djafarian_Koranaros_Miele_Paolino_Pell_Plessl_D. Santambrogio_Bolchini_2014, title={SAVE: Towards efficient resource management in heterogeneous system architectures}, DOI={10.1007/978-3-319-05960-0_38}, booktitle={Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)}, publisher={Springer}, author={C. Durelli, Gianluca and Copolla, Marcello and Djafarian, Karim and Koranaros, George and Miele, Antonio and Paolino, Michele and Pell, Oliver and Plessl, Christian and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014} }","apa":"C. Durelli, G., Copolla, M., Djafarian, K., Koranaros, G., Miele, A., Paolino, M., Pell, O., Plessl, C., D. Santambrogio, M., & Bolchini, C. (2014). SAVE: Towards efficient resource management in heterogeneous system architectures. Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). https://doi.org/10.1007/978-3-319-05960-0_38","ama":"C. Durelli G, Copolla M, Djafarian K, et al. SAVE: Towards efficient resource management in heterogeneous system architectures. In: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer; 2014. doi:10.1007/978-3-319-05960-0_38","chicago":"C. Durelli, Gianluca, Marcello Copolla, Karim Djafarian, George Koranaros, Antonio Miele, Michele Paolino, Oliver Pell, Christian Plessl, Marco D. Santambrogio, and Cristiana Bolchini. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” In Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer, 2014. https://doi.org/10.1007/978-3-319-05960-0_38."},"type":"conference","year":"2014","language":[{"iso":"eng"}],"title":"SAVE: Towards efficient resource management in heterogeneous system architectures","user_id":"15278","date_created":"2018-03-26T13:45:35Z","project":[{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"status":"public","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)","quality_controlled":"1","publisher":"Springer","author":[{"full_name":"C. Durelli, Gianluca","first_name":"Gianluca","last_name":"C. Durelli"},{"last_name":"Copolla","full_name":"Copolla, Marcello","first_name":"Marcello"},{"first_name":"Karim","full_name":"Djafarian, Karim","last_name":"Djafarian"},{"first_name":"George","full_name":"Koranaros, George","last_name":"Koranaros"},{"full_name":"Miele, Antonio","first_name":"Antonio","last_name":"Miele"},{"full_name":"Paolino, Michele","first_name":"Michele","last_name":"Paolino"},{"first_name":"Oliver","full_name":"Pell, Oliver","last_name":"Pell"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"last_name":"D. Santambrogio","full_name":"D. Santambrogio, Marco","first_name":"Marco"},{"full_name":"Bolchini, Cristiana","first_name":"Cristiana","last_name":"Bolchini"}]},{"publication":"ACM SIGARCH Computer Architecture News","keyword":["funding-maxup","tet_topic_hpc"],"quality_controlled":"1","publisher":"ACM","author":[{"last_name":"Giefers","full_name":"Giefers, Heiner","first_name":"Heiner"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"orcid":"0000-0001-7059-9862","full_name":"Förstner, Jens","first_name":"Jens","id":"158","last_name":"Förstner"}],"volume":41,"date_created":"2018-03-26T13:42:34Z","status":"public","user_id":"15278","page":"65-70","citation":{"ama":"Giefers H, Plessl C, Förstner J. Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH Computer Architecture News. 2014;41(5):65-70. doi:10.1145/2641361.2641372","apa":"Giefers, H., Plessl, C., & Förstner, J. (2014). Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH Computer Architecture News, 41(5), 65–70. https://doi.org/10.1145/2641361.2641372","chicago":"Giefers, Heiner, Christian Plessl, and Jens Förstner. “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” ACM SIGARCH Computer Architecture News 41, no. 5 (2014): 65–70. https://doi.org/10.1145/2641361.2641372.","bibtex":"@article{Giefers_Plessl_Förstner_2014, title={Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers}, volume={41}, DOI={10.1145/2641361.2641372}, number={5}, journal={ACM SIGARCH Computer Architecture News}, publisher={ACM}, author={Giefers, Heiner and Plessl, Christian and Förstner, Jens}, year={2014}, pages={65–70} }","mla":"Giefers, Heiner, et al. “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” ACM SIGARCH Computer Architecture News, vol. 41, no. 5, ACM, 2014, pp. 65–70, doi:10.1145/2641361.2641372.","short":"H. Giefers, C. Plessl, J. Förstner, ACM SIGARCH Computer Architecture News 41 (2014) 65–70.","ieee":"H. Giefers, C. Plessl, and J. Förstner, “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers,” ACM SIGARCH Computer Architecture News, vol. 41, no. 5, pp. 65–70, 2014, doi: 10.1145/2641361.2641372."},"year":"2014","type":"journal_article","_id":"1779","intvolume":" 41","issue":"5","department":[{"_id":"27"},{"_id":"518"},{"_id":"61"},{"_id":"78"}],"publication_identifier":{"issn":["0163-5964"]},"title":"Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:35:58Z","doi":"10.1145/2641361.2641372"},{"title":"Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs","user_id":"477","keyword":["coldboot"],"department":[{"_id":"27"},{"_id":"518"}],"publisher":"Universität Paderborn","author":[{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"}],"project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C1","_id":"13"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"}],"date_created":"2017-10-17T12:42:34Z","status":"public","_id":"521","date_updated":"2022-01-06T07:01:46Z","type":"mastersthesis","citation":{"bibtex":"@book{Riebler_2013, title={Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs}, publisher={Universität Paderborn}, author={Riebler, Heinrich}, year={2013} }","mla":"Riebler, Heinrich. Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Universität Paderborn, 2013.","chicago":"Riebler, Heinrich. Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Universität Paderborn, 2013.","apa":"Riebler, H. (2013). Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Universität Paderborn.","ama":"Riebler H. Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Universität Paderborn; 2013.","ieee":"H. Riebler, Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Universität Paderborn, 2013.","short":"H. Riebler, Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs, Universität Paderborn, 2013."},"year":"2013","language":[{"iso":"ger"}]},{"_id":"528","citation":{"short":"H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389.","ieee":"H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search for Cold-Boot Attacks against AES,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2013, pp. 386–389, doi: 10.1109/FPT.2013.6718394.","chicago":"Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–89. IEEE, 2013. https://doi.org/10.1109/FPT.2013.6718394.","ama":"Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot Attacks against AES. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2013:386-389. doi:10.1109/FPT.2013.6718394","apa":"Riebler, H., Kenter, T., Sorge, C., & Plessl, C. (2013). FPGA-accelerated Key Search for Cold-Boot Attacks against AES. Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–389. https://doi.org/10.1109/FPT.2013.6718394","mla":"Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–89, doi:10.1109/FPT.2013.6718394.","bibtex":"@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated Key Search for Cold-Boot Attacks against AES}, DOI={10.1109/FPT.2013.6718394}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge, Christoph and Plessl, Christian}, year={2013}, pages={386–389} }"},"type":"conference","year":"2013","page":"386-389","abstract":[{"lang":"eng","text":"Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES."}],"user_id":"15278","ddc":["040"],"file":[{"success":1,"relation":"main_file","date_updated":"2018-03-15T10:36:08Z","content_type":"application/pdf","creator":"florida","file_id":"1294","file_size":822680,"access_level":"closed","date_created":"2018-03-15T10:36:08Z","file_name":"528-plessl13_fpt.pdf"}],"publisher":"IEEE","author":[{"id":"8961","last_name":"Riebler","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"full_name":"Sorge, Christoph","first_name":"Christoph","last_name":"Sorge"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","keyword":["coldboot"],"file_date_updated":"2018-03-15T10:36:08Z","publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:35Z","date_updated":"2023-09-26T13:37:35Z","doi":"10.1109/FPT.2013.6718394","language":[{"iso":"eng"}],"title":"FPGA-accelerated Key Search for Cold-Boot Attacks against AES","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Subproject C1","_id":"13"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}]},{"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"}],"department":[{"_id":"63"},{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"On-The-Fly Computing: A Novel Paradigm for Individualized IT Services","language":[{"iso":"eng"}],"doi":"10.1109/ISORC.2013.6913232","date_updated":"2023-09-26T13:38:20Z","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:30Z","publisher":"IEEE","quality_controlled":"1","author":[{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"first_name":"Peter","full_name":"Kling, Peter","last_name":"Kling"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"full_name":"Meyer auf der Heide, Friedhelm","first_name":"Friedhelm","id":"15523","last_name":"Meyer auf der Heide"}],"file_date_updated":"2018-03-15T13:38:56Z","publication":"Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)","file":[{"file_size":1040834,"creator":"florida","file_id":"1308","content_type":"application/pdf","date_updated":"2018-03-15T13:38:56Z","relation":"main_file","success":1,"file_name":"505-Plessl13_seus.pdf","date_created":"2018-03-15T13:38:56Z","access_level":"closed"}],"ddc":["040"],"user_id":"15278","abstract":[{"text":"In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas.","lang":"eng"}],"year":"2013","citation":{"bibtex":"@inproceedings{Happe_Kling_Plessl_Platzner_Meyer auf der Heide_2013, title={On-The-Fly Computing: A Novel Paradigm for Individualized IT Services}, DOI={10.1109/ISORC.2013.6913232}, booktitle={Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)}, publisher={IEEE}, author={Happe, Markus and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide, Friedhelm}, year={2013} }","mla":"Happe, Markus, et al. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013, doi:10.1109/ISORC.2013.6913232.","chicago":"Happe, Markus, Peter Kling, Christian Plessl, Marco Platzner, and Friedhelm Meyer auf der Heide. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” In Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE, 2013. https://doi.org/10.1109/ISORC.2013.6913232.","apa":"Happe, M., Kling, P., Plessl, C., Platzner, M., & Meyer auf der Heide, F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). https://doi.org/10.1109/ISORC.2013.6913232","ama":"Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. In: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE; 2013. doi:10.1109/ISORC.2013.6913232","ieee":"M. Happe, P. Kling, C. Plessl, M. Platzner, and F. Meyer auf der Heide, “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services,” 2013, doi: 10.1109/ISORC.2013.6913232.","short":"M. Happe, P. Kling, C. Plessl, M. Platzner, F. Meyer auf der Heide, in: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013."},"type":"conference","_id":"505"},{"publication_identifier":{"isbn":["978-0-7695-4979-8"]},"status":"public","project":[{"_id":"30","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A"}],"date_created":"2018-03-26T14:51:05Z","quality_controlled":"1","publisher":"IEEE Computer Society","author":[{"full_name":"Suess, Tim","first_name":"Tim","last_name":"Suess"},{"full_name":"Schoenrock, Andrew","first_name":"Andrew","last_name":"Schoenrock"},{"last_name":"Meisner","first_name":"Sebastian","full_name":"Meisner, Sebastian"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"},{"_id":"63"}],"publication":"Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)","title":"Parallel Macro Pipelining on the Intel SCC Many-Core Computer","user_id":"15278","place":"Washington, DC, USA","year":"2013","citation":{"mla":"Suess, Tim, et al. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, 2013, pp. 64–73, doi:10.1109/IPDPSW.2013.136.","bibtex":"@inproceedings{Suess_Schoenrock_Meisner_Plessl_2013, place={Washington, DC, USA}, title={Parallel Macro Pipelining on the Intel SCC Many-Core Computer}, DOI={10.1109/IPDPSW.2013.136}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)}, publisher={IEEE Computer Society}, author={Suess, Tim and Schoenrock, Andrew and Meisner, Sebastian and Plessl, Christian}, year={2013}, pages={64–73} }","ama":"Suess T, Schoenrock A, Meisner S, Plessl C. Parallel Macro Pipelining on the Intel SCC Many-Core Computer. In: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE Computer Society; 2013:64-73. doi:10.1109/IPDPSW.2013.136","apa":"Suess, T., Schoenrock, A., Meisner, S., & Plessl, C. (2013). Parallel Macro Pipelining on the Intel SCC Many-Core Computer. Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. https://doi.org/10.1109/IPDPSW.2013.136","chicago":"Suess, Tim, Andrew Schoenrock, Sebastian Meisner, and Christian Plessl. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. Washington, DC, USA: IEEE Computer Society, 2013. https://doi.org/10.1109/IPDPSW.2013.136.","ieee":"T. Suess, A. Schoenrock, S. Meisner, and C. Plessl, “Parallel Macro Pipelining on the Intel SCC Many-Core Computer,” in Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 2013, pp. 64–73, doi: 10.1109/IPDPSW.2013.136.","short":"T. Suess, A. Schoenrock, S. Meisner, C. Plessl, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, Washington, DC, USA, 2013, pp. 64–73."},"type":"conference","page":"64-73","language":[{"iso":"eng"}],"doi":"10.1109/IPDPSW.2013.136","date_updated":"2023-09-26T13:38:05Z","_id":"1787"},{"year":"2012","type":"conference","citation":{"ieee":"R. Grunzke et al., “A Data Driven Science Gateway for Computational Workflows,” in Proc. UNICORE Summit, 2012.","short":"R. Grunzke, G. Birkenheuer, D. Blunk, S. Breuers, A. Brinkmann, S. Gesing, S. Herres-Pawlis, O. Kohlbacher, J. Krüger, M. Kruse, R. Müller-Pfefferkorn, P. Schäfer, B. Schuller, T. Steinke, A. Zink, in: Proc. UNICORE Summit, 2012.","bibtex":"@inproceedings{Grunzke_Birkenheuer_Blunk_Breuers_Brinkmann_Gesing_Herres-Pawlis_Kohlbacher_Krüger_Kruse_et al._2012, title={A Data Driven Science Gateway for Computational Workflows}, booktitle={Proc. UNICORE Summit}, author={Grunzke, Richard and Birkenheuer, Georg and Blunk, Dirk and Breuers, Sebastian and Brinkmann, André and Gesing, Sandra and Herres-Pawlis, Sonja and Kohlbacher, Oliver and Krüger, Jens and Kruse, Martin and et al.}, year={2012} }","mla":"Grunzke, Richard, et al. “A Data Driven Science Gateway for Computational Workflows.” Proc. UNICORE Summit, 2012.","chicago":"Grunzke, Richard, Georg Birkenheuer, Dirk Blunk, Sebastian Breuers, André Brinkmann, Sandra Gesing, Sonja Herres-Pawlis, et al. “A Data Driven Science Gateway for Computational Workflows.” In Proc. UNICORE Summit, 2012.","ama":"Grunzke R, Birkenheuer G, Blunk D, et al. A Data Driven Science Gateway for Computational Workflows. In: Proc. UNICORE Summit. ; 2012.","apa":"Grunzke, R., Birkenheuer, G., Blunk, D., Breuers, S., Brinkmann, A., Gesing, S., … Zink, A. (2012). A Data Driven Science Gateway for Computational Workflows. In Proc. UNICORE Summit."},"_id":"2107","date_updated":"2022-01-06T06:54:44Z","author":[{"last_name":"Grunzke","first_name":"Richard","full_name":"Grunzke, Richard"},{"full_name":"Birkenheuer, Georg","first_name":"Georg","last_name":"Birkenheuer"},{"last_name":"Blunk","full_name":"Blunk, Dirk","first_name":"Dirk"},{"full_name":"Breuers, Sebastian","first_name":"Sebastian","last_name":"Breuers"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"},{"last_name":"Gesing","first_name":"Sandra","full_name":"Gesing, Sandra"},{"last_name":"Herres-Pawlis","full_name":"Herres-Pawlis, Sonja","first_name":"Sonja"},{"last_name":"Kohlbacher","first_name":"Oliver","full_name":"Kohlbacher, Oliver"},{"last_name":"Krüger","full_name":"Krüger, Jens","first_name":"Jens"},{"first_name":"Martin","full_name":"Kruse, Martin","last_name":"Kruse"},{"first_name":"Ralph","full_name":"Müller-Pfefferkorn, Ralph","last_name":"Müller-Pfefferkorn"},{"last_name":"Schäfer","full_name":"Schäfer, Patrick","first_name":"Patrick"},{"full_name":"Schuller, Bernd","first_name":"Bernd","last_name":"Schuller"},{"full_name":"Steinke, Thomas","first_name":"Thomas","last_name":"Steinke"},{"full_name":"Zink, Andreas","first_name":"Andreas","last_name":"Zink"}],"department":[{"_id":"27"},{"_id":"518"}],"publication":"Proc. UNICORE Summit","status":"public","date_created":"2018-03-29T15:06:46Z","title":"A Data Driven Science Gateway for Computational Workflows","user_id":"24135"},{"language":[{"iso":"eng"}],"citation":{"chicago":"Plessl, Christian, Marco Platzner, Andreas Agne, Markus Happe, and Enno Lübbers. Programming Models for Reconfigurable Heterogeneous Multi-Cores. Awareness Magazine, 2012.","apa":"Plessl, C., Platzner, M., Agne, A., Happe, M., & Lübbers, E. (2012). Programming models for reconfigurable heterogeneous multi-cores. Awareness Magazine.","ama":"Plessl C, Platzner M, Agne A, Happe M, Lübbers E. Programming Models for Reconfigurable Heterogeneous Multi-Cores. Awareness Magazine; 2012.","bibtex":"@book{Plessl_Platzner_Agne_Happe_Lübbers_2012, title={Programming models for reconfigurable heterogeneous multi-cores}, publisher={Awareness Magazine}, author={Plessl, Christian and Platzner, Marco and Agne, Andreas and Happe, Markus and Lübbers, Enno}, year={2012} }","mla":"Plessl, Christian, et al. Programming Models for Reconfigurable Heterogeneous Multi-Cores. Awareness Magazine, 2012.","short":"C. Plessl, M. Platzner, A. Agne, M. Happe, E. Lübbers, Programming Models for Reconfigurable Heterogeneous Multi-Cores, Awareness Magazine, 2012.","ieee":"C. Plessl, M. Platzner, A. Agne, M. Happe, and E. Lübbers, Programming models for reconfigurable heterogeneous multi-cores. Awareness Magazine, 2012."},"type":"misc","year":"2012","_id":"587","date_updated":"2022-01-06T07:02:44Z","file":[{"content_type":"application/pdf","date_updated":"2018-03-15T08:37:02Z","relation":"main_file","success":1,"file_size":353057,"file_id":"1260","creator":"florida","access_level":"closed","date_created":"2018-03-15T08:37:02Z","file_name":"587-2012_plessl_awareness_magazine.pdf"}],"author":[{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"last_name":"Lübbers","full_name":"Lübbers, Enno","first_name":"Enno"}],"publisher":"Awareness Magazine","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"file_date_updated":"2018-03-15T08:37:02Z","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:46Z","project":[{"_id":"1","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"}],"user_id":"398","ddc":["040"],"title":"Programming models for reconfigurable heterogeneous multi-cores"},{"title":"Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?","department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"doi":"10.1109/FPL.2012.6339370","date_updated":"2023-09-26T13:39:13Z","language":[{"iso":"eng"}],"user_id":"15278","ddc":["000"],"abstract":[{"lang":"eng","text":"Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator.\r\nIn this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort\r\ncan actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like\r\nprogramming environment exists. As case study we use an application from computational nanophotonics. Our results\r\nshow that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view."}],"status":"public","has_accepted_license":"1","date_created":"2018-03-29T15:04:25Z","file":[{"access_level":"closed","date_created":"2019-02-13T09:04:46Z","file_name":"2012-11 Meyer,Schumacher,Plessl,Förstner_Convey vector personalities-FPGA acceleratin with an openmp-like programming effort.pdf","date_updated":"2019-02-13T09:04:46Z","content_type":"application/pdf","relation":"main_file","success":1,"file_size":2148787,"file_id":"7638","creator":"fossie"}],"publisher":"IEEE","quality_controlled":"1","author":[{"last_name":"Meyer","first_name":"Björn","full_name":"Meyer, Björn"},{"first_name":"Jörn","full_name":"Schumacher, Jörn","last_name":"Schumacher"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"id":"158","last_name":"Förstner","full_name":"Förstner, Jens","orcid":"0000-0001-7059-9862","first_name":"Jens"}],"file_date_updated":"2019-02-13T09:04:46Z","keyword":["funding-upb-forschungspreis","funding-maxup","tet_topic_hpc"],"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","_id":"2106","conference":{"name":"22nd International Conference on Field Programmable Logic and Applicaitons (FPL)"},"type":"conference","citation":{"chicago":"Meyer, Björn, Jörn Schumacher, Christian Plessl, and Jens Förstner. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–96. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370.","ama":"Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2012:189-196. doi:10.1109/FPL.2012.6339370","apa":"Meyer, B., Schumacher, J., Plessl, C., & Förstner, J. (2012). Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–196. https://doi.org/10.1109/FPL.2012.6339370","bibtex":"@inproceedings{Meyer_Schumacher_Plessl_Förstner_2012, title={Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?}, DOI={10.1109/FPL.2012.6339370}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Meyer, Björn and Schumacher, Jörn and Plessl, Christian and Förstner, Jens}, year={2012}, pages={189–196} }","mla":"Meyer, Björn, et al. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–96, doi:10.1109/FPL.2012.6339370.","short":"B. Meyer, J. Schumacher, C. Plessl, J. Förstner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–196.","ieee":"B. Meyer, J. Schumacher, C. Plessl, and J. Förstner, “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2012, pp. 189–196, doi: 10.1109/FPL.2012.6339370."},"year":"2012","page":"189-196"},{"publication_identifier":{"issn":["0141-9331"]},"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators","language":[{"iso":"eng"}],"doi":"10.1016/j.micpro.2011.04.002","date_updated":"2023-09-26T13:39:30Z","volume":36,"date_created":"2018-03-29T15:12:38Z","status":"public","keyword":["funding-altera"],"publication":"Microprocessors and Microsystems","author":[{"full_name":"Schumacher, Tobias","first_name":"Tobias","last_name":"Schumacher"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"quality_controlled":"1","user_id":"15278","page":"110-126","year":"2012","type":"journal_article","citation":{"mla":"Schumacher, Tobias, et al. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” Microprocessors and Microsystems, vol. 36, no. 2, 2012, pp. 110–26, doi:10.1016/j.micpro.2011.04.002.","bibtex":"@article{Schumacher_Plessl_Platzner_2012, title={IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators}, volume={36}, DOI={10.1016/j.micpro.2011.04.002}, number={2}, journal={Microprocessors and Microsystems}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2012}, pages={110–126} }","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2012). IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. Microprocessors and Microsystems, 36(2), 110–126. https://doi.org/10.1016/j.micpro.2011.04.002","ama":"Schumacher T, Plessl C, Platzner M. IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. Microprocessors and Microsystems. 2012;36(2):110-126. doi:10.1016/j.micpro.2011.04.002","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” Microprocessors and Microsystems 36, no. 2 (2012): 110–26. https://doi.org/10.1016/j.micpro.2011.04.002.","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators,” Microprocessors and Microsystems, vol. 36, no. 2, pp. 110–126, 2012, doi: 10.1016/j.micpro.2011.04.002.","short":"T. Schumacher, C. Plessl, M. Platzner, Microprocessors and Microsystems 36 (2012) 110–126."},"issue":"2","_id":"2108","intvolume":" 36"},{"has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:51Z","quality_controlled":"1","author":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"first_name":"Hendrik","full_name":"Hangmann, Hendrik","last_name":"Hangmann"},{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"publisher":"IEEE","file_date_updated":"2018-03-15T06:48:32Z","publication":"Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)","file":[{"file_name":"615-ReConFig12_01.pdf","date_created":"2018-03-15T06:48:32Z","access_level":"closed","file_id":"1246","creator":"florida","file_size":730144,"relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-03-15T06:48:32Z"}],"ddc":["040"],"user_id":"15278","abstract":[{"lang":"eng","text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices."}],"citation":{"ieee":"M. Happe, H. Hangmann, A. Agne, and C. Plessl, “Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators,” in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416745.","short":"M. Happe, H. Hangmann, A. Agne, C. Plessl, in: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","bibtex":"@inproceedings{Happe_Hangmann_Agne_Plessl_2012, title={Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}, DOI={10.1109/ReConFig.2012.6416745}, booktitle={Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}, year={2012}, pages={1–8} }","mla":"Happe, Markus, et al. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416745.","chicago":"Happe, Markus, Hendrik Hangmann, Andreas Agne, and Christian Plessl. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416745.","apa":"Happe, M., Hangmann, H., Agne, A., & Plessl, C. (2012). Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416745","ama":"Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416745"},"year":"2012","type":"conference","page":"1-8","_id":"615","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators","language":[{"iso":"eng"}],"doi":"10.1109/ReConFig.2012.6416745","date_updated":"2023-09-26T13:42:26Z"},{"citation":{"apa":"Kenter, T., Plessl, C., & Schmitz, H. (2012). Pragma based parallelization - Trading hardware efficiency for ease of use? Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416773","ama":"Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416773","chicago":"Kenter, Tobias, Christian Plessl, and Henning Schmitz. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416773.","mla":"Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416773.","bibtex":"@inproceedings{Kenter_Plessl_Schmitz_2012, title={Pragma based parallelization - Trading hardware efficiency for ease of use?}, DOI={10.1109/ReConFig.2012.6416773}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Plessl, Christian and Schmitz, Henning}, year={2012}, pages={1–8} }","short":"T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","ieee":"T. Kenter, C. Plessl, and H. Schmitz, “Pragma based parallelization - Trading hardware efficiency for ease of use?,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416773."},"type":"conference","year":"2012","page":"1-8","_id":"591","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:47Z","publisher":"IEEE","quality_controlled":"1","author":[{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"last_name":"Schmitz","full_name":"Schmitz, Henning","first_name":"Henning"}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-15T08:33:18Z","file":[{"content_type":"application/pdf","date_updated":"2018-03-15T08:33:18Z","success":1,"relation":"main_file","file_size":371235,"creator":"florida","file_id":"1257","access_level":"closed","file_name":"591-ReConFig2012Kenter_Schmitz_Plessl.pdf","date_created":"2018-03-15T08:33:18Z"}],"ddc":["040"],"user_id":"15278","abstract":[{"text":"One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort.","lang":"eng"}],"language":[{"iso":"eng"}],"doi":"10.1109/ReConFig.2012.6416773","date_updated":"2023-09-26T13:41:08Z","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Pragma based parallelization - Trading hardware efficiency for ease of use?"},{"date_created":"2017-10-17T12:42:50Z","status":"public","has_accepted_license":"1","file":[{"content_type":"application/pdf","date_updated":"2018-03-15T08:14:17Z","relation":"main_file","success":1,"file_size":146789,"file_id":"1249","creator":"florida","access_level":"closed","date_created":"2018-03-15T08:14:17Z","file_name":"609-happe12_fpl_awareness.pdf"}],"file_date_updated":"2018-03-15T08:14:17Z","publication":"Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)","author":[{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"quality_controlled":"1","user_id":"15278","ddc":["040"],"abstract":[{"text":"Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method.","lang":"eng"}],"page":"8-9","type":"conference","citation":{"short":"M. Happe, A. Agne, C. Plessl, M. Platzner, in: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","ieee":"M. Happe, A. Agne, C. Plessl, and M. Platzner, “Hardware/Software Platform for Self-aware Compute Nodes,” in Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","apa":"Happe, M., Agne, A., Plessl, C., & Platzner, M. (2012). Hardware/Software Platform for Self-aware Compute Nodes. Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9.","ama":"Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS). ; 2012:8-9.","chicago":"Happe, Markus, Andreas Agne, Christian Plessl, and Marco Platzner. “Hardware/Software Platform for Self-Aware Compute Nodes.” In Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9, 2012.","mla":"Happe, Markus, et al. “Hardware/Software Platform for Self-Aware Compute Nodes.” Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","bibtex":"@inproceedings{Happe_Agne_Plessl_Platzner_2012, title={Hardware/Software Platform for Self-aware Compute Nodes}, booktitle={Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}, author={Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}, year={2012}, pages={8–9} }"},"year":"2012","_id":"609","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Hardware/Software Platform for Self-aware Compute Nodes","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:41:36Z"},{"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Turning control flow graphs into function calls: Code generation for heterogeneous architectures","language":[{"iso":"eng"}],"doi":"10.1109/HPCSim.2012.6266973","date_updated":"2023-09-26T13:42:54Z","date_created":"2017-10-17T12:42:42Z","has_accepted_license":"1","status":"public","publication":"Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)","file_date_updated":"2018-03-15T10:20:24Z","author":[{"first_name":"Pablo","full_name":"Barrio, Pablo","last_name":"Barrio"},{"first_name":"Carlos","full_name":"Carreras, Carlos","last_name":"Carreras"},{"last_name":"Sierra","first_name":"Roberto","full_name":"Sierra, Roberto"},{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","publisher":"IEEE","file":[{"content_type":"application/pdf","date_updated":"2018-03-15T10:20:24Z","relation":"main_file","success":1,"file_size":288508,"file_id":"1275","creator":"florida","access_level":"closed","date_created":"2018-03-15T10:20:24Z","file_name":"567-ba-ca-12a.pdf"}],"ddc":["040"],"user_id":"15278","abstract":[{"lang":"eng","text":"Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided."}],"page":"559-565","year":"2012","type":"conference","citation":{"ieee":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl, “Turning control flow graphs into function calls: Code generation for heterogeneous architectures,” in Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 2012, pp. 559–565, doi: 10.1109/HPCSim.2012.6266973.","short":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. Plessl, in: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–565.","mla":"Barrio, Pablo, et al. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–65, doi:10.1109/HPCSim.2012.6266973.","bibtex":"@inproceedings{Barrio_Carreras_Sierra_Kenter_Plessl_2012, title={Turning control flow graphs into function calls: Code generation for heterogeneous architectures}, DOI={10.1109/HPCSim.2012.6266973}, booktitle={Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}, publisher={IEEE}, author={Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}, year={2012}, pages={559–565} }","chicago":"Barrio, Pablo, Carlos Carreras, Roberto Sierra, Tobias Kenter, and Christian Plessl. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” In Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–65. IEEE, 2012. https://doi.org/10.1109/HPCSim.2012.6266973.","ama":"Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS). IEEE; 2012:559-565. doi:10.1109/HPCSim.2012.6266973","apa":"Barrio, P., Carreras, C., Sierra, R., Kenter, T., & Plessl, C. (2012). Turning control flow graphs into function calls: Code generation for heterogeneous architectures. Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–565. https://doi.org/10.1109/HPCSim.2012.6266973"},"_id":"567"},{"_id":"612","page":"559-562","citation":{"short":"C. Rüthing, M. Happe, A. Agne, C. Plessl, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–562.","ieee":"C. Rüthing, M. Happe, A. Agne, and C. Plessl, “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 2012, pp. 559–562, doi: 10.1109/FPL.2012.6339370.","apa":"Rüthing, C., Happe, M., Agne, A., & Plessl, C. (2012). Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 559–562. https://doi.org/10.1109/FPL.2012.6339370","ama":"Rüthing C, Happe M, Agne A, Plessl C. Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2012:559-562. doi:10.1109/FPL.2012.6339370","chicago":"Rüthing, Christoph, Markus Happe, Andreas Agne, and Christian Plessl. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 559–62. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370.","mla":"Rüthing, Christoph, et al. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–62, doi:10.1109/FPL.2012.6339370.","bibtex":"@inproceedings{Rüthing_Happe_Agne_Plessl_2012, title={Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs}, DOI={10.1109/FPL.2012.6339370}, booktitle={Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Rüthing, Christoph and Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2012}, pages={559–562} }"},"type":"conference","year":"2012","abstract":[{"lang":"eng","text":"While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA."}],"user_id":"15278","ddc":["040"],"file":[{"access_level":"closed","file_name":"612-ruething_fpl12.pdf","date_created":"2018-03-15T06:49:03Z","date_updated":"2018-03-15T06:49:03Z","content_type":"application/pdf","relation":"main_file","success":1,"file_size":202923,"creator":"florida","file_id":"1247"}],"publication":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)","file_date_updated":"2018-03-15T06:49:03Z","quality_controlled":"1","author":[{"last_name":"Rüthing","first_name":"Christoph","full_name":"Rüthing, Christoph"},{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"publisher":"IEEE","date_created":"2017-10-17T12:42:51Z","status":"public","has_accepted_license":"1","date_updated":"2023-09-26T13:42:03Z","doi":"10.1109/FPL.2012.6339370","language":[{"iso":"eng"}],"title":"Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}]},{"title":"Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux","user_id":"15278","author":[{"last_name":"Beisel","full_name":"Beisel, Tobias","first_name":"Tobias"},{"last_name":"Wiersema","id":"3118","first_name":"Tobias","full_name":"Wiersema, Tobias"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"}],"quality_controlled":"1","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"keyword":["funding-enhance"],"publication":"Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)","status":"public","date_created":"2018-04-03T09:18:33Z","project":[{"_id":"30","grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models"}],"date_updated":"2023-09-26T13:40:17Z","_id":"2180","type":"conference","citation":{"mla":"Beisel, Tobias, et al. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2012, title={Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux}, booktitle={Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2012} }","chicago":"Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” In Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","apa":"Beisel, T., Wiersema, T., Plessl, C., & Brinkmann, A. (2012). Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS).","ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. In: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS). ; 2012.","ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux,” 2012.","short":"T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012."},"year":"2012","language":[{"iso":"eng"}]},{"publication":"Int. Journal of Reconfigurable Computing (IJRC)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publisher":"Hindawi Publishing Corp.","author":[{"first_name":"Mariusz","full_name":"Grad, Mariusz","last_name":"Grad"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"quality_controlled":"1","date_created":"2018-04-03T09:13:22Z","status":"public","title":"On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors","user_id":"15278","year":"2012","citation":{"short":"M. Grad, C. Plessl, Int. Journal of Reconfigurable Computing (IJRC) (2012).","ieee":"M. Grad and C. Plessl, “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors,” Int. Journal of Reconfigurable Computing (IJRC), 2012, doi: 10.1155/2012/418315.","apa":"Grad, M., & Plessl, C. (2012). On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. Int. Journal of Reconfigurable Computing (IJRC). https://doi.org/10.1155/2012/418315","ama":"Grad M, Plessl C. On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. Int Journal of Reconfigurable Computing (IJRC). Published online 2012. doi:10.1155/2012/418315","chicago":"Grad, Mariusz, and Christian Plessl. “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.” Int. Journal of Reconfigurable Computing (IJRC), 2012. https://doi.org/10.1155/2012/418315.","bibtex":"@article{Grad_Plessl_2012, title={On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors}, DOI={10.1155/2012/418315}, journal={Int. Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi Publishing Corp.}, author={Grad, Mariusz and Plessl, Christian}, year={2012} }","mla":"Grad, Mariusz, and Christian Plessl. “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.” Int. Journal of Reconfigurable Computing (IJRC), Hindawi Publishing Corp., 2012, doi:10.1155/2012/418315."},"type":"journal_article","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:39:48Z","_id":"2177","doi":"10.1155/2012/418315"},{"date_updated":"2022-01-06T06:55:19Z","_id":"2191","type":"conference","year":"2011","citation":{"short":"T. Kenter, C. Plessl, M. Platzner, M. Kauschke, in: Intel European Research and Innovation Conference, 2011.","ieee":"T. Kenter, C. Plessl, M. Platzner, and M. Kauschke, “Estimation and Partitioning for CPU-Accelerator Architectures,” in Intel European Research and Innovation Conference, 2011.","chicago":"Kenter, Tobias, Christian Plessl, Marco Platzner, and Michael Kauschke. “Estimation and Partitioning for CPU-Accelerator Architectures.” In Intel European Research and Innovation Conference, 2011.","ama":"Kenter T, Plessl C, Platzner M, Kauschke M. Estimation and Partitioning for CPU-Accelerator Architectures. In: Intel European Research and Innovation Conference. ; 2011.","apa":"Kenter, T., Plessl, C., Platzner, M., & Kauschke, M. (2011). Estimation and Partitioning for CPU-Accelerator Architectures. In Intel European Research and Innovation Conference.","mla":"Kenter, Tobias, et al. “Estimation and Partitioning for CPU-Accelerator Architectures.” Intel European Research and Innovation Conference, 2011.","bibtex":"@inproceedings{Kenter_Plessl_Platzner_Kauschke_2011, title={Estimation and Partitioning for CPU-Accelerator Architectures}, booktitle={Intel European Research and Innovation Conference}, author={Kenter, Tobias and Plessl, Christian and Platzner, Marco and Kauschke, Michael}, year={2011} }"},"title":"Estimation and Partitioning for CPU-Accelerator Architectures","user_id":"24135","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"last_name":"Kauschke","full_name":"Kauschke, Michael","first_name":"Michael"}],"keyword":["funding-intel"],"publication":"Intel European Research and Innovation Conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"status":"public","date_created":"2018-04-03T14:34:57Z"},{"place":"Hershey, PA, USA","title":"Hardware Virtualization on Dynamically Reconfigurable Embedded Processors","user_id":"24135","publication":"Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"author":[{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"IGI Global","publication_identifier":{"isbn":["978-1-60960-086-0"]},"editor":[{"last_name":"Khalgui","full_name":"Khalgui, Mohamed","first_name":"Mohamed"},{"last_name":"Hanisch","first_name":"Hans-Michael","full_name":"Hanisch, Hans-Michael"}],"project":[{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"date_created":"2018-04-03T15:11:16Z","status":"public","_id":"2202","date_updated":"2022-01-06T06:55:22Z","doi":"10.4018/978-1-60960-086-0","type":"book_chapter","year":"2011","citation":{"short":"C. Plessl, M. Platzner, in: M. Khalgui, H.-M. Hanisch (Eds.), Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility, IGI Global, Hershey, PA, USA, 2011.","ieee":"C. Plessl and M. Platzner, “Hardware Virtualization on Dynamically Reconfigurable Embedded Processors,” in Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility, M. Khalgui and H.-M. Hanisch, Eds. Hershey, PA, USA: IGI Global, 2011.","ama":"Plessl C, Platzner M. Hardware Virtualization on Dynamically Reconfigurable Embedded Processors. In: Khalgui M, Hanisch H-M, eds. Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility. Hershey, PA, USA: IGI Global; 2011. doi:10.4018/978-1-60960-086-0","apa":"Plessl, C., & Platzner, M. (2011). Hardware Virtualization on Dynamically Reconfigurable Embedded Processors. In M. Khalgui & H.-M. Hanisch (Eds.), Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility. Hershey, PA, USA: IGI Global. https://doi.org/10.4018/978-1-60960-086-0","chicago":"Plessl, Christian, and Marco Platzner. “Hardware Virtualization on Dynamically Reconfigurable Embedded Processors.” In Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility, edited by Mohamed Khalgui and Hans-Michael Hanisch. Hershey, PA, USA: IGI Global, 2011. https://doi.org/10.4018/978-1-60960-086-0.","mla":"Plessl, Christian, and Marco Platzner. “Hardware Virtualization on Dynamically Reconfigurable Embedded Processors.” Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility, edited by Mohamed Khalgui and Hans-Michael Hanisch, IGI Global, 2011, doi:10.4018/978-1-60960-086-0.","bibtex":"@inbook{Plessl_Platzner_2011, place={Hershey, PA, USA}, title={Hardware Virtualization on Dynamically Reconfigurable Embedded Processors}, DOI={10.4018/978-1-60960-086-0}, booktitle={Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility}, publisher={IGI Global}, author={Plessl, Christian and Platzner, Marco}, editor={Khalgui, Mohamed and Hanisch, Hans-MichaelEditors}, year={2011} }"}},{"date_updated":"2022-01-06T06:50:50Z","_id":"10737","series_title":"Natural Computing Series","language":[{"iso":"eng"}],"type":"book_chapter","citation":{"bibtex":"@inbook{Sekanina_Walker_Kaufmann_Plessl_Platzner_2011, series={Natural Computing Series}, title={Evolution of Electronic Circuits}, booktitle={Cartesian Genetic Programming}, publisher={Springer Berlin Heidelberg}, author={Sekanina, Lukas and Walker, James Alfred and Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2011}, pages={125–179}, collection={Natural Computing Series} }","mla":"Sekanina, Lukas, et al. “Evolution of Electronic Circuits.” Cartesian Genetic Programming, Springer Berlin Heidelberg, 2011, pp. 125–79.","chicago":"Sekanina, Lukas, James Alfred Walker, Paul Kaufmann, Christian Plessl, and Marco Platzner. “Evolution of Electronic Circuits.” In Cartesian Genetic Programming, 125–79. Natural Computing Series. Springer Berlin Heidelberg, 2011.","apa":"Sekanina, L., Walker, J. A., Kaufmann, P., Plessl, C., & Platzner, M. (2011). Evolution of Electronic Circuits. In Cartesian Genetic Programming (pp. 125–179). Springer Berlin Heidelberg.","ama":"Sekanina L, Walker JA, Kaufmann P, Plessl C, Platzner M. Evolution of Electronic Circuits. In: Cartesian Genetic Programming. Natural Computing Series. Springer Berlin Heidelberg; 2011:125-179.","ieee":"L. Sekanina, J. A. Walker, P. Kaufmann, C. Plessl, and M. Platzner, “Evolution of Electronic Circuits,” in Cartesian Genetic Programming, Springer Berlin Heidelberg, 2011, pp. 125–179.","short":"L. Sekanina, J.A. Walker, P. Kaufmann, C. Plessl, M. Platzner, in: Cartesian Genetic Programming, Springer Berlin Heidelberg, 2011, pp. 125–179."},"year":"2011","page":"125-179","user_id":"3118","title":"Evolution of Electronic Circuits","publisher":"Springer Berlin Heidelberg","author":[{"full_name":"Sekanina, Lukas","first_name":"Lukas","last_name":"Sekanina"},{"full_name":"Walker, James Alfred","first_name":"James Alfred","last_name":"Walker"},{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publication":"Cartesian Genetic Programming","department":[{"_id":"78"},{"_id":"518"}],"status":"public","date_created":"2019-07-10T11:59:35Z"},{"page":"60-63","year":"2011","type":"conference","citation":{"ieee":"B. Meyer, C. Plessl, and J. Förstner, “Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend,” in Symp. on Application Accelerators in High Performance Computing (SAAHPC), 2011, pp. 60–63, doi: 10.1109/SAAHPC.2011.12.","short":"B. Meyer, C. Plessl, J. Förstner, in: Symp. on Application Accelerators in High Performance Computing (SAAHPC), IEEE Computer Society, 2011, pp. 60–63.","bibtex":"@inproceedings{Meyer_Plessl_Förstner_2011, title={Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend}, DOI={10.1109/SAAHPC.2011.12}, booktitle={Symp. on Application Accelerators in High Performance Computing (SAAHPC)}, publisher={IEEE Computer Society}, author={Meyer, Björn and Plessl, Christian and Förstner, Jens}, year={2011}, pages={60–63} }","mla":"Meyer, Björn, et al. “Transformation of Scientific Algorithms to Parallel Computing Code: Subdomain Support in a MPI-Multi-GPU Backend.” Symp. on Application Accelerators in High Performance Computing (SAAHPC), IEEE Computer Society, 2011, pp. 60–63, doi:10.1109/SAAHPC.2011.12.","ama":"Meyer B, Plessl C, Förstner J. Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. In: Symp. on Application Accelerators in High Performance Computing (SAAHPC). IEEE Computer Society; 2011:60-63. doi:10.1109/SAAHPC.2011.12","apa":"Meyer, B., Plessl, C., & Förstner, J. (2011). Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. Symp. on Application Accelerators in High Performance Computing (SAAHPC), 60–63. https://doi.org/10.1109/SAAHPC.2011.12","chicago":"Meyer, Björn, Christian Plessl, and Jens Förstner. “Transformation of Scientific Algorithms to Parallel Computing Code: Subdomain Support in a MPI-Multi-GPU Backend.” In Symp. on Application Accelerators in High Performance Computing (SAAHPC), 60–63. IEEE Computer Society, 2011. https://doi.org/10.1109/SAAHPC.2011.12."},"language":[{"iso":"eng"}],"doi":"10.1109/SAAHPC.2011.12","date_updated":"2023-09-26T13:44:11Z","_id":"2194","project":[{"grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30"}],"date_created":"2018-04-03T14:55:57Z","status":"public","keyword":["tet_topic_hpc"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"publication":"Symp. on Application Accelerators in High Performance Computing (SAAHPC)","quality_controlled":"1","author":[{"first_name":"Björn","full_name":"Meyer, Björn","last_name":"Meyer"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"id":"158","last_name":"Förstner","full_name":"Förstner, Jens","orcid":"0000-0001-7059-9862","first_name":"Jens"}],"publisher":"IEEE Computer Society","title":"Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend","user_id":"15278"},{"user_id":"15278","title":"Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler","status":"public","project":[{"_id":"30","grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models"}],"date_created":"2018-04-03T14:37:14Z","quality_controlled":"1","author":[{"first_name":"Tobias","full_name":"Beisel, Tobias","last_name":"Beisel"},{"full_name":"Wiersema, Tobias","first_name":"Tobias","id":"3118","last_name":"Wiersema"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"}],"publisher":"IEEE Computer Society","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)","doi":"10.1109/ASAP.2011.6043273","_id":"2193","date_updated":"2023-09-26T13:43:48Z","language":[{"iso":"eng"}],"type":"conference","citation":{"ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler,” in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2011, pp. 223–226, doi: 10.1109/ASAP.2011.6043273.","short":"T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–226.","mla":"Beisel, Tobias, et al. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–26, doi:10.1109/ASAP.2011.6043273.","bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2011, title={Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler}, DOI={10.1109/ASAP.2011.6043273}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2011}, pages={223–226} }","chicago":"Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 223–26. IEEE Computer Society, 2011. https://doi.org/10.1109/ASAP.2011.6043273.","apa":"Beisel, T., Wiersema, T., Plessl, C., & Brinkmann, A. (2011). Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 223–226. https://doi.org/10.1109/ASAP.2011.6043273","ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2011:223-226. doi:10.1109/ASAP.2011.6043273"},"year":"2011","page":"223-226"}]