[{"abstract":[{"lang":"eng","text":"In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time."}],"ddc":["040"],"user_id":"15278","publisher":"IEEE","quality_controlled":"1","author":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"publication":"Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-14T13:49:39Z","file":[{"relation":"main_file","success":1,"date_updated":"2018-03-14T13:49:39Z","content_type":"application/pdf","creator":"florida","file_id":"1220","file_size":502244,"access_level":"closed","file_name":"656-2011_happe_reconfig.pdf","date_created":"2018-03-14T13:49:39Z"}],"has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:59Z","_id":"656","year":"2011","citation":{"ieee":"M. Happe, A. Agne, and C. Plessl, “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time,” in Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2011, pp. 55–60, doi: 10.1109/ReConFig.2011.59.","short":"M. Happe, A. Agne, C. Plessl, in: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60.","mla":"Happe, Markus, et al. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60, doi:10.1109/ReConFig.2011.59.","bibtex":"@inproceedings{Happe_Agne_Plessl_2011, title={Measuring and Predicting Temperature Distributions on FPGAs at Run-Time}, DOI={10.1109/ReConFig.2011.59}, booktitle={Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2011}, pages={55–60} }","chicago":"Happe, Markus, Andreas Agne, and Christian Plessl. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” In Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60. 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Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60. https://doi.org/10.1109/ReConFig.2011.59"},"type":"conference","page":"55-60","title":"Measuring and Predicting Temperature Distributions on FPGAs at Run-Time","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"date_updated":"2023-09-26T13:46:08Z","doi":"10.1109/ReConFig.2011.59","language":[{"iso":"eng"}]},{"publication_identifier":{"isbn":["978-1-4503-0554-9"]},"status":"public","date_created":"2018-04-03T15:08:13Z","quality_controlled":"1","author":[{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"first_name":"Michael","full_name":"Kauschke, Michael","last_name":"Kauschke"}],"publisher":"ACM","keyword":["design space exploration","LLVM","partitioning","performance","estimation","funding-intel"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. 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Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010, pp. 65–72.","ieee":"T. Beisel, M. Niekamp, and C. Plessl, “Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators,” in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2010, pp. 65–72, doi: 10.1109/ASAP.2010.5540798.","ama":"Beisel T, Niekamp M, Plessl C. Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2010:65-72. doi:10.1109/ASAP.2010.5540798","apa":"Beisel, T., Niekamp, M., & Plessl, C. (2010). Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators. Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 65–72. https://doi.org/10.1109/ASAP.2010.5540798","chicago":"Beisel, Tobias, Manuel Niekamp, and Christian Plessl. “Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators.” In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 65–72. IEEE Computer Society, 2010. https://doi.org/10.1109/ASAP.2010.5540798.","mla":"Beisel, Tobias, et al. “Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators.” Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010, pp. 65–72, doi:10.1109/ASAP.2010.5540798.","bibtex":"@inproceedings{Beisel_Niekamp_Plessl_2010, title={Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators}, DOI={10.1109/ASAP.2010.5540798}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Beisel, Tobias and Niekamp, Manuel and Plessl, Christian}, year={2010}, pages={65–72} }"},"year":"2010","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:49:21Z","_id":"2226","doi":"10.1109/ASAP.2010.5540798","publication":"Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"author":[{"first_name":"Tobias","full_name":"Beisel, Tobias","last_name":"Beisel"},{"first_name":"Manuel","full_name":"Niekamp, Manuel","last_name":"Niekamp"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"publisher":"IEEE Computer Society","quality_controlled":"1","publication_identifier":{"isbn":["978-1-4244-6965-9"]},"date_created":"2018-04-05T16:39:34Z","status":"public","title":"Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators","user_id":"15278"},{"language":[{"iso":"eng"}],"page":"372-376","type":"conference","year":"2010","citation":{"short":"A. Keller, B. Plattner, E. Lübbers, M. Platzner, C. Plessl, in: Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp. 372–376.","ieee":"A. Keller, B. Plattner, E. Lübbers, M. Platzner, and C. Plessl, “Reconfigurable Nodes for Future Networks,” in Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), 2010, pp. 372–376, doi: 10.1109/GLOCOMW.2010.5700341.","apa":"Keller, A., Plattner, B., Lübbers, E., Platzner, M., & Plessl, C. (2010). Reconfigurable Nodes for Future Networks. Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), 372–376. https://doi.org/10.1109/GLOCOMW.2010.5700341","ama":"Keller A, Plattner B, Lübbers E, Platzner M, Plessl C. Reconfigurable Nodes for Future Networks. In: Proc. IEEE Globecom Workshop on Network of the Future (FutureNet). IEEE; 2010:372-376. doi:10.1109/GLOCOMW.2010.5700341","chicago":"Keller, Ariane, Bernhard Plattner, Enno Lübbers, Marco Platzner, and Christian Plessl. “Reconfigurable Nodes for Future Networks.” In Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), 372–76. IEEE, 2010. https://doi.org/10.1109/GLOCOMW.2010.5700341.","bibtex":"@inproceedings{Keller_Plattner_Lübbers_Platzner_Plessl_2010, title={Reconfigurable Nodes for Future Networks}, DOI={10.1109/GLOCOMW.2010.5700341}, booktitle={Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)}, publisher={IEEE}, author={Keller, Ariane and Plattner, Bernhard and Lübbers, Enno and Platzner, Marco and Plessl, Christian}, year={2010}, pages={372–376} }","mla":"Keller, Ariane, et al. “Reconfigurable Nodes for Future Networks.” Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp. 372–76, doi:10.1109/GLOCOMW.2010.5700341."},"_id":"2206","date_updated":"2023-09-26T13:51:00Z","doi":"10.1109/GLOCOMW.2010.5700341","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)","publisher":"IEEE","author":[{"last_name":"Keller","first_name":"Ariane","full_name":"Keller, Ariane"},{"full_name":"Plattner, Bernhard","first_name":"Bernhard","last_name":"Plattner"},{"last_name":"Lübbers","first_name":"Enno","full_name":"Lübbers, Enno"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","date_created":"2018-04-04T09:36:16Z","status":"public","publication_identifier":{"isbn":["978-1-4244-8864-3"]},"user_id":"15278","title":"Reconfigurable Nodes for Future Networks"},{"doi":"10.1109/INSS.2010.5572211","date_updated":"2023-09-26T13:49:38Z","_id":"2227","year":"2010","type":"conference","citation":{"mla":"Woehrle, Matthias, et al. “Rupeas: Ruby Powered Event Analysis DSL.” Proc. Int. Conf. Networked Sensing Systems (INSS), IEEE, 2010, pp. 245–48, doi:10.1109/INSS.2010.5572211.","bibtex":"@inproceedings{Woehrle_Plessl_Thiele_2010, title={Rupeas: Ruby Powered Event Analysis DSL}, DOI={10.1109/INSS.2010.5572211}, booktitle={Proc. Int. Conf. Networked Sensing Systems (INSS)}, publisher={IEEE}, author={Woehrle, Matthias and Plessl, Christian and Thiele, Lothar}, year={2010}, pages={245–248} }","chicago":"Woehrle, Matthias, Christian Plessl, and Lothar Thiele. “Rupeas: Ruby Powered Event Analysis DSL.” In Proc. Int. Conf. Networked Sensing Systems (INSS), 245–48. IEEE, 2010. https://doi.org/10.1109/INSS.2010.5572211.","ama":"Woehrle M, Plessl C, Thiele L. Rupeas: Ruby Powered Event Analysis DSL. In: Proc. Int. Conf. Networked Sensing Systems (INSS). IEEE; 2010:245-248. doi:10.1109/INSS.2010.5572211","apa":"Woehrle, M., Plessl, C., & Thiele, L. (2010). Rupeas: Ruby Powered Event Analysis DSL. Proc. Int. Conf. Networked Sensing Systems (INSS), 245–248. https://doi.org/10.1109/INSS.2010.5572211","ieee":"M. Woehrle, C. Plessl, and L. Thiele, “Rupeas: Ruby Powered Event Analysis DSL,” in Proc. Int. Conf. Networked Sensing Systems (INSS), 2010, pp. 245–248, doi: 10.1109/INSS.2010.5572211.","short":"M. Woehrle, C. Plessl, L. Thiele, in: Proc. Int. Conf. Networked Sensing Systems (INSS), IEEE, 2010, pp. 245–248."},"page":"245-248","language":[{"iso":"eng"}],"title":"Rupeas: Ruby Powered Event Analysis DSL","user_id":"15278","extern":"1","publication_identifier":{"isbn":["978-1-4244-7911-5"]},"status":"public","date_created":"2018-04-05T16:41:02Z","publisher":"IEEE","quality_controlled":"1","author":[{"first_name":"Matthias","full_name":"Woehrle, Matthias","last_name":"Woehrle"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"full_name":"Thiele, Lothar","first_name":"Lothar","last_name":"Thiele"}],"publication":"Proc. Int. Conf. Networked Sensing Systems (INSS)","department":[{"_id":"27"},{"_id":"518"}]},{"user_id":"15278","title":"Performance Estimation for the Exploration of CPU-Accelerator Architectures","date_created":"2018-04-05T16:43:04Z","status":"public","editor":[{"first_name":"Omar","full_name":"Hammami, Omar","last_name":"Hammami"},{"first_name":"Sandra","full_name":"Larrabee, Sandra","last_name":"Larrabee"}],"publication":"Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"author":[{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"last_name":"Kauschke","first_name":"Michael","full_name":"Kauschke, Michael"}],"quality_controlled":"1","date_updated":"2023-09-26T13:50:04Z","_id":"2228","language":[{"iso":"eng"}],"citation":{"bibtex":"@inproceedings{Kenter_Platzner_Plessl_Kauschke_2010, title={Performance Estimation for the Exploration of CPU-Accelerator Architectures}, booktitle={Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)}, author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}, editor={Hammami, Omar and Larrabee, Sandra}, year={2010} }","mla":"Kenter, Tobias, et al. “Performance Estimation for the Exploration of CPU-Accelerator Architectures.” Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), edited by Omar Hammami and Sandra Larrabee, 2010.","chicago":"Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke. “Performance Estimation for the Exploration of CPU-Accelerator Architectures.” In Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), edited by Omar Hammami and Sandra Larrabee, 2010.","apa":"Kenter, T., Platzner, M., Plessl, C., & Kauschke, M. (2010). Performance Estimation for the Exploration of CPU-Accelerator Architectures. In O. Hammami & S. Larrabee (Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA).","ama":"Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation for the Exploration of CPU-Accelerator Architectures. In: Hammami O, Larrabee S, eds. Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA). ; 2010.","ieee":"T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation for the Exploration of CPU-Accelerator Architectures,” in Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), 2010.","short":"T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: O. Hammami, S. Larrabee (Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), 2010."},"type":"conference","year":"2010"},{"abstract":[{"lang":"eng","text":"Wireless Sensor Networks (WSNs) are unique embedded computation systems for distributed sensing of a dispersed phenomenon. While being a strongly concurrent distributed system, its embedded aspects with severe resource limitations and the wireless communication requires a fusion of technologies and methodologies from very different fields. As WSNs are deployed in remote locations for long-term unattended operation, assurance of correct functioning of the system is of prime concern. Thus, the design and development of WSNs requires specialized tools to allow for testing and debugging the system. To this end, we present a framework for analyzing and checking WSNs based on collected events during system operation. It allows for abstracting from the event trace by means of behavioral queries and uses assertions for checking the accordance of an execution to its specification. The framework is independent from WSN test platforms, applications and logging semantics and thus generally applicable for analyzing event logs of WSN test executions. "}],"place":"Computer Engineering and Networks Lab, ETH Zurich","extern":"1","user_id":"16153","title":"Rupeas: Ruby Powered Event Analysis DSL","keyword":["Rupeas","DSL","WSN","testing"],"department":[{"_id":"27"},{"_id":"518"}],"author":[{"first_name":"Matthias","full_name":"Woehrle, Matthias","last_name":"Woehrle"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"first_name":"Lothar","full_name":"Thiele, Lothar","last_name":"Thiele"}],"date_created":"2018-04-16T15:09:19Z","status":"public","_id":"2353","date_updated":"2022-01-06T06:55:56Z","report_number":"TIK-Report 290","language":[{"iso":"eng"}],"year":"2009","citation":{"ieee":"M. Woehrle, C. Plessl, and L. Thiele, Rupeas: Ruby Powered Event Analysis DSL. Computer Engineering and Networks Lab, ETH Zurich, 2009.","short":"M. Woehrle, C. Plessl, L. Thiele, Rupeas: Ruby Powered Event Analysis DSL, Computer Engineering and Networks Lab, ETH Zurich, 2009.","mla":"Woehrle, Matthias, et al. Rupeas: Ruby Powered Event Analysis DSL. 2009.","bibtex":"@book{Woehrle_Plessl_Thiele_2009, place={Computer Engineering and Networks Lab, ETH Zurich}, title={Rupeas: Ruby Powered Event Analysis DSL}, author={Woehrle, Matthias and Plessl, Christian and Thiele, Lothar}, year={2009} }","apa":"Woehrle, M., Plessl, C., & Thiele, L. (2009). Rupeas: Ruby Powered Event Analysis DSL. Computer Engineering and Networks Lab, ETH Zurich.","ama":"Woehrle M, Plessl C, Thiele L. Rupeas: Ruby Powered Event Analysis DSL. Computer Engineering and Networks Lab, ETH Zurich; 2009.","chicago":"Woehrle, Matthias, Christian Plessl, and Lothar Thiele. Rupeas: Ruby Powered Event Analysis DSL. Computer Engineering and Networks Lab, ETH Zurich, 2009."},"type":"report"},{"type":"conference","citation":{"mla":"Schumacher, Tobias, et al. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–78, doi:10.1109/FCCM.2009.25.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing}, DOI={10.1109/FCCM.2009.25}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={275–278} }","ama":"Schumacher T, Plessl C, Platzner M. IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society; 2009:275-278. doi:10.1109/FCCM.2009.25","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2009). IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–278. https://doi.org/10.1109/FCCM.2009.25","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–78. IEEE Computer Society, 2009. https://doi.org/10.1109/FCCM.2009.25.","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing,” in Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2009, pp. 275–278, doi: 10.1109/FCCM.2009.25.","short":"T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–278."},"year":"2009","page":"275-278","_id":"2350","publisher":"IEEE Computer Society","quality_controlled":"1","author":[{"last_name":"Schumacher","first_name":"Tobias","full_name":"Schumacher, Tobias"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"keyword":["IMORC","interconnect","performance"],"publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","status":"public","date_created":"2018-04-16T15:05:52Z","abstract":[{"text":"Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. ","lang":"eng"}],"user_id":"15278","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:51:44Z","doi":"10.1109/FCCM.2009.25","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication_identifier":{"isbn":["978-1-4244-4450-2"]},"title":"IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing"},{"user_id":"15278","title":"EvoCaches: Application-specific Adaptation of Cache Mapping","abstract":[{"lang":"eng","text":"In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. "}],"place":"Los Alamitos, CA, USA","date_created":"2018-04-06T15:18:24Z","status":"public","keyword":["EvoCache","evolvable hardware","computer architecture"],"publication":"Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publisher":"IEEE Computer Society","quality_controlled":"1","author":[{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"date_updated":"2023-09-26T13:53:11Z","_id":"2262","language":[{"iso":"eng"}],"page":"11-18","type":"conference","year":"2009","citation":{"ieee":"P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific Adaptation of Cache Mapping,” in Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2009, pp. 11–18.","short":"P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 11–18.","mla":"Kaufmann, Paul, et al. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, 2009, pp. 11–18.","bibtex":"@inproceedings{Kaufmann_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={EvoCaches: Application-specific Adaptation of Cache Mapping}, booktitle={Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}, publisher={IEEE Computer Society}, author={Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2009}, pages={11–18} }","apa":"Kaufmann, P., Plessl, C., & Platzner, M. (2009). EvoCaches: Application-specific Adaptation of Cache Mapping. Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18.","ama":"Kaufmann P, Plessl C, Platzner M. EvoCaches: Application-specific Adaptation of Cache Mapping. In: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS). IEEE Computer Society; 2009:11-18.","chicago":"Kaufmann, Paul, Christian Plessl, and Marco Platzner. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” In Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18. Los Alamitos, CA, USA: IEEE Computer Society, 2009."}},{"date_updated":"2023-09-26T13:52:01Z","_id":"2352","language":[{"iso":"eng"}],"page":"265-276","type":"conference","year":"2009","citation":{"mla":"Beutel, Jan, et al. “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes.” Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), IEEE Computer Society, 2009, pp. 265–76.","bibtex":"@inproceedings{Beutel_Gruber_Hasler_Lim_Meier_Plessl_Talzi_Thiele_Tschudin_Woehrle_et al._2009, place={Washington, DC, USA}, title={PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes}, booktitle={Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)}, publisher={IEEE Computer Society}, author={Beutel, Jan and Gruber, Stephan and Hasler, Andi and Lim, Roman and Meier, Andreas and Plessl, Christian and Talzi, Igor and Thiele, Lothar and Tschudin, Christian and Woehrle, Matthias and et al.}, year={2009}, pages={265–276} }","ama":"Beutel J, Gruber S, Hasler A, et al. PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes. In: Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN). 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Networked Sensing Systems (INSS)","department":[{"_id":"27"},{"_id":"518"}],"keyword":["WSN","testing","verification"],"quality_controlled":"1","author":[{"last_name":"Beutel","full_name":"Beutel, Jan","first_name":"Jan"},{"last_name":"Dyer","full_name":"Dyer, Matthias","first_name":"Matthias"},{"first_name":"Roman","full_name":"Lim, Roman","last_name":"Lim"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"last_name":"Woehrle","full_name":"Woehrle, Matthias","first_name":"Matthias"},{"last_name":"Yuecel","full_name":"Yuecel, Mustafa","first_name":"Mustafa"},{"last_name":"Thiele","full_name":"Thiele, Lothar","first_name":"Lothar"}],"publisher":"IEEE","publication_identifier":{"isbn":["1-4244-1231-5"]},"date_created":"2018-04-17T13:35:55Z","status":"public","place":"Piscataway, NJ, USA","title":"Automated Wireless Sensor Network Testing","user_id":"15278","page":"303-303","type":"conference","citation":{"ama":"Beutel J, Dyer M, Lim R, et al. Automated Wireless Sensor Network Testing. In: Proc. Int. Conf. Networked Sensing Systems (INSS). IEEE; 2007:303-303. doi:10.1109/INSS.2007.4297445","apa":"Beutel, J., Dyer, M., Lim, R., Plessl, C., Woehrle, M., Yuecel, M., & Thiele, L. (2007). Automated Wireless Sensor Network Testing. Proc. Int. Conf. Networked Sensing Systems (INSS), 303–303. https://doi.org/10.1109/INSS.2007.4297445","chicago":"Beutel, Jan, Matthias Dyer, Roman Lim, Christian Plessl, Matthias Woehrle, Mustafa Yuecel, and Lothar Thiele. “Automated Wireless Sensor Network Testing.” In Proc. Int. Conf. Networked Sensing Systems (INSS), 303–303. Piscataway, NJ, USA: IEEE, 2007. https://doi.org/10.1109/INSS.2007.4297445.","bibtex":"@inproceedings{Beutel_Dyer_Lim_Plessl_Woehrle_Yuecel_Thiele_2007, place={Piscataway, NJ, USA}, title={Automated Wireless Sensor Network Testing}, DOI={10.1109/INSS.2007.4297445}, booktitle={Proc. Int. Conf. Networked Sensing Systems (INSS)}, publisher={IEEE}, author={Beutel, Jan and Dyer, Matthias and Lim, Roman and Plessl, Christian and Woehrle, Matthias and Yuecel, Mustafa and Thiele, Lothar}, year={2007}, pages={303–303} }","mla":"Beutel, Jan, et al. “Automated Wireless Sensor Network Testing.” Proc. Int. Conf. Networked Sensing Systems (INSS), IEEE, 2007, pp. 303–303, doi:10.1109/INSS.2007.4297445.","short":"J. Beutel, M. Dyer, R. Lim, C. Plessl, M. Woehrle, M. Yuecel, L. Thiele, in: Proc. Int. Conf. Networked Sensing Systems (INSS), IEEE, Piscataway, NJ, USA, 2007, pp. 303–303.","ieee":"J. Beutel et al., “Automated Wireless Sensor Network Testing,” in Proc. Int. Conf. Networked Sensing Systems (INSS), 2007, pp. 303–303, doi: 10.1109/INSS.2007.4297445."},"year":"2007","language":[{"iso":"eng"}],"_id":"2393","date_updated":"2023-09-26T14:00:58Z","doi":"10.1109/INSS.2007.4297445"},{"doi":"10.2370/9783832255619","_id":"2404","date_updated":"2022-01-06T06:56:06Z","citation":{"short":"C. Plessl, Hardware Virtualization on a Coarse-Grained Reconfigurable Processor, Shaker Verlag, Aachen, Germany, 2006.","ieee":"C. Plessl, Hardware virtualization on a coarse-grained reconfigurable processor. Aachen, Germany: Shaker Verlag, 2006.","chicago":"Plessl, Christian. Hardware Virtualization on a Coarse-Grained Reconfigurable Processor. Technische Informatik. Aachen, Germany: Shaker Verlag, 2006. https://doi.org/10.2370/9783832255619.","apa":"Plessl, C. (2006). Hardware virtualization on a coarse-grained reconfigurable processor. Aachen, Germany: Shaker Verlag. https://doi.org/10.2370/9783832255619","ama":"Plessl C. Hardware Virtualization on a Coarse-Grained Reconfigurable Processor. Aachen, Germany: Shaker Verlag; 2006. doi:10.2370/9783832255619","mla":"Plessl, Christian. Hardware Virtualization on a Coarse-Grained Reconfigurable Processor. Shaker Verlag, 2006, doi:10.2370/9783832255619.","bibtex":"@book{Plessl_2006, place={Aachen, Germany}, series={Technische Informatik}, title={Hardware virtualization on a coarse-grained reconfigurable processor}, DOI={10.2370/9783832255619}, publisher={Shaker Verlag}, author={Plessl, Christian}, year={2006}, collection={Technische Informatik} }"},"type":"dissertation","year":"2006","series_title":"Technische Informatik","title":"Hardware virtualization on a coarse-grained reconfigurable processor","user_id":"24135","abstract":[{"lang":"eng","text":" In this thesis, we propose to use a reconfigurable processor as main computation element in embedded systems for applications from the multi-media and communications domain. A reconfigurable processor integrates an embedded CPU core with a Reconfigurable Processing Unit (RPU). Many of our target applications require real-time signal-processing of data streams and expose a high computational demand. The key challenge in designing embedded systems for these applications is to find an implementation that satisfies the performance goals and is adaptable to new applications, while the system cost is minimized. Implementations that solely use an embedded CPU are likely to miss the performance goals. Application-Specific Integrated Circuit (ASIC)-based coprocessors can be used for some high-volume products with fixed functions, but fall short for systems with varying applications. We argue that a reconfigurable processor with a coarse-grained, dynamically reconfigurable array of modest size provides an attractive implementation platform for our application domain. The computational intensive application kernels are executed on the RPU, while the remaining parts of the application are executed on the CPU. Reconfigurable hardware allows for implementing application specific coprocessors with a high performance, while the function of the coprocessor can still be adapted due to the programmability. So far, reconfigurable technology is used in embedded systems primarily with static configurations, e.g., for implementing glue-logic, replacing ASICs, and for implementing fixed-function coprocessors. Changing the configuration at runtime enables a number of interesting application modes, e.g., on-demand loading of coprocessors and time-multiplexed execution of coprocessors, which is commonly denoted as hardware virtualization. While the use of static configurations is well understood and supported by design-tools, the role of dynamic reconfiguration is not well investigated yet. Current application specification methods and design-tools do not provide an end-to-end tool-flow that considers dynamic reconfiguration. A key idea of our approach is to reduce system cost by keeping the size of the reconfigurable array small and to use hardware virtualization techniques to compensate for the limited hardware resources. The main contribution of this thesis is the codesign of a reconfigurable processor architecture named ZIPPY, the corresponding hardware and software implementation tools, and an application specification model which explicitly considers hardware virtualization. The ZIPPY architecture is widely parametrized and allows for specifying a whole family of processor architectures. The implementation tools are also parametrized and can target any architectural variant. We evaluate the performance of the architecture with a system-level, cycle-accurate cosimulation framework. This framework enables us to perform design-space exploration for a variety of reconfigurable processor architectures. With two case studies, we demonstrate, that hardware virtualization on the Zippy architecture is feasible and enables us to trade-off performance for area in embedded systems. Finally, we present a novel method for optimal temporal partitioning of sequential circuits, which is an important form of hardware virtualization. The method based on Slowdown and Retiming allows us to decompose any sequential circuit into a number of smaller, communicating subcircuits that can be executed on a dynamically reconfigurable architecture. "}],"place":"Aachen, Germany","publication_identifier":{"isbn":["978-3-8322-5561-3"]},"date_created":"2018-04-17T13:46:27Z","status":"public","department":[{"_id":"518"}],"keyword":["Zippy"],"publisher":"Shaker Verlag","author":[{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}]},{"type":"conference","citation":{"short":"C. Plessl, M. Platzner, L. Thiele, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2006, pp. 345–348.","ieee":"C. Plessl, M. Platzner, and L. Thiele, “Optimal Temporal Partitioning based on Slowdown and Retiming,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2006, pp. 345–348.","apa":"Plessl, C., Platzner, M., & Thiele, L. (2006). Optimal Temporal Partitioning based on Slowdown and Retiming. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 345–348). IEEE Computer Society. https://doi.org/10.1109/FPT.2006.270344","ama":"Plessl C, Platzner M, Thiele L. Optimal Temporal Partitioning based on Slowdown and Retiming. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2006:345-348. doi:10.1109/FPT.2006.270344","chicago":"Plessl, Christian, Marco Platzner, and Lothar Thiele. “Optimal Temporal Partitioning Based on Slowdown and Retiming.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 345–48. IEEE Computer Society, 2006. https://doi.org/10.1109/FPT.2006.270344.","bibtex":"@inproceedings{Plessl_Platzner_Thiele_2006, title={Optimal Temporal Partitioning based on Slowdown and Retiming}, DOI={10.1109/FPT.2006.270344}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco and Thiele, Lothar}, year={2006}, pages={345–348} }","mla":"Plessl, Christian, et al. “Optimal Temporal Partitioning Based on Slowdown and Retiming.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2006, pp. 345–48, doi:10.1109/FPT.2006.270344."},"year":"2006","page":"345-348","_id":"2401","date_updated":"2022-01-06T06:56:05Z","doi":"10.1109/FPT.2006.270344","publisher":"IEEE Computer Society","author":[{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"last_name":"Thiele","full_name":"Thiele, Lothar","first_name":"Lothar"}],"keyword":["temporal partitioning","retiming","ILP"],"publication":"Proc. Int. Conf. on Field Programmable Technology (ICFPT)","department":[{"_id":"518"},{"_id":"78"}],"status":"public","date_created":"2018-04-17T13:43:21Z","abstract":[{"text":" This paper presents a novel method for optimal temporal partitioning of sequential circuits for time-multiplexed reconfigurable architectures. The method bases on slowdown and retiming and maximizes the circuit's performance during execution while restricting the size of the partitions to respect the resource constraints of the reconfigurable architecture. We provide a mixed integer linear program (MILP) formulation of the problem, which can be solved exactly. In contrast to related work, our approach optimizes performance directly, takes structural modifications of the circuit into account, and is extensible. We present the application of the new method to temporal partitioning for a coarse-grained reconfigurable architecture. ","lang":"eng"}],"title":"Optimal Temporal Partitioning based on Slowdown and Retiming","user_id":"24135"},{"doi":"10.1109/ASAP.2005.69","_id":"2411","date_updated":"2022-01-06T06:56:07Z","page":"213-218","type":"conference","year":"2005","citation":{"chicago":"Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 213–18. IEEE Computer Society, 2005. https://doi.org/10.1109/ASAP.2005.69.","ama":"Plessl C, Platzner M. Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2005:213-218. doi:10.1109/ASAP.2005.69","apa":"Plessl, C., & Platzner, M. (2005). Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) (pp. 213–218). IEEE Computer Society. https://doi.org/10.1109/ASAP.2005.69","bibtex":"@inproceedings{Plessl_Platzner_2005, title={Zippy – A coarse-grained reconfigurable array with support for hardware virtualization}, DOI={10.1109/ASAP.2005.69}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2005}, pages={213–218} }","mla":"Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–18, doi:10.1109/ASAP.2005.69.","short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–218.","ieee":"C. Plessl and M. Platzner, “Zippy – A coarse-grained reconfigurable array with support for hardware virtualization,” in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2005, pp. 213–218."},"user_id":"24135","title":"Zippy – A coarse-grained reconfigurable array with support for hardware virtualization","abstract":[{"lang":"eng","text":" This paper motivates the use of hardware virtualization on coarse-grained reconfigurable architectures. We introduce Zippy, a coarse-grained multi-context hybrid CPU with architectural support for efficient hardware virtualization. The architectural details and the corresponding tool flow are outlined. As a case study, we compare the non-virtualized and the virtualized execution of an ADPCM decoder. "}],"date_created":"2018-04-17T14:34:03Z","status":"public","publication":"Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)","keyword":["Zippy"],"department":[{"_id":"518"},{"_id":"78"}],"publisher":"IEEE Computer Society","author":[{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}]},{"abstract":[{"text":" Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving impact of these design decisions on the overall system performance is a challenging task. In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors.","lang":"eng"}],"user_id":"24135","title":"System-level performance evaluation of reconfigurable processors","publisher":"Elsevier","author":[{"first_name":"Rolf","full_name":"Enzler, Rolf","last_name":"Enzler"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publication":"Microprocessors and Microsystems","department":[{"_id":"518"},{"_id":"78"}],"keyword":["FPGA","reconfigurable computing","co-simulation","Zippy"],"status":"public","date_created":"2018-04-17T14:36:10Z","volume":29,"date_updated":"2022-01-06T06:56:07Z","_id":"2412","intvolume":" 29","issue":"2-3","doi":"10.1016/j.micpro.2004.06.004","citation":{"ieee":"R. Enzler, C. Plessl, and M. Platzner, “System-level performance evaluation of reconfigurable processors,” Microprocessors and Microsystems, vol. 29, no. 2–3, pp. 63–73, 2005.","short":"R. Enzler, C. Plessl, M. Platzner, Microprocessors and Microsystems 29 (2005) 63–73.","bibtex":"@article{Enzler_Plessl_Platzner_2005, title={System-level performance evaluation of reconfigurable processors}, volume={29}, DOI={10.1016/j.micpro.2004.06.004}, number={2–3}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2005}, pages={63–73} }","mla":"Enzler, Rolf, et al. “System-Level Performance Evaluation of Reconfigurable Processors.” Microprocessors and Microsystems, vol. 29, no. 2–3, Elsevier, 2005, pp. 63–73, doi:10.1016/j.micpro.2004.06.004.","apa":"Enzler, R., Plessl, C., & Platzner, M. (2005). System-level performance evaluation of reconfigurable processors. Microprocessors and Microsystems, 29(2–3), 63–73. https://doi.org/10.1016/j.micpro.2004.06.004","ama":"Enzler R, Plessl C, Platzner M. System-level performance evaluation of reconfigurable processors. Microprocessors and Microsystems. 2005;29(2-3):63-73. doi:10.1016/j.micpro.2004.06.004","chicago":"Enzler, Rolf, Christian Plessl, and Marco Platzner. “System-Level Performance Evaluation of Reconfigurable Processors.” Microprocessors and Microsystems 29, no. 2–3 (2005): 63–73. https://doi.org/10.1016/j.micpro.2004.06.004."},"year":"2005","type":"journal_article","page":"63-73"},{"date_created":"2018-04-17T14:45:57Z","status":"public","publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"518"},{"_id":"78"}],"keyword":["hardware virtualization"],"author":[{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publisher":"CSREA Press","title":"Virtualization of Hardware – Introduction and Survey","user_id":"24135","abstract":[{"text":"In this paper we introduce to virtualization of hardware on reconfigurable devices. We identify three main approaches denoted with temporal partitioning, virtualized execution, and virtual machine. For each virtualization approach, we discuss the application models, the required execution architectures, the design tools and the run-time systems. Then, we survey a selection of important projects in the field. ","lang":"eng"}],"page":"63-69","citation":{"chicago":"Plessl, Christian, and Marco Platzner. “Virtualization of Hardware – Introduction and Survey.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 63–69. CSREA Press, 2004.","ama":"Plessl C, Platzner M. Virtualization of Hardware – Introduction and Survey. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2004:63-69.","apa":"Plessl, C., & Platzner, M. (2004). Virtualization of Hardware – Introduction and Survey. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 63–69). CSREA Press.","bibtex":"@inproceedings{Plessl_Platzner_2004, title={Virtualization of Hardware – Introduction and Survey}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Plessl, Christian and Platzner, Marco}, year={2004}, pages={63–69} }","mla":"Plessl, Christian, and Marco Platzner. “Virtualization of Hardware – Introduction and Survey.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004, pp. 63–69.","short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004, pp. 63–69.","ieee":"C. Plessl and M. Platzner, “Virtualization of Hardware – Introduction and Survey,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2004, pp. 63–69."},"year":"2004","type":"conference","_id":"2415","date_updated":"2022-01-06T06:56:08Z"},{"type":"conference","citation":{"chicago":"Plessl, Christian, and Marco Platzner. “TKDM – A Reconfigurable Co-Processor in a PC’s Memory Slot.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 252–59. IEEE Computer Society, 2003. https://doi.org/10.1109/FPT.2003.1275755.","apa":"Plessl, C., & Platzner, M. (2003). TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 252–259). IEEE Computer Society. https://doi.org/10.1109/FPT.2003.1275755","ama":"Plessl C, Platzner M. TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2003:252-259. doi:10.1109/FPT.2003.1275755","mla":"Plessl, Christian, and Marco Platzner. “TKDM – A Reconfigurable Co-Processor in a PC’s Memory Slot.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2003, pp. 252–59, doi:10.1109/FPT.2003.1275755.","bibtex":"@inproceedings{Plessl_Platzner_2003, title={TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot}, DOI={10.1109/FPT.2003.1275755}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2003}, pages={252–259} }","short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2003, pp. 252–259.","ieee":"C. Plessl and M. Platzner, “TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2003, pp. 252–259."},"year":"2003","page":"252-259","doi":"10.1109/FPT.2003.1275755","_id":"2418","date_updated":"2022-01-06T06:56:09Z","status":"public","date_created":"2018-04-17T15:03:34Z","publisher":"IEEE Computer Society","author":[{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"keyword":["coprocessor","DIMM","memory bus","FPGA","high performance computing"],"department":[{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Field Programmable Technology (ICFPT)","user_id":"24135","title":"TKDM – A Reconfigurable Co-processor in a PC's Memory Slot","abstract":[{"lang":"eng","text":" This paper presents TKDM, a PC-based high-performance reconfigurable computing environment. The TKDM hardware consists of an FPGA module that uses the DIMM (dual inline memory module) bus for high-bandwidth and low-latency communication with the host CPU. The system's firmware is integrated with the Linux host operating system and offers functions for data communication and FPGA reconfiguration. The intended use of TKDM is that of a dynamically reconfigurable co-processor for data streaming applications. The system's firmware can be customized for specific application domains to facilitate simple and easy-to-use programming interfaces. "}]},{"title":"The Case for Reconfigurable Hardware in Wearable Computing","department":[{"_id":"518"},{"_id":"78"}],"doi":"10.1007/s00779-003-0243-x","date_updated":"2022-01-06T06:56:09Z","language":[{"iso":"eng"}],"user_id":"398","extern":"1","abstract":[{"lang":"eng","text":"Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM."}],"volume":7,"status":"public","date_created":"2018-04-17T15:04:47Z","author":[{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"last_name":"Enzler","full_name":"Enzler, Rolf","first_name":"Rolf"},{"last_name":"Walder","full_name":"Walder, Herbert","first_name":"Herbert"},{"first_name":"Jan","full_name":"Beutel, Jan","last_name":"Beutel"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"last_name":"Thiele","full_name":"Thiele, Lothar","first_name":"Lothar"},{"last_name":"Tröster","first_name":"Gerhard","full_name":"Tröster, Gerhard"}],"publisher":"Springer","publication":"Personal and Ubiquitous Computing","issue":"5","_id":"2419","intvolume":" 7","type":"journal_article","citation":{"short":"C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, G. Tröster, Personal and Ubiquitous Computing 7 (2003) 299–308.","ieee":"C. Plessl et al., “The Case for Reconfigurable Hardware in Wearable Computing,” Personal and Ubiquitous Computing, vol. 7, no. 5, pp. 299–308, 2003.","chicago":"Plessl, Christian, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, Lothar Thiele, and Gerhard Tröster. “The Case for Reconfigurable Hardware in Wearable Computing.” Personal and Ubiquitous Computing 7, no. 5 (2003): 299–308. https://doi.org/10.1007/s00779-003-0243-x.","ama":"Plessl C, Enzler R, Walder H, et al. The Case for Reconfigurable Hardware in Wearable Computing. Personal and Ubiquitous Computing. 2003;7(5):299-308. doi:10.1007/s00779-003-0243-x","apa":"Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., Thiele, L., & Tröster, G. (2003). The Case for Reconfigurable Hardware in Wearable Computing. Personal and Ubiquitous Computing, 7(5), 299–308. https://doi.org/10.1007/s00779-003-0243-x","mla":"Plessl, Christian, et al. “The Case for Reconfigurable Hardware in Wearable Computing.” Personal and Ubiquitous Computing, vol. 7, no. 5, Springer, 2003, pp. 299–308, doi:10.1007/s00779-003-0243-x.","bibtex":"@article{Plessl_Enzler_Walder_Beutel_Platzner_Thiele_Tröster_2003, title={The Case for Reconfigurable Hardware in Wearable Computing}, volume={7}, DOI={10.1007/s00779-003-0243-x}, number={5}, journal={Personal and Ubiquitous Computing}, publisher={Springer}, author={Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan and Platzner, Marco and Thiele, Lothar and Tröster, Gerhard}, year={2003}, pages={299–308} }"},"year":"2003","page":"299-308"},{"publication_identifier":{"issn":["0920-8542"]},"department":[{"_id":"518"},{"_id":"78"}],"title":"Instance-Specific Accelerators for Minimum Covering","language":[{"iso":"eng"}],"doi":"10.1023/a:1024443416592","date_updated":"2022-01-06T06:56:10Z","date_created":"2018-04-17T15:10:00Z","status":"public","volume":26,"keyword":["reconfigurable computing","instance-specific acceleration","minimum covering"],"publication":"Journal of Supercomputing","author":[{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"Kluwer Academic Publishers","user_id":"398","abstract":[{"lang":"eng","text":" This paper presents the acceleration of minimum-cost covering problems by instance-specific hardware. First, we formulate the minimum-cost covering problem and discuss a branch \\& bound algorithm to solve it. Then we describe instance-specific hardware architectures that implement branch \\& bound in 3-valued logic and use reduction techniques similar to those found in software solvers. We further present prototypical accelerator implementations and a corresponding design tool flow. Our experiments reveal significant raw speedups up to five orders of magnitude for a set of smaller unate covering problems. Provided that hardware compilation times can be reduced, we conclude that instance-specific acceleration of hard minimum-cost covering problems will lead to substantial overall speedups. "}],"extern":"1","page":"109-129","type":"journal_article","citation":{"ieee":"C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” Journal of Supercomputing, vol. 26, no. 2, pp. 109–129, 2003.","short":"C. Plessl, M. Platzner, Journal of Supercomputing 26 (2003) 109–129.","mla":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” Journal of Supercomputing, vol. 26, no. 2, Kluwer Academic Publishers, 2003, pp. 109–29, doi:10.1023/a:1024443416592.","bibtex":"@article{Plessl_Platzner_2003, title={Instance-Specific Accelerators for Minimum Covering}, volume={26}, DOI={10.1023/a:1024443416592}, number={2}, journal={Journal of Supercomputing}, publisher={Kluwer Academic Publishers}, author={Plessl, Christian and Platzner, Marco}, year={2003}, pages={109–129} }","apa":"Plessl, C., & Platzner, M. (2003). Instance-Specific Accelerators for Minimum Covering. Journal of Supercomputing, 26(2), 109–129. https://doi.org/10.1023/a:1024443416592","ama":"Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. Journal of Supercomputing. 2003;26(2):109-129. doi:10.1023/a:1024443416592","chicago":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” Journal of Supercomputing 26, no. 2 (2003): 109–29. https://doi.org/10.1023/a:1024443416592."},"year":"2003","issue":"2","_id":"2420","intvolume":" 26"},{"volume":2778,"status":"public","date_created":"2018-04-17T15:11:25Z","author":[{"full_name":"Enzler, Rolf","first_name":"Rolf","last_name":"Enzler"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"Springer","publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","department":[{"_id":"518"},{"_id":"78"}],"keyword":["Zippy","multi-context","FPGA"],"title":"Virtualizing Hardware with Multi-Context Reconfigurable Arrays","user_id":"24135","abstract":[{"lang":"eng","text":"In contrast to processors, current reconfigurable devices totally lack programming models that would allow for device independent compilation and forward compatibility. The key to overcome this limitation is hardware virtualization. In this paper, we resort to a macro-pipelined execution model to achieve hardware virtualization for data streaming applications. As a hardware implementation we present a hybrid multi-context architecture that attaches a coarse-grained reconfigurable array to a host CPU. A co-simulation framework enables cycle-accurate simulation of the complete architecture. As a case study we map an FIR filter to our virtualized hardware model and evaluate different designs. We discuss the impact of the number of contexts and the feature of context state on the speedup and the CPU load."}],"year":"2003","citation":{"ieee":"R. Enzler, C. Plessl, and M. Platzner, “Virtualizing Hardware with Multi-Context Reconfigurable Arrays,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2003, vol. 2778, pp. 151–160.","short":"R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), Springer, 2003, pp. 151–160.","mla":"Enzler, Rolf, et al. “Virtualizing Hardware with Multi-Context Reconfigurable Arrays.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), vol. 2778, Springer, 2003, pp. 151–60, doi:10.1007/b12007.","bibtex":"@inproceedings{Enzler_Plessl_Platzner_2003, series={Lecture Notes in Computer Science (LNCS)}, title={Virtualizing Hardware with Multi-Context Reconfigurable Arrays}, volume={2778}, DOI={10.1007/b12007}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2003}, pages={151–160}, collection={Lecture Notes in Computer Science (LNCS)} }","chicago":"Enzler, Rolf, Christian Plessl, and Marco Platzner. “Virtualizing Hardware with Multi-Context Reconfigurable Arrays.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2778:151–60. Lecture Notes in Computer Science (LNCS). Springer, 2003. https://doi.org/10.1007/b12007.","ama":"Enzler R, Plessl C, Platzner M. Virtualizing Hardware with Multi-Context Reconfigurable Arrays. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). Vol 2778. Lecture Notes in Computer Science (LNCS). Springer; 2003:151-160. doi:10.1007/b12007","apa":"Enzler, R., Plessl, C., & Platzner, M. (2003). Virtualizing Hardware with Multi-Context Reconfigurable Arrays. In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (Vol. 2778, pp. 151–160). Springer. https://doi.org/10.1007/b12007"},"type":"conference","page":"151-160","series_title":"Lecture Notes in Computer Science (LNCS)","doi":"10.1007/b12007","intvolume":" 2778","_id":"2421","date_updated":"2022-01-06T06:56:13Z"},{"abstract":[{"text":"Reconfigurable computing architectures aim to dynamically adapt their hardware to the application at hand. As research shows, the time it takes to reconfigure the hardware forms an overhead that can significantly impair the benefits of hardware customization. Multi-context devices are one promising approach to overcome the limitations posed by long reconfiguration times. In contrast to more traditional reconfigurable architectures, multi-context devices hold several configurations on-chip. On demand, the device can quickly switch to another context. In this paper we present a co-simulation environment to investigate design trade-offs for hybrid multi-context architectures. Our architectural model comprises a reconfigurable unit closely coupled to a CPU core. As a case study, we discuss the implementation of a FIR filter partitioned into several contexts. We outline the mapping process and present simulation results for single- and multi-context reconfigurable units coupled with both embedded and high-end CPUs.","lang":"eng"}],"user_id":"24135","title":"Co-simulation of a Hybrid Multi-Context Architecture","author":[{"last_name":"Enzler","full_name":"Enzler, Rolf","first_name":"Rolf"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"CSREA Press","publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","keyword":["Zippy","co-simulation"],"department":[{"_id":"518"},{"_id":"78"}],"status":"public","date_created":"2018-04-17T15:12:56Z","publication_identifier":{"isbn":["1-932415-05-X"]},"date_updated":"2022-01-06T06:56:13Z","_id":"2422","citation":{"ama":"Enzler R, Plessl C, Platzner M. Co-simulation of a Hybrid Multi-Context Architecture. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2003:174-180.","apa":"Enzler, R., Plessl, C., & Platzner, M. (2003). Co-simulation of a Hybrid Multi-Context Architecture. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 174–180). CSREA Press.","chicago":"Enzler, Rolf, Christian Plessl, and Marco Platzner. “Co-Simulation of a Hybrid Multi-Context Architecture.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 174–80. CSREA Press, 2003.","mla":"Enzler, Rolf, et al. “Co-Simulation of a Hybrid Multi-Context Architecture.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 174–80.","bibtex":"@inproceedings{Enzler_Plessl_Platzner_2003, title={Co-simulation of a Hybrid Multi-Context Architecture}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2003}, pages={174–180} }","short":"R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 174–180.","ieee":"R. Enzler, C. Plessl, and M. Platzner, “Co-simulation of a Hybrid Multi-Context Architecture,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2003, pp. 174–180."},"type":"conference","year":"2003","page":"174-180"},{"year":"2002","type":"conference","citation":{"ama":"Plessl C, Enzler R, Walder H, Beutel J, Platzner M, Thiele L. Reconfigurable Hardware in Wearable Computing Nodes. In: Proc. Int. Symp. on Wearable Computers (ISWC). IEEE Computer Society; 2002:215-222. doi:10.1109/ISWC.2002.1167250","apa":"Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., & Thiele, L. (2002). Reconfigurable Hardware in Wearable Computing Nodes. In Proc. Int. Symp. on Wearable Computers (ISWC) (pp. 215–222). IEEE Computer Society. https://doi.org/10.1109/ISWC.2002.1167250","chicago":"Plessl, Christian, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, and Lothar Thiele. “Reconfigurable Hardware in Wearable Computing Nodes.” In Proc. Int. Symp. on Wearable Computers (ISWC), 215–22. IEEE Computer Society, 2002. https://doi.org/10.1109/ISWC.2002.1167250.","mla":"Plessl, Christian, et al. “Reconfigurable Hardware in Wearable Computing Nodes.” Proc. Int. Symp. on Wearable Computers (ISWC), IEEE Computer Society, 2002, pp. 215–22, doi:10.1109/ISWC.2002.1167250.","bibtex":"@inproceedings{Plessl_Enzler_Walder_Beutel_Platzner_Thiele_2002, title={Reconfigurable Hardware in Wearable Computing Nodes}, DOI={10.1109/ISWC.2002.1167250}, booktitle={Proc. Int. Symp. on Wearable Computers (ISWC)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan and Platzner, Marco and Thiele, Lothar}, year={2002}, pages={215–222} }","short":"C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, in: Proc. Int. Symp. on Wearable Computers (ISWC), IEEE Computer Society, 2002, pp. 215–222.","ieee":"C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, and L. Thiele, “Reconfigurable Hardware in Wearable Computing Nodes,” in Proc. Int. Symp. on Wearable Computers (ISWC), 2002, pp. 215–222."},"page":"215-222","doi":"10.1109/ISWC.2002.1167250","date_updated":"2022-01-06T06:56:13Z","_id":"2423","publication_identifier":{"isbn":["0-7695-1816-8"]},"status":"public","date_created":"2018-04-17T15:13:50Z","publisher":"IEEE Computer Society","author":[{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"last_name":"Enzler","first_name":"Rolf","full_name":"Enzler, Rolf"},{"first_name":"Herbert","full_name":"Walder, Herbert","last_name":"Walder"},{"last_name":"Beutel","first_name":"Jan","full_name":"Beutel, Jan"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"full_name":"Thiele, Lothar","first_name":"Lothar","last_name":"Thiele"}],"keyword":["wearable computing"],"publication":"Proc. Int. Symp. on Wearable Computers (ISWC)","department":[{"_id":"518"},{"_id":"78"}],"title":"Reconfigurable Hardware in Wearable Computing Nodes","user_id":"24135","abstract":[{"text":"Wearable computers are embedded into the mobile environment of the human body. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with low energy consumption required to maximize battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss two experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we develop and evaluate task placement techniques used in the operating system layer of WURM.","lang":"eng"}]},{"status":"public","date_created":"2018-04-17T15:14:39Z","volume":2438,"author":[{"last_name":"Dyer","first_name":"Matthias","full_name":"Dyer, Matthias"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"Springer","publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","department":[{"_id":"518"},{"_id":"78"}],"keyword":["partial reconfiguration"],"user_id":"24135","title":"Partially Reconfigurable Cores for Xilinx Virtex","abstract":[{"lang":"eng","text":" Recent generations of high-density and high-speed FPGAs provide a sufficient capacity for implementing complete configurable systems on a chip (CSoCs). Hybrid CPUs that combine standard CPU cores with reconfigurable coprocessors are an important subclass of CSoCs. With partially reconfigurable FPGAs, coprocessors can be loaded on demand while the CPU remains running. However, the lack of high-level design tools for partial reconfiguration makes practical implementations a challenging task. In this paper, we introduce a design flow to implement hybrid processors on Xilinx Virtex. The design flow is based on two techniques, virtual sockets and feed-through components, and can efficiently generate partial configurations from industry-quality cores. We discuss the design flow and present a fully operational audio streaming prototype to demonstrate its feasibility. "}],"type":"conference","year":"2002","citation":{"short":"M. Dyer, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), Springer, 2002, pp. 292–301.","ieee":"M. Dyer, C. Plessl, and M. Platzner, “Partially Reconfigurable Cores for Xilinx Virtex,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2002, vol. 2438, pp. 292–301.","chicago":"Dyer, Matthias, Christian Plessl, and Marco Platzner. “Partially Reconfigurable Cores for Xilinx Virtex.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2438:292–301. Lecture Notes in Computer Science (LNCS). Springer, 2002. https://doi.org/10.1007/3-540-46117-5.","ama":"Dyer M, Plessl C, Platzner M. Partially Reconfigurable Cores for Xilinx Virtex. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). Vol 2438. Lecture Notes in Computer Science (LNCS). Springer; 2002:292-301. doi:10.1007/3-540-46117-5","apa":"Dyer, M., Plessl, C., & Platzner, M. (2002). Partially Reconfigurable Cores for Xilinx Virtex. In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (Vol. 2438, pp. 292–301). Springer. https://doi.org/10.1007/3-540-46117-5","bibtex":"@inproceedings{Dyer_Plessl_Platzner_2002, series={Lecture Notes in Computer Science (LNCS)}, title={Partially Reconfigurable Cores for Xilinx Virtex}, volume={2438}, DOI={10.1007/3-540-46117-5}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Dyer, Matthias and Plessl, Christian and Platzner, Marco}, year={2002}, pages={292–301}, collection={Lecture Notes in Computer Science (LNCS)} }","mla":"Dyer, Matthias, et al. “Partially Reconfigurable Cores for Xilinx Virtex.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), vol. 2438, Springer, 2002, pp. 292–301, doi:10.1007/3-540-46117-5."},"page":"292-301","series_title":"Lecture Notes in Computer Science (LNCS)","doi":"10.1007/3-540-46117-5","intvolume":" 2438","_id":"2424","date_updated":"2022-01-06T06:56:13Z"},{"citation":{"mla":"Plessl, Christian, and Marco Platzner. “Custom Computing Machines for the Set Covering Problem.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2002, pp. 163–72, doi:10.1109/FPGA.2002.1106671.","bibtex":"@inproceedings{Plessl_Platzner_2002, title={Custom Computing Machines for the Set Covering Problem}, DOI={10.1109/FPGA.2002.1106671}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2002}, pages={163–172} }","chicago":"Plessl, Christian, and Marco Platzner. “Custom Computing Machines for the Set Covering Problem.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 163–72. IEEE Computer Society, 2002. https://doi.org/10.1109/FPGA.2002.1106671.","apa":"Plessl, C., & Platzner, M. (2002). Custom Computing Machines for the Set Covering Problem. In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) (pp. 163–172). IEEE Computer Society. https://doi.org/10.1109/FPGA.2002.1106671","ama":"Plessl C, Platzner M. Custom Computing Machines for the Set Covering Problem. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society; 2002:163-172. doi:10.1109/FPGA.2002.1106671","ieee":"C. Plessl and M. Platzner, “Custom Computing Machines for the Set Covering Problem,” in Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2002, pp. 163–172.","short":"C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2002, pp. 163–172."},"year":"2002","type":"conference","page":"163-172","doi":"10.1109/FPGA.2002.1106671","_id":"2425","date_updated":"2022-01-06T06:56:13Z","status":"public","date_created":"2018-04-17T15:15:44Z","author":[{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"IEEE Computer Society","publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","department":[{"_id":"518"},{"_id":"78"}],"title":"Custom Computing Machines for the Set Covering Problem","user_id":"24135","abstract":[{"text":" We present instance-specific custom computing machines for the set covering problem. Four accelerator architectures are developed that implement branch \\& bound in 3-valued logic and many of the deduction techniques found in software solvers. We use set covering benchmarks from two-level logic minimization and Steiner triple systems to derive and discuss experimental results. The resulting raw speedups are in the order of four magnitudes on average. Finally, we propose a hybrid solver architecture that combines the raw speed of instance-specific reconfigurable hardware with flexible bounding schemes implemented in software. ","lang":"eng"}]},{"_id":"2428","date_updated":"2022-01-06T06:56:17Z","page":"85-91","year":"2001","citation":{"bibtex":"@inproceedings{Plessl_Platzner_2001, title={Instance-Specific Accelerators for Minimum Covering}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Plessl, Christian and Platzner, Marco}, year={2001}, pages={85–91} }","mla":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2001, pp. 85–91.","chicago":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 85–91. CSREA Press, 2001.","apa":"Plessl, C., & Platzner, M. (2001). Instance-Specific Accelerators for Minimum Covering. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 85–91). CSREA Press.","ama":"Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2001:85-91.","ieee":"C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2001, pp. 85–91.","short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2001, pp. 85–91."},"type":"conference","title":"Instance-Specific Accelerators for Minimum Covering","user_id":"24135","abstract":[{"text":" In this paper we present instance-specific accelerators for minimum-cost covering problems. We first define the covering problem and discuss a branch&bound algorithm to solve it. Then we describe an instance-specific hardware architecture that implements branch&bound in 3-valued logic and uses reduction techniques usually found in software solvers. Results for small unate covering problems reveal significant raw speedups. ","lang":"eng"}],"date_created":"2018-04-17T15:39:17Z","status":"public","publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"518"},{"_id":"78"}],"keyword":["minimum covering","accelerator","funding-sundance"],"author":[{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"CSREA Press"},{"status":"public","date_created":"2018-04-17T15:43:29Z","author":[{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"last_name":"Wilde","full_name":"Wilde, Erik","first_name":"Erik"}],"publisher":"Heise Verlag","department":[{"_id":"518"}],"publication":"iX","title":"Server-Side-Techniken im Web – ein Überblick","user_id":"24135","type":"journal_article","citation":{"apa":"Plessl, C., & Wilde, E. (2001). Server-Side-Techniken im Web – ein Überblick. IX, 88–93.","ama":"Plessl C, Wilde E. Server-Side-Techniken im Web – ein Überblick. iX. 2001:88-93.","chicago":"Plessl, Christian, and Erik Wilde. “Server-Side-Techniken Im Web – Ein Überblick.” IX, 2001, 88–93.","bibtex":"@article{Plessl_Wilde_2001, title={Server-Side-Techniken im Web – ein Überblick}, journal={iX}, publisher={Heise Verlag}, author={Plessl, Christian and Wilde, Erik}, year={2001}, pages={88–93} }","mla":"Plessl, Christian, and Erik Wilde. “Server-Side-Techniken Im Web – Ein Überblick.” IX, Heise Verlag, 2001, pp. 88–93.","short":"C. Plessl, E. Wilde, IX (2001) 88–93.","ieee":"C. Plessl and E. Wilde, “Server-Side-Techniken im Web – ein Überblick,” iX, pp. 88–93, 2001."},"year":"2001","page":"88-93","date_updated":"2022-01-06T06:56:17Z","_id":"2429"},{"user_id":"24135","title":"Reconfigurable Accelerators for Minimum Covering","abstract":[{"text":"In this report the design and implementation of an instance-specific accelerator for solving minimum covering problems will be presented. After an introduction to configurable computing in general, the minimum covering problem is defined and a branch and bound algorithm to solve it in software is presented. The remainder of the report shows how this branch and bound algorithm can be adopted to hardware. Specifically it is stressed how the various sophisticated strategies for deducing conditions for variables used by software solvers can be adopted to hardware and how a system which uses 3-valued logic to solve this problem can be designed. In addition to these considerations focusing on the architecture of the system, some important details of the actual implementation are given. A prototype has been implemented for showing the feasibility of the concept and for gaining information about speed and size of the hardware implementation. Cycle-accurate simulations for a set of benchmark problems have been done for determining the performance of the accelerator. The speed of the resulting accelerators has been compared to the time a reference software solver (espresso) needs and the resulting speedups have been calculated. I have shown that a raw speedup of several orders of maginitude can be achieved for many problems; for some problems no speedup is achieved yet. After a discussion of the results, ideas for future work are presented.","lang":"eng"}],"date_created":"2018-04-17T15:47:26Z","status":"public","department":[{"_id":"518"}],"author":[{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"publisher":"Computer Engineering and Networks Lab, ETH Zurich, Switzerland","date_updated":"2022-01-06T06:56:17Z","_id":"2430","type":"mastersthesis","year":"2001","citation":{"mla":"Plessl, Christian. Reconfigurable Accelerators for Minimum Covering. Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2001.","bibtex":"@book{Plessl_2001, title={Reconfigurable Accelerators for Minimum Covering}, publisher={Computer Engineering and Networks Lab, ETH Zurich, Switzerland}, author={Plessl, Christian}, year={2001} }","apa":"Plessl, C. (2001). Reconfigurable Accelerators for Minimum Covering. Computer Engineering and Networks Lab, ETH Zurich, Switzerland.","ama":"Plessl C. Reconfigurable Accelerators for Minimum Covering. Computer Engineering and Networks Lab, ETH Zurich, Switzerland; 2001.","chicago":"Plessl, Christian. Reconfigurable Accelerators for Minimum Covering. Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2001.","ieee":"C. Plessl, Reconfigurable Accelerators for Minimum Covering. Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2001.","short":"C. Plessl, Reconfigurable Accelerators for Minimum Covering, Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2001."}},{"doi":"10.1117/12.434376","_id":"2432","date_updated":"2022-01-06T06:56:17Z","intvolume":" 4525","page":"135-146","citation":{"bibtex":"@inproceedings{Enzler_Platzner_Plessl_Thiele_Tröster_2001, series={Proc. SPIE}, title={Reconfigurable Processors for Handhelds and Wearables: Application Analysis}, volume={4525}, DOI={10.1117/12.434376}, booktitle={Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III}, author={Enzler, Rolf and Platzner, Marco and Plessl, Christian and Thiele, Lothar and Tröster, Gerhard}, year={2001}, pages={135–146}, collection={Proc. SPIE} }","mla":"Enzler, Rolf, et al. “Reconfigurable Processors for Handhelds and Wearables: Application Analysis.” Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, vol. 4525, 2001, pp. 135–46, doi:10.1117/12.434376.","apa":"Enzler, R., Platzner, M., Plessl, C., Thiele, L., & Tröster, G. (2001). Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III (Vol. 4525, pp. 135–146). https://doi.org/10.1117/12.434376","ama":"Enzler R, Platzner M, Plessl C, Thiele L, Tröster G. Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In: Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III. Vol 4525. Proc. SPIE. ; 2001:135-146. doi:10.1117/12.434376","chicago":"Enzler, Rolf, Marco Platzner, Christian Plessl, Lothar Thiele, and Gerhard Tröster. “Reconfigurable Processors for Handhelds and Wearables: Application Analysis.” In Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, 4525:135–46. Proc. SPIE, 2001. https://doi.org/10.1117/12.434376.","ieee":"R. Enzler, M. Platzner, C. Plessl, L. Thiele, and G. Tröster, “Reconfigurable Processors for Handhelds and Wearables: Application Analysis,” in Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, 2001, vol. 4525, pp. 135–146.","short":"R. Enzler, M. Platzner, C. Plessl, L. Thiele, G. Tröster, in: Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, 2001, pp. 135–146."},"year":"2001","type":"conference","series_title":"Proc. SPIE","title":"Reconfigurable Processors for Handhelds and Wearables: Application Analysis","user_id":"24135","abstract":[{"lang":"eng","text":"In this paper, we present the analysis of applications from the domain of handheld and wearable computing. This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurable processors. We discuss the selection of representative benchmarks for handhelds and wearables and group the applications into multimedia, communications, and cryptography programs. We simulate the applications on a cycle-accurate processor simulator and gather statistical data such as instruction mix, cache hit rates and memory requirements for an embedded processor model. A breakdown of the executed cycles into different functions identifies the most compute-intensive code sections - the kernels. Then, we analyze the applications and discuss parameters that strongly influence the design of dynamically reconfigurable processors. Finally, we outline the construction of a parameterizable simulation model for a reconfigurable unit that is attached to a processor core."}],"volume":4525,"date_created":"2018-04-17T15:51:39Z","status":"public","publication":"Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III","department":[{"_id":"518"},{"_id":"78"}],"keyword":["benchmark"],"author":[{"full_name":"Enzler, Rolf","first_name":"Rolf","last_name":"Enzler"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"last_name":"Thiele","full_name":"Thiele, Lothar","first_name":"Lothar"},{"first_name":"Gerhard","full_name":"Tröster, Gerhard","last_name":"Tröster"}]},{"title":"Hardware/Software Codesign in Speech Compression Applications","user_id":"24135","author":[{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"first_name":"Simon","full_name":"Maurer, Simon","last_name":"Maurer"}],"publisher":"Computer Engineering and Networks Lab, ETH Zurich, Switzerland","department":[{"_id":"518"}],"keyword":["co-design","speech processing"],"status":"public","date_created":"2018-04-17T15:56:00Z","_id":"2433","date_updated":"2022-01-06T06:56:17Z","type":"mastersthesis","year":"2000","citation":{"ieee":"C. Plessl and S. Maurer, Hardware/Software Codesign in Speech Compression Applications. Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2000.","short":"C. Plessl, S. Maurer, Hardware/Software Codesign in Speech Compression Applications, Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2000.","bibtex":"@book{Plessl_Maurer_2000, title={Hardware/Software Codesign in Speech Compression Applications}, publisher={Computer Engineering and Networks Lab, ETH Zurich, Switzerland}, author={Plessl, Christian and Maurer, Simon}, year={2000} }","mla":"Plessl, Christian, and Simon Maurer. Hardware/Software Codesign in Speech Compression Applications. Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2000.","ama":"Plessl C, Maurer S. Hardware/Software Codesign in Speech Compression Applications. Computer Engineering and Networks Lab, ETH Zurich, Switzerland; 2000.","apa":"Plessl, C., & Maurer, S. (2000). Hardware/Software Codesign in Speech Compression Applications. Computer Engineering and Networks Lab, ETH Zurich, Switzerland.","chicago":"Plessl, Christian, and Simon Maurer. Hardware/Software Codesign in Speech Compression Applications. Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2000."}}]