[{"place":"Cham","title":"Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"date_updated":"2023-09-26T13:34:08Z","doi":"10.1007/978-3-319-05960-0_13","series_title":"Lecture Notes in Computer Science (LNCS)","language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties."}],"ddc":["040"],"user_id":"15278","publisher":"Springer International Publishing","quality_controlled":"1","author":[{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","last_name":"Vaz","id":"30332"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"publication":"Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)","file_date_updated":"2018-03-20T07:02:02Z","file":[{"success":1,"relation":"main_file","date_updated":"2018-03-20T07:02:02Z","content_type":"application/pdf","file_id":"1387","creator":"florida","file_size":330193,"access_level":"closed","file_name":"388-plessl14_arc.pdf","date_created":"2018-03-20T07:02:02Z"}],"volume":8405,"has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:07Z","intvolume":" 8405","_id":"388","year":"2014","citation":{"chicago":"Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 8405:144–55. Lecture Notes in Computer Science (LNCS). Cham: Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-05960-0_13.","ama":"Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. In: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC). Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International Publishing; 2014:144-155. doi:10.1007/978-3-319-05960-0_13","apa":"Kenter, T., Vaz, G. F., & Plessl, C. (2014). Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 8405, 144–155. https://doi.org/10.1007/978-3-319-05960-0_13","bibtex":"@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer}, volume={8405}, DOI={10.1007/978-3-319-05960-0_13}, booktitle={Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)}, publisher={Springer International Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian}, year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)} }","mla":"Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:10.1007/978-3-319-05960-0_13.","short":"T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer International Publishing, Cham, 2014, pp. 144–155.","ieee":"T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer,” in Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 2014, vol. 8405, pp. 144–155, doi: 10.1007/978-3-319-05960-0_13."},"type":"conference","page":"144-155"},{"ddc":["040"],"user_id":"15278","abstract":[{"lang":"eng","text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices."}],"volume":38,"date_created":"2017-10-17T12:42:02Z","status":"public","has_accepted_license":"1","publication":"Microprocessors and Microsystems","file_date_updated":"2018-03-20T07:20:31Z","publisher":"Elsevier","author":[{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"full_name":"Hangmann, Hendrik","first_name":"Hendrik","last_name":"Hangmann"},{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","file":[{"content_type":"application/pdf","date_updated":"2018-03-20T07:20:31Z","success":1,"relation":"main_file","file_size":1499996,"file_id":"1408","creator":"florida","access_level":"closed","file_name":"363-plessl13_micpro.pdf","date_created":"2018-03-20T07:20:31Z"}],"issue":"8, Part B","intvolume":" 38","_id":"363","page":"911-919","type":"journal_article","citation":{"ieee":"A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl, “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators,” Microprocessors and Microsystems, vol. 38, no. 8, Part B, pp. 911–919, 2014, doi: 10.1016/j.micpro.2013.12.001.","short":"A. Agne, H. Hangmann, M. Happe, M. Platzner, C. Plessl, Microprocessors and Microsystems 38 (2014) 911–919.","mla":"Agne, Andreas, et al. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” Microprocessors and Microsystems, vol. 38, no. 8, Part B, Elsevier, 2014, pp. 911–19, doi:10.1016/j.micpro.2013.12.001.","bibtex":"@article{Agne_Hangmann_Happe_Platzner_Plessl_2014, title={Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators}, volume={38}, DOI={10.1016/j.micpro.2013.12.001}, number={8, Part B}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco and Plessl, Christian}, year={2014}, pages={911–919} }","ama":"Agne A, Hangmann H, Happe M, Platzner M, Plessl C. Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems. 2014;38(8, Part B):911-919. doi:10.1016/j.micpro.2013.12.001","apa":"Agne, A., Hangmann, H., Happe, M., Platzner, M., & Plessl, C. (2014). Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems, 38(8, Part B), 911–919. https://doi.org/10.1016/j.micpro.2013.12.001","chicago":"Agne, Andreas, Hendrik Hangmann, Markus Happe, Marco Platzner, and Christian Plessl. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” Microprocessors and Microsystems 38, no. 8, Part B (2014): 911–19. https://doi.org/10.1016/j.micpro.2013.12.001."},"year":"2014","title":"Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1016/j.micpro.2013.12.001","date_updated":"2023-09-26T13:33:06Z","language":[{"iso":"eng"}]},{"publisher":"IEEE","author":[{"first_name":"Heinrich","full_name":"Riebler, Heinrich","last_name":"Riebler","id":"8961"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Sorge","full_name":"Sorge, Christoph","first_name":"Christoph"}],"quality_controlled":"1","publication":"Proceedings of Field-Programmable Custom Computing Machines (FCCM)","keyword":["coldboot"],"file_date_updated":"2018-03-20T07:14:20Z","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-20T07:14:20Z","creator":"florida","file_id":"1397","file_size":1003907,"access_level":"closed","file_name":"377-FCCM14.pdf","date_created":"2018-03-20T07:14:20Z"}],"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:05Z","abstract":[{"lang":"eng","text":"In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates."}],"ddc":["040"],"user_id":"15278","year":"2014","type":"conference","citation":{"short":"H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.","ieee":"H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules from Decayed Memory with FPGAs,” in Proceedings of Field-Programmable Custom Computing Machines (FCCM), 2014, pp. 222–229, doi: 10.1109/FCCM.2014.67.","chicago":"Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–29. IEEE, 2014. https://doi.org/10.1109/FCCM.2014.67.","apa":"Riebler, H., Kenter, T., Plessl, C., & Sorge, C. (2014). Reconstructing AES Key Schedules from Decayed Memory with FPGAs. Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–229. https://doi.org/10.1109/FCCM.2014.67","ama":"Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from Decayed Memory with FPGAs. In: Proceedings of Field-Programmable Custom Computing Machines (FCCM). IEEE; 2014:222-229. doi:10.1109/FCCM.2014.67","bibtex":"@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing AES Key Schedules from Decayed Memory with FPGAs}, DOI={10.1109/FCCM.2014.67}, booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian and Sorge, Christoph}, year={2014}, pages={222–229} }","mla":"Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–29, doi:10.1109/FCCM.2014.67."},"page":"222-229","_id":"377","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"title":"Reconstructing AES Key Schedules from Decayed Memory with FPGAs","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:33:50Z","doi":"10.1109/FCCM.2014.67"},{"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:03Z","volume":7,"file":[{"creator":"florida","file_id":"1406","file_size":916052,"relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-03-20T07:19:19Z","date_created":"2018-03-20T07:19:19Z","file_name":"365-plessl14_trets_01.pdf","access_level":"closed"}],"quality_controlled":"1","publisher":"ACM","author":[{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"full_name":"Lösch, Achim","first_name":"Achim","id":"43646","last_name":"Lösch"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publication":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","file_date_updated":"2018-03-20T07:19:19Z","user_id":"15278","ddc":["040"],"abstract":[{"text":"Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems.","lang":"eng"}],"type":"journal_article","citation":{"ieee":"A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-awareness as a Model for Designing and Operating Heterogeneous Multicores,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, Art. no. 13, 2014, doi: 10.1145/2617596.","short":"A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (2014).","mla":"Agne, Andreas, et al. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, 13, ACM, 2014, doi:10.1145/2617596.","bibtex":"@article{Agne_Happe_Lösch_Plessl_Platzner_2014, title={Self-awareness as a Model for Designing and Operating Heterogeneous Multicores}, volume={7}, DOI={10.1145/2617596}, number={213}, journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={ACM}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2014} }","chicago":"Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7, no. 2 (2014). https://doi.org/10.1145/2617596.","apa":"Agne, A., Happe, M., Lösch, A., Plessl, C., & Platzner, M. (2014). Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 7(2), Article 13. https://doi.org/10.1145/2617596","ama":"Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. ACM Transactions on Reconfigurable Technology and Systems (TRETS). 2014;7(2). doi:10.1145/2617596"},"year":"2014","issue":"2","article_number":"13","intvolume":" 7","_id":"365","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"department":[{"_id":"27"},{"_id":"78"},{"_id":"518"}],"title":"Self-awareness as a Model for Designing and Operating Heterogeneous Multicores","language":[{"iso":"eng"}],"doi":"10.1145/2617596","date_updated":"2023-09-26T13:33:31Z"},{"language":[{"iso":"eng"}],"doi":"10.1109/MM.2013.110","date_updated":"2023-09-26T13:32:31Z","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","grant_number":"257906","name":"Engineering Proprioception in Computing Systems"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"ReconOS - An Operating System Approach for Reconfigurable Computing","page":"60-71","year":"2014","type":"journal_article","citation":{"bibtex":"@article{Agne_Happe_Keller_Lübbers_Plattner_Platzner_Plessl_2014, title={ReconOS - An Operating System Approach for Reconfigurable Computing}, volume={34}, DOI={10.1109/MM.2013.110}, number={1}, journal={IEEE Micro}, publisher={IEEE}, author={Agne, Andreas and Happe, Markus and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco and Plessl, Christian}, year={2014}, pages={60–71} }","mla":"Agne, Andreas, et al. “ReconOS - An Operating System Approach for Reconfigurable Computing.” IEEE Micro, vol. 34, no. 1, IEEE, 2014, pp. 60–71, doi:10.1109/MM.2013.110.","apa":"Agne, A., Happe, M., Keller, A., Lübbers, E., Plattner, B., Platzner, M., & Plessl, C. (2014). ReconOS - An Operating System Approach for Reconfigurable Computing. IEEE Micro, 34(1), 60–71. https://doi.org/10.1109/MM.2013.110","ama":"Agne A, Happe M, Keller A, et al. ReconOS - An Operating System Approach for Reconfigurable Computing. IEEE Micro. 2014;34(1):60-71. doi:10.1109/MM.2013.110","chicago":"Agne, Andreas, Markus Happe, Ariane Keller, Enno Lübbers, Bernhard Plattner, Marco Platzner, and Christian Plessl. “ReconOS - An Operating System Approach for Reconfigurable Computing.” IEEE Micro 34, no. 1 (2014): 60–71. https://doi.org/10.1109/MM.2013.110.","ieee":"A. Agne et al., “ReconOS - An Operating System Approach for Reconfigurable Computing,” IEEE Micro, vol. 34, no. 1, pp. 60–71, 2014, doi: 10.1109/MM.2013.110.","short":"A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl, IEEE Micro 34 (2014) 60–71."},"issue":"1","_id":"328","intvolume":" 34","date_created":"2017-10-17T12:41:55Z","status":"public","has_accepted_license":"1","volume":34,"file":[{"date_updated":"2018-03-20T07:31:40Z","content_type":"application/pdf","success":1,"relation":"main_file","file_size":1877185,"creator":"florida","file_id":"1426","access_level":"closed","file_name":"328-plessl14_micro_01.pdf","date_created":"2018-03-20T07:31:40Z"}],"publication":"IEEE Micro","file_date_updated":"2018-03-20T07:31:40Z","author":[{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"last_name":"Keller","first_name":"Ariane","full_name":"Keller, Ariane"},{"last_name":"Lübbers","first_name":"Enno","full_name":"Lübbers, Enno"},{"last_name":"Plattner","full_name":"Plattner, Bernhard","first_name":"Bernhard"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"publisher":"IEEE","quality_controlled":"1","user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications"}]},{"year":"2014","citation":{"bibtex":"@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014, title={Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach}, DOI={10.1109/ISPA.2014.27}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149} }","mla":"C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–49, doi:10.1109/ISPA.2014.27.","ama":"C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. In: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA). IEEE; 2014:142-149. doi:10.1109/ISPA.2014.27","apa":"C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G. F., D. Santambrogio, M., & Bolchini, C. (2014). Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–149. https://doi.org/10.1109/ISPA.2014.27","chicago":"C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl, Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” In Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–49. IEEE, 2014. https://doi.org/10.1109/ISPA.2014.27.","ieee":"G. C. Durelli et al., “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach,” in Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 2014, pp. 142–149, doi: 10.1109/ISPA.2014.27.","short":"G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–149."},"type":"conference","page":"142-149","language":[{"iso":"eng"}],"_id":"1778","date_updated":"2023-09-26T13:35:40Z","doi":"10.1109/ISPA.2014.27","author":[{"last_name":"C. Durelli","first_name":"Gianluca","full_name":"C. Durelli, Gianluca"},{"first_name":"Marcello","full_name":"Pogliani, Marcello","last_name":"Pogliani"},{"last_name":"Miele","first_name":"Antonio","full_name":"Miele, Antonio"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","id":"30332","last_name":"Vaz"},{"full_name":"D. Santambrogio, Marco","first_name":"Marco","last_name":"D. Santambrogio"},{"full_name":"Bolchini, Cristiana","first_name":"Cristiana","last_name":"Bolchini"}],"quality_controlled":"1","publisher":"IEEE","publication":"Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"status":"public","date_created":"2018-03-26T13:40:14Z","project":[{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"title":"Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach","user_id":"15278"},{"title":"Deferring Accelerator Offloading Decisions to Application Runtime","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1109/ReConFig.2014.7032509","date_updated":"2023-09-26T13:37:02Z","language":[{"iso":"eng"}],"ddc":["040"],"user_id":"15278","abstract":[{"lang":"eng","text":"Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes."}],"date_created":"2017-10-17T12:42:17Z","has_accepted_license":"1","status":"public","file_date_updated":"2018-03-16T11:29:52Z","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","publisher":"IEEE","author":[{"full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","id":"30332","last_name":"Vaz"},{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"quality_controlled":"1","file":[{"access_level":"closed","date_created":"2018-03-16T11:29:52Z","file_name":"439-plessl14a_reconfig.pdf","content_type":"application/pdf","date_updated":"2018-03-16T11:29:52Z","relation":"main_file","success":1,"file_size":557362,"creator":"florida","file_id":"1353"}],"_id":"439","page":"1-8","year":"2014","type":"conference","citation":{"chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Deferring Accelerator Offloading Decisions to Application Runtime.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032509.","ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions to Application Runtime. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509","apa":"Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2014). Deferring Accelerator Offloading Decisions to Application Runtime. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032509","mla":"Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application Runtime.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509.","bibtex":"@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator Offloading Decisions to Application Runtime}, DOI={10.1109/ReConFig.2014.7032509}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading Decisions to Application Runtime,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032509."}},{"abstract":[{"text":"Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design.","lang":"eng"}],"ddc":["040"],"user_id":"15278","file_date_updated":"2018-03-16T11:37:42Z","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","publisher":"IEEE","author":[{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"last_name":"Schmitz","first_name":"Henning","full_name":"Schmitz, Henning"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"quality_controlled":"1","file":[{"file_name":"406-ReConFig14.pdf","date_created":"2018-03-16T11:37:42Z","access_level":"closed","file_size":932852,"creator":"florida","file_id":"1366","date_updated":"2018-03-16T11:37:42Z","content_type":"application/pdf","success":1,"relation":"main_file"}],"date_created":"2017-10-17T12:42:11Z","has_accepted_license":"1","status":"public","_id":"406","page":"1-8","year":"2014","citation":{"short":"T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High Accuracy Stereo-Matching,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032535.","ama":"Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy Stereo-Matching. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032535","apa":"Kenter, T., Schmitz, H., & Plessl, C. (2014). Kernel-Centric Acceleration of High Accuracy Stereo-Matching. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032535","chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032535.","mla":"Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535.","bibtex":"@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration of High Accuracy Stereo-Matching}, DOI={10.1109/ReConFig.2014.7032535}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2014}, pages={1–8} }"},"type":"conference","title":"Kernel-Centric Acceleration of High Accuracy Stereo-Matching","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"date_updated":"2023-09-26T13:36:40Z","doi":"10.1109/ReConFig.2014.7032535","language":[{"iso":"eng"}]},{"doi":"10.1007/978-3-319-05960-0_38","_id":"1780","date_updated":"2023-09-26T13:36:20Z","type":"conference","year":"2014","citation":{"bibtex":"@inproceedings{C. Durelli_Copolla_Djafarian_Koranaros_Miele_Paolino_Pell_Plessl_D. Santambrogio_Bolchini_2014, title={SAVE: Towards efficient resource management in heterogeneous system architectures}, DOI={10.1007/978-3-319-05960-0_38}, booktitle={Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)}, publisher={Springer}, author={C. Durelli, Gianluca and Copolla, Marcello and Djafarian, Karim and Koranaros, George and Miele, Antonio and Paolino, Michele and Pell, Oliver and Plessl, Christian and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014} }","mla":"C. Durelli, Gianluca, et al. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014, doi:10.1007/978-3-319-05960-0_38.","chicago":"C. Durelli, Gianluca, Marcello Copolla, Karim Djafarian, George Koranaros, Antonio Miele, Michele Paolino, Oliver Pell, Christian Plessl, Marco D. Santambrogio, and Cristiana Bolchini. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” In Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer, 2014. https://doi.org/10.1007/978-3-319-05960-0_38.","apa":"C. Durelli, G., Copolla, M., Djafarian, K., Koranaros, G., Miele, A., Paolino, M., Pell, O., Plessl, C., D. Santambrogio, M., & Bolchini, C. (2014). SAVE: Towards efficient resource management in heterogeneous system architectures. Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). https://doi.org/10.1007/978-3-319-05960-0_38","ama":"C. Durelli G, Copolla M, Djafarian K, et al. SAVE: Towards efficient resource management in heterogeneous system architectures. In: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer; 2014. doi:10.1007/978-3-319-05960-0_38","ieee":"G. C. Durelli et al., “SAVE: Towards efficient resource management in heterogeneous system architectures,” 2014, doi: 10.1007/978-3-319-05960-0_38.","short":"G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino, O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014."},"language":[{"iso":"eng"}],"title":"SAVE: Towards efficient resource management in heterogeneous system architectures","user_id":"15278","status":"public","date_created":"2018-03-26T13:45:35Z","project":[{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"quality_controlled":"1","author":[{"full_name":"C. Durelli, Gianluca","first_name":"Gianluca","last_name":"C. Durelli"},{"first_name":"Marcello","full_name":"Copolla, Marcello","last_name":"Copolla"},{"last_name":"Djafarian","full_name":"Djafarian, Karim","first_name":"Karim"},{"last_name":"Koranaros","first_name":"George","full_name":"Koranaros, George"},{"last_name":"Miele","first_name":"Antonio","full_name":"Miele, Antonio"},{"last_name":"Paolino","full_name":"Paolino, Michele","first_name":"Michele"},{"last_name":"Pell","full_name":"Pell, Oliver","first_name":"Oliver"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"last_name":"D. Santambrogio","first_name":"Marco","full_name":"D. Santambrogio, Marco"},{"last_name":"Bolchini","first_name":"Cristiana","full_name":"Bolchini, Cristiana"}],"publisher":"Springer","publication":"Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}]},{"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:35:58Z","doi":"10.1145/2641361.2641372","department":[{"_id":"27"},{"_id":"518"},{"_id":"61"},{"_id":"78"}],"publication_identifier":{"issn":["0163-5964"]},"title":"Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers","page":"65-70","year":"2014","type":"journal_article","citation":{"short":"H. Giefers, C. Plessl, J. Förstner, ACM SIGARCH Computer Architecture News 41 (2014) 65–70.","ieee":"H. Giefers, C. Plessl, and J. Förstner, “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers,” ACM SIGARCH Computer Architecture News, vol. 41, no. 5, pp. 65–70, 2014, doi: 10.1145/2641361.2641372.","apa":"Giefers, H., Plessl, C., & Förstner, J. (2014). Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH Computer Architecture News, 41(5), 65–70. https://doi.org/10.1145/2641361.2641372","ama":"Giefers H, Plessl C, Förstner J. Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH Computer Architecture News. 2014;41(5):65-70. doi:10.1145/2641361.2641372","chicago":"Giefers, Heiner, Christian Plessl, and Jens Förstner. “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” ACM SIGARCH Computer Architecture News 41, no. 5 (2014): 65–70. https://doi.org/10.1145/2641361.2641372.","bibtex":"@article{Giefers_Plessl_Förstner_2014, title={Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers}, volume={41}, DOI={10.1145/2641361.2641372}, number={5}, journal={ACM SIGARCH Computer Architecture News}, publisher={ACM}, author={Giefers, Heiner and Plessl, Christian and Förstner, Jens}, year={2014}, pages={65–70} }","mla":"Giefers, Heiner, et al. “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” ACM SIGARCH Computer Architecture News, vol. 41, no. 5, ACM, 2014, pp. 65–70, doi:10.1145/2641361.2641372."},"_id":"1779","intvolume":" 41","issue":"5","keyword":["funding-maxup","tet_topic_hpc"],"publication":"ACM SIGARCH Computer Architecture News","publisher":"ACM","quality_controlled":"1","author":[{"full_name":"Giefers, Heiner","first_name":"Heiner","last_name":"Giefers"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"orcid":"0000-0001-7059-9862","full_name":"Förstner, Jens","first_name":"Jens","id":"158","last_name":"Förstner"}],"date_created":"2018-03-26T13:42:34Z","status":"public","volume":41,"user_id":"15278"},{"keyword":["coldboot"],"department":[{"_id":"27"},{"_id":"518"}],"publisher":"Universität Paderborn","author":[{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"}],"project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C1","_id":"13"},{"name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"}],"date_created":"2017-10-17T12:42:34Z","status":"public","user_id":"477","title":"Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs","language":[{"iso":"ger"}],"citation":{"short":"H. Riebler, Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs, Universität Paderborn, 2013.","ieee":"H. Riebler, Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Universität Paderborn, 2013.","chicago":"Riebler, Heinrich. Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Universität Paderborn, 2013.","apa":"Riebler, H. (2013). Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Universität Paderborn.","ama":"Riebler H. Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Universität Paderborn; 2013.","mla":"Riebler, Heinrich. Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Universität Paderborn, 2013.","bibtex":"@book{Riebler_2013, title={Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs}, publisher={Universität Paderborn}, author={Riebler, Heinrich}, year={2013} }"},"type":"mastersthesis","year":"2013","_id":"521","date_updated":"2022-01-06T07:01:46Z"},{"ddc":["040"],"user_id":"15278","abstract":[{"text":"Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES.","lang":"eng"}],"date_created":"2017-10-17T12:42:35Z","has_accepted_license":"1","status":"public","publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","file_date_updated":"2018-03-15T10:36:08Z","keyword":["coldboot"],"quality_controlled":"1","author":[{"first_name":"Heinrich","full_name":"Riebler, Heinrich","last_name":"Riebler","id":"8961"},{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"first_name":"Christoph","full_name":"Sorge, Christoph","last_name":"Sorge"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"publisher":"IEEE","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-15T10:36:08Z","creator":"florida","file_id":"1294","file_size":822680,"access_level":"closed","file_name":"528-plessl13_fpt.pdf","date_created":"2018-03-15T10:36:08Z"}],"_id":"528","page":"386-389","year":"2013","type":"conference","citation":{"chicago":"Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–89. IEEE, 2013. https://doi.org/10.1109/FPT.2013.6718394.","apa":"Riebler, H., Kenter, T., Sorge, C., & Plessl, C. (2013). FPGA-accelerated Key Search for Cold-Boot Attacks against AES. Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–389. https://doi.org/10.1109/FPT.2013.6718394","ama":"Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot Attacks against AES. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2013:386-389. doi:10.1109/FPT.2013.6718394","bibtex":"@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated Key Search for Cold-Boot Attacks against AES}, DOI={10.1109/FPT.2013.6718394}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge, Christoph and Plessl, Christian}, year={2013}, pages={386–389} }","mla":"Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–89, doi:10.1109/FPT.2013.6718394.","short":"H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389.","ieee":"H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search for Cold-Boot Attacks against AES,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2013, pp. 386–389, doi: 10.1109/FPT.2013.6718394."},"title":"FPGA-accelerated Key Search for Cold-Boot Attacks against AES","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"13","name":"SFB 901 - Subproject C1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1109/FPT.2013.6718394","date_updated":"2023-09-26T13:37:35Z","language":[{"iso":"eng"}]},{"ddc":["040"],"user_id":"15278","abstract":[{"lang":"eng","text":"In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas."}],"has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:30Z","author":[{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"first_name":"Peter","full_name":"Kling, Peter","last_name":"Kling"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"full_name":"Meyer auf der Heide, Friedhelm","first_name":"Friedhelm","id":"15523","last_name":"Meyer auf der Heide"}],"quality_controlled":"1","publisher":"IEEE","publication":"Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)","file_date_updated":"2018-03-15T13:38:56Z","file":[{"date_created":"2018-03-15T13:38:56Z","file_name":"505-Plessl13_seus.pdf","access_level":"closed","file_size":1040834,"file_id":"1308","creator":"florida","date_updated":"2018-03-15T13:38:56Z","content_type":"application/pdf","success":1,"relation":"main_file"}],"_id":"505","citation":{"chicago":"Happe, Markus, Peter Kling, Christian Plessl, Marco Platzner, and Friedhelm Meyer auf der Heide. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” In Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE, 2013. https://doi.org/10.1109/ISORC.2013.6913232.","ama":"Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. In: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE; 2013. doi:10.1109/ISORC.2013.6913232","apa":"Happe, M., Kling, P., Plessl, C., Platzner, M., & Meyer auf der Heide, F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). https://doi.org/10.1109/ISORC.2013.6913232","mla":"Happe, Markus, et al. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013, doi:10.1109/ISORC.2013.6913232.","bibtex":"@inproceedings{Happe_Kling_Plessl_Platzner_Meyer auf der Heide_2013, title={On-The-Fly Computing: A Novel Paradigm for Individualized IT Services}, DOI={10.1109/ISORC.2013.6913232}, booktitle={Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)}, publisher={IEEE}, author={Happe, Markus and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide, Friedhelm}, year={2013} }","short":"M. Happe, P. Kling, C. Plessl, M. Platzner, F. Meyer auf der Heide, in: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013.","ieee":"M. Happe, P. Kling, C. Plessl, M. Platzner, and F. Meyer auf der Heide, “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services,” 2013, doi: 10.1109/ISORC.2013.6913232."},"type":"conference","year":"2013","title":"On-The-Fly Computing: A Novel Paradigm for Individualized IT Services","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"}],"department":[{"_id":"63"},{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1109/ISORC.2013.6913232","date_updated":"2023-09-26T13:38:20Z","language":[{"iso":"eng"}]},{"publication_identifier":{"isbn":["978-0-7695-4979-8"]},"date_created":"2018-03-26T14:51:05Z","project":[{"name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A","_id":"30"}],"status":"public","publication":"Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"},{"_id":"63"}],"author":[{"first_name":"Tim","full_name":"Suess, Tim","last_name":"Suess"},{"full_name":"Schoenrock, Andrew","first_name":"Andrew","last_name":"Schoenrock"},{"first_name":"Sebastian","full_name":"Meisner, Sebastian","last_name":"Meisner"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"publisher":"IEEE Computer Society","quality_controlled":"1","title":"Parallel Macro Pipelining on the Intel SCC Many-Core Computer","user_id":"15278","place":"Washington, DC, USA","page":"64-73","type":"conference","year":"2013","citation":{"ama":"Suess T, Schoenrock A, Meisner S, Plessl C. Parallel Macro Pipelining on the Intel SCC Many-Core Computer. In: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE Computer Society; 2013:64-73. doi:10.1109/IPDPSW.2013.136","apa":"Suess, T., Schoenrock, A., Meisner, S., & Plessl, C. (2013). Parallel Macro Pipelining on the Intel SCC Many-Core Computer. Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. https://doi.org/10.1109/IPDPSW.2013.136","chicago":"Suess, Tim, Andrew Schoenrock, Sebastian Meisner, and Christian Plessl. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. Washington, DC, USA: IEEE Computer Society, 2013. https://doi.org/10.1109/IPDPSW.2013.136.","mla":"Suess, Tim, et al. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, 2013, pp. 64–73, doi:10.1109/IPDPSW.2013.136.","bibtex":"@inproceedings{Suess_Schoenrock_Meisner_Plessl_2013, place={Washington, DC, USA}, title={Parallel Macro Pipelining on the Intel SCC Many-Core Computer}, DOI={10.1109/IPDPSW.2013.136}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)}, publisher={IEEE Computer Society}, author={Suess, Tim and Schoenrock, Andrew and Meisner, Sebastian and Plessl, Christian}, year={2013}, pages={64–73} }","short":"T. Suess, A. Schoenrock, S. Meisner, C. Plessl, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, Washington, DC, USA, 2013, pp. 64–73.","ieee":"T. Suess, A. Schoenrock, S. Meisner, and C. Plessl, “Parallel Macro Pipelining on the Intel SCC Many-Core Computer,” in Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 2013, pp. 64–73, doi: 10.1109/IPDPSW.2013.136."},"language":[{"iso":"eng"}],"doi":"10.1109/IPDPSW.2013.136","_id":"1787","date_updated":"2023-09-26T13:38:05Z"},{"date_updated":"2022-01-06T06:54:44Z","_id":"2107","citation":{"ieee":"R. Grunzke et al., “A Data Driven Science Gateway for Computational Workflows,” in Proc. UNICORE Summit, 2012.","short":"R. Grunzke, G. Birkenheuer, D. Blunk, S. Breuers, A. Brinkmann, S. Gesing, S. Herres-Pawlis, O. Kohlbacher, J. Krüger, M. Kruse, R. Müller-Pfefferkorn, P. Schäfer, B. Schuller, T. Steinke, A. Zink, in: Proc. UNICORE Summit, 2012.","mla":"Grunzke, Richard, et al. “A Data Driven Science Gateway for Computational Workflows.” Proc. UNICORE Summit, 2012.","bibtex":"@inproceedings{Grunzke_Birkenheuer_Blunk_Breuers_Brinkmann_Gesing_Herres-Pawlis_Kohlbacher_Krüger_Kruse_et al._2012, title={A Data Driven Science Gateway for Computational Workflows}, booktitle={Proc. UNICORE Summit}, author={Grunzke, Richard and Birkenheuer, Georg and Blunk, Dirk and Breuers, Sebastian and Brinkmann, André and Gesing, Sandra and Herres-Pawlis, Sonja and Kohlbacher, Oliver and Krüger, Jens and Kruse, Martin and et al.}, year={2012} }","ama":"Grunzke R, Birkenheuer G, Blunk D, et al. A Data Driven Science Gateway for Computational Workflows. In: Proc. UNICORE Summit. ; 2012.","apa":"Grunzke, R., Birkenheuer, G., Blunk, D., Breuers, S., Brinkmann, A., Gesing, S., … Zink, A. (2012). A Data Driven Science Gateway for Computational Workflows. In Proc. UNICORE Summit.","chicago":"Grunzke, Richard, Georg Birkenheuer, Dirk Blunk, Sebastian Breuers, André Brinkmann, Sandra Gesing, Sonja Herres-Pawlis, et al. “A Data Driven Science Gateway for Computational Workflows.” In Proc. UNICORE Summit, 2012."},"year":"2012","type":"conference","title":"A Data Driven Science Gateway for Computational Workflows","user_id":"24135","author":[{"last_name":"Grunzke","first_name":"Richard","full_name":"Grunzke, Richard"},{"full_name":"Birkenheuer, Georg","first_name":"Georg","last_name":"Birkenheuer"},{"first_name":"Dirk","full_name":"Blunk, Dirk","last_name":"Blunk"},{"last_name":"Breuers","first_name":"Sebastian","full_name":"Breuers, Sebastian"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"},{"last_name":"Gesing","first_name":"Sandra","full_name":"Gesing, Sandra"},{"full_name":"Herres-Pawlis, Sonja","first_name":"Sonja","last_name":"Herres-Pawlis"},{"last_name":"Kohlbacher","first_name":"Oliver","full_name":"Kohlbacher, Oliver"},{"first_name":"Jens","full_name":"Krüger, Jens","last_name":"Krüger"},{"full_name":"Kruse, Martin","first_name":"Martin","last_name":"Kruse"},{"last_name":"Müller-Pfefferkorn","full_name":"Müller-Pfefferkorn, Ralph","first_name":"Ralph"},{"first_name":"Patrick","full_name":"Schäfer, Patrick","last_name":"Schäfer"},{"first_name":"Bernd","full_name":"Schuller, Bernd","last_name":"Schuller"},{"last_name":"Steinke","first_name":"Thomas","full_name":"Steinke, Thomas"},{"first_name":"Andreas","full_name":"Zink, Andreas","last_name":"Zink"}],"department":[{"_id":"27"},{"_id":"518"}],"publication":"Proc. UNICORE Summit","status":"public","date_created":"2018-03-29T15:06:46Z"},{"date_updated":"2022-01-06T07:02:44Z","_id":"587","citation":{"ieee":"C. Plessl, M. Platzner, A. Agne, M. Happe, and E. Lübbers, Programming models for reconfigurable heterogeneous multi-cores. Awareness Magazine, 2012.","short":"C. Plessl, M. Platzner, A. Agne, M. Happe, E. Lübbers, Programming Models for Reconfigurable Heterogeneous Multi-Cores, Awareness Magazine, 2012.","bibtex":"@book{Plessl_Platzner_Agne_Happe_Lübbers_2012, title={Programming models for reconfigurable heterogeneous multi-cores}, publisher={Awareness Magazine}, author={Plessl, Christian and Platzner, Marco and Agne, Andreas and Happe, Markus and Lübbers, Enno}, year={2012} }","mla":"Plessl, Christian, et al. Programming Models for Reconfigurable Heterogeneous Multi-Cores. Awareness Magazine, 2012.","apa":"Plessl, C., Platzner, M., Agne, A., Happe, M., & Lübbers, E. (2012). Programming models for reconfigurable heterogeneous multi-cores. Awareness Magazine.","ama":"Plessl C, Platzner M, Agne A, Happe M, Lübbers E. Programming Models for Reconfigurable Heterogeneous Multi-Cores. Awareness Magazine; 2012.","chicago":"Plessl, Christian, Marco Platzner, Andreas Agne, Markus Happe, and Enno Lübbers. Programming Models for Reconfigurable Heterogeneous Multi-Cores. Awareness Magazine, 2012."},"type":"misc","year":"2012","language":[{"iso":"eng"}],"title":"Programming models for reconfigurable heterogeneous multi-cores","ddc":["040"],"user_id":"398","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"}],"date_created":"2017-10-17T12:42:46Z","status":"public","has_accepted_license":"1","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"file_date_updated":"2018-03-15T08:37:02Z","publisher":"Awareness Magazine","author":[{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"last_name":"Lübbers","full_name":"Lübbers, Enno","first_name":"Enno"}],"file":[{"date_created":"2018-03-15T08:37:02Z","file_name":"587-2012_plessl_awareness_magazine.pdf","access_level":"closed","file_size":353057,"file_id":"1260","creator":"florida","date_updated":"2018-03-15T08:37:02Z","content_type":"application/pdf","success":1,"relation":"main_file"}]},{"page":"189-196","citation":{"ieee":"B. Meyer, J. Schumacher, C. Plessl, and J. Förstner, “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2012, pp. 189–196, doi: 10.1109/FPL.2012.6339370.","short":"B. Meyer, J. Schumacher, C. Plessl, J. Förstner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–196.","bibtex":"@inproceedings{Meyer_Schumacher_Plessl_Förstner_2012, title={Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?}, DOI={10.1109/FPL.2012.6339370}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Meyer, Björn and Schumacher, Jörn and Plessl, Christian and Förstner, Jens}, year={2012}, pages={189–196} }","mla":"Meyer, Björn, et al. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–96, doi:10.1109/FPL.2012.6339370.","chicago":"Meyer, Björn, Jörn Schumacher, Christian Plessl, and Jens Förstner. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–96. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370.","apa":"Meyer, B., Schumacher, J., Plessl, C., & Förstner, J. (2012). Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–196. https://doi.org/10.1109/FPL.2012.6339370","ama":"Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2012:189-196. doi:10.1109/FPL.2012.6339370"},"year":"2012","type":"conference","conference":{"name":"22nd International Conference on Field Programmable Logic and Applicaitons (FPL)"},"_id":"2106","date_created":"2018-03-29T15:04:25Z","status":"public","has_accepted_license":"1","file":[{"date_updated":"2019-02-13T09:04:46Z","content_type":"application/pdf","relation":"main_file","success":1,"file_size":2148787,"creator":"fossie","file_id":"7638","access_level":"closed","date_created":"2019-02-13T09:04:46Z","file_name":"2012-11 Meyer,Schumacher,Plessl,Förstner_Convey vector personalities-FPGA acceleratin with an openmp-like programming effort.pdf"}],"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","file_date_updated":"2019-02-13T09:04:46Z","keyword":["funding-upb-forschungspreis","funding-maxup","tet_topic_hpc"],"publisher":"IEEE","author":[{"full_name":"Meyer, Björn","first_name":"Björn","last_name":"Meyer"},{"last_name":"Schumacher","first_name":"Jörn","full_name":"Schumacher, Jörn"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"first_name":"Jens","orcid":"0000-0001-7059-9862","full_name":"Förstner, Jens","last_name":"Förstner","id":"158"}],"quality_controlled":"1","user_id":"15278","ddc":["000"],"abstract":[{"lang":"eng","text":"Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator.\r\nIn this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort\r\ncan actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like\r\nprogramming environment exists. As case study we use an application from computational nanophotonics. Our results\r\nshow that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view."}],"language":[{"iso":"eng"}],"doi":"10.1109/FPL.2012.6339370","date_updated":"2023-09-26T13:39:13Z","department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"title":"Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?"},{"status":"public","date_created":"2018-03-29T15:12:38Z","volume":36,"quality_controlled":"1","author":[{"full_name":"Schumacher, Tobias","first_name":"Tobias","last_name":"Schumacher"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publication":"Microprocessors and Microsystems","keyword":["funding-altera"],"user_id":"15278","type":"journal_article","year":"2012","citation":{"bibtex":"@article{Schumacher_Plessl_Platzner_2012, title={IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators}, volume={36}, DOI={10.1016/j.micpro.2011.04.002}, number={2}, journal={Microprocessors and Microsystems}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2012}, pages={110–126} }","mla":"Schumacher, Tobias, et al. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” Microprocessors and Microsystems, vol. 36, no. 2, 2012, pp. 110–26, doi:10.1016/j.micpro.2011.04.002.","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” Microprocessors and Microsystems 36, no. 2 (2012): 110–26. https://doi.org/10.1016/j.micpro.2011.04.002.","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2012). IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. Microprocessors and Microsystems, 36(2), 110–126. https://doi.org/10.1016/j.micpro.2011.04.002","ama":"Schumacher T, Plessl C, Platzner M. IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. Microprocessors and Microsystems. 2012;36(2):110-126. doi:10.1016/j.micpro.2011.04.002","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators,” Microprocessors and Microsystems, vol. 36, no. 2, pp. 110–126, 2012, doi: 10.1016/j.micpro.2011.04.002.","short":"T. Schumacher, C. Plessl, M. Platzner, Microprocessors and Microsystems 36 (2012) 110–126."},"page":"110-126","issue":"2","_id":"2108","intvolume":" 36","publication_identifier":{"issn":["0141-9331"]},"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators","language":[{"iso":"eng"}],"doi":"10.1016/j.micpro.2011.04.002","date_updated":"2023-09-26T13:39:30Z"},{"year":"2012","type":"conference","citation":{"chicago":"Happe, Markus, Hendrik Hangmann, Andreas Agne, and Christian Plessl. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416745.","ama":"Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416745","apa":"Happe, M., Hangmann, H., Agne, A., & Plessl, C. (2012). Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416745","mla":"Happe, Markus, et al. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416745.","bibtex":"@inproceedings{Happe_Hangmann_Agne_Plessl_2012, title={Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}, DOI={10.1109/ReConFig.2012.6416745}, booktitle={Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}, year={2012}, pages={1–8} }","short":"M. Happe, H. Hangmann, A. Agne, C. Plessl, in: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","ieee":"M. Happe, H. Hangmann, A. Agne, and C. Plessl, “Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators,” in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416745."},"page":"1-8","_id":"615","quality_controlled":"1","author":[{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"first_name":"Hendrik","full_name":"Hangmann, Hendrik","last_name":"Hangmann"},{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"publisher":"IEEE","publication":"Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-15T06:48:32Z","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-15T06:48:32Z","creator":"florida","file_id":"1246","file_size":730144,"access_level":"closed","file_name":"615-ReConFig12_01.pdf","date_created":"2018-03-15T06:48:32Z"}],"has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:51Z","abstract":[{"lang":"eng","text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices."}],"ddc":["040"],"user_id":"15278","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:42:26Z","doi":"10.1109/ReConFig.2012.6416745","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"title":"Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators"},{"title":"Pragma based parallelization - Trading hardware efficiency for ease of use?","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1109/ReConFig.2012.6416773","date_updated":"2023-09-26T13:41:08Z","language":[{"iso":"eng"}],"user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort."}],"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:47Z","file":[{"access_level":"closed","date_created":"2018-03-15T08:33:18Z","file_name":"591-ReConFig2012Kenter_Schmitz_Plessl.pdf","content_type":"application/pdf","date_updated":"2018-03-15T08:33:18Z","relation":"main_file","success":1,"file_size":371235,"file_id":"1257","creator":"florida"}],"quality_controlled":"1","author":[{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"last_name":"Schmitz","first_name":"Henning","full_name":"Schmitz, Henning"}],"publisher":"IEEE","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-15T08:33:18Z","_id":"591","citation":{"mla":"Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416773.","bibtex":"@inproceedings{Kenter_Plessl_Schmitz_2012, title={Pragma based parallelization - Trading hardware efficiency for ease of use?}, DOI={10.1109/ReConFig.2012.6416773}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Plessl, Christian and Schmitz, Henning}, year={2012}, pages={1–8} }","chicago":"Kenter, Tobias, Christian Plessl, and Henning Schmitz. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416773.","apa":"Kenter, T., Plessl, C., & Schmitz, H. (2012). Pragma based parallelization - Trading hardware efficiency for ease of use? Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416773","ama":"Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416773","ieee":"T. Kenter, C. Plessl, and H. Schmitz, “Pragma based parallelization - Trading hardware efficiency for ease of use?,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416773.","short":"T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8."},"type":"conference","year":"2012","page":"1-8"},{"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:41:36Z","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"31","grant_number":"257906","name":"Engineering Proprioception in Computing Systems"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Hardware/Software Platform for Self-aware Compute Nodes","page":"8-9","year":"2012","type":"conference","citation":{"short":"M. Happe, A. Agne, C. Plessl, M. Platzner, in: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","ieee":"M. Happe, A. Agne, C. Plessl, and M. Platzner, “Hardware/Software Platform for Self-aware Compute Nodes,” in Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","apa":"Happe, M., Agne, A., Plessl, C., & Platzner, M. (2012). Hardware/Software Platform for Self-aware Compute Nodes. Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9.","ama":"Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS). ; 2012:8-9.","chicago":"Happe, Markus, Andreas Agne, Christian Plessl, and Marco Platzner. “Hardware/Software Platform for Self-Aware Compute Nodes.” In Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9, 2012.","mla":"Happe, Markus, et al. “Hardware/Software Platform for Self-Aware Compute Nodes.” Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","bibtex":"@inproceedings{Happe_Agne_Plessl_Platzner_2012, title={Hardware/Software Platform for Self-aware Compute Nodes}, booktitle={Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}, author={Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}, year={2012}, pages={8–9} }"},"_id":"609","date_created":"2017-10-17T12:42:50Z","status":"public","has_accepted_license":"1","publication":"Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)","file_date_updated":"2018-03-15T08:14:17Z","author":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"quality_controlled":"1","file":[{"date_updated":"2018-03-15T08:14:17Z","content_type":"application/pdf","relation":"main_file","success":1,"file_size":146789,"file_id":"1249","creator":"florida","access_level":"closed","file_name":"609-happe12_fpl_awareness.pdf","date_created":"2018-03-15T08:14:17Z"}],"ddc":["040"],"user_id":"15278","abstract":[{"text":"Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method.","lang":"eng"}]},{"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:42:54Z","doi":"10.1109/HPCSim.2012.6266973","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"}],"title":"Turning control flow graphs into function calls: Code generation for heterogeneous architectures","page":"559-565","type":"conference","year":"2012","citation":{"bibtex":"@inproceedings{Barrio_Carreras_Sierra_Kenter_Plessl_2012, title={Turning control flow graphs into function calls: Code generation for heterogeneous architectures}, DOI={10.1109/HPCSim.2012.6266973}, booktitle={Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}, publisher={IEEE}, author={Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}, year={2012}, pages={559–565} }","mla":"Barrio, Pablo, et al. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–65, doi:10.1109/HPCSim.2012.6266973.","chicago":"Barrio, Pablo, Carlos Carreras, Roberto Sierra, Tobias Kenter, and Christian Plessl. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” In Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–65. IEEE, 2012. https://doi.org/10.1109/HPCSim.2012.6266973.","ama":"Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS). IEEE; 2012:559-565. doi:10.1109/HPCSim.2012.6266973","apa":"Barrio, P., Carreras, C., Sierra, R., Kenter, T., & Plessl, C. (2012). Turning control flow graphs into function calls: Code generation for heterogeneous architectures. Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–565. https://doi.org/10.1109/HPCSim.2012.6266973","ieee":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl, “Turning control flow graphs into function calls: Code generation for heterogeneous architectures,” in Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 2012, pp. 559–565, doi: 10.1109/HPCSim.2012.6266973.","short":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. Plessl, in: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–565."},"_id":"567","publication":"Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)","file_date_updated":"2018-03-15T10:20:24Z","quality_controlled":"1","publisher":"IEEE","author":[{"full_name":"Barrio, Pablo","first_name":"Pablo","last_name":"Barrio"},{"last_name":"Carreras","full_name":"Carreras, Carlos","first_name":"Carlos"},{"full_name":"Sierra, Roberto","first_name":"Roberto","last_name":"Sierra"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"file":[{"content_type":"application/pdf","date_updated":"2018-03-15T10:20:24Z","success":1,"relation":"main_file","file_size":288508,"creator":"florida","file_id":"1275","access_level":"closed","file_name":"567-ba-ca-12a.pdf","date_created":"2018-03-15T10:20:24Z"}],"date_created":"2017-10-17T12:42:42Z","has_accepted_license":"1","status":"public","abstract":[{"lang":"eng","text":"Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided."}],"ddc":["040"],"user_id":"15278"},{"citation":{"short":"C. Rüthing, M. Happe, A. Agne, C. Plessl, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–562.","ieee":"C. Rüthing, M. Happe, A. Agne, and C. Plessl, “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 2012, pp. 559–562, doi: 10.1109/FPL.2012.6339370.","chicago":"Rüthing, Christoph, Markus Happe, Andreas Agne, and Christian Plessl. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 559–62. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370.","ama":"Rüthing C, Happe M, Agne A, Plessl C. Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2012:559-562. doi:10.1109/FPL.2012.6339370","apa":"Rüthing, C., Happe, M., Agne, A., & Plessl, C. (2012). Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 559–562. https://doi.org/10.1109/FPL.2012.6339370","mla":"Rüthing, Christoph, et al. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–62, doi:10.1109/FPL.2012.6339370.","bibtex":"@inproceedings{Rüthing_Happe_Agne_Plessl_2012, title={Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs}, DOI={10.1109/FPL.2012.6339370}, booktitle={Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Rüthing, Christoph and Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2012}, pages={559–562} }"},"type":"conference","year":"2012","page":"559-562","_id":"612","author":[{"full_name":"Rüthing, Christoph","first_name":"Christoph","last_name":"Rüthing"},{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","publisher":"IEEE","file_date_updated":"2018-03-15T06:49:03Z","publication":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)","file":[{"creator":"florida","file_id":"1247","file_size":202923,"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-15T06:49:03Z","file_name":"612-ruething_fpl12.pdf","date_created":"2018-03-15T06:49:03Z","access_level":"closed"}],"has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:51Z","abstract":[{"text":"While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA.","lang":"eng"}],"ddc":["040"],"user_id":"15278","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:42:03Z","doi":"10.1109/FPL.2012.6339370","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","grant_number":"257906","name":"Engineering Proprioception in Computing Systems"}],"title":"Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs"},{"language":[{"iso":"eng"}],"type":"conference","citation":{"ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. In: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS). ; 2012.","apa":"Beisel, T., Wiersema, T., Plessl, C., & Brinkmann, A. (2012). Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS).","chicago":"Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” In Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","mla":"Beisel, Tobias, et al. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2012, title={Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux}, booktitle={Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2012} }","short":"T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux,” 2012."},"year":"2012","date_updated":"2023-09-26T13:40:17Z","_id":"2180","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)","keyword":["funding-enhance"],"quality_controlled":"1","author":[{"first_name":"Tobias","full_name":"Beisel, Tobias","last_name":"Beisel"},{"full_name":"Wiersema, Tobias","first_name":"Tobias","id":"3118","last_name":"Wiersema"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"}],"project":[{"_id":"30","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A"}],"date_created":"2018-04-03T09:18:33Z","status":"public","user_id":"15278","title":"Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux"},{"date_updated":"2023-09-26T13:39:48Z","_id":"2177","doi":"10.1155/2012/418315","language":[{"iso":"eng"}],"citation":{"mla":"Grad, Mariusz, and Christian Plessl. “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.” Int. Journal of Reconfigurable Computing (IJRC), Hindawi Publishing Corp., 2012, doi:10.1155/2012/418315.","bibtex":"@article{Grad_Plessl_2012, title={On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors}, DOI={10.1155/2012/418315}, journal={Int. Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi Publishing Corp.}, author={Grad, Mariusz and Plessl, Christian}, year={2012} }","ama":"Grad M, Plessl C. On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. Int Journal of Reconfigurable Computing (IJRC). Published online 2012. doi:10.1155/2012/418315","apa":"Grad, M., & Plessl, C. (2012). On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. Int. Journal of Reconfigurable Computing (IJRC). https://doi.org/10.1155/2012/418315","chicago":"Grad, Mariusz, and Christian Plessl. “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.” Int. Journal of Reconfigurable Computing (IJRC), 2012. https://doi.org/10.1155/2012/418315.","ieee":"M. Grad and C. Plessl, “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors,” Int. Journal of Reconfigurable Computing (IJRC), 2012, doi: 10.1155/2012/418315.","short":"M. Grad, C. Plessl, Int. Journal of Reconfigurable Computing (IJRC) (2012)."},"year":"2012","type":"journal_article","user_id":"15278","title":"On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors","author":[{"last_name":"Grad","full_name":"Grad, Mariusz","first_name":"Mariusz"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"publisher":"Hindawi Publishing Corp.","quality_controlled":"1","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Int. Journal of Reconfigurable Computing (IJRC)","status":"public","date_created":"2018-04-03T09:13:22Z"},{"year":"2011","type":"conference","citation":{"bibtex":"@inproceedings{Kenter_Plessl_Platzner_Kauschke_2011, title={Estimation and Partitioning for CPU-Accelerator Architectures}, booktitle={Intel European Research and Innovation Conference}, author={Kenter, Tobias and Plessl, Christian and Platzner, Marco and Kauschke, Michael}, year={2011} }","mla":"Kenter, Tobias, et al. “Estimation and Partitioning for CPU-Accelerator Architectures.” Intel European Research and Innovation Conference, 2011.","chicago":"Kenter, Tobias, Christian Plessl, Marco Platzner, and Michael Kauschke. “Estimation and Partitioning for CPU-Accelerator Architectures.” In Intel European Research and Innovation Conference, 2011.","apa":"Kenter, T., Plessl, C., Platzner, M., & Kauschke, M. (2011). Estimation and Partitioning for CPU-Accelerator Architectures. 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Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time.","lang":"eng"}],"citation":{"short":"M. Happe, A. Agne, C. Plessl, in: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60.","ieee":"M. Happe, A. Agne, and C. Plessl, “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time,” in Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2011, pp. 55–60, doi: 10.1109/ReConFig.2011.59.","apa":"Happe, M., Agne, A., & Plessl, C. (2011). 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Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"author":[{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"last_name":"Kauschke","first_name":"Michael","full_name":"Kauschke, Michael"}],"quality_controlled":"1","date_created":"2018-04-05T16:43:04Z","status":"public","editor":[{"last_name":"Hammami","first_name":"Omar","full_name":"Hammami, Omar"},{"full_name":"Larrabee, Sandra","first_name":"Sandra","last_name":"Larrabee"}]},{"date_created":"2018-04-16T15:09:19Z","status":"public","department":[{"_id":"27"},{"_id":"518"}],"keyword":["Rupeas","DSL","WSN","testing"],"author":[{"full_name":"Woehrle, Matthias","first_name":"Matthias","last_name":"Woehrle"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Thiele","first_name":"Lothar","full_name":"Thiele, Lothar"}],"user_id":"16153","title":"Rupeas: Ruby Powered Event Analysis DSL","abstract":[{"text":"Wireless Sensor Networks (WSNs) are unique embedded computation systems for distributed sensing of a dispersed phenomenon. While being a strongly concurrent distributed system, its embedded aspects with severe resource limitations and the wireless communication requires a fusion of technologies and methodologies from very different fields. As WSNs are deployed in remote locations for long-term unattended operation, assurance of correct functioning of the system is of prime concern. Thus, the design and development of WSNs requires specialized tools to allow for testing and debugging the system. To this end, we present a framework for analyzing and checking WSNs based on collected events during system operation. It allows for abstracting from the event trace by means of behavioral queries and uses assertions for checking the accordance of an execution to its specification. The framework is independent from WSN test platforms, applications and logging semantics and thus generally applicable for analyzing event logs of WSN test executions. ","lang":"eng"}],"place":"Computer Engineering and Networks Lab, ETH Zurich","extern":"1","report_number":"TIK-Report 290","language":[{"iso":"eng"}],"year":"2009","citation":{"short":"M. Woehrle, C. Plessl, L. Thiele, Rupeas: Ruby Powered Event Analysis DSL, Computer Engineering and Networks Lab, ETH Zurich, 2009.","ieee":"M. Woehrle, C. Plessl, and L. Thiele, Rupeas: Ruby Powered Event Analysis DSL. Computer Engineering and Networks Lab, ETH Zurich, 2009.","chicago":"Woehrle, Matthias, Christian Plessl, and Lothar Thiele. Rupeas: Ruby Powered Event Analysis DSL. Computer Engineering and Networks Lab, ETH Zurich, 2009.","apa":"Woehrle, M., Plessl, C., & Thiele, L. (2009). Rupeas: Ruby Powered Event Analysis DSL. Computer Engineering and Networks Lab, ETH Zurich.","ama":"Woehrle M, Plessl C, Thiele L. Rupeas: Ruby Powered Event Analysis DSL. Computer Engineering and Networks Lab, ETH Zurich; 2009.","mla":"Woehrle, Matthias, et al. Rupeas: Ruby Powered Event Analysis DSL. 2009.","bibtex":"@book{Woehrle_Plessl_Thiele_2009, place={Computer Engineering and Networks Lab, ETH Zurich}, title={Rupeas: Ruby Powered Event Analysis DSL}, author={Woehrle, Matthias and Plessl, Christian and Thiele, Lothar}, year={2009} }"},"type":"report","date_updated":"2022-01-06T06:55:56Z","_id":"2353"},{"doi":"10.1109/FCCM.2009.25","date_updated":"2023-09-26T13:51:44Z","language":[{"iso":"eng"}],"title":"IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing","publication_identifier":{"isbn":["978-1-4244-4450-2"]},"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"_id":"2350","year":"2009","citation":{"mla":"Schumacher, Tobias, et al. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–78, doi:10.1109/FCCM.2009.25.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing}, DOI={10.1109/FCCM.2009.25}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={275–278} }","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–78. IEEE Computer Society, 2009. https://doi.org/10.1109/FCCM.2009.25.","ama":"Schumacher T, Plessl C, Platzner M. IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society; 2009:275-278. doi:10.1109/FCCM.2009.25","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2009). IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–278. https://doi.org/10.1109/FCCM.2009.25","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing,” in Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2009, pp. 275–278, doi: 10.1109/FCCM.2009.25.","short":"T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–278."},"type":"conference","page":"275-278","user_id":"15278","abstract":[{"lang":"eng","text":"Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. "}],"status":"public","date_created":"2018-04-16T15:05:52Z","author":[{"full_name":"Schumacher, Tobias","first_name":"Tobias","last_name":"Schumacher"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"quality_controlled":"1","publisher":"IEEE Computer Society","publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","keyword":["IMORC","interconnect","performance"]},{"language":[{"iso":"eng"}],"page":"11-18","year":"2009","type":"conference","citation":{"ama":"Kaufmann P, Plessl C, Platzner M. EvoCaches: Application-specific Adaptation of Cache Mapping. In: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS). IEEE Computer Society; 2009:11-18.","apa":"Kaufmann, P., Plessl, C., & Platzner, M. (2009). EvoCaches: Application-specific Adaptation of Cache Mapping. Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18.","chicago":"Kaufmann, Paul, Christian Plessl, and Marco Platzner. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” In Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18. Los Alamitos, CA, USA: IEEE Computer Society, 2009.","mla":"Kaufmann, Paul, et al. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, 2009, pp. 11–18.","bibtex":"@inproceedings{Kaufmann_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={EvoCaches: Application-specific Adaptation of Cache Mapping}, booktitle={Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}, publisher={IEEE Computer Society}, author={Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2009}, pages={11–18} }","short":"P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 11–18.","ieee":"P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific Adaptation of Cache Mapping,” in Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2009, pp. 11–18."},"_id":"2262","date_updated":"2023-09-26T13:53:11Z","date_created":"2018-04-06T15:18:24Z","status":"public","publication":"Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"keyword":["EvoCache","evolvable hardware","computer architecture"],"quality_controlled":"1","publisher":"IEEE Computer Society","author":[{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"user_id":"15278","title":"EvoCaches: Application-specific Adaptation of Cache Mapping","abstract":[{"lang":"eng","text":"In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. "}],"place":"Los Alamitos, CA, USA"},{"author":[{"last_name":"Beutel","first_name":"Jan","full_name":"Beutel, Jan"},{"first_name":"Stephan","full_name":"Gruber, Stephan","last_name":"Gruber"},{"full_name":"Hasler, Andi","first_name":"Andi","last_name":"Hasler"},{"last_name":"Lim","first_name":"Roman","full_name":"Lim, Roman"},{"first_name":"Andreas","full_name":"Meier, Andreas","last_name":"Meier"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"full_name":"Talzi, Igor","first_name":"Igor","last_name":"Talzi"},{"last_name":"Thiele","first_name":"Lothar","full_name":"Thiele, Lothar"},{"full_name":"Tschudin, Christian","first_name":"Christian","last_name":"Tschudin"},{"last_name":"Woehrle","full_name":"Woehrle, Matthias","first_name":"Matthias"},{"last_name":"Yuecel","full_name":"Yuecel, Mustafa","first_name":"Mustafa"}],"publisher":"IEEE Computer Society","quality_controlled":"1","keyword":["WSN","PermaSense"],"publication":"Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)","department":[{"_id":"27"},{"_id":"518"}],"publication_identifier":{"isbn":["978-1-4244-5108-1"]},"status":"public","date_created":"2018-04-16T15:08:07Z","extern":"1","place":"Washington, DC, USA","title":"PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes","user_id":"15278","year":"2009","citation":{"short":"J. Beutel, S. Gruber, A. Hasler, R. Lim, A. Meier, C. Plessl, I. Talzi, L. Thiele, C. Tschudin, M. Woehrle, M. Yuecel, in: Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), IEEE Computer Society, Washington, DC, USA, 2009, pp. 265–276.","ieee":"J. Beutel et al., “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes,” in Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), 2009, pp. 265–276.","chicago":"Beutel, Jan, Stephan Gruber, Andi Hasler, Roman Lim, Andreas Meier, Christian Plessl, Igor Talzi, et al. “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes.” In Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), 265–76. Washington, DC, USA: IEEE Computer Society, 2009.","apa":"Beutel, J., Gruber, S., Hasler, A., Lim, R., Meier, A., Plessl, C., Talzi, I., Thiele, L., Tschudin, C., Woehrle, M., & Yuecel, M. (2009). PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes. Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), 265–276.","ama":"Beutel J, Gruber S, Hasler A, et al. PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes. In: Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN). IEEE Computer Society; 2009:265-276.","bibtex":"@inproceedings{Beutel_Gruber_Hasler_Lim_Meier_Plessl_Talzi_Thiele_Tschudin_Woehrle_et al._2009, place={Washington, DC, USA}, title={PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes}, booktitle={Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)}, publisher={IEEE Computer Society}, author={Beutel, Jan and Gruber, Stephan and Hasler, Andi and Lim, Roman and Meier, Andreas and Plessl, Christian and Talzi, Igor and Thiele, Lothar and Tschudin, Christian and Woehrle, Matthias and et al.}, year={2009}, pages={265–276} }","mla":"Beutel, Jan, et al. “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes.” Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), IEEE Computer Society, 2009, pp. 265–76."},"type":"conference","page":"265-276","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:52:01Z","_id":"2352"},{"language":[{"iso":"eng"}],"type":"conference","citation":{"mla":"Schumacher, Tobias, et al. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, 2009, pp. 119–24, doi:10.1109/ReConFig.2009.32.","bibtex":"@inproceedings{Schumacher_Süß_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000}, DOI={10.1109/ReConFig.2009.32}, booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}, year={2009}, pages={119–124} }","chicago":"Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–24. Los Alamitos, CA, USA: IEEE Computer Society, 2009. https://doi.org/10.1109/ReConFig.2009.32.","ama":"Schumacher T, Süß T, Plessl C, Platzner M. Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. In: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig). IEEE Computer Society; 2009:119-124. doi:10.1109/ReConFig.2009.32","apa":"Schumacher, T., Süß, T., Plessl, C., & Platzner, M. (2009). Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–124. https://doi.org/10.1109/ReConFig.2009.32","ieee":"T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000,” in Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 2009, pp. 119–124, doi: 10.1109/ReConFig.2009.32.","short":"T. Schumacher, T. Süß, C. Plessl, M. Platzner, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 119–124."},"year":"2009","page":"119-124","doi":"10.1109/ReConFig.2009.32","date_updated":"2023-09-26T13:52:32Z","_id":"2238","status":"public","date_created":"2018-04-05T17:11:28Z","publication_identifier":{"isbn":["978-0-7695-3917-1"]},"quality_controlled":"1","publisher":"IEEE Computer Society","author":[{"last_name":"Schumacher","full_name":"Schumacher, Tobias","first_name":"Tobias"},{"first_name":"Tim","full_name":"Süß, Tim","last_name":"Süß"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publication":"Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"keyword":["IMORC","graphics"],"user_id":"15278","title":"Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000","place":"Los Alamitos, CA, USA"},{"language":[{"iso":"eng"}],"type":"conference","year":"2009","citation":{"short":"T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338–344.","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2009, pp. 338–344.","ama":"Schumacher T, Plessl C, Platzner M. An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2009:338-344.","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2009). An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 338–344.","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 338–44. IEEE, 2009.","mla":"Schumacher, Tobias, et al. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338–44.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={338–344} }"},"page":"338-344","_id":"2261","date_updated":"2023-09-26T13:52:52Z","publisher":"IEEE","author":[{"first_name":"Tobias","full_name":"Schumacher, Tobias","last_name":"Schumacher"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"quality_controlled":"1","publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","keyword":["IMORC","NOC","KNN","accelerator"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"status":"public","date_created":"2018-04-06T15:15:47Z","publication_identifier":{"isbn":["978-1-4244-3892-1"],"issn":["1946-1488"]},"user_id":"15278","title":"An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure"},{"language":[{"iso":"eng"}],"citation":{"ieee":"M. Grad and C. Plessl, “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2009, pp. 319–322.","short":"M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, USA, 2009, pp. 319–322.","mla":"Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2009, pp. 319–22.","bibtex":"@inproceedings{Grad_Plessl_2009, place={USA}, title={Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Grad, Mariusz and Plessl, Christian}, year={2009}, pages={319–322} }","ama":"Grad M, Plessl C. Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2009:319-322.","apa":"Grad, M., & Plessl, C. (2009). Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 319–322.","chicago":"Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 319–22. USA: CSREA Press, 2009."},"year":"2009","type":"conference","page":"319-322","_id":"2263","date_updated":"2023-09-26T13:53:30Z","status":"public","date_created":"2018-04-06T15:19:51Z","publication_identifier":{"isbn":["1-60132-101-5"]},"publisher":"CSREA Press","author":[{"full_name":"Grad, Mariusz","first_name":"Mariusz","last_name":"Grad"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"quality_controlled":"1","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","user_id":"15278","title":"Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX","place":"USA","abstract":[{"lang":"eng","text":"In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Unit (APU) as well as the partial reconfiguration capabilities to provide dynamically reconfigurable custom instructions. We also present a hardware tool flow that automatically translates software functions into custom instructions and a software tool flow that creates binaries using these instructions. While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit. "}]}]