[{"date_updated":"2023-09-26T13:46:08Z","doi":"10.1109/ReConFig.2011.59","language":[{"iso":"eng"}],"title":"Measuring and Predicting Temperature Distributions on FPGAs at Run-Time","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","grant_number":"257906","name":"Engineering Proprioception in Computing Systems"}],"_id":"656","type":"conference","citation":{"apa":"Happe, M., Agne, A., & Plessl, C. (2011). Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60. https://doi.org/10.1109/ReConFig.2011.59","ama":"Happe M, Agne A, Plessl C. Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. In: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2011:55-60. doi:10.1109/ReConFig.2011.59","chicago":"Happe, Markus, Andreas Agne, and Christian Plessl. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” In Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60. IEEE, 2011. https://doi.org/10.1109/ReConFig.2011.59.","bibtex":"@inproceedings{Happe_Agne_Plessl_2011, title={Measuring and Predicting Temperature Distributions on FPGAs at Run-Time}, DOI={10.1109/ReConFig.2011.59}, booktitle={Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2011}, pages={55–60} }","mla":"Happe, Markus, et al. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60, doi:10.1109/ReConFig.2011.59.","short":"M. Happe, A. Agne, C. Plessl, in: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60.","ieee":"M. Happe, A. Agne, and C. Plessl, “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time,” in Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2011, pp. 55–60, doi: 10.1109/ReConFig.2011.59."},"year":"2011","page":"55-60","abstract":[{"text":"In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time.","lang":"eng"}],"user_id":"15278","ddc":["040"],"file":[{"file_size":502244,"creator":"florida","file_id":"1220","date_updated":"2018-03-14T13:49:39Z","content_type":"application/pdf","relation":"main_file","success":1,"file_name":"656-2011_happe_reconfig.pdf","date_created":"2018-03-14T13:49:39Z","access_level":"closed"}],"publisher":"IEEE","author":[{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","file_date_updated":"2018-03-14T13:49:39Z","publication":"Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:59Z"},{"status":"public","date_created":"2018-04-03T15:08:13Z","publication_identifier":{"isbn":["978-1-4503-0554-9"]},"author":[{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Kauschke","full_name":"Kauschke, Michael","first_name":"Michael"}],"quality_controlled":"1","publisher":"ACM","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)","keyword":["design space exploration","LLVM","partitioning","performance","estimation","funding-intel"],"user_id":"15278","title":"Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures","place":"New York, NY, USA","language":[{"iso":"eng"}],"citation":{"bibtex":"@inproceedings{Kenter_Platzner_Plessl_Kauschke_2011, place={New York, NY, USA}, title={Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures}, DOI={10.1145/1950413.1950448}, booktitle={Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}, publisher={ACM}, author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}, year={2011}, pages={177–180} }","mla":"Kenter, Tobias, et al. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, 2011, pp. 177–80, doi:10.1145/1950413.1950448.","ama":"Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. In: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA). ACM; 2011:177-180. doi:10.1145/1950413.1950448","apa":"Kenter, T., Platzner, M., Plessl, C., & Kauschke, M. (2011). Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 177–180. https://doi.org/10.1145/1950413.1950448","chicago":"Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” In Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 177–80. New York, NY, USA: ACM, 2011. https://doi.org/10.1145/1950413.1950448.","ieee":"T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures,” in Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 2011, pp. 177–180, doi: 10.1145/1950413.1950448.","short":"T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, New York, NY, USA, 2011, pp. 177–180."},"type":"conference","year":"2011","page":"177-180","doi":"10.1145/1950413.1950448","_id":"2200","date_updated":"2023-09-26T13:45:04Z"},{"user_id":"15278","title":"FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study","keyword":["funding-altera"],"publication":"Int. Journal of Recon- figurable Computing (IJRC)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"author":[{"full_name":"Schumacher, Tobias","first_name":"Tobias","last_name":"Schumacher"},{"last_name":"Süß","full_name":"Süß, Tim","first_name":"Tim"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"Hindawi Publishing Corp.","quality_controlled":"1","date_created":"2018-04-03T15:09:49Z","status":"public","date_updated":"2023-09-26T13:45:46Z","_id":"2201","doi":"10.1155/2011/760954","language":[{"iso":"eng"}],"type":"journal_article","year":"2011","citation":{"ieee":"T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study,” Int. Journal of Recon- figurable Computing (IJRC), 2011, doi: 10.1155/2011/760954.","short":"T. Schumacher, T. Süß, C. Plessl, M. Platzner, Int. Journal of Recon- Figurable Computing (IJRC) (2011).","bibtex":"@article{Schumacher_Süß_Plessl_Platzner_2011, title={FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study}, DOI={10.1155/2011/760954}, journal={Int. Journal of Recon- figurable Computing (IJRC)}, publisher={Hindawi Publishing Corp.}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}, year={2011} }","mla":"Schumacher, Tobias, et al. “FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study.” Int. Journal of Recon- Figurable Computing (IJRC), Hindawi Publishing Corp., 2011, doi:10.1155/2011/760954.","chicago":"Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study.” Int. Journal of Recon- Figurable Computing (IJRC), 2011. https://doi.org/10.1155/2011/760954.","apa":"Schumacher, T., Süß, T., Plessl, C., & Platzner, M. (2011). FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. Int. Journal of Recon- Figurable Computing (IJRC). https://doi.org/10.1155/2011/760954","ama":"Schumacher T, Süß T, Plessl C, Platzner M. FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. Int Journal of Recon- figurable Computing (IJRC). Published online 2011. doi:10.1155/2011/760954"}},{"language":[{"iso":"eng"}],"page":"278-285","year":"2011","type":"conference","citation":{"mla":"Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.” Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, 2011, pp. 278–85, doi:10.1109/IPDPS.2011.153.","bibtex":"@inproceedings{Grad_Plessl_2011, title={Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture}, DOI={10.1109/IPDPS.2011.153}, booktitle={Proc. Reconfigurable Architectures Workshop (RAW)}, publisher={IEEE Computer Society}, author={Grad, Mariusz and Plessl, Christian}, year={2011}, pages={278–285} }","chicago":"Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.” In Proc. Reconfigurable Architectures Workshop (RAW), 278–85. IEEE Computer Society, 2011. https://doi.org/10.1109/IPDPS.2011.153.","ama":"Grad M, Plessl C. Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. In: Proc. Reconfigurable Architectures Workshop (RAW). IEEE Computer Society; 2011:278-285. doi:10.1109/IPDPS.2011.153","apa":"Grad, M., & Plessl, C. (2011). Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. Proc. Reconfigurable Architectures Workshop (RAW), 278–285. https://doi.org/10.1109/IPDPS.2011.153","ieee":"M. Grad and C. Plessl, “Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture,” in Proc. Reconfigurable Architectures Workshop (RAW), 2011, pp. 278–285, doi: 10.1109/IPDPS.2011.153.","short":"M. Grad, C. Plessl, in: Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, 2011, pp. 278–285."},"doi":"10.1109/IPDPS.2011.153","date_updated":"2023-09-26T13:44:39Z","_id":"2198","date_created":"2018-04-03T15:05:52Z","status":"public","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Reconfigurable Architectures Workshop (RAW)","quality_controlled":"1","publisher":"IEEE Computer Society","author":[{"last_name":"Grad","full_name":"Grad, Mariusz","first_name":"Mariusz"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"user_id":"15278","title":"Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture"},{"citation":{"mla":"Lübbers, Enno, et al. “Towards Adaptive Networking for Embedded Devices Based on Reconfigurable Hardware.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 225–31.","bibtex":"@inproceedings{Lübbers_Platzner_Plessl_Keller_Plattner_2010, title={Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Lübbers, Enno and Platzner, Marco and Plessl, Christian and Keller, Ariane and Plattner, Bernhard}, year={2010}, pages={225–231} }","chicago":"Lübbers, Enno, Marco Platzner, Christian Plessl, Ariane Keller, and Bernhard Plattner. “Towards Adaptive Networking for Embedded Devices Based on Reconfigurable Hardware.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 225–31. CSREA Press, 2010.","ama":"Lübbers E, Platzner M, Plessl C, Keller A, Plattner B. Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010:225-231.","apa":"Lübbers, E., Platzner, M., Plessl, C., Keller, A., & Plattner, B. (2010). Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 225–231.","ieee":"E. Lübbers, M. Platzner, C. Plessl, A. Keller, and B. Plattner, “Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, pp. 225–231.","short":"E. Lübbers, M. Platzner, C. Plessl, A. Keller, B. Plattner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 225–231."},"year":"2010","type":"conference","page":"225-231","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:48:32Z","_id":"2223","publisher":"CSREA Press","quality_controlled":"1","author":[{"first_name":"Enno","full_name":"Lübbers, Enno","last_name":"Lübbers"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"full_name":"Keller, Ariane","first_name":"Ariane","last_name":"Keller"},{"last_name":"Plattner","full_name":"Plattner, Bernhard","first_name":"Bernhard"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","publication_identifier":{"isbn":["1-60132-140-6"]},"status":"public","date_created":"2018-04-05T16:27:13Z","title":"Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware","user_id":"15278"},{"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)","quality_controlled":"1","publisher":"IEEE Computer Society","author":[{"last_name":"Grad","full_name":"Grad, Mariusz","first_name":"Mariusz"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"date_created":"2018-04-05T14:48:51Z","status":"public","place":"Los Alamitos, CA, USA","title":"Pruning the Design Space for Just-In-Time Processor Customization","user_id":"15278","page":"67-72","citation":{"chicago":"Grad, Mariusz, and Christian Plessl. “Pruning the Design Space for Just-In-Time Processor Customization.” In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 67–72. Los Alamitos, CA, USA: IEEE Computer Society, 2010. https://doi.org/10.1109/ReConFig.2010.19.","apa":"Grad, M., & Plessl, C. (2010). Pruning the Design Space for Just-In-Time Processor Customization. Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 67–72. https://doi.org/10.1109/ReConFig.2010.19","ama":"Grad M, Plessl C. Pruning the Design Space for Just-In-Time Processor Customization. In: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig). IEEE Computer Society; 2010:67-72. doi:10.1109/ReConFig.2010.19","mla":"Grad, Mariusz, and Christian Plessl. “Pruning the Design Space for Just-In-Time Processor Customization.” Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, 2010, pp. 67–72, doi:10.1109/ReConFig.2010.19.","bibtex":"@inproceedings{Grad_Plessl_2010, place={Los Alamitos, CA, USA}, title={Pruning the Design Space for Just-In-Time Processor Customization}, DOI={10.1109/ReConFig.2010.19}, booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE Computer Society}, author={Grad, Mariusz and Plessl, Christian}, year={2010}, pages={67–72} }","short":"M. Grad, C. Plessl, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2010, pp. 67–72.","ieee":"M. Grad and C. Plessl, “Pruning the Design Space for Just-In-Time Processor Customization,” in Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 2010, pp. 67–72, doi: 10.1109/ReConFig.2010.19."},"type":"conference","year":"2010","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:47:11Z","_id":"2216","doi":"10.1109/ReConFig.2010.19"},{"page":"144-150","year":"2010","type":"conference","citation":{"short":"M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144–150.","ieee":"M. Grad and C. Plessl, “An Open Source Circuit Library with Benchmarking Facilities,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, pp. 144–150.","chicago":"Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with Benchmarking Facilities.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 144–50. CSREA Press, 2010.","ama":"Grad M, Plessl C. An Open Source Circuit Library with Benchmarking Facilities. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010:144-150.","apa":"Grad, M., & Plessl, C. (2010). An Open Source Circuit Library with Benchmarking Facilities. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 144–150.","bibtex":"@inproceedings{Grad_Plessl_2010, title={An Open Source Circuit Library with Benchmarking Facilities}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Grad, Mariusz and Plessl, Christian}, year={2010}, pages={144–150} }","mla":"Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with Benchmarking Facilities.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144–50."},"language":[{"iso":"eng"}],"_id":"2224","date_updated":"2023-09-26T13:48:59Z","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","author":[{"first_name":"Mariusz","full_name":"Grad, Mariusz","last_name":"Grad"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","publisher":"CSREA Press","publication_identifier":{"isbn":["1-60132-140-6"]},"date_created":"2018-04-05T16:28:38Z","status":"public","title":"An Open Source Circuit Library with Benchmarking Facilities","user_id":"15278"},{"date_updated":"2023-09-26T13:47:33Z","_id":"2220","language":[{"iso":"eng"}],"page":"165","year":"2010","citation":{"short":"D. Andrews, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, p. 165.","ieee":"D. Andrews and C. Plessl, “Configurable Processor Architectures: History and Trends,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, p. 165.","chicago":"Andrews, David, and Christian Plessl. “Configurable Processor Architectures: History and Trends.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 165. CSREA Press, 2010.","apa":"Andrews, D., & Plessl, C. (2010). Configurable Processor Architectures: History and Trends. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 165.","ama":"Andrews D, Plessl C. Configurable Processor Architectures: History and Trends. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010:165.","bibtex":"@inproceedings{Andrews_Plessl_2010, title={Configurable Processor Architectures: History and Trends}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Andrews, David and Plessl, Christian}, year={2010}, pages={165} }","mla":"Andrews, David, and Christian Plessl. “Configurable Processor Architectures: History and Trends.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, p. 165."},"type":"conference","user_id":"15278","title":"Configurable Processor Architectures: History and Trends","date_created":"2018-04-05T14:57:07Z","status":"public","publication_identifier":{"isbn":["1-60132-140-6"]},"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"quality_controlled":"1","publisher":"CSREA Press","author":[{"first_name":"David","full_name":"Andrews, David","last_name":"Andrews"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}]},{"type":"conference_editor","year":"2010","citation":{"short":"T.P. Plaks, D. Andrews, R. DeMara, H. Lam, J. Lee, C. Plessl, G. Stitt, eds., Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010.","ieee":"T. P. Plaks et al., Eds., Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2010.","apa":"Plaks, T. P., Andrews, D., DeMara, R., Lam, H., Lee, J., Plessl, C., & Stitt, G. (Eds.). (2010). Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press.","ama":"Plaks TP, Andrews D, DeMara R, et al., eds. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010.","chicago":"Plaks, Toomas P., David Andrews, Ronald DeMara, Herman Lam, Jooheung Lee, Christian Plessl, and Greg Stitt, eds. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2010.","mla":"Plaks, Toomas P., et al., editors. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2010.","bibtex":"@book{Plaks_Andrews_DeMara_Lam_Lee_Plessl_Stitt_2010, title={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, year={2010} }"},"language":[{"iso":"eng"}],"_id":"2222","date_updated":"2023-09-26T13:48:00Z","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"quality_controlled":"1","publisher":"CSREA Press","publication_identifier":{"isbn":["1-60132-140-6"]},"editor":[{"last_name":"Plaks","full_name":"Plaks, Toomas P.","first_name":"Toomas P."},{"last_name":"Andrews","full_name":"Andrews, David","first_name":"David"},{"full_name":"DeMara, Ronald","first_name":"Ronald","last_name":"DeMara"},{"last_name":"Lam","first_name":"Herman","full_name":"Lam, Herman"},{"full_name":"Lee, Jooheung","first_name":"Jooheung","last_name":"Lee"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"first_name":"Greg","full_name":"Stitt, Greg","last_name":"Stitt"}],"date_created":"2018-04-05T15:00:49Z","status":"public","title":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","user_id":"15278"},{"title":"Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators","user_id":"15278","quality_controlled":"1","author":[{"last_name":"Beisel","first_name":"Tobias","full_name":"Beisel, Tobias"},{"full_name":"Niekamp, Manuel","first_name":"Manuel","last_name":"Niekamp"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"publisher":"IEEE Computer Society","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)","publication_identifier":{"isbn":["978-1-4244-6965-9"]},"status":"public","date_created":"2018-04-05T16:39:34Z","date_updated":"2023-09-26T13:49:21Z","_id":"2226","doi":"10.1109/ASAP.2010.5540798","year":"2010","citation":{"apa":"Beisel, T., Niekamp, M., & Plessl, C. (2010). Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators. Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 65–72. https://doi.org/10.1109/ASAP.2010.5540798","ama":"Beisel T, Niekamp M, Plessl C. Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2010:65-72. doi:10.1109/ASAP.2010.5540798","chicago":"Beisel, Tobias, Manuel Niekamp, and Christian Plessl. “Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators.” In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 65–72. IEEE Computer Society, 2010. https://doi.org/10.1109/ASAP.2010.5540798.","mla":"Beisel, Tobias, et al. “Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators.” Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010, pp. 65–72, doi:10.1109/ASAP.2010.5540798.","bibtex":"@inproceedings{Beisel_Niekamp_Plessl_2010, title={Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators}, DOI={10.1109/ASAP.2010.5540798}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Beisel, Tobias and Niekamp, Manuel and Plessl, Christian}, year={2010}, pages={65–72} }","short":"T. Beisel, M. Niekamp, C. Plessl, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010, pp. 65–72.","ieee":"T. Beisel, M. Niekamp, and C. Plessl, “Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators,” in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2010, pp. 65–72, doi: 10.1109/ASAP.2010.5540798."},"type":"conference","page":"65-72","language":[{"iso":"eng"}]},{"language":[{"iso":"eng"}],"page":"372-376","year":"2010","type":"conference","citation":{"ieee":"A. Keller, B. Plattner, E. Lübbers, M. Platzner, and C. Plessl, “Reconfigurable Nodes for Future Networks,” in Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), 2010, pp. 372–376, doi: 10.1109/GLOCOMW.2010.5700341.","short":"A. Keller, B. Plattner, E. Lübbers, M. Platzner, C. Plessl, in: Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp. 372–376.","mla":"Keller, Ariane, et al. “Reconfigurable Nodes for Future Networks.” Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp. 372–76, doi:10.1109/GLOCOMW.2010.5700341.","bibtex":"@inproceedings{Keller_Plattner_Lübbers_Platzner_Plessl_2010, title={Reconfigurable Nodes for Future Networks}, DOI={10.1109/GLOCOMW.2010.5700341}, booktitle={Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)}, publisher={IEEE}, author={Keller, Ariane and Plattner, Bernhard and Lübbers, Enno and Platzner, Marco and Plessl, Christian}, year={2010}, pages={372–376} }","ama":"Keller A, Plattner B, Lübbers E, Platzner M, Plessl C. Reconfigurable Nodes for Future Networks. In: Proc. IEEE Globecom Workshop on Network of the Future (FutureNet). IEEE; 2010:372-376. doi:10.1109/GLOCOMW.2010.5700341","apa":"Keller, A., Plattner, B., Lübbers, E., Platzner, M., & Plessl, C. (2010). Reconfigurable Nodes for Future Networks. Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), 372–376. https://doi.org/10.1109/GLOCOMW.2010.5700341","chicago":"Keller, Ariane, Bernhard Plattner, Enno Lübbers, Marco Platzner, and Christian Plessl. “Reconfigurable Nodes for Future Networks.” In Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), 372–76. IEEE, 2010. https://doi.org/10.1109/GLOCOMW.2010.5700341."},"doi":"10.1109/GLOCOMW.2010.5700341","_id":"2206","date_updated":"2023-09-26T13:51:00Z","date_created":"2018-04-04T09:36:16Z","status":"public","publication_identifier":{"isbn":["978-1-4244-8864-3"]},"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)","quality_controlled":"1","author":[{"last_name":"Keller","first_name":"Ariane","full_name":"Keller, Ariane"},{"last_name":"Plattner","full_name":"Plattner, Bernhard","first_name":"Bernhard"},{"full_name":"Lübbers, Enno","first_name":"Enno","last_name":"Lübbers"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"publisher":"IEEE","user_id":"15278","title":"Reconfigurable Nodes for Future Networks"},{"user_id":"15278","title":"Rupeas: Ruby Powered Event Analysis DSL","extern":"1","status":"public","date_created":"2018-04-05T16:41:02Z","publication_identifier":{"isbn":["978-1-4244-7911-5"]},"author":[{"last_name":"Woehrle","full_name":"Woehrle, Matthias","first_name":"Matthias"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"last_name":"Thiele","full_name":"Thiele, Lothar","first_name":"Lothar"}],"quality_controlled":"1","publisher":"IEEE","department":[{"_id":"27"},{"_id":"518"}],"publication":"Proc. Int. Conf. Networked Sensing Systems (INSS)","doi":"10.1109/INSS.2010.5572211","_id":"2227","date_updated":"2023-09-26T13:49:38Z","language":[{"iso":"eng"}],"citation":{"short":"M. Woehrle, C. Plessl, L. Thiele, in: Proc. Int. Conf. Networked Sensing Systems (INSS), IEEE, 2010, pp. 245–248.","ieee":"M. Woehrle, C. Plessl, and L. Thiele, “Rupeas: Ruby Powered Event Analysis DSL,” in Proc. Int. Conf. Networked Sensing Systems (INSS), 2010, pp. 245–248, doi: 10.1109/INSS.2010.5572211.","chicago":"Woehrle, Matthias, Christian Plessl, and Lothar Thiele. “Rupeas: Ruby Powered Event Analysis DSL.” In Proc. Int. Conf. Networked Sensing Systems (INSS), 245–48. IEEE, 2010. https://doi.org/10.1109/INSS.2010.5572211.","apa":"Woehrle, M., Plessl, C., & Thiele, L. (2010). Rupeas: Ruby Powered Event Analysis DSL. Proc. Int. Conf. Networked Sensing Systems (INSS), 245–248. https://doi.org/10.1109/INSS.2010.5572211","ama":"Woehrle M, Plessl C, Thiele L. Rupeas: Ruby Powered Event Analysis DSL. In: Proc. Int. Conf. Networked Sensing Systems (INSS). IEEE; 2010:245-248. doi:10.1109/INSS.2010.5572211","mla":"Woehrle, Matthias, et al. “Rupeas: Ruby Powered Event Analysis DSL.” Proc. Int. Conf. Networked Sensing Systems (INSS), IEEE, 2010, pp. 245–48, doi:10.1109/INSS.2010.5572211.","bibtex":"@inproceedings{Woehrle_Plessl_Thiele_2010, title={Rupeas: Ruby Powered Event Analysis DSL}, DOI={10.1109/INSS.2010.5572211}, booktitle={Proc. Int. Conf. Networked Sensing Systems (INSS)}, publisher={IEEE}, author={Woehrle, Matthias and Plessl, Christian and Thiele, Lothar}, year={2010}, pages={245–248} }"},"type":"conference","year":"2010","page":"245-248"},{"date_updated":"2023-09-26T13:50:04Z","_id":"2228","language":[{"iso":"eng"}],"year":"2010","citation":{"ieee":"T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation for the Exploration of CPU-Accelerator Architectures,” in Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), 2010.","short":"T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: O. Hammami, S. Larrabee (Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), 2010.","bibtex":"@inproceedings{Kenter_Platzner_Plessl_Kauschke_2010, title={Performance Estimation for the Exploration of CPU-Accelerator Architectures}, booktitle={Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)}, author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}, editor={Hammami, Omar and Larrabee, Sandra}, year={2010} }","mla":"Kenter, Tobias, et al. “Performance Estimation for the Exploration of CPU-Accelerator Architectures.” Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), edited by Omar Hammami and Sandra Larrabee, 2010.","chicago":"Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke. “Performance Estimation for the Exploration of CPU-Accelerator Architectures.” In Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), edited by Omar Hammami and Sandra Larrabee, 2010.","apa":"Kenter, T., Platzner, M., Plessl, C., & Kauschke, M. (2010). Performance Estimation for the Exploration of CPU-Accelerator Architectures. In O. Hammami & S. Larrabee (Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA).","ama":"Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation for the Exploration of CPU-Accelerator Architectures. In: Hammami O, Larrabee S, eds. Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA). ; 2010."},"type":"conference","user_id":"15278","title":"Performance Estimation for the Exploration of CPU-Accelerator Architectures","status":"public","date_created":"2018-04-05T16:43:04Z","editor":[{"last_name":"Hammami","first_name":"Omar","full_name":"Hammami, Omar"},{"last_name":"Larrabee","full_name":"Larrabee, Sandra","first_name":"Sandra"}],"quality_controlled":"1","author":[{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"last_name":"Kauschke","full_name":"Kauschke, Michael","first_name":"Michael"}],"publication":"Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}]},{"place":"Computer Engineering and Networks Lab, ETH Zurich","abstract":[{"lang":"eng","text":"Wireless Sensor Networks (WSNs) are unique embedded computation systems for distributed sensing of a dispersed phenomenon. While being a strongly concurrent distributed system, its embedded aspects with severe resource limitations and the wireless communication requires a fusion of technologies and methodologies from very different fields. As WSNs are deployed in remote locations for long-term unattended operation, assurance of correct functioning of the system is of prime concern. Thus, the design and development of WSNs requires specialized tools to allow for testing and debugging the system. To this end, we present a framework for analyzing and checking WSNs based on collected events during system operation. It allows for abstracting from the event trace by means of behavioral queries and uses assertions for checking the accordance of an execution to its specification. The framework is independent from WSN test platforms, applications and logging semantics and thus generally applicable for analyzing event logs of WSN test executions. "}],"extern":"1","user_id":"16153","title":"Rupeas: Ruby Powered Event Analysis DSL","author":[{"first_name":"Matthias","full_name":"Woehrle, Matthias","last_name":"Woehrle"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Thiele","full_name":"Thiele, Lothar","first_name":"Lothar"}],"keyword":["Rupeas","DSL","WSN","testing"],"department":[{"_id":"27"},{"_id":"518"}],"status":"public","date_created":"2018-04-16T15:09:19Z","_id":"2353","date_updated":"2022-01-06T06:55:56Z","language":[{"iso":"eng"}],"report_number":"TIK-Report 290","citation":{"short":"M. Woehrle, C. Plessl, L. Thiele, Rupeas: Ruby Powered Event Analysis DSL, Computer Engineering and Networks Lab, ETH Zurich, 2009.","ieee":"M. Woehrle, C. Plessl, and L. Thiele, Rupeas: Ruby Powered Event Analysis DSL. Computer Engineering and Networks Lab, ETH Zurich, 2009.","chicago":"Woehrle, Matthias, Christian Plessl, and Lothar Thiele. Rupeas: Ruby Powered Event Analysis DSL. Computer Engineering and Networks Lab, ETH Zurich, 2009.","ama":"Woehrle M, Plessl C, Thiele L. Rupeas: Ruby Powered Event Analysis DSL. Computer Engineering and Networks Lab, ETH Zurich; 2009.","apa":"Woehrle, M., Plessl, C., & Thiele, L. (2009). Rupeas: Ruby Powered Event Analysis DSL. Computer Engineering and Networks Lab, ETH Zurich.","bibtex":"@book{Woehrle_Plessl_Thiele_2009, place={Computer Engineering and Networks Lab, ETH Zurich}, title={Rupeas: Ruby Powered Event Analysis DSL}, author={Woehrle, Matthias and Plessl, Christian and Thiele, Lothar}, year={2009} }","mla":"Woehrle, Matthias, et al. Rupeas: Ruby Powered Event Analysis DSL. 2009."},"type":"report","year":"2009"},{"year":"2009","citation":{"ama":"Schumacher T, Plessl C, Platzner M. IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society; 2009:275-278. doi:10.1109/FCCM.2009.25","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2009). IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–278. https://doi.org/10.1109/FCCM.2009.25","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–78. IEEE Computer Society, 2009. https://doi.org/10.1109/FCCM.2009.25.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing}, DOI={10.1109/FCCM.2009.25}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={275–278} }","mla":"Schumacher, Tobias, et al. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–78, doi:10.1109/FCCM.2009.25.","short":"T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–278.","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing,” in Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2009, pp. 275–278, doi: 10.1109/FCCM.2009.25."},"type":"conference","page":"275-278","_id":"2350","status":"public","date_created":"2018-04-16T15:05:52Z","author":[{"last_name":"Schumacher","first_name":"Tobias","full_name":"Schumacher, Tobias"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"IEEE Computer Society","quality_controlled":"1","keyword":["IMORC","interconnect","performance"],"publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","user_id":"15278","abstract":[{"text":"Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. ","lang":"eng"}],"language":[{"iso":"eng"}],"doi":"10.1109/FCCM.2009.25","date_updated":"2023-09-26T13:51:44Z","publication_identifier":{"isbn":["978-1-4244-4450-2"]},"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing"},{"date_updated":"2023-09-26T13:53:11Z","_id":"2262","page":"11-18","year":"2009","citation":{"chicago":"Kaufmann, Paul, Christian Plessl, and Marco Platzner. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” In Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18. Los Alamitos, CA, USA: IEEE Computer Society, 2009.","ama":"Kaufmann P, Plessl C, Platzner M. EvoCaches: Application-specific Adaptation of Cache Mapping. In: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS). IEEE Computer Society; 2009:11-18.","apa":"Kaufmann, P., Plessl, C., & Platzner, M. (2009). EvoCaches: Application-specific Adaptation of Cache Mapping. Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18.","bibtex":"@inproceedings{Kaufmann_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={EvoCaches: Application-specific Adaptation of Cache Mapping}, booktitle={Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}, publisher={IEEE Computer Society}, author={Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2009}, pages={11–18} }","mla":"Kaufmann, Paul, et al. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, 2009, pp. 11–18.","short":"P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 11–18.","ieee":"P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific Adaptation of Cache Mapping,” in Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2009, pp. 11–18."},"type":"conference","language":[{"iso":"eng"}],"abstract":[{"text":"In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. ","lang":"eng"}],"place":"Los Alamitos, CA, USA","title":"EvoCaches: Application-specific Adaptation of Cache Mapping","user_id":"15278","keyword":["EvoCache","evolvable hardware","computer architecture"],"publication":"Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publisher":"IEEE Computer Society","quality_controlled":"1","author":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"date_created":"2018-04-06T15:18:24Z","status":"public"},{"place":"Washington, DC, USA","extern":"1","user_id":"15278","title":"PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes","keyword":["WSN","PermaSense"],"publication":"Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)","department":[{"_id":"27"},{"_id":"518"}],"author":[{"last_name":"Beutel","first_name":"Jan","full_name":"Beutel, Jan"},{"full_name":"Gruber, Stephan","first_name":"Stephan","last_name":"Gruber"},{"first_name":"Andi","full_name":"Hasler, Andi","last_name":"Hasler"},{"full_name":"Lim, Roman","first_name":"Roman","last_name":"Lim"},{"full_name":"Meier, Andreas","first_name":"Andreas","last_name":"Meier"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"full_name":"Talzi, Igor","first_name":"Igor","last_name":"Talzi"},{"first_name":"Lothar","full_name":"Thiele, Lothar","last_name":"Thiele"},{"last_name":"Tschudin","full_name":"Tschudin, Christian","first_name":"Christian"},{"full_name":"Woehrle, Matthias","first_name":"Matthias","last_name":"Woehrle"},{"full_name":"Yuecel, Mustafa","first_name":"Mustafa","last_name":"Yuecel"}],"quality_controlled":"1","publisher":"IEEE Computer Society","date_created":"2018-04-16T15:08:07Z","status":"public","publication_identifier":{"isbn":["978-1-4244-5108-1"]},"date_updated":"2023-09-26T13:52:01Z","_id":"2352","language":[{"iso":"eng"}],"page":"265-276","type":"conference","year":"2009","citation":{"ieee":"J. Beutel et al., “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes,” in Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), 2009, pp. 265–276.","short":"J. Beutel, S. Gruber, A. Hasler, R. Lim, A. Meier, C. Plessl, I. Talzi, L. Thiele, C. Tschudin, M. Woehrle, M. Yuecel, in: Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), IEEE Computer Society, Washington, DC, USA, 2009, pp. 265–276.","bibtex":"@inproceedings{Beutel_Gruber_Hasler_Lim_Meier_Plessl_Talzi_Thiele_Tschudin_Woehrle_et al._2009, place={Washington, DC, USA}, title={PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes}, booktitle={Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)}, publisher={IEEE Computer Society}, author={Beutel, Jan and Gruber, Stephan and Hasler, Andi and Lim, Roman and Meier, Andreas and Plessl, Christian and Talzi, Igor and Thiele, Lothar and Tschudin, Christian and Woehrle, Matthias and et al.}, year={2009}, pages={265–276} }","mla":"Beutel, Jan, et al. “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes.” Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), IEEE Computer Society, 2009, pp. 265–76.","chicago":"Beutel, Jan, Stephan Gruber, Andi Hasler, Roman Lim, Andreas Meier, Christian Plessl, Igor Talzi, et al. “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes.” In Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), 265–76. Washington, DC, USA: IEEE Computer Society, 2009.","ama":"Beutel J, Gruber S, Hasler A, et al. PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes. In: Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN). IEEE Computer Society; 2009:265-276.","apa":"Beutel, J., Gruber, S., Hasler, A., Lim, R., Meier, A., Plessl, C., Talzi, I., Thiele, L., Tschudin, C., Woehrle, M., & Yuecel, M. (2009). PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes. Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), 265–276."}},{"language":[{"iso":"eng"}],"page":"119-124","type":"conference","year":"2009","citation":{"short":"T. Schumacher, T. Süß, C. Plessl, M. Platzner, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 119–124.","ieee":"T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000,” in Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 2009, pp. 119–124, doi: 10.1109/ReConFig.2009.32.","chicago":"Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–24. Los Alamitos, CA, USA: IEEE Computer Society, 2009. https://doi.org/10.1109/ReConFig.2009.32.","ama":"Schumacher T, Süß T, Plessl C, Platzner M. Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. In: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig). IEEE Computer Society; 2009:119-124. doi:10.1109/ReConFig.2009.32","apa":"Schumacher, T., Süß, T., Plessl, C., & Platzner, M. (2009). Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–124. https://doi.org/10.1109/ReConFig.2009.32","mla":"Schumacher, Tobias, et al. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, 2009, pp. 119–24, doi:10.1109/ReConFig.2009.32.","bibtex":"@inproceedings{Schumacher_Süß_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000}, DOI={10.1109/ReConFig.2009.32}, booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}, year={2009}, pages={119–124} }"},"date_updated":"2023-09-26T13:52:32Z","_id":"2238","doi":"10.1109/ReConFig.2009.32","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"keyword":["IMORC","graphics"],"publication":"Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)","author":[{"last_name":"Schumacher","first_name":"Tobias","full_name":"Schumacher, Tobias"},{"last_name":"Süß","first_name":"Tim","full_name":"Süß, Tim"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"quality_controlled":"1","publisher":"IEEE Computer Society","date_created":"2018-04-05T17:11:28Z","status":"public","publication_identifier":{"isbn":["978-0-7695-3917-1"]},"place":"Los Alamitos, CA, USA","user_id":"15278","title":"Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000"},{"date_updated":"2023-09-26T13:52:52Z","_id":"2261","page":"338-344","type":"conference","year":"2009","citation":{"ieee":"T. Schumacher, C. Plessl, and M. Platzner, “An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2009, pp. 338–344.","short":"T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338–344.","mla":"Schumacher, Tobias, et al. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338–44.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={338–344} }","ama":"Schumacher T, Plessl C, Platzner M. An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2009:338-344.","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2009). An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 338–344.","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 338–44. IEEE, 2009."},"language":[{"iso":"eng"}],"title":"An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure","user_id":"15278","keyword":["IMORC","NOC","KNN","accelerator"],"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publisher":"IEEE","author":[{"first_name":"Tobias","full_name":"Schumacher, Tobias","last_name":"Schumacher"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"quality_controlled":"1","publication_identifier":{"isbn":["978-1-4244-3892-1"],"issn":["1946-1488"]},"date_created":"2018-04-06T15:15:47Z","status":"public"},{"_id":"2263","date_updated":"2023-09-26T13:53:30Z","citation":{"short":"M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, USA, 2009, pp. 319–322.","ieee":"M. Grad and C. Plessl, “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2009, pp. 319–322.","chicago":"Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 319–22. USA: CSREA Press, 2009.","ama":"Grad M, Plessl C. Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2009:319-322.","apa":"Grad, M., & Plessl, C. (2009). Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 319–322.","mla":"Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2009, pp. 319–22.","bibtex":"@inproceedings{Grad_Plessl_2009, place={USA}, title={Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Grad, Mariusz and Plessl, Christian}, year={2009}, pages={319–322} }"},"year":"2009","type":"conference","page":"319-322","language":[{"iso":"eng"}],"place":"USA","abstract":[{"lang":"eng","text":"In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Unit (APU) as well as the partial reconfiguration capabilities to provide dynamically reconfigurable custom instructions. We also present a hardware tool flow that automatically translates software functions into custom instructions and a software tool flow that creates binaries using these instructions. While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit. "}],"title":"Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX","user_id":"15278","quality_controlled":"1","author":[{"last_name":"Grad","full_name":"Grad, Mariusz","first_name":"Mariusz"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"publisher":"CSREA Press","publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication_identifier":{"isbn":["1-60132-101-5"]},"status":"public","date_created":"2018-04-06T15:19:51Z"}]