[{"type":"conference","department":[{"_id":"27"},{"_id":"518"}],"date_created":"2018-04-05T16:41:02Z","quality_controlled":"1","extern":"1","publication":"Proc. Int. Conf. Networked Sensing Systems (INSS)","citation":{"bibtex":"@inproceedings{Woehrle_Plessl_Thiele_2010, title={Rupeas: Ruby Powered Event Analysis DSL}, DOI={<a href=\"https://doi.org/10.1109/INSS.2010.5572211\">10.1109/INSS.2010.5572211</a>}, booktitle={Proc. Int. Conf. Networked Sensing Systems (INSS)}, publisher={IEEE}, author={Woehrle, Matthias and Plessl, Christian and Thiele, Lothar}, year={2010}, pages={245–248} }","ama":"Woehrle M, Plessl C, Thiele L. Rupeas: Ruby Powered Event Analysis DSL. In: <i>Proc. Int. Conf. Networked Sensing Systems (INSS)</i>. IEEE; 2010:245-248. doi:<a href=\"https://doi.org/10.1109/INSS.2010.5572211\">10.1109/INSS.2010.5572211</a>","mla":"Woehrle, Matthias, et al. “Rupeas: Ruby Powered Event Analysis DSL.” <i>Proc. Int. Conf. Networked Sensing Systems (INSS)</i>, IEEE, 2010, pp. 245–48, doi:<a href=\"https://doi.org/10.1109/INSS.2010.5572211\">10.1109/INSS.2010.5572211</a>.","chicago":"Woehrle, Matthias, Christian Plessl, and Lothar Thiele. “Rupeas: Ruby Powered Event Analysis DSL.” In <i>Proc. Int. Conf. Networked Sensing Systems (INSS)</i>, 245–48. IEEE, 2010. <a href=\"https://doi.org/10.1109/INSS.2010.5572211\">https://doi.org/10.1109/INSS.2010.5572211</a>.","short":"M. Woehrle, C. Plessl, L. Thiele, in: Proc. Int. Conf. Networked Sensing Systems (INSS), IEEE, 2010, pp. 245–248.","ieee":"M. Woehrle, C. Plessl, and L. Thiele, “Rupeas: Ruby Powered Event Analysis DSL,” in <i>Proc. Int. Conf. Networked Sensing Systems (INSS)</i>, 2010, pp. 245–248, doi: <a href=\"https://doi.org/10.1109/INSS.2010.5572211\">10.1109/INSS.2010.5572211</a>.","apa":"Woehrle, M., Plessl, C., &#38; Thiele, L. (2010). Rupeas: Ruby Powered Event Analysis DSL. <i>Proc. Int. Conf. Networked Sensing Systems (INSS)</i>, 245–248. <a href=\"https://doi.org/10.1109/INSS.2010.5572211\">https://doi.org/10.1109/INSS.2010.5572211</a>"},"doi":"10.1109/INSS.2010.5572211","user_id":"15278","page":"245-248","language":[{"iso":"eng"}],"_id":"2227","publisher":"IEEE","date_updated":"2023-09-26T13:49:38Z","year":"2010","title":"Rupeas: Ruby Powered Event Analysis DSL","status":"public","publication_identifier":{"isbn":["978-1-4244-7911-5"]},"author":[{"last_name":"Woehrle","first_name":"Matthias","full_name":"Woehrle, Matthias"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian","full_name":"Plessl, Christian"},{"last_name":"Thiele","first_name":"Lothar","full_name":"Thiele, Lothar"}]},{"date_updated":"2023-09-26T13:50:04Z","status":"public","title":"Performance Estimation for the Exploration of CPU-Accelerator Architectures","year":"2010","author":[{"id":"3145","full_name":"Kenter, Tobias","first_name":"Tobias","last_name":"Kenter"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian","full_name":"Plessl, Christian"},{"full_name":"Kauschke, Michael","last_name":"Kauschke","first_name":"Michael"}],"user_id":"15278","editor":[{"full_name":"Hammami, Omar","last_name":"Hammami","first_name":"Omar"},{"full_name":"Larrabee, Sandra","last_name":"Larrabee","first_name":"Sandra"}],"_id":"2228","language":[{"iso":"eng"}],"quality_controlled":"1","publication":"Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)","citation":{"mla":"Kenter, Tobias, et al. “Performance Estimation for the Exploration of CPU-Accelerator Architectures.” <i>Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)</i>, edited by Omar Hammami and Sandra Larrabee, 2010.","ama":"Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation for the Exploration of CPU-Accelerator Architectures. In: Hammami O, Larrabee S, eds. <i>Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)</i>. ; 2010.","bibtex":"@inproceedings{Kenter_Platzner_Plessl_Kauschke_2010, title={Performance Estimation for the Exploration of CPU-Accelerator Architectures}, booktitle={Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)}, author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}, editor={Hammami, Omar and Larrabee, Sandra}, year={2010} }","apa":"Kenter, T., Platzner, M., Plessl, C., &#38; Kauschke, M. (2010). Performance Estimation for the Exploration of CPU-Accelerator Architectures. In O. Hammami &#38; S. Larrabee (Eds.), <i>Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)</i>.","ieee":"T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation for the Exploration of CPU-Accelerator Architectures,” in <i>Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)</i>, 2010.","short":"T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: O. Hammami, S. Larrabee (Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), 2010.","chicago":"Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke. “Performance Estimation for the Exploration of CPU-Accelerator Architectures.” In <i>Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)</i>, edited by Omar Hammami and Sandra Larrabee, 2010."},"type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"date_created":"2018-04-05T16:43:04Z"},{"keyword":["Rupeas","DSL","WSN","testing"],"type":"report","department":[{"_id":"27"},{"_id":"518"}],"date_created":"2018-04-16T15:09:19Z","place":"Computer Engineering and Networks Lab, ETH Zurich","extern":"1","abstract":[{"text":"Wireless Sensor Networks (WSNs) are unique embedded computation systems for distributed sensing of a dispersed phenomenon. While being a strongly concurrent distributed system, its embedded aspects with severe resource limitations and the wireless communication requires a fusion of technologies and methodologies from very different fields. As WSNs are deployed in remote locations for long-term unattended operation, assurance of correct functioning of the system is of prime concern. Thus, the design and development of WSNs requires specialized tools to allow for testing and debugging the system. To this end, we present a framework for analyzing and checking WSNs based on collected events during system operation. It allows for abstracting from the event trace by means of behavioral queries and uses assertions for checking the accordance of an execution to its specification. The framework is independent from WSN test platforms, applications and logging semantics and thus generally applicable for analyzing event logs of WSN test executions. ","lang":"eng"}],"report_number":"TIK-Report 290","citation":{"bibtex":"@book{Woehrle_Plessl_Thiele_2009, place={Computer Engineering and Networks Lab, ETH Zurich}, title={Rupeas: Ruby Powered Event Analysis DSL}, author={Woehrle, Matthias and Plessl, Christian and Thiele, Lothar}, year={2009} }","ama":"Woehrle M, Plessl C, Thiele L. <i>Rupeas: Ruby Powered Event Analysis DSL</i>. Computer Engineering and Networks Lab, ETH Zurich; 2009.","mla":"Woehrle, Matthias, et al. <i>Rupeas: Ruby Powered Event Analysis DSL</i>. 2009.","short":"M. Woehrle, C. Plessl, L. Thiele, Rupeas: Ruby Powered Event Analysis DSL, Computer Engineering and Networks Lab, ETH Zurich, 2009.","chicago":"Woehrle, Matthias, Christian Plessl, and Lothar Thiele. <i>Rupeas: Ruby Powered Event Analysis DSL</i>. Computer Engineering and Networks Lab, ETH Zurich, 2009.","ieee":"M. Woehrle, C. Plessl, and L. Thiele, <i>Rupeas: Ruby Powered Event Analysis DSL</i>. Computer Engineering and Networks Lab, ETH Zurich, 2009.","apa":"Woehrle, M., Plessl, C., &#38; Thiele, L. (2009). <i>Rupeas: Ruby Powered Event Analysis DSL</i>. Computer Engineering and Networks Lab, ETH Zurich."},"user_id":"16153","language":[{"iso":"eng"}],"_id":"2353","date_updated":"2022-01-06T06:55:56Z","year":"2009","status":"public","title":"Rupeas: Ruby Powered Event Analysis DSL","author":[{"full_name":"Woehrle, Matthias","last_name":"Woehrle","first_name":"Matthias"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian","full_name":"Plessl, Christian","id":"16153"},{"full_name":"Thiele, Lothar","first_name":"Lothar","last_name":"Thiele"}]},{"citation":{"short":"T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–278.","ama":"Schumacher T, Plessl C, Platzner M. IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. In: <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>. IEEE Computer Society; 2009:275-278. doi:<a href=\"https://doi.org/10.1109/FCCM.2009.25\">10.1109/FCCM.2009.25</a>","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” In <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, 275–78. IEEE Computer Society, 2009. <a href=\"https://doi.org/10.1109/FCCM.2009.25\">https://doi.org/10.1109/FCCM.2009.25</a>.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing}, DOI={<a href=\"https://doi.org/10.1109/FCCM.2009.25\">10.1109/FCCM.2009.25</a>}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={275–278} }","mla":"Schumacher, Tobias, et al. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, IEEE Computer Society, 2009, pp. 275–78, doi:<a href=\"https://doi.org/10.1109/FCCM.2009.25\">10.1109/FCCM.2009.25</a>.","apa":"Schumacher, T., Plessl, C., &#38; Platzner, M. (2009). IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, 275–278. <a href=\"https://doi.org/10.1109/FCCM.2009.25\">https://doi.org/10.1109/FCCM.2009.25</a>","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing,” in <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, 2009, pp. 275–278, doi: <a href=\"https://doi.org/10.1109/FCCM.2009.25\">10.1109/FCCM.2009.25</a>."},"quality_controlled":"1","page":"275-278","_id":"2350","publisher":"IEEE Computer Society","user_id":"15278","status":"public","date_created":"2018-04-16T15:05:52Z","keyword":["IMORC","interconnect","performance"],"type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","abstract":[{"text":"Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. ","lang":"eng"}],"language":[{"iso":"eng"}],"doi":"10.1109/FCCM.2009.25","year":"2009","title":"IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing","publication_identifier":{"isbn":["978-1-4244-4450-2"]},"author":[{"full_name":"Schumacher, Tobias","first_name":"Tobias","last_name":"Schumacher"},{"orcid":"0000-0001-5728-9982","first_name":"Christian","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"date_updated":"2023-09-26T13:51:44Z"},{"date_updated":"2023-09-26T13:53:11Z","title":"EvoCaches: Application-specific Adaptation of Cache Mapping","year":"2009","status":"public","author":[{"full_name":"Kaufmann, Paul","last_name":"Kaufmann","first_name":"Paul"},{"orcid":"0000-0001-5728-9982","first_name":"Christian","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"}],"user_id":"15278","page":"11-18","_id":"2262","language":[{"iso":"eng"}],"publisher":"IEEE Computer Society","abstract":[{"lang":"eng","text":"In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. "}],"quality_controlled":"1","publication":"Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","citation":{"mla":"Kaufmann, Paul, et al. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>, IEEE Computer Society, 2009, pp. 11–18.","ama":"Kaufmann P, Plessl C, Platzner M. EvoCaches: Application-specific Adaptation of Cache Mapping. In: <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>. IEEE Computer Society; 2009:11-18.","bibtex":"@inproceedings{Kaufmann_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={EvoCaches: Application-specific Adaptation of Cache Mapping}, booktitle={Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}, publisher={IEEE Computer Society}, author={Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2009}, pages={11–18} }","apa":"Kaufmann, P., Plessl, C., &#38; Platzner, M. (2009). EvoCaches: Application-specific Adaptation of Cache Mapping. <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>, 11–18.","ieee":"P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific Adaptation of Cache Mapping,” in <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>, 2009, pp. 11–18.","short":"P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 11–18.","chicago":"Kaufmann, Paul, Christian Plessl, and Marco Platzner. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” In <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>, 11–18. Los Alamitos, CA, USA: IEEE Computer Society, 2009."},"keyword":["EvoCache","evolvable hardware","computer architecture"],"type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"place":"Los Alamitos, CA, USA","date_created":"2018-04-06T15:18:24Z"},{"date_updated":"2023-09-26T13:52:01Z","year":"2009","status":"public","title":"PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes","author":[{"last_name":"Beutel","first_name":"Jan","full_name":"Beutel, Jan"},{"last_name":"Gruber","first_name":"Stephan","full_name":"Gruber, Stephan"},{"first_name":"Andi","last_name":"Hasler","full_name":"Hasler, Andi"},{"first_name":"Roman","last_name":"Lim","full_name":"Lim, Roman"},{"full_name":"Meier, Andreas","first_name":"Andreas","last_name":"Meier"},{"full_name":"Plessl, Christian","last_name":"Plessl","first_name":"Christian","orcid":"0000-0001-5728-9982","id":"16153"},{"full_name":"Talzi, Igor","first_name":"Igor","last_name":"Talzi"},{"full_name":"Thiele, Lothar","first_name":"Lothar","last_name":"Thiele"},{"last_name":"Tschudin","first_name":"Christian","full_name":"Tschudin, Christian"},{"last_name":"Woehrle","first_name":"Matthias","full_name":"Woehrle, Matthias"},{"full_name":"Yuecel, Mustafa","last_name":"Yuecel","first_name":"Mustafa"}],"publication_identifier":{"isbn":["978-1-4244-5108-1"]},"user_id":"15278","page":"265-276","publisher":"IEEE Computer Society","_id":"2352","language":[{"iso":"eng"}],"extern":"1","quality_controlled":"1","publication":"Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)","citation":{"mla":"Beutel, Jan, et al. “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes.” <i>Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)</i>, IEEE Computer Society, 2009, pp. 265–76.","bibtex":"@inproceedings{Beutel_Gruber_Hasler_Lim_Meier_Plessl_Talzi_Thiele_Tschudin_Woehrle_et al._2009, place={Washington, DC, USA}, title={PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes}, booktitle={Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)}, publisher={IEEE Computer Society}, author={Beutel, Jan and Gruber, Stephan and Hasler, Andi and Lim, Roman and Meier, Andreas and Plessl, Christian and Talzi, Igor and Thiele, Lothar and Tschudin, Christian and Woehrle, Matthias and et al.}, year={2009}, pages={265–276} }","ama":"Beutel J, Gruber S, Hasler A, et al. PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes. In: <i>Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)</i>. IEEE Computer Society; 2009:265-276.","ieee":"J. Beutel <i>et al.</i>, “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes,” in <i>Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)</i>, 2009, pp. 265–276.","apa":"Beutel, J., Gruber, S., Hasler, A., Lim, R., Meier, A., Plessl, C., Talzi, I., Thiele, L., Tschudin, C., Woehrle, M., &#38; Yuecel, M. (2009). PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes. <i>Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)</i>, 265–276.","chicago":"Beutel, Jan, Stephan Gruber, Andi Hasler, Roman Lim, Andreas Meier, Christian Plessl, Igor Talzi, et al. “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes.” In <i>Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)</i>, 265–76. Washington, DC, USA: IEEE Computer Society, 2009.","short":"J. Beutel, S. Gruber, A. Hasler, R. Lim, A. Meier, C. Plessl, I. Talzi, L. Thiele, C. Tschudin, M. Woehrle, M. Yuecel, in: Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), IEEE Computer Society, Washington, DC, USA, 2009, pp. 265–276."},"type":"conference","keyword":["WSN","PermaSense"],"department":[{"_id":"27"},{"_id":"518"}],"date_created":"2018-04-16T15:08:07Z","place":"Washington, DC, USA"},{"date_updated":"2023-09-26T13:52:32Z","status":"public","title":"Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000","year":"2009","author":[{"full_name":"Schumacher, Tobias","last_name":"Schumacher","first_name":"Tobias"},{"full_name":"Süß, Tim","first_name":"Tim","last_name":"Süß"},{"id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"publication_identifier":{"isbn":["978-0-7695-3917-1"]},"doi":"10.1109/ReConFig.2009.32","user_id":"15278","page":"119-124","_id":"2238","language":[{"iso":"eng"}],"publisher":"IEEE Computer Society","quality_controlled":"1","publication":"Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)","citation":{"mla":"Schumacher, Tobias, et al. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE Computer Society, 2009, pp. 119–24, doi:<a href=\"https://doi.org/10.1109/ReConFig.2009.32\">10.1109/ReConFig.2009.32</a>.","ama":"Schumacher T, Süß T, Plessl C, Platzner M. Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. In: <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE Computer Society; 2009:119-124. doi:<a href=\"https://doi.org/10.1109/ReConFig.2009.32\">10.1109/ReConFig.2009.32</a>","bibtex":"@inproceedings{Schumacher_Süß_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2009.32\">10.1109/ReConFig.2009.32</a>}, booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}, year={2009}, pages={119–124} }","apa":"Schumacher, T., Süß, T., Plessl, C., &#38; Platzner, M. (2009). Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, 119–124. <a href=\"https://doi.org/10.1109/ReConFig.2009.32\">https://doi.org/10.1109/ReConFig.2009.32</a>","ieee":"T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000,” in <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2009, pp. 119–124, doi: <a href=\"https://doi.org/10.1109/ReConFig.2009.32\">10.1109/ReConFig.2009.32</a>.","short":"T. Schumacher, T. Süß, C. Plessl, M. Platzner, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 119–124.","chicago":"Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” In <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, 119–24. Los Alamitos, CA, USA: IEEE Computer Society, 2009. <a href=\"https://doi.org/10.1109/ReConFig.2009.32\">https://doi.org/10.1109/ReConFig.2009.32</a>."},"keyword":["IMORC","graphics"],"type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"place":"Los Alamitos, CA, USA","date_created":"2018-04-05T17:11:28Z"},{"publication_identifier":{"issn":["1946-1488"],"isbn":["978-1-4244-3892-1"]},"author":[{"full_name":"Schumacher, Tobias","last_name":"Schumacher","first_name":"Tobias"},{"full_name":"Plessl, Christian","first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"year":"2009","title":"An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure","status":"public","date_updated":"2023-09-26T13:52:52Z","language":[{"iso":"eng"}],"_id":"2261","publisher":"IEEE","page":"338-344","user_id":"15278","citation":{"ieee":"T. Schumacher, C. Plessl, and M. Platzner, “An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure,” in <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2009, pp. 338–344.","mla":"Schumacher, Tobias, et al. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2009, pp. 338–44.","apa":"Schumacher, T., Plessl, C., &#38; Platzner, M. (2009). An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 338–344.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}, booktitle={Proc. Int. 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While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit. ","lang":"eng"}],"citation":{"ama":"Grad M, Plessl C. Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2009:319-322.","bibtex":"@inproceedings{Grad_Plessl_2009, place={USA}, title={Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX}, booktitle={Proc. Int. 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Piscataway, NJ, USA: IEEE, 2007. <a href=\"https://doi.org/10.1109/INSS.2007.4297445\">https://doi.org/10.1109/INSS.2007.4297445</a>.","short":"J. Beutel, M. Dyer, R. Lim, C. Plessl, M. Woehrle, M. Yuecel, L. Thiele, in: Proc. Int. Conf. Networked Sensing Systems (INSS), IEEE, Piscataway, NJ, USA, 2007, pp. 303–303."},"quality_controlled":"1","place":"Piscataway, NJ, USA","date_created":"2018-04-17T13:35:55Z","keyword":["WSN","testing","verification"],"type":"conference","department":[{"_id":"27"},{"_id":"518"}],"year":"2007","status":"public","title":"Automated Wireless Sensor Network Testing","author":[{"first_name":"Jan","last_name":"Beutel","full_name":"Beutel, Jan"},{"full_name":"Dyer, Matthias","last_name":"Dyer","first_name":"Matthias"},{"full_name":"Lim, Roman","last_name":"Lim","first_name":"Roman"},{"id":"16153","last_name":"Plessl","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"first_name":"Matthias","last_name":"Woehrle","full_name":"Woehrle, Matthias"},{"full_name":"Yuecel, Mustafa","first_name":"Mustafa","last_name":"Yuecel"},{"last_name":"Thiele","first_name":"Lothar","full_name":"Thiele, Lothar"}],"publication_identifier":{"isbn":["1-4244-1231-5"]},"date_updated":"2023-09-26T14:00:58Z","page":"303-303","_id":"2393","publisher":"IEEE","language":[{"iso":"eng"}],"doi":"10.1109/INSS.2007.4297445","user_id":"15278"},{"date_created":"2018-04-17T13:46:27Z","place":"Aachen, Germany","department":[{"_id":"518"}],"type":"dissertation","keyword":["Zippy"],"citation":{"ama":"Plessl C. <i>Hardware Virtualization on a Coarse-Grained Reconfigurable Processor</i>. Aachen, Germany: Shaker Verlag; 2006. doi:<a href=\"https://doi.org/10.2370/9783832255619\">10.2370/9783832255619</a>","bibtex":"@book{Plessl_2006, place={Aachen, Germany}, series={Technische Informatik}, title={Hardware virtualization on a coarse-grained reconfigurable processor}, DOI={<a href=\"https://doi.org/10.2370/9783832255619\">10.2370/9783832255619</a>}, publisher={Shaker Verlag}, author={Plessl, Christian}, year={2006}, collection={Technische Informatik} }","mla":"Plessl, Christian. <i>Hardware Virtualization on a Coarse-Grained Reconfigurable Processor</i>. Shaker Verlag, 2006, doi:<a href=\"https://doi.org/10.2370/9783832255619\">10.2370/9783832255619</a>.","chicago":"Plessl, Christian. <i>Hardware Virtualization on a Coarse-Grained Reconfigurable Processor</i>. Technische Informatik. Aachen, Germany: Shaker Verlag, 2006. <a href=\"https://doi.org/10.2370/9783832255619\">https://doi.org/10.2370/9783832255619</a>.","short":"C. Plessl, Hardware Virtualization on a Coarse-Grained Reconfigurable Processor, Shaker Verlag, Aachen, Germany, 2006.","apa":"Plessl, C. (2006). <i>Hardware virtualization on a coarse-grained reconfigurable processor</i>. Aachen, Germany: Shaker Verlag. <a href=\"https://doi.org/10.2370/9783832255619\">https://doi.org/10.2370/9783832255619</a>","ieee":"C. Plessl, <i>Hardware virtualization on a coarse-grained reconfigurable processor</i>. Aachen, Germany: Shaker Verlag, 2006."},"abstract":[{"text":" In this thesis, we propose to use a reconfigurable processor as main computation element in embedded systems for applications from the multi-media and communications domain. A reconfigurable processor integrates an embedded CPU core with a Reconfigurable Processing Unit (RPU). Many of our target applications require real-time signal-processing of data streams and expose a high computational demand. The key challenge in designing embedded systems for these applications is to find an implementation that satisfies the performance goals and is adaptable to new applications, while the system cost is minimized. Implementations that solely use an embedded CPU are likely to miss the performance goals. Application-Specific Integrated Circuit (ASIC)-based coprocessors can be used for some high-volume products with fixed functions, but fall short for systems with varying applications. We argue that a reconfigurable processor with a coarse-grained, dynamically reconfigurable array of modest size provides an attractive implementation platform for our application domain. The computational intensive application kernels are executed on the RPU, while the remaining parts of the application are executed on the CPU. Reconfigurable hardware allows for implementing application specific coprocessors with a high performance, while the function of the coprocessor can still be adapted due to the programmability. So far, reconfigurable technology is used in embedded systems primarily with static configurations, e.g., for implementing glue-logic, replacing ASICs, and for implementing fixed-function coprocessors. Changing the configuration at runtime enables a number of interesting application modes, e.g., on-demand loading of coprocessors and time-multiplexed execution of coprocessors, which is commonly denoted as hardware virtualization. While the use of static configurations is well understood and supported by design-tools, the role of dynamic reconfiguration is not well investigated yet. Current application specification methods and design-tools do not provide an end-to-end tool-flow that considers dynamic reconfiguration. A key idea of our approach is to reduce system cost by keeping the size of the reconfigurable array small and to use hardware virtualization techniques to compensate for the limited hardware resources. The main contribution of this thesis is the codesign of a reconfigurable processor architecture named ZIPPY, the corresponding hardware and software implementation tools, and an application specification model which explicitly considers hardware virtualization. The ZIPPY architecture is widely parametrized and allows for specifying a whole family of processor architectures. The implementation tools are also parametrized and can target any architectural variant. We evaluate the performance of the architecture with a system-level, cycle-accurate cosimulation framework. This framework enables us to perform design-space exploration for a variety of reconfigurable processor architectures. With two case studies, we demonstrate, that hardware virtualization on the Zippy architecture is feasible and enables us to trade-off performance for area in embedded systems. Finally, we present a novel method for optimal temporal partitioning of sequential circuits, which is an important form of hardware virtualization. The method based on Slowdown and Retiming allows us to decompose any sequential circuit into a number of smaller, communicating subcircuits that can be executed on a dynamically reconfigurable architecture. ","lang":"eng"}],"series_title":"Technische Informatik","_id":"2404","publisher":"Shaker Verlag","user_id":"24135","doi":"10.2370/9783832255619","author":[{"id":"16153","full_name":"Plessl, Christian","first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl"}],"publication_identifier":{"isbn":["978-3-8322-5561-3"]},"title":"Hardware virtualization on a coarse-grained reconfigurable processor","year":"2006","status":"public","date_updated":"2022-01-06T06:56:06Z"},{"user_id":"24135","doi":"10.1109/FPT.2006.270344","page":"345-348","_id":"2401","publisher":"IEEE Computer Society","date_updated":"2022-01-06T06:56:05Z","title":"Optimal Temporal Partitioning based on Slowdown and Retiming","status":"public","year":"2006","author":[{"orcid":"0000-0001-5728-9982","first_name":"Christian","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"},{"last_name":"Thiele","first_name":"Lothar","full_name":"Thiele, Lothar"}],"type":"conference","keyword":["temporal partitioning","retiming","ILP"],"department":[{"_id":"518"},{"_id":"78"}],"date_created":"2018-04-17T13:43:21Z","abstract":[{"lang":"eng","text":" This paper presents a novel method for optimal temporal partitioning of sequential circuits for time-multiplexed reconfigurable architectures. The method bases on slowdown and retiming and maximizes the circuit's performance during execution while restricting the size of the partitions to respect the resource constraints of the reconfigurable architecture. We provide a mixed integer linear program (MILP) formulation of the problem, which can be solved exactly. In contrast to related work, our approach optimizes performance directly, takes structural modifications of the circuit into account, and is extensible. We present the application of the new method to temporal partitioning for a coarse-grained reconfigurable architecture. "}],"publication":"Proc. Int. Conf. on Field Programmable Technology (ICFPT)","citation":{"apa":"Plessl, C., Platzner, M., &#38; Thiele, L. (2006). Optimal Temporal Partitioning based on Slowdown and Retiming. In <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i> (pp. 345–348). IEEE Computer Society. <a href=\"https://doi.org/10.1109/FPT.2006.270344\">https://doi.org/10.1109/FPT.2006.270344</a>","ieee":"C. Plessl, M. Platzner, and L. Thiele, “Optimal Temporal Partitioning based on Slowdown and Retiming,” in <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>, 2006, pp. 345–348.","chicago":"Plessl, Christian, Marco Platzner, and Lothar Thiele. “Optimal Temporal Partitioning Based on Slowdown and Retiming.” In <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>, 345–48. IEEE Computer Society, 2006. <a href=\"https://doi.org/10.1109/FPT.2006.270344\">https://doi.org/10.1109/FPT.2006.270344</a>.","short":"C. Plessl, M. Platzner, L. Thiele, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2006, pp. 345–348.","mla":"Plessl, Christian, et al. “Optimal Temporal Partitioning Based on Slowdown and Retiming.” <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>, IEEE Computer Society, 2006, pp. 345–48, doi:<a href=\"https://doi.org/10.1109/FPT.2006.270344\">10.1109/FPT.2006.270344</a>.","ama":"Plessl C, Platzner M, Thiele L. Optimal Temporal Partitioning based on Slowdown and Retiming. In: <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>. IEEE Computer Society; 2006:345-348. doi:<a href=\"https://doi.org/10.1109/FPT.2006.270344\">10.1109/FPT.2006.270344</a>","bibtex":"@inproceedings{Plessl_Platzner_Thiele_2006, title={Optimal Temporal Partitioning based on Slowdown and Retiming}, DOI={<a href=\"https://doi.org/10.1109/FPT.2006.270344\">10.1109/FPT.2006.270344</a>}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco and Thiele, Lothar}, year={2006}, pages={345–348} }"}},{"abstract":[{"text":" This paper motivates the use of hardware virtualization on coarse-grained reconfigurable architectures. We introduce Zippy, a coarse-grained multi-context hybrid CPU with architectural support for efficient hardware virtualization. The architectural details and the corresponding tool flow are outlined. As a case study, we compare the non-virtualized and the virtualized execution of an ADPCM decoder. ","lang":"eng"}],"publication":"Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)","citation":{"apa":"Plessl, C., &#38; Platzner, M. (2005). Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i> (pp. 213–218). IEEE Computer Society. <a href=\"https://doi.org/10.1109/ASAP.2005.69\">https://doi.org/10.1109/ASAP.2005.69</a>","ieee":"C. Plessl and M. Platzner, “Zippy – A coarse-grained reconfigurable array with support for hardware virtualization,” in <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, 2005, pp. 213–218.","chicago":"Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” In <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, 213–18. IEEE Computer Society, 2005. <a href=\"https://doi.org/10.1109/ASAP.2005.69\">https://doi.org/10.1109/ASAP.2005.69</a>.","short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–218.","mla":"Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, IEEE Computer Society, 2005, pp. 213–18, doi:<a href=\"https://doi.org/10.1109/ASAP.2005.69\">10.1109/ASAP.2005.69</a>.","ama":"Plessl C, Platzner M. Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In: <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>. IEEE Computer Society; 2005:213-218. doi:<a href=\"https://doi.org/10.1109/ASAP.2005.69\">10.1109/ASAP.2005.69</a>","bibtex":"@inproceedings{Plessl_Platzner_2005, title={Zippy – A coarse-grained reconfigurable array with support for hardware virtualization}, DOI={<a href=\"https://doi.org/10.1109/ASAP.2005.69\">10.1109/ASAP.2005.69</a>}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2005}, pages={213–218} }"},"type":"conference","keyword":["Zippy"],"department":[{"_id":"518"},{"_id":"78"}],"date_created":"2018-04-17T14:34:03Z","date_updated":"2022-01-06T06:56:07Z","title":"Zippy – A coarse-grained reconfigurable array with support for hardware virtualization","status":"public","year":"2005","author":[{"full_name":"Plessl, Christian","last_name":"Plessl","first_name":"Christian","orcid":"0000-0001-5728-9982","id":"16153"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"user_id":"24135","doi":"10.1109/ASAP.2005.69","page":"213-218","_id":"2411","publisher":"IEEE Computer Society"},{"department":[{"_id":"518"},{"_id":"78"}],"type":"journal_article","keyword":["FPGA","reconfigurable computing","co-simulation","Zippy"],"date_created":"2018-04-17T14:36:10Z","abstract":[{"text":" Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving impact of these design decisions on the overall system performance is a challenging task. In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors.","lang":"eng"}],"citation":{"short":"R. Enzler, C. Plessl, M. Platzner, Microprocessors and Microsystems 29 (2005) 63–73.","chicago":"Enzler, Rolf, Christian Plessl, and Marco Platzner. “System-Level Performance Evaluation of Reconfigurable Processors.” <i>Microprocessors and Microsystems</i> 29, no. 2–3 (2005): 63–73. <a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">https://doi.org/10.1016/j.micpro.2004.06.004</a>.","apa":"Enzler, R., Plessl, C., &#38; Platzner, M. (2005). System-level performance evaluation of reconfigurable processors. <i>Microprocessors and Microsystems</i>, <i>29</i>(2–3), 63–73. <a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">https://doi.org/10.1016/j.micpro.2004.06.004</a>","ieee":"R. Enzler, C. Plessl, and M. Platzner, “System-level performance evaluation of reconfigurable processors,” <i>Microprocessors and Microsystems</i>, vol. 29, no. 2–3, pp. 63–73, 2005.","ama":"Enzler R, Plessl C, Platzner M. System-level performance evaluation of reconfigurable processors. <i>Microprocessors and Microsystems</i>. 2005;29(2-3):63-73. doi:<a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">10.1016/j.micpro.2004.06.004</a>","bibtex":"@article{Enzler_Plessl_Platzner_2005, title={System-level performance evaluation of reconfigurable processors}, volume={29}, DOI={<a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">10.1016/j.micpro.2004.06.004</a>}, number={2–3}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2005}, pages={63–73} }","mla":"Enzler, Rolf, et al. “System-Level Performance Evaluation of Reconfigurable Processors.” <i>Microprocessors and Microsystems</i>, vol. 29, no. 2–3, Elsevier, 2005, pp. 63–73, doi:<a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">10.1016/j.micpro.2004.06.004</a>."},"publication":"Microprocessors and Microsystems","issue":"2-3","volume":29,"user_id":"24135","doi":"10.1016/j.micpro.2004.06.004","publisher":"Elsevier","_id":"2412","page":"63-73","intvolume":"        29","date_updated":"2022-01-06T06:56:07Z","author":[{"full_name":"Enzler, Rolf","first_name":"Rolf","last_name":"Enzler"},{"id":"16153","first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"}],"title":"System-level performance evaluation of reconfigurable processors","year":"2005","status":"public"},{"author":[{"orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian","full_name":"Plessl, Christian","id":"16153"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"}],"title":"Virtualization of Hardware – Introduction and Survey","year":"2004","status":"public","date_updated":"2022-01-06T06:56:08Z","publisher":"CSREA Press","_id":"2415","page":"63-69","user_id":"24135","citation":{"bibtex":"@inproceedings{Plessl_Platzner_2004, title={Virtualization of Hardware – Introduction and Survey}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Plessl, Christian and Platzner, Marco}, year={2004}, pages={63–69} }","ama":"Plessl C, Platzner M. Virtualization of Hardware – Introduction and Survey. In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2004:63-69.","mla":"Plessl, Christian, and Marco Platzner. “Virtualization of Hardware – Introduction and Survey.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2004, pp. 63–69.","chicago":"Plessl, Christian, and Marco Platzner. “Virtualization of Hardware – Introduction and Survey.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 63–69. CSREA Press, 2004.","short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004, pp. 63–69.","ieee":"C. Plessl and M. Platzner, “Virtualization of Hardware – Introduction and Survey,” in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2004, pp. 63–69.","apa":"Plessl, C., &#38; Platzner, M. (2004). Virtualization of Hardware – Introduction and Survey. In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i> (pp. 63–69). CSREA Press."},"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","abstract":[{"text":"In this paper we introduce to virtualization of hardware on reconfigurable devices. We identify three main approaches denoted with temporal partitioning, virtualized execution, and virtual machine. For each virtualization approach, we discuss the application models, the required execution architectures, the design tools and the run-time systems. Then, we survey a selection of important projects in the field. ","lang":"eng"}],"date_created":"2018-04-17T14:45:57Z","department":[{"_id":"518"},{"_id":"78"}],"type":"conference","keyword":["hardware virtualization"]}]