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Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","citation":{"apa":"Schumacher, T., Meiche, R., Kaufmann, P., Lübbers, E., Plessl, C., &#38; Platzner, M. (2008). A Hardware Accelerator for k-th Nearest Neighbor Thinning. <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 245–251.","ieee":"T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, and M. Platzner, “A Hardware Accelerator for k-th Nearest Neighbor Thinning,” in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2008, pp. 245–251.","chicago":"Schumacher, Tobias, Robert Meiche, Paul Kaufmann, Enno Lübbers, Christian Plessl, and Marco Platzner. “A Hardware Accelerator for K-Th Nearest Neighbor Thinning.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 245–51. CSREA Press, 2008.","short":"T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–251.","mla":"Schumacher, Tobias, et al. “A Hardware Accelerator for K-Th Nearest Neighbor Thinning.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2008, pp. 245–51.","ama":"Schumacher T, Meiche R, Kaufmann P, Lübbers E, Plessl C, Platzner M. A Hardware Accelerator for k-th Nearest Neighbor Thinning. In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2008:245-251.","bibtex":"@inproceedings{Schumacher_Meiche_Kaufmann_Lübbers_Plessl_Platzner_2008, title={A Hardware Accelerator for k-th Nearest Neighbor Thinning}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Schumacher, Tobias and Meiche, Robert and Kaufmann, Paul and Lübbers, Enno and Plessl, Christian and Platzner, Marco}, year={2008}, pages={245–251} }"},"type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"date_created":"2018-04-17T11:33:32Z"},{"user_id":"15278","language":[{"iso":"eng"}],"_id":"2372","date_updated":"2023-09-26T13:55:51Z","author":[{"first_name":"Tobias","last_name":"Schumacher","full_name":"Schumacher, Tobias"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian","full_name":"Plessl, Christian","id":"16153"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"}],"status":"public","title":"IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers","year":"2008","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"conference","keyword":["IMORC","IP core","interconnect"],"date_created":"2018-04-17T12:05:28Z","quality_controlled":"1","citation":{"mla":"Schumacher, Tobias, et al. “IMORC: An Infrastructure for Performance Monitoring and Optimization of Reconfigurable Computers.” <i>Many-Core and Reconfigurable Supercomputing Conference (MRSC)</i>, 2008.","ama":"Schumacher T, Plessl C, Platzner M. IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers. In: <i>Many-Core and Reconfigurable Supercomputing Conference (MRSC)</i>. ; 2008.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2008, title={IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers}, booktitle={Many-core and Reconfigurable Supercomputing Conference (MRSC)}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2008} }","apa":"Schumacher, T., Plessl, C., &#38; Platzner, M. (2008). IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers. <i>Many-Core and Reconfigurable Supercomputing Conference (MRSC)</i>.","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers,” 2008.","short":"T. Schumacher, C. Plessl, M. Platzner, in: Many-Core and Reconfigurable Supercomputing Conference (MRSC), 2008.","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure for Performance Monitoring and Optimization of Reconfigurable Computers.” In <i>Many-Core and Reconfigurable Supercomputing Conference (MRSC)</i>, 2008."},"publication":"Many-core and Reconfigurable Supercomputing Conference (MRSC)"},{"date_updated":"2022-01-06T06:56:04Z","title":"Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework","status":"public","year":"2007","author":[{"full_name":"Beutel, Jan","last_name":"Beutel","first_name":"Jan"},{"id":"16153","full_name":"Plessl, Christian","first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl"},{"first_name":"Matthias","last_name":"Woehrle","full_name":"Woehrle, Matthias"}],"user_id":"24135","_id":"2394","report_number":"TIK-Report 272","citation":{"mla":"Beutel, Jan, et al. <i>Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework</i>. 2007.","bibtex":"@book{Beutel_Plessl_Woehrle_2007, place={Computer Engineering and Networks Laboratory, ETH Zurich}, title={Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework}, author={Beutel, Jan and Plessl, Christian and Woehrle, Matthias}, year={2007} }","ama":"Beutel J, Plessl C, Woehrle M. <i>Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework</i>. Computer Engineering and Networks Laboratory, ETH Zurich; 2007.","ieee":"J. Beutel, C. Plessl, and M. Woehrle, <i>Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework</i>. Computer Engineering and Networks Laboratory, ETH Zurich, 2007.","apa":"Beutel, J., Plessl, C., &#38; Woehrle, M. (2007). <i>Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework</i>. Computer Engineering and Networks Laboratory, ETH Zurich.","chicago":"Beutel, Jan, Christian Plessl, and Matthias Woehrle. <i>Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework</i>. Computer Engineering and Networks Laboratory, ETH Zurich, 2007.","short":"J. Beutel, C. Plessl, M. Woehrle, Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework, Computer Engineering and Networks Laboratory, ETH Zurich, 2007."},"type":"report","department":[{"_id":"27"},{"_id":"518"}],"place":"Computer Engineering and Networks Laboratory, ETH Zurich","date_created":"2018-04-17T13:36:38Z"},{"date_created":"2018-04-17T13:34:42Z","place":"New York, NY, USA","department":[{"_id":"27"},{"_id":"518"}],"type":"conference","keyword":["WSN","testing","distributed","embedded"],"citation":{"apa":"Woehrle, M., Plessl, C., Beutel, J., &#38; Thiele, L. (2007). Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework. <i>Proc. Workshop on Embedded Networked Sensors (EmNets)</i>, 93–97. <a href=\"https://doi.org/10.1145/1278972.1278996\">https://doi.org/10.1145/1278972.1278996</a>","ieee":"M. Woehrle, C. Plessl, J. Beutel, and L. Thiele, “Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework,” in <i>Proc. Workshop on Embedded Networked Sensors (EmNets)</i>, 2007, pp. 93–97, doi: <a href=\"https://doi.org/10.1145/1278972.1278996\">10.1145/1278972.1278996</a>.","short":"M. Woehrle, C. Plessl, J. Beutel, L. Thiele, in: Proc. Workshop on Embedded Networked Sensors (EmNets), ACM, New York, NY, USA, 2007, pp. 93–97.","chicago":"Woehrle, Matthias, Christian Plessl, Jan Beutel, and Lothar Thiele. “Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework.” In <i>Proc. Workshop on Embedded Networked Sensors (EmNets)</i>, 93–97. New York, NY, USA: ACM, 2007. <a href=\"https://doi.org/10.1145/1278972.1278996\">https://doi.org/10.1145/1278972.1278996</a>.","mla":"Woehrle, Matthias, et al. “Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework.” <i>Proc. Workshop on Embedded Networked Sensors (EmNets)</i>, ACM, 2007, pp. 93–97, doi:<a href=\"https://doi.org/10.1145/1278972.1278996\">10.1145/1278972.1278996</a>.","ama":"Woehrle M, Plessl C, Beutel J, Thiele L. Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework. In: <i>Proc. Workshop on Embedded Networked Sensors (EmNets)</i>. ACM; 2007:93-97. doi:<a href=\"https://doi.org/10.1145/1278972.1278996\">10.1145/1278972.1278996</a>","bibtex":"@inproceedings{Woehrle_Plessl_Beutel_Thiele_2007, place={New York, NY, USA}, title={Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework}, DOI={<a href=\"https://doi.org/10.1145/1278972.1278996\">10.1145/1278972.1278996</a>}, booktitle={Proc. Workshop on Embedded Networked Sensors (EmNets)}, publisher={ACM}, author={Woehrle, Matthias and Plessl, Christian and Beutel, Jan and Thiele, Lothar}, year={2007}, pages={93–97} }"},"publication":"Proc. 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Int. Conf. Networked Sensing Systems (INSS)","citation":{"short":"J. Beutel, M. Dyer, R. Lim, C. Plessl, M. Woehrle, M. Yuecel, L. Thiele, in: Proc. Int. Conf. Networked Sensing Systems (INSS), IEEE, Piscataway, NJ, USA, 2007, pp. 303–303.","chicago":"Beutel, Jan, Matthias Dyer, Roman Lim, Christian Plessl, Matthias Woehrle, Mustafa Yuecel, and Lothar Thiele. “Automated Wireless Sensor Network Testing.” In <i>Proc. Int. Conf. Networked Sensing Systems (INSS)</i>, 303–303. Piscataway, NJ, USA: IEEE, 2007. <a href=\"https://doi.org/10.1109/INSS.2007.4297445\">https://doi.org/10.1109/INSS.2007.4297445</a>.","apa":"Beutel, J., Dyer, M., Lim, R., Plessl, C., Woehrle, M., Yuecel, M., &#38; Thiele, L. (2007). Automated Wireless Sensor Network Testing. <i>Proc. Int. Conf. Networked Sensing Systems (INSS)</i>, 303–303. <a href=\"https://doi.org/10.1109/INSS.2007.4297445\">https://doi.org/10.1109/INSS.2007.4297445</a>","ieee":"J. Beutel <i>et al.</i>, “Automated Wireless Sensor Network Testing,” in <i>Proc. Int. Conf. Networked Sensing Systems (INSS)</i>, 2007, pp. 303–303, doi: <a href=\"https://doi.org/10.1109/INSS.2007.4297445\">10.1109/INSS.2007.4297445</a>.","ama":"Beutel J, Dyer M, Lim R, et al. Automated Wireless Sensor Network Testing. In: <i>Proc. Int. Conf. Networked Sensing Systems (INSS)</i>. IEEE; 2007:303-303. doi:<a href=\"https://doi.org/10.1109/INSS.2007.4297445\">10.1109/INSS.2007.4297445</a>","bibtex":"@inproceedings{Beutel_Dyer_Lim_Plessl_Woehrle_Yuecel_Thiele_2007, place={Piscataway, NJ, USA}, title={Automated Wireless Sensor Network Testing}, DOI={<a href=\"https://doi.org/10.1109/INSS.2007.4297445\">10.1109/INSS.2007.4297445</a>}, booktitle={Proc. Int. Conf. Networked Sensing Systems (INSS)}, publisher={IEEE}, author={Beutel, Jan and Dyer, Matthias and Lim, Roman and Plessl, Christian and Woehrle, Matthias and Yuecel, Mustafa and Thiele, Lothar}, year={2007}, pages={303–303} }","mla":"Beutel, Jan, et al. “Automated Wireless Sensor Network Testing.” <i>Proc. Int. Conf. Networked Sensing Systems (INSS)</i>, IEEE, 2007, pp. 303–303, doi:<a href=\"https://doi.org/10.1109/INSS.2007.4297445\">10.1109/INSS.2007.4297445</a>."},"quality_controlled":"1","place":"Piscataway, NJ, USA","date_created":"2018-04-17T13:35:55Z","keyword":["WSN","testing","verification"],"type":"conference","department":[{"_id":"27"},{"_id":"518"}]},{"user_id":"24135","doi":"10.2370/9783832255619","_id":"2404","series_title":"Technische Informatik","publisher":"Shaker Verlag","date_updated":"2022-01-06T06:56:06Z","title":"Hardware virtualization on a coarse-grained reconfigurable processor","status":"public","year":"2006","author":[{"orcid":"0000-0001-5728-9982","first_name":"Christian","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"}],"publication_identifier":{"isbn":["978-3-8322-5561-3"]},"type":"dissertation","keyword":["Zippy"],"department":[{"_id":"518"}],"date_created":"2018-04-17T13:46:27Z","place":"Aachen, Germany","abstract":[{"text":" In this thesis, we propose to use a reconfigurable processor as main computation element in embedded systems for applications from the multi-media and communications domain. A reconfigurable processor integrates an embedded CPU core with a Reconfigurable Processing Unit (RPU). Many of our target applications require real-time signal-processing of data streams and expose a high computational demand. The key challenge in designing embedded systems for these applications is to find an implementation that satisfies the performance goals and is adaptable to new applications, while the system cost is minimized. Implementations that solely use an embedded CPU are likely to miss the performance goals. Application-Specific Integrated Circuit (ASIC)-based coprocessors can be used for some high-volume products with fixed functions, but fall short for systems with varying applications. We argue that a reconfigurable processor with a coarse-grained, dynamically reconfigurable array of modest size provides an attractive implementation platform for our application domain. The computational intensive application kernels are executed on the RPU, while the remaining parts of the application are executed on the CPU. Reconfigurable hardware allows for implementing application specific coprocessors with a high performance, while the function of the coprocessor can still be adapted due to the programmability. So far, reconfigurable technology is used in embedded systems primarily with static configurations, e.g., for implementing glue-logic, replacing ASICs, and for implementing fixed-function coprocessors. Changing the configuration at runtime enables a number of interesting application modes, e.g., on-demand loading of coprocessors and time-multiplexed execution of coprocessors, which is commonly denoted as hardware virtualization. While the use of static configurations is well understood and supported by design-tools, the role of dynamic reconfiguration is not well investigated yet. Current application specification methods and design-tools do not provide an end-to-end tool-flow that considers dynamic reconfiguration. A key idea of our approach is to reduce system cost by keeping the size of the reconfigurable array small and to use hardware virtualization techniques to compensate for the limited hardware resources. The main contribution of this thesis is the codesign of a reconfigurable processor architecture named ZIPPY, the corresponding hardware and software implementation tools, and an application specification model which explicitly considers hardware virtualization. The ZIPPY architecture is widely parametrized and allows for specifying a whole family of processor architectures. The implementation tools are also parametrized and can target any architectural variant. We evaluate the performance of the architecture with a system-level, cycle-accurate cosimulation framework. This framework enables us to perform design-space exploration for a variety of reconfigurable processor architectures. With two case studies, we demonstrate, that hardware virtualization on the Zippy architecture is feasible and enables us to trade-off performance for area in embedded systems. Finally, we present a novel method for optimal temporal partitioning of sequential circuits, which is an important form of hardware virtualization. The method based on Slowdown and Retiming allows us to decompose any sequential circuit into a number of smaller, communicating subcircuits that can be executed on a dynamically reconfigurable architecture. ","lang":"eng"}],"citation":{"bibtex":"@book{Plessl_2006, place={Aachen, Germany}, series={Technische Informatik}, title={Hardware virtualization on a coarse-grained reconfigurable processor}, DOI={<a href=\"https://doi.org/10.2370/9783832255619\">10.2370/9783832255619</a>}, publisher={Shaker Verlag}, author={Plessl, Christian}, year={2006}, collection={Technische Informatik} }","ama":"Plessl C. <i>Hardware Virtualization on a Coarse-Grained Reconfigurable Processor</i>. Aachen, Germany: Shaker Verlag; 2006. doi:<a href=\"https://doi.org/10.2370/9783832255619\">10.2370/9783832255619</a>","mla":"Plessl, Christian. <i>Hardware Virtualization on a Coarse-Grained Reconfigurable Processor</i>. Shaker Verlag, 2006, doi:<a href=\"https://doi.org/10.2370/9783832255619\">10.2370/9783832255619</a>.","short":"C. Plessl, Hardware Virtualization on a Coarse-Grained Reconfigurable Processor, Shaker Verlag, Aachen, Germany, 2006.","chicago":"Plessl, Christian. <i>Hardware Virtualization on a Coarse-Grained Reconfigurable Processor</i>. Technische Informatik. Aachen, Germany: Shaker Verlag, 2006. <a href=\"https://doi.org/10.2370/9783832255619\">https://doi.org/10.2370/9783832255619</a>.","ieee":"C. Plessl, <i>Hardware virtualization on a coarse-grained reconfigurable processor</i>. Aachen, Germany: Shaker Verlag, 2006.","apa":"Plessl, C. (2006). <i>Hardware virtualization on a coarse-grained reconfigurable processor</i>. Aachen, Germany: Shaker Verlag. <a href=\"https://doi.org/10.2370/9783832255619\">https://doi.org/10.2370/9783832255619</a>"}},{"user_id":"24135","doi":"10.1109/FPT.2006.270344","_id":"2401","publisher":"IEEE Computer Society","page":"345-348","date_updated":"2022-01-06T06:56:05Z","author":[{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","last_name":"Plessl","id":"16153"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"},{"first_name":"Lothar","last_name":"Thiele","full_name":"Thiele, Lothar"}],"status":"public","title":"Optimal Temporal Partitioning based on Slowdown and Retiming","year":"2006","department":[{"_id":"518"},{"_id":"78"}],"type":"conference","keyword":["temporal partitioning","retiming","ILP"],"date_created":"2018-04-17T13:43:21Z","abstract":[{"lang":"eng","text":" This paper presents a novel method for optimal temporal partitioning of sequential circuits for time-multiplexed reconfigurable architectures. The method bases on slowdown and retiming and maximizes the circuit's performance during execution while restricting the size of the partitions to respect the resource constraints of the reconfigurable architecture. We provide a mixed integer linear program (MILP) formulation of the problem, which can be solved exactly. In contrast to related work, our approach optimizes performance directly, takes structural modifications of the circuit into account, and is extensible. We present the application of the new method to temporal partitioning for a coarse-grained reconfigurable architecture. "}],"citation":{"short":"C. Plessl, M. Platzner, L. Thiele, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2006, pp. 345–348.","chicago":"Plessl, Christian, Marco Platzner, and Lothar Thiele. “Optimal Temporal Partitioning Based on Slowdown and Retiming.” In <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>, 345–48. IEEE Computer Society, 2006. <a href=\"https://doi.org/10.1109/FPT.2006.270344\">https://doi.org/10.1109/FPT.2006.270344</a>.","apa":"Plessl, C., Platzner, M., &#38; Thiele, L. (2006). Optimal Temporal Partitioning based on Slowdown and Retiming. In <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i> (pp. 345–348). IEEE Computer Society. <a href=\"https://doi.org/10.1109/FPT.2006.270344\">https://doi.org/10.1109/FPT.2006.270344</a>","ieee":"C. Plessl, M. Platzner, and L. Thiele, “Optimal Temporal Partitioning based on Slowdown and Retiming,” in <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>, 2006, pp. 345–348.","ama":"Plessl C, Platzner M, Thiele L. Optimal Temporal Partitioning based on Slowdown and Retiming. In: <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>. IEEE Computer Society; 2006:345-348. doi:<a href=\"https://doi.org/10.1109/FPT.2006.270344\">10.1109/FPT.2006.270344</a>","bibtex":"@inproceedings{Plessl_Platzner_Thiele_2006, title={Optimal Temporal Partitioning based on Slowdown and Retiming}, DOI={<a href=\"https://doi.org/10.1109/FPT.2006.270344\">10.1109/FPT.2006.270344</a>}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco and Thiele, Lothar}, year={2006}, pages={345–348} }","mla":"Plessl, Christian, et al. “Optimal Temporal Partitioning Based on Slowdown and Retiming.” <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>, IEEE Computer Society, 2006, pp. 345–48, doi:<a href=\"https://doi.org/10.1109/FPT.2006.270344\">10.1109/FPT.2006.270344</a>."},"publication":"Proc. Int. Conf. on Field Programmable Technology (ICFPT)"},{"date_updated":"2022-01-06T06:56:07Z","title":"Zippy – A coarse-grained reconfigurable array with support for hardware virtualization","year":"2005","status":"public","author":[{"id":"16153","first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco","id":"398"}],"user_id":"24135","doi":"10.1109/ASAP.2005.69","page":"213-218","publisher":"IEEE Computer Society","_id":"2411","abstract":[{"text":" This paper motivates the use of hardware virtualization on coarse-grained reconfigurable architectures. We introduce Zippy, a coarse-grained multi-context hybrid CPU with architectural support for efficient hardware virtualization. The architectural details and the corresponding tool flow are outlined. As a case study, we compare the non-virtualized and the virtualized execution of an ADPCM decoder. ","lang":"eng"}],"publication":"Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)","citation":{"chicago":"Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” In <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, 213–18. IEEE Computer Society, 2005. <a href=\"https://doi.org/10.1109/ASAP.2005.69\">https://doi.org/10.1109/ASAP.2005.69</a>.","short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–218.","apa":"Plessl, C., &#38; Platzner, M. (2005). Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i> (pp. 213–218). IEEE Computer Society. <a href=\"https://doi.org/10.1109/ASAP.2005.69\">https://doi.org/10.1109/ASAP.2005.69</a>","ieee":"C. Plessl and M. Platzner, “Zippy – A coarse-grained reconfigurable array with support for hardware virtualization,” in <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, 2005, pp. 213–218.","ama":"Plessl C, Platzner M. Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In: <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>. IEEE Computer Society; 2005:213-218. doi:<a href=\"https://doi.org/10.1109/ASAP.2005.69\">10.1109/ASAP.2005.69</a>","bibtex":"@inproceedings{Plessl_Platzner_2005, title={Zippy – A coarse-grained reconfigurable array with support for hardware virtualization}, DOI={<a href=\"https://doi.org/10.1109/ASAP.2005.69\">10.1109/ASAP.2005.69</a>}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2005}, pages={213–218} }","mla":"Plessl, Christian, and Marco Platzner. “Zippy – A Coarse-Grained Reconfigurable Array with Support for Hardware Virtualization.” <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, IEEE Computer Society, 2005, pp. 213–18, doi:<a href=\"https://doi.org/10.1109/ASAP.2005.69\">10.1109/ASAP.2005.69</a>."},"type":"conference","keyword":["Zippy"],"department":[{"_id":"518"},{"_id":"78"}],"date_created":"2018-04-17T14:34:03Z"},{"date_created":"2018-04-17T14:36:10Z","department":[{"_id":"518"},{"_id":"78"}],"type":"journal_article","keyword":["FPGA","reconfigurable computing","co-simulation","Zippy"],"citation":{"mla":"Enzler, Rolf, et al. “System-Level Performance Evaluation of Reconfigurable Processors.” <i>Microprocessors and Microsystems</i>, vol. 29, no. 2–3, Elsevier, 2005, pp. 63–73, doi:<a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">10.1016/j.micpro.2004.06.004</a>.","bibtex":"@article{Enzler_Plessl_Platzner_2005, title={System-level performance evaluation of reconfigurable processors}, volume={29}, DOI={<a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">10.1016/j.micpro.2004.06.004</a>}, number={2–3}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2005}, pages={63–73} }","ama":"Enzler R, Plessl C, Platzner M. System-level performance evaluation of reconfigurable processors. <i>Microprocessors and Microsystems</i>. 2005;29(2-3):63-73. doi:<a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">10.1016/j.micpro.2004.06.004</a>","ieee":"R. Enzler, C. Plessl, and M. Platzner, “System-level performance evaluation of reconfigurable processors,” <i>Microprocessors and Microsystems</i>, vol. 29, no. 2–3, pp. 63–73, 2005.","apa":"Enzler, R., Plessl, C., &#38; Platzner, M. (2005). System-level performance evaluation of reconfigurable processors. <i>Microprocessors and Microsystems</i>, <i>29</i>(2–3), 63–73. <a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">https://doi.org/10.1016/j.micpro.2004.06.004</a>","short":"R. Enzler, C. Plessl, M. Platzner, Microprocessors and Microsystems 29 (2005) 63–73.","chicago":"Enzler, Rolf, Christian Plessl, and Marco Platzner. “System-Level Performance Evaluation of Reconfigurable Processors.” <i>Microprocessors and Microsystems</i> 29, no. 2–3 (2005): 63–73. <a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">https://doi.org/10.1016/j.micpro.2004.06.004</a>."},"issue":"2-3","publication":"Microprocessors and Microsystems","abstract":[{"lang":"eng","text":" Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving impact of these design decisions on the overall system performance is a challenging task. In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors."}],"publisher":"Elsevier","_id":"2412","page":"63-73","volume":29,"user_id":"24135","doi":"10.1016/j.micpro.2004.06.004","author":[{"full_name":"Enzler, Rolf","last_name":"Enzler","first_name":"Rolf"},{"id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","last_name":"Plessl"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"status":"public","year":"2005","title":"System-level performance evaluation of reconfigurable processors","intvolume":"        29","date_updated":"2022-01-06T06:56:07Z"},{"page":"63-69","_id":"2415","publisher":"CSREA Press","user_id":"24135","title":"Virtualization of Hardware – Introduction and Survey","year":"2004","status":"public","author":[{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian","id":"16153"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}],"date_updated":"2022-01-06T06:56:08Z","date_created":"2018-04-17T14:45:57Z","type":"conference","keyword":["hardware virtualization"],"department":[{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","citation":{"chicago":"Plessl, Christian, and Marco Platzner. “Virtualization of Hardware – Introduction and Survey.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 63–69. CSREA Press, 2004.","short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004, pp. 63–69.","apa":"Plessl, C., &#38; Platzner, M. (2004). Virtualization of Hardware – Introduction and Survey. In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i> (pp. 63–69). CSREA Press.","ieee":"C. Plessl and M. Platzner, “Virtualization of Hardware – Introduction and Survey,” in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2004, pp. 63–69.","ama":"Plessl C, Platzner M. Virtualization of Hardware – Introduction and Survey. In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2004:63-69.","bibtex":"@inproceedings{Plessl_Platzner_2004, title={Virtualization of Hardware – Introduction and Survey}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Plessl, Christian and Platzner, Marco}, year={2004}, pages={63–69} }","mla":"Plessl, Christian, and Marco Platzner. “Virtualization of Hardware – Introduction and Survey.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2004, pp. 63–69."},"abstract":[{"text":"In this paper we introduce to virtualization of hardware on reconfigurable devices. We identify three main approaches denoted with temporal partitioning, virtualized execution, and virtual machine. For each virtualization approach, we discuss the application models, the required execution architectures, the design tools and the run-time systems. Then, we survey a selection of important projects in the field. ","lang":"eng"}]},{"type":"conference","keyword":["coprocessor","DIMM","memory bus","FPGA","high performance computing"],"department":[{"_id":"518"},{"_id":"78"}],"date_created":"2018-04-17T15:03:34Z","abstract":[{"text":" This paper presents TKDM, a PC-based high-performance reconfigurable computing environment. The TKDM hardware consists of an FPGA module that uses the DIMM (dual inline memory module) bus for high-bandwidth and low-latency communication with the host CPU. The system's firmware is integrated with the Linux host operating system and offers functions for data communication and FPGA reconfiguration. The intended use of TKDM is that of a dynamically reconfigurable co-processor for data streaming applications. The system's firmware can be customized for specific application domains to facilitate simple and easy-to-use programming interfaces. ","lang":"eng"}],"publication":"Proc. Int. Conf. on Field Programmable Technology (ICFPT)","citation":{"mla":"Plessl, Christian, and Marco Platzner. “TKDM – A Reconfigurable Co-Processor in a PC’s Memory Slot.” <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>, IEEE Computer Society, 2003, pp. 252–59, doi:<a href=\"https://doi.org/10.1109/FPT.2003.1275755\">10.1109/FPT.2003.1275755</a>.","bibtex":"@inproceedings{Plessl_Platzner_2003, title={TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot}, DOI={<a href=\"https://doi.org/10.1109/FPT.2003.1275755\">10.1109/FPT.2003.1275755</a>}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2003}, pages={252–259} }","ama":"Plessl C, Platzner M. TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In: <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>. IEEE Computer Society; 2003:252-259. doi:<a href=\"https://doi.org/10.1109/FPT.2003.1275755\">10.1109/FPT.2003.1275755</a>","ieee":"C. Plessl and M. Platzner, “TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot,” in <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>, 2003, pp. 252–259.","apa":"Plessl, C., &#38; Platzner, M. (2003). TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i> (pp. 252–259). IEEE Computer Society. <a href=\"https://doi.org/10.1109/FPT.2003.1275755\">https://doi.org/10.1109/FPT.2003.1275755</a>","chicago":"Plessl, Christian, and Marco Platzner. “TKDM – A Reconfigurable Co-Processor in a PC’s Memory Slot.” In <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>, 252–59. IEEE Computer Society, 2003. <a href=\"https://doi.org/10.1109/FPT.2003.1275755\">https://doi.org/10.1109/FPT.2003.1275755</a>.","short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2003, pp. 252–259."},"doi":"10.1109/FPT.2003.1275755","user_id":"24135","page":"252-259","publisher":"IEEE Computer Society","_id":"2418","date_updated":"2022-01-06T06:56:09Z","year":"2003","title":"TKDM – A Reconfigurable Co-processor in a PC's Memory Slot","status":"public","author":[{"id":"16153","first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}]},{"user_id":"398","volume":7,"page":"299-308","_id":"2419","publisher":"Springer","status":"public","citation":{"ama":"Plessl C, Enzler R, Walder H, et al. The Case for Reconfigurable Hardware in Wearable Computing. <i>Personal and Ubiquitous Computing</i>. 2003;7(5):299-308. doi:<a href=\"https://doi.org/10.1007/s00779-003-0243-x\">10.1007/s00779-003-0243-x</a>","bibtex":"@article{Plessl_Enzler_Walder_Beutel_Platzner_Thiele_Tröster_2003, title={The Case for Reconfigurable Hardware in Wearable Computing}, volume={7}, DOI={<a href=\"https://doi.org/10.1007/s00779-003-0243-x\">10.1007/s00779-003-0243-x</a>}, number={5}, journal={Personal and Ubiquitous Computing}, publisher={Springer}, author={Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan and Platzner, Marco and Thiele, Lothar and Tröster, Gerhard}, year={2003}, pages={299–308} }","mla":"Plessl, Christian, et al. “The Case for Reconfigurable Hardware in Wearable Computing.” <i>Personal and Ubiquitous Computing</i>, vol. 7, no. 5, Springer, 2003, pp. 299–308, doi:<a href=\"https://doi.org/10.1007/s00779-003-0243-x\">10.1007/s00779-003-0243-x</a>.","short":"C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, G. Tröster, Personal and Ubiquitous Computing 7 (2003) 299–308.","chicago":"Plessl, Christian, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, Lothar Thiele, and Gerhard Tröster. “The Case for Reconfigurable Hardware in Wearable Computing.” <i>Personal and Ubiquitous Computing</i> 7, no. 5 (2003): 299–308. <a href=\"https://doi.org/10.1007/s00779-003-0243-x\">https://doi.org/10.1007/s00779-003-0243-x</a>.","apa":"Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., Thiele, L., &#38; Tröster, G. (2003). The Case for Reconfigurable Hardware in Wearable Computing. <i>Personal and Ubiquitous Computing</i>, <i>7</i>(5), 299–308. <a href=\"https://doi.org/10.1007/s00779-003-0243-x\">https://doi.org/10.1007/s00779-003-0243-x</a>","ieee":"C. Plessl <i>et al.</i>, “The Case for Reconfigurable Hardware in Wearable Computing,” <i>Personal and Ubiquitous Computing</i>, vol. 7, no. 5, pp. 299–308, 2003."},"doi":"10.1007/s00779-003-0243-x","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:56:09Z","intvolume":"         7","year":"2003","title":"The Case for Reconfigurable Hardware in Wearable Computing","author":[{"full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153"},{"first_name":"Rolf","last_name":"Enzler","full_name":"Enzler, Rolf"},{"full_name":"Walder, Herbert","last_name":"Walder","first_name":"Herbert"},{"first_name":"Jan","last_name":"Beutel","full_name":"Beutel, Jan"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"},{"first_name":"Lothar","last_name":"Thiele","full_name":"Thiele, Lothar"},{"full_name":"Tröster, Gerhard","last_name":"Tröster","first_name":"Gerhard"}],"type":"journal_article","department":[{"_id":"518"},{"_id":"78"}],"date_created":"2018-04-17T15:04:47Z","extern":"1","abstract":[{"lang":"eng","text":"Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM."}],"issue":"5","publication":"Personal and Ubiquitous Computing"},{"citation":{"apa":"Plessl, C., &#38; Platzner, M. (2003). Instance-Specific Accelerators for Minimum Covering. <i>Journal of Supercomputing</i>, <i>26</i>(2), 109–129. <a href=\"https://doi.org/10.1023/a:1024443416592\">https://doi.org/10.1023/a:1024443416592</a>","ieee":"C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” <i>Journal of Supercomputing</i>, vol. 26, no. 2, pp. 109–129, 2003.","chicago":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” <i>Journal of Supercomputing</i> 26, no. 2 (2003): 109–29. <a href=\"https://doi.org/10.1023/a:1024443416592\">https://doi.org/10.1023/a:1024443416592</a>.","short":"C. Plessl, M. Platzner, Journal of Supercomputing 26 (2003) 109–129.","mla":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” <i>Journal of Supercomputing</i>, vol. 26, no. 2, Kluwer Academic Publishers, 2003, pp. 109–29, doi:<a href=\"https://doi.org/10.1023/a:1024443416592\">10.1023/a:1024443416592</a>.","ama":"Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. <i>Journal of Supercomputing</i>. 2003;26(2):109-129. doi:<a href=\"https://doi.org/10.1023/a:1024443416592\">10.1023/a:1024443416592</a>","bibtex":"@article{Plessl_Platzner_2003, title={Instance-Specific Accelerators for Minimum Covering}, volume={26}, DOI={<a href=\"https://doi.org/10.1023/a:1024443416592\">10.1023/a:1024443416592</a>}, number={2}, journal={Journal of Supercomputing}, publisher={Kluwer Academic Publishers}, author={Plessl, Christian and Platzner, Marco}, year={2003}, pages={109–129} }"},"page":"109-129","publisher":"Kluwer Academic Publishers","_id":"2420","user_id":"398","volume":26,"status":"public","date_created":"2018-04-17T15:10:00Z","type":"journal_article","keyword":["reconfigurable computing","instance-specific acceleration","minimum covering"],"department":[{"_id":"518"},{"_id":"78"}],"issue":"2","publication":"Journal of Supercomputing","abstract":[{"text":" This paper presents the acceleration of minimum-cost covering problems by instance-specific hardware. First, we formulate the minimum-cost covering problem and discuss a branch \\& bound algorithm to solve it. Then we describe instance-specific hardware architectures that implement branch \\& bound in 3-valued logic and use reduction techniques similar to those found in software solvers. We further present prototypical accelerator implementations and a corresponding design tool flow. Our experiments reveal significant raw speedups up to five orders of magnitude for a set of smaller unate covering problems. Provided that hardware compilation times can be reduced, we conclude that instance-specific acceleration of hard minimum-cost covering problems will lead to substantial overall speedups. ","lang":"eng"}],"extern":"1","language":[{"iso":"eng"}],"doi":"10.1023/a:1024443416592","title":"Instance-Specific Accelerators for Minimum Covering","year":"2003","publication_identifier":{"issn":["0920-8542"]},"author":[{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"}],"date_updated":"2022-01-06T06:56:10Z","intvolume":"        26"},{"type":"conference","keyword":["Zippy","multi-context","FPGA"],"department":[{"_id":"518"},{"_id":"78"}],"date_created":"2018-04-17T15:11:25Z","abstract":[{"lang":"eng","text":"In contrast to processors, current reconfigurable devices totally lack programming models that would allow for device independent compilation and forward compatibility. The key to overcome this limitation is hardware virtualization. In this paper, we resort to a macro-pipelined execution model to achieve hardware virtualization for data streaming applications. As a hardware implementation we present a hybrid multi-context architecture that attaches a coarse-grained reconfigurable array to a host CPU. A co-simulation framework enables cycle-accurate simulation of the complete architecture. As a case study we map an FIR filter to our virtualized hardware model and evaluate different designs. We discuss the impact of the number of contexts and the feature of context state on the speedup and the CPU load."}],"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","citation":{"bibtex":"@inproceedings{Enzler_Plessl_Platzner_2003, series={Lecture Notes in Computer Science (LNCS)}, title={Virtualizing Hardware with Multi-Context Reconfigurable Arrays}, volume={2778}, DOI={<a href=\"https://doi.org/10.1007/b12007\">10.1007/b12007</a>}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2003}, pages={151–160}, collection={Lecture Notes in Computer Science (LNCS)} }","chicago":"Enzler, Rolf, Christian Plessl, and Marco Platzner. “Virtualizing Hardware with Multi-Context Reconfigurable Arrays.” In <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2778:151–60. Lecture Notes in Computer Science (LNCS). Springer, 2003. <a href=\"https://doi.org/10.1007/b12007\">https://doi.org/10.1007/b12007</a>.","short":"R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), Springer, 2003, pp. 151–160.","ama":"Enzler R, Plessl C, Platzner M. Virtualizing Hardware with Multi-Context Reconfigurable Arrays. In: <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>. Vol 2778. Lecture Notes in Computer Science (LNCS). Springer; 2003:151-160. doi:<a href=\"https://doi.org/10.1007/b12007\">10.1007/b12007</a>","ieee":"R. Enzler, C. Plessl, and M. Platzner, “Virtualizing Hardware with Multi-Context Reconfigurable Arrays,” in <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2003, vol. 2778, pp. 151–160.","apa":"Enzler, R., Plessl, C., &#38; Platzner, M. (2003). Virtualizing Hardware with Multi-Context Reconfigurable Arrays. In <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i> (Vol. 2778, pp. 151–160). Springer. <a href=\"https://doi.org/10.1007/b12007\">https://doi.org/10.1007/b12007</a>","mla":"Enzler, Rolf, et al. “Virtualizing Hardware with Multi-Context Reconfigurable Arrays.” <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, vol. 2778, Springer, 2003, pp. 151–60, doi:<a href=\"https://doi.org/10.1007/b12007\">10.1007/b12007</a>."},"user_id":"24135","doi":"10.1007/b12007","volume":2778,"page":"151-160","_id":"2421","series_title":"Lecture Notes in Computer Science (LNCS)","publisher":"Springer","date_updated":"2022-01-06T06:56:13Z","intvolume":"      2778","status":"public","title":"Virtualizing Hardware with Multi-Context Reconfigurable Arrays","year":"2003","author":[{"first_name":"Rolf","last_name":"Enzler","full_name":"Enzler, Rolf"},{"full_name":"Plessl, Christian","first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}]},{"abstract":[{"lang":"eng","text":"Reconfigurable computing architectures aim to dynamically adapt their hardware to the application at hand. As research shows, the time it takes to reconfigure the hardware forms an overhead that can significantly impair the benefits of hardware customization. Multi-context devices are one promising approach to overcome the limitations posed by long reconfiguration times. In contrast to more traditional reconfigurable architectures, multi-context devices hold several configurations on-chip. On demand, the device can quickly switch to another context. In this paper we present a co-simulation environment to investigate design trade-offs for hybrid multi-context architectures. Our architectural model comprises a reconfigurable unit closely coupled to a CPU core. As a case study, we discuss the implementation of a FIR filter partitioned into several contexts. We outline the mapping process and present simulation results for single- and multi-context reconfigurable units coupled with both embedded and high-end CPUs."}],"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","citation":{"ieee":"R. Enzler, C. Plessl, and M. Platzner, “Co-simulation of a Hybrid Multi-Context Architecture,” in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2003, pp. 174–180.","apa":"Enzler, R., Plessl, C., &#38; Platzner, M. (2003). Co-simulation of a Hybrid Multi-Context Architecture. In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i> (pp. 174–180). CSREA Press.","short":"R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 174–180.","chicago":"Enzler, Rolf, Christian Plessl, and Marco Platzner. “Co-Simulation of a Hybrid Multi-Context Architecture.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 174–80. CSREA Press, 2003.","mla":"Enzler, Rolf, et al. “Co-Simulation of a Hybrid Multi-Context Architecture.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2003, pp. 174–80.","bibtex":"@inproceedings{Enzler_Plessl_Platzner_2003, title={Co-simulation of a Hybrid Multi-Context Architecture}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2003}, pages={174–180} }","ama":"Enzler R, Plessl C, Platzner M. Co-simulation of a Hybrid Multi-Context Architecture. In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2003:174-180."},"type":"conference","keyword":["Zippy","co-simulation"],"department":[{"_id":"518"},{"_id":"78"}],"date_created":"2018-04-17T15:12:56Z","date_updated":"2022-01-06T06:56:13Z","status":"public","year":"2003","title":"Co-simulation of a Hybrid Multi-Context Architecture","author":[{"full_name":"Enzler, Rolf","first_name":"Rolf","last_name":"Enzler"},{"id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"publication_identifier":{"isbn":["1-932415-05-X"]},"user_id":"24135","page":"174-180","publisher":"CSREA Press","_id":"2422"},{"publication_identifier":{"isbn":["0-7695-1816-8"]},"author":[{"id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","last_name":"Plessl"},{"first_name":"Rolf","last_name":"Enzler","full_name":"Enzler, Rolf"},{"last_name":"Walder","first_name":"Herbert","full_name":"Walder, Herbert"},{"last_name":"Beutel","first_name":"Jan","full_name":"Beutel, Jan"},{"full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner","id":"398"},{"first_name":"Lothar","last_name":"Thiele","full_name":"Thiele, Lothar"}],"year":"2002","status":"public","title":"Reconfigurable Hardware in Wearable Computing Nodes","date_updated":"2022-01-06T06:56:13Z","_id":"2423","publisher":"IEEE Computer Society","page":"215-222","doi":"10.1109/ISWC.2002.1167250","user_id":"24135","citation":{"chicago":"Plessl, Christian, Rolf Enzler, Herbert Walder, Jan Beutel, Marco Platzner, and Lothar Thiele. “Reconfigurable Hardware in Wearable Computing Nodes.” In <i>Proc. Int. Symp. on Wearable Computers (ISWC)</i>, 215–22. IEEE Computer Society, 2002. <a href=\"https://doi.org/10.1109/ISWC.2002.1167250\">https://doi.org/10.1109/ISWC.2002.1167250</a>.","short":"C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, in: Proc. Int. Symp. on Wearable Computers (ISWC), IEEE Computer Society, 2002, pp. 215–222.","ieee":"C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, and L. Thiele, “Reconfigurable Hardware in Wearable Computing Nodes,” in <i>Proc. Int. Symp. on Wearable Computers (ISWC)</i>, 2002, pp. 215–222.","apa":"Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., &#38; Thiele, L. (2002). Reconfigurable Hardware in Wearable Computing Nodes. In <i>Proc. Int. Symp. on Wearable Computers (ISWC)</i> (pp. 215–222). IEEE Computer Society. <a href=\"https://doi.org/10.1109/ISWC.2002.1167250\">https://doi.org/10.1109/ISWC.2002.1167250</a>","bibtex":"@inproceedings{Plessl_Enzler_Walder_Beutel_Platzner_Thiele_2002, title={Reconfigurable Hardware in Wearable Computing Nodes}, DOI={<a href=\"https://doi.org/10.1109/ISWC.2002.1167250\">10.1109/ISWC.2002.1167250</a>}, booktitle={Proc. Int. Symp. on Wearable Computers (ISWC)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan and Platzner, Marco and Thiele, Lothar}, year={2002}, pages={215–222} }","ama":"Plessl C, Enzler R, Walder H, Beutel J, Platzner M, Thiele L. Reconfigurable Hardware in Wearable Computing Nodes. In: <i>Proc. Int. Symp. on Wearable Computers (ISWC)</i>. IEEE Computer Society; 2002:215-222. doi:<a href=\"https://doi.org/10.1109/ISWC.2002.1167250\">10.1109/ISWC.2002.1167250</a>","mla":"Plessl, Christian, et al. “Reconfigurable Hardware in Wearable Computing Nodes.” <i>Proc. Int. Symp. on Wearable Computers (ISWC)</i>, IEEE Computer Society, 2002, pp. 215–22, doi:<a href=\"https://doi.org/10.1109/ISWC.2002.1167250\">10.1109/ISWC.2002.1167250</a>."},"publication":"Proc. Int. Symp. on Wearable Computers (ISWC)","abstract":[{"lang":"eng","text":"Wearable computers are embedded into the mobile environment of the human body. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with low energy consumption required to maximize battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss two experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we develop and evaluate task placement techniques used in the operating system layer of WURM."}],"date_created":"2018-04-17T15:13:50Z","department":[{"_id":"518"},{"_id":"78"}],"type":"conference","keyword":["wearable computing"]},{"type":"conference","keyword":["partial reconfiguration"],"department":[{"_id":"518"},{"_id":"78"}],"date_created":"2018-04-17T15:14:39Z","abstract":[{"lang":"eng","text":" Recent generations of high-density and high-speed FPGAs provide a sufficient capacity for implementing complete configurable systems on a chip (CSoCs). Hybrid CPUs that combine standard CPU cores with reconfigurable coprocessors are an important subclass of CSoCs. With partially reconfigurable FPGAs, coprocessors can be loaded on demand while the CPU remains running. However, the lack of high-level design tools for partial reconfiguration makes practical implementations a challenging task. In this paper, we introduce a design flow to implement hybrid processors on Xilinx Virtex. The design flow is based on two techniques, virtual sockets and feed-through components, and can efficiently generate partial configurations from industry-quality cores. We discuss the design flow and present a fully operational audio streaming prototype to demonstrate its feasibility. "}],"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","citation":{"short":"M. Dyer, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), Springer, 2002, pp. 292–301.","chicago":"Dyer, Matthias, Christian Plessl, and Marco Platzner. “Partially Reconfigurable Cores for Xilinx Virtex.” In <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2438:292–301. Lecture Notes in Computer Science (LNCS). Springer, 2002. <a href=\"https://doi.org/10.1007/3-540-46117-5\">https://doi.org/10.1007/3-540-46117-5</a>.","apa":"Dyer, M., Plessl, C., &#38; Platzner, M. (2002). Partially Reconfigurable Cores for Xilinx Virtex. In <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i> (Vol. 2438, pp. 292–301). Springer. <a href=\"https://doi.org/10.1007/3-540-46117-5\">https://doi.org/10.1007/3-540-46117-5</a>","ieee":"M. Dyer, C. Plessl, and M. Platzner, “Partially Reconfigurable Cores for Xilinx Virtex,” in <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2002, vol. 2438, pp. 292–301.","ama":"Dyer M, Plessl C, Platzner M. Partially Reconfigurable Cores for Xilinx Virtex. In: <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>. Vol 2438. Lecture Notes in Computer Science (LNCS). Springer; 2002:292-301. doi:<a href=\"https://doi.org/10.1007/3-540-46117-5\">10.1007/3-540-46117-5</a>","bibtex":"@inproceedings{Dyer_Plessl_Platzner_2002, series={Lecture Notes in Computer Science (LNCS)}, title={Partially Reconfigurable Cores for Xilinx Virtex}, volume={2438}, DOI={<a href=\"https://doi.org/10.1007/3-540-46117-5\">10.1007/3-540-46117-5</a>}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={Springer}, author={Dyer, Matthias and Plessl, Christian and Platzner, Marco}, year={2002}, pages={292–301}, collection={Lecture Notes in Computer Science (LNCS)} }","mla":"Dyer, Matthias, et al. “Partially Reconfigurable Cores for Xilinx Virtex.” <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, vol. 2438, Springer, 2002, pp. 292–301, doi:<a href=\"https://doi.org/10.1007/3-540-46117-5\">10.1007/3-540-46117-5</a>."},"doi":"10.1007/3-540-46117-5","user_id":"24135","volume":2438,"page":"292-301","series_title":"Lecture Notes in Computer Science (LNCS)","_id":"2424","publisher":"Springer","date_updated":"2022-01-06T06:56:13Z","intvolume":"      2438","status":"public","year":"2002","title":"Partially Reconfigurable Cores for Xilinx Virtex","author":[{"full_name":"Dyer, Matthias","last_name":"Dyer","first_name":"Matthias"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian","full_name":"Plessl, Christian","id":"16153"},{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"}]},{"abstract":[{"text":" We present instance-specific custom computing machines for the set covering problem. Four accelerator architectures are developed that implement branch \\& bound in 3-valued logic and many of the deduction techniques found in software solvers. We use set covering benchmarks from two-level logic minimization and Steiner triple systems to derive and discuss experimental results. The resulting raw speedups are in the order of four magnitudes on average. Finally, we propose a hybrid solver architecture that combines the raw speed of instance-specific reconfigurable hardware with flexible bounding schemes implemented in software. ","lang":"eng"}],"citation":{"short":"C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2002, pp. 163–172.","chicago":"Plessl, Christian, and Marco Platzner. “Custom Computing Machines for the Set Covering Problem.” In <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, 163–72. IEEE Computer Society, 2002. <a href=\"https://doi.org/10.1109/FPGA.2002.1106671\">https://doi.org/10.1109/FPGA.2002.1106671</a>.","apa":"Plessl, C., &#38; Platzner, M. (2002). Custom Computing Machines for the Set Covering Problem. In <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i> (pp. 163–172). IEEE Computer Society. <a href=\"https://doi.org/10.1109/FPGA.2002.1106671\">https://doi.org/10.1109/FPGA.2002.1106671</a>","ieee":"C. Plessl and M. Platzner, “Custom Computing Machines for the Set Covering Problem,” in <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, 2002, pp. 163–172.","ama":"Plessl C, Platzner M. Custom Computing Machines for the Set Covering Problem. In: <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>. IEEE Computer Society; 2002:163-172. doi:<a href=\"https://doi.org/10.1109/FPGA.2002.1106671\">10.1109/FPGA.2002.1106671</a>","bibtex":"@inproceedings{Plessl_Platzner_2002, title={Custom Computing Machines for the Set Covering Problem}, DOI={<a href=\"https://doi.org/10.1109/FPGA.2002.1106671\">10.1109/FPGA.2002.1106671</a>}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco}, year={2002}, pages={163–172} }","mla":"Plessl, Christian, and Marco Platzner. “Custom Computing Machines for the Set Covering Problem.” <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, IEEE Computer Society, 2002, pp. 163–72, doi:<a href=\"https://doi.org/10.1109/FPGA.2002.1106671\">10.1109/FPGA.2002.1106671</a>."},"publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","department":[{"_id":"518"},{"_id":"78"}],"type":"conference","date_created":"2018-04-17T15:15:44Z","date_updated":"2022-01-06T06:56:13Z","author":[{"id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian","full_name":"Plessl, Christian"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"title":"Custom Computing Machines for the Set Covering Problem","year":"2002","status":"public","doi":"10.1109/FPGA.2002.1106671","user_id":"24135","_id":"2425","publisher":"IEEE Computer Society","page":"163-172"},{"citation":{"ama":"Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2001:85-91.","bibtex":"@inproceedings{Plessl_Platzner_2001, title={Instance-Specific Accelerators for Minimum Covering}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Plessl, Christian and Platzner, Marco}, year={2001}, pages={85–91} }","mla":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2001, pp. 85–91.","chicago":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 85–91. CSREA Press, 2001.","short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2001, pp. 85–91.","apa":"Plessl, C., &#38; Platzner, M. (2001). Instance-Specific Accelerators for Minimum Covering. In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i> (pp. 85–91). CSREA Press.","ieee":"C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2001, pp. 85–91."},"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","abstract":[{"lang":"eng","text":" In this paper we present instance-specific accelerators for minimum-cost covering problems. We first define the covering problem and discuss a branch&bound algorithm to solve it. Then we describe an instance-specific hardware architecture that implements branch&bound in 3-valued logic and uses reduction techniques usually found in software solvers. Results for small unate covering problems reveal significant raw speedups. "}],"date_created":"2018-04-17T15:39:17Z","department":[{"_id":"518"},{"_id":"78"}],"type":"conference","keyword":["minimum covering","accelerator","funding-sundance"],"author":[{"last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian","full_name":"Plessl, Christian","id":"16153"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"}],"year":"2001","title":"Instance-Specific Accelerators for Minimum Covering","status":"public","date_updated":"2022-01-06T06:56:17Z","_id":"2428","publisher":"CSREA Press","page":"85-91","user_id":"24135"},{"department":[{"_id":"518"}],"type":"journal_article","date_created":"2018-04-17T15:43:29Z","citation":{"chicago":"Plessl, Christian, and Erik Wilde. “Server-Side-Techniken Im Web – Ein Überblick.” <i>IX</i>, 2001, 88–93.","short":"C. Plessl, E. Wilde, IX (2001) 88–93.","ieee":"C. Plessl and E. Wilde, “Server-Side-Techniken im Web – ein Überblick,” <i>iX</i>, pp. 88–93, 2001.","apa":"Plessl, C., &#38; Wilde, E. (2001). Server-Side-Techniken im Web – ein Überblick. <i>IX</i>, 88–93.","bibtex":"@article{Plessl_Wilde_2001, title={Server-Side-Techniken im Web – ein Überblick}, journal={iX}, publisher={Heise Verlag}, author={Plessl, Christian and Wilde, Erik}, year={2001}, pages={88–93} }","ama":"Plessl C, Wilde E. Server-Side-Techniken im Web – ein Überblick. <i>iX</i>. 2001:88-93.","mla":"Plessl, Christian, and Erik Wilde. “Server-Side-Techniken Im Web – Ein Überblick.” <i>IX</i>, Heise Verlag, 2001, pp. 88–93."},"publication":"iX","user_id":"24135","_id":"2429","publisher":"Heise Verlag","page":"88-93","date_updated":"2022-01-06T06:56:17Z","author":[{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153"},{"last_name":"Wilde","first_name":"Erik","full_name":"Wilde, Erik"}],"title":"Server-Side-Techniken im Web – ein Überblick","status":"public","year":"2001"}]