[{"abstract":[{"text":"Approximate computing has shown to provide new ways to improve performance\r\nand power consumption of error-resilient applications. While many of these\r\napplications can be found in image processing, data classification or machine\r\nlearning, we demonstrate its suitability to a problem from scientific\r\ncomputing. Utilizing the self-correcting behavior of iterative algorithms, we\r\nshow that approximate computing can be applied to the calculation of inverse\r\nmatrix p-th roots which are required in many applications in scientific\r\ncomputing. Results show great opportunities to reduce the computational effort\r\nand bandwidth required for the execution of the discussed algorithm, especially\r\nwhen targeting special accelerator hardware.","lang":"eng"}],"publication":"Embedded Systems Letters","language":[{"iso":"eng"}],"external_id":{"arxiv":["1703.02283"]},"year":"2018","issue":"2","title":"Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots","date_created":"2017-07-25T14:41:08Z","publisher":"IEEE","status":"public","type":"journal_article","department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"user_id":"16153","_id":"20","project":[{"grant_number":"PL 595/2-1","_id":"32","name":"Performance and Efficiency in HPC with Custom Computing"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"intvolume":"        10","page":" 33-36","citation":{"ieee":"M. Lass, T. Kühne, and C. Plessl, “Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots,” <i>Embedded Systems Letters</i>, vol. 10, no. 2, pp. 33–36, 2018.","chicago":"Lass, Michael, Thomas Kühne, and Christian Plessl. “Using Approximate Computing for the Calculation of Inverse Matrix P-Th Roots.” <i>Embedded Systems Letters</i> 10, no. 2 (2018): 33–36. <a href=\"https://doi.org/10.1109/LES.2017.2760923\">https://doi.org/10.1109/LES.2017.2760923</a>.","ama":"Lass M, Kühne T, Plessl C. Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots. <i>Embedded Systems Letters</i>. 2018;10(2):33-36. doi:<a href=\"https://doi.org/10.1109/LES.2017.2760923\">10.1109/LES.2017.2760923</a>","apa":"Lass, M., Kühne, T., &#38; Plessl, C. (2018). Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots. <i>Embedded Systems Letters</i>, <i>10</i>(2), 33–36. <a href=\"https://doi.org/10.1109/LES.2017.2760923\">https://doi.org/10.1109/LES.2017.2760923</a>","bibtex":"@article{Lass_Kühne_Plessl_2018, title={Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots}, volume={10}, DOI={<a href=\"https://doi.org/10.1109/LES.2017.2760923\">10.1109/LES.2017.2760923</a>}, number={2}, journal={Embedded Systems Letters}, publisher={IEEE}, author={Lass, Michael and Kühne, Thomas and Plessl, Christian}, year={2018}, pages={33–36} }","mla":"Lass, Michael, et al. “Using Approximate Computing for the Calculation of Inverse Matrix P-Th Roots.” <i>Embedded Systems Letters</i>, vol. 10, no. 2, IEEE, 2018, pp. 33–36, doi:<a href=\"https://doi.org/10.1109/LES.2017.2760923\">10.1109/LES.2017.2760923</a>.","short":"M. Lass, T. Kühne, C. Plessl, Embedded Systems Letters 10 (2018) 33–36."},"publication_identifier":{"issn":["1943-0663"],"eissn":["1943-0671"]},"publication_status":"published","doi":"10.1109/LES.2017.2760923","volume":10,"author":[{"id":"24135","full_name":"Lass, Michael","orcid":"0000-0002-5708-7632","last_name":"Lass","first_name":"Michael"},{"last_name":"Kühne","full_name":"Kühne, Thomas","id":"49079","first_name":"Thomas"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"}],"date_updated":"2022-01-06T06:54:18Z"},{"date_updated":"2022-01-06T07:01:52Z","publisher":"Universität Paderborn","date_created":"2018-11-07T15:14:26Z","author":[{"first_name":"Tasneem","full_name":"Filmwala, Tasneem","last_name":"Filmwala"}],"supervisor":[{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"}],"title":"Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate it on FPGA Platform","year":"2018","citation":{"chicago":"Filmwala, Tasneem. <i>Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate It on FPGA Platform</i>. Universität Paderborn, 2018.","ieee":"T. Filmwala, <i>Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate it on FPGA Platform</i>. Universität Paderborn, 2018.","ama":"Filmwala T. <i>Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate It on FPGA Platform</i>. Universität Paderborn; 2018.","short":"T. Filmwala, Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate It on FPGA Platform, Universität Paderborn, 2018.","mla":"Filmwala, Tasneem. <i>Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate It on FPGA Platform</i>. Universität Paderborn, 2018.","bibtex":"@book{Filmwala_2018, title={Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate it on FPGA Platform}, publisher={Universität Paderborn}, author={Filmwala, Tasneem}, year={2018} }","apa":"Filmwala, T. (2018). <i>Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate it on FPGA Platform</i>. Universität Paderborn."},"project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901 - Subproject C2","_id":"14"}],"_id":"5414","user_id":"477","department":[{"_id":"27"},{"_id":"518"}],"language":[{"iso":"eng"}],"type":"mastersthesis","status":"public"},{"department":[{"_id":"27"},{"_id":"518"}],"user_id":"477","_id":"5421","project":[{"name":"SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"language":[{"iso":"eng"}],"type":"mastersthesis","status":"public","date_created":"2018-11-07T16:16:56Z","supervisor":[{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl"}],"author":[{"first_name":"Onkar","full_name":"Gadewar, Onkar","last_name":"Gadewar"}],"publisher":"Universität Paderborn","date_updated":"2022-01-06T07:01:53Z","title":"Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL","citation":{"short":"O. Gadewar, Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL, Universität Paderborn, 2018.","mla":"Gadewar, Onkar. <i>Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL</i>. Universität Paderborn, 2018.","bibtex":"@book{Gadewar_2018, title={Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL}, publisher={Universität Paderborn}, author={Gadewar, Onkar}, year={2018} }","apa":"Gadewar, O. (2018). <i>Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL</i>. Universität Paderborn.","ama":"Gadewar O. <i>Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL</i>. Universität Paderborn; 2018.","ieee":"O. Gadewar, <i>Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL</i>. Universität Paderborn, 2018.","chicago":"Gadewar, Onkar. <i>Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL</i>. Universität Paderborn, 2018."},"year":"2018"},{"doi":"10.1007/s12283-018-0291-0","volume":21,"author":[{"first_name":"Jan Cedric","full_name":"Mertens, Jan Cedric","last_name":"Mertens"},{"last_name":"Boschmann","full_name":"Boschmann, Alexander","first_name":"Alexander"},{"full_name":"Schmidt, M.","last_name":"Schmidt","first_name":"M."},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982"}],"date_updated":"2022-01-06T07:03:09Z","intvolume":"        21","page":"441-451","citation":{"mla":"Mertens, Jan Cedric, et al. “Sprint Diagnostic with GPS and Inertial Sensor Fusion.” <i>Sports Engineering</i>, vol. 21, no. 4, Springer Nature, 2018, pp. 441–51, doi:<a href=\"https://doi.org/10.1007/s12283-018-0291-0\">10.1007/s12283-018-0291-0</a>.","bibtex":"@article{Mertens_Boschmann_Schmidt_Plessl_2018, title={Sprint diagnostic with GPS and inertial sensor fusion}, volume={21}, DOI={<a href=\"https://doi.org/10.1007/s12283-018-0291-0\">10.1007/s12283-018-0291-0</a>}, number={4}, journal={Sports Engineering}, publisher={Springer Nature}, author={Mertens, Jan Cedric and Boschmann, Alexander and Schmidt, M. and Plessl, Christian}, year={2018}, pages={441–451} }","short":"J.C. Mertens, A. Boschmann, M. Schmidt, C. Plessl, Sports Engineering 21 (2018) 441–451.","apa":"Mertens, J. C., Boschmann, A., Schmidt, M., &#38; Plessl, C. (2018). Sprint diagnostic with GPS and inertial sensor fusion. <i>Sports Engineering</i>, <i>21</i>(4), 441–451. <a href=\"https://doi.org/10.1007/s12283-018-0291-0\">https://doi.org/10.1007/s12283-018-0291-0</a>","chicago":"Mertens, Jan Cedric, Alexander Boschmann, M. Schmidt, and Christian Plessl. “Sprint Diagnostic with GPS and Inertial Sensor Fusion.” <i>Sports Engineering</i> 21, no. 4 (2018): 441–51. <a href=\"https://doi.org/10.1007/s12283-018-0291-0\">https://doi.org/10.1007/s12283-018-0291-0</a>.","ieee":"J. C. Mertens, A. Boschmann, M. Schmidt, and C. Plessl, “Sprint diagnostic with GPS and inertial sensor fusion,” <i>Sports Engineering</i>, vol. 21, no. 4, pp. 441–451, 2018.","ama":"Mertens JC, Boschmann A, Schmidt M, Plessl C. Sprint diagnostic with GPS and inertial sensor fusion. <i>Sports Engineering</i>. 2018;21(4):441-451. doi:<a href=\"https://doi.org/10.1007/s12283-018-0291-0\">10.1007/s12283-018-0291-0</a>"},"has_accepted_license":"1","publication_identifier":{"issn":["1369-7072","1460-2687"]},"publication_status":"published","file_date_updated":"2019-01-08T17:47:06Z","department":[{"_id":"27"},{"_id":"518"}],"user_id":"16153","_id":"6516","status":"public","type":"journal_article","title":"Sprint diagnostic with GPS and inertial sensor fusion","date_created":"2019-01-08T17:44:43Z","publisher":"Springer Nature","year":"2018","issue":"4","quality_controlled":"1","language":[{"iso":"eng"}],"ddc":["000"],"file":[{"content_type":"application/pdf","relation":"main_file","date_updated":"2019-01-08T17:47:06Z","creator":"plessl","date_created":"2019-01-08T17:47:06Z","file_size":2141021,"file_id":"6517","access_level":"closed","file_name":"plessl18_sportseng.pdf"}],"publication":"Sports Engineering"},{"citation":{"chicago":"Ramaswami, Arjun. <i>Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA</i>. Universität Paderborn, 2018.","ieee":"A. Ramaswami, <i>Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA</i>. Universität Paderborn, 2018.","ama":"Ramaswami A. <i>Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA</i>. Universität Paderborn; 2018.","apa":"Ramaswami, A. (2018). <i>Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA</i>. Universität Paderborn.","bibtex":"@book{Ramaswami_2018, title={Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA}, publisher={Universität Paderborn}, author={Ramaswami, Arjun}, year={2018} }","mla":"Ramaswami, Arjun. <i>Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA</i>. Universität Paderborn, 2018.","short":"A. Ramaswami, Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA, Universität Paderborn, 2018."},"has_accepted_license":"1","main_file_link":[{"open_access":"1"}],"supervisor":[{"orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"}],"author":[{"last_name":"Ramaswami","orcid":"https://orcid.org/0000-0002-0909-1178","id":"49171","full_name":"Ramaswami, Arjun","first_name":"Arjun"}],"date_updated":"2022-01-12T16:32:23Z","oa":"1","status":"public","type":"mastersthesis","file_date_updated":"2020-06-15T11:29:38Z","user_id":"49171","department":[{"_id":"27"},{"_id":"518"}],"project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"_id":"5417","year":"2018","title":"Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA","date_created":"2018-11-07T16:08:32Z","publisher":"Universität Paderborn","file":[{"relation":"main_file","success":1,"content_type":"application/pdf","file_id":"17093","file_name":"masterthesis.pdf","access_level":"closed","file_size":1297585,"date_created":"2020-06-15T11:29:38Z","creator":"arjunr","date_updated":"2020-06-15T11:29:38Z"}],"abstract":[{"text":"Molecular Dynamic (MD) simulations are computationally intensive and accelerating them using specialized hardware is a topic of investigation in many studies. One of the routines in the critical path of MD simulations is the three-dimensional Fast Fourier Transformation (FFT3d). The potential in accelerating FFT3d using hardware is usually bound by bandwidth and memory. Therefore, designing a high throughput solution for an FPGA that overcomes this problem is challenging.\r\nIn this thesis, the feasibility of offloading FFT3d computations to FPGA implemented using OpenCL is investigated. In order to mask the latency in memory access, an FFT3d that overlaps computation with communication is designed. The implementa- tion of this design is synthesized for the Arria 10 GX 1150 FPGA and evaluated with the FFTW benchmark. Analysis shows a better performance using FPGA over CPU for larger FFT sizes, with the 643 FFT showing a 70% improvement in runtime using FPGAs.\r\nThis FFT3d design is integrated with CP2K to explore the potential in accelerating molecular dynamic simulations. Evaluation of CP2K simulations using FPGA shows a 41% improvement in runtime in FFT3d computations over CPU for larger FFT3d designs.","lang":"eng"}],"language":[{"iso":"eng"}],"ddc":["000"],"keyword":["FFT: FPGA","CP2K","OpenCL"]},{"publisher":"IEEE","date_created":"2018-03-22T10:48:01Z","title":"OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes","quality_controlled":"1","year":"2018","ddc":["000"],"keyword":["tet_topic_hpc"],"language":[{"iso":"eng"}],"publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","abstract":[{"lang":"eng","text":"The exploration of FPGAs as accelerators for scientific simulations has so far mostly been focused on small kernels of methods working on regular data structures, for example in the form of stencil computations for finite difference methods. In computational sciences, often more advanced methods are employed that promise better stability, convergence, locality and scaling. Unstructured meshes are shown to be more effective and more accurate, compared to regular grids, in representing computation domains of various shapes. Using unstructured meshes, the discontinuous Galerkin method preserves the ability to perform explicit local update operations for simulations in the time domain. In this work, we investigate FPGAs as target platform for an implementation of the nodal discontinuous Galerkin method to find time-domain solutions of Maxwell's equations in an unstructured mesh. When maximizing data reuse and fitting constant coefficients into suitably partitioned on-chip memory, high computational intensity allows us to implement and feed wide data paths with hundreds of floating point operators. By decoupling off-chip memory accesses from the computations, high memory bandwidth can be sustained, even for the irregular access pattern required by parts of the application. Using the Intel/Altera OpenCL SDK for FPGAs, we present different implementation variants for different polynomial orders of the method. In different phases of the algorithm, either computational or bandwidth limits of the Arria 10 platform are almost reached, thus outperforming a highly multithreaded CPU implementation by around 2x."}],"file":[{"content_type":"application/pdf","relation":"main_file","success":1,"creator":"ups","date_created":"2018-11-02T14:45:05Z","date_updated":"2018-11-02T14:45:05Z","file_name":"08457652.pdf","file_id":"5282","access_level":"closed","file_size":269130}],"date_updated":"2023-09-26T11:47:52Z","author":[{"last_name":"Kenter","full_name":"Kenter, Tobias","id":"3145","first_name":"Tobias"},{"full_name":"Mahale, Gopinath","last_name":"Mahale","first_name":"Gopinath"},{"full_name":"Alhaddad, Samer","id":"42456","last_name":"Alhaddad","first_name":"Samer"},{"last_name":"Grynko","id":"26059","full_name":"Grynko, Yevgen","first_name":"Yevgen"},{"first_name":"Christian","last_name":"Schmitt","full_name":"Schmitt, Christian"},{"full_name":"Afzal, Ayesha","last_name":"Afzal","first_name":"Ayesha"},{"first_name":"Frank","full_name":"Hannig, Frank","last_name":"Hannig"},{"orcid":"0000-0001-7059-9862","last_name":"Förstner","id":"158","full_name":"Förstner, Jens","first_name":"Jens"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"}],"conference":{"name":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)"},"doi":"10.1109/FCCM.2018.00037","has_accepted_license":"1","citation":{"apa":"Kenter, T., Mahale, G., Alhaddad, S., Grynko, Y., Schmitt, C., Afzal, A., Hannig, F., Förstner, J., &#38; Plessl, C. (2018). OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). <a href=\"https://doi.org/10.1109/FCCM.2018.00037\">https://doi.org/10.1109/FCCM.2018.00037</a>","short":"T. Kenter, G. Mahale, S. Alhaddad, Y. Grynko, C. Schmitt, A. Afzal, F. Hannig, J. Förstner, C. Plessl, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2018.","mla":"Kenter, Tobias, et al. “OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.” <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, IEEE, 2018, doi:<a href=\"https://doi.org/10.1109/FCCM.2018.00037\">10.1109/FCCM.2018.00037</a>.","bibtex":"@inproceedings{Kenter_Mahale_Alhaddad_Grynko_Schmitt_Afzal_Hannig_Förstner_Plessl_2018, title={OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes}, DOI={<a href=\"https://doi.org/10.1109/FCCM.2018.00037\">10.1109/FCCM.2018.00037</a>}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Kenter, Tobias and Mahale, Gopinath and Alhaddad, Samer and Grynko, Yevgen and Schmitt, Christian and Afzal, Ayesha and Hannig, Frank and Förstner, Jens and Plessl, Christian}, year={2018} }","chicago":"Kenter, Tobias, Gopinath Mahale, Samer Alhaddad, Yevgen Grynko, Christian Schmitt, Ayesha Afzal, Frank Hannig, Jens Förstner, and Christian Plessl. “OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.” In <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>. IEEE, 2018. <a href=\"https://doi.org/10.1109/FCCM.2018.00037\">https://doi.org/10.1109/FCCM.2018.00037</a>.","ieee":"T. Kenter <i>et al.</i>, “OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes,” presented at the Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2018, doi: <a href=\"https://doi.org/10.1109/FCCM.2018.00037\">10.1109/FCCM.2018.00037</a>.","ama":"Kenter T, Mahale G, Alhaddad S, et al. OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. In: <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>. IEEE; 2018. doi:<a href=\"https://doi.org/10.1109/FCCM.2018.00037\">10.1109/FCCM.2018.00037</a>"},"project":[{"_id":"33","name":"HighPerMeshes","grant_number":"01|H16005A"},{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subproject C2"}],"_id":"1588","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"61"}],"file_date_updated":"2018-11-02T14:45:05Z","type":"conference","status":"public"},{"date_updated":"2023-09-26T11:48:12Z","author":[{"first_name":"Michael","last_name":"Lass","orcid":"0000-0002-5708-7632","full_name":"Lass, Michael","id":"24135"},{"first_name":"Stephan","last_name":"Mohr","full_name":"Mohr, Stephan"},{"first_name":"Hendrik","last_name":"Wiebeler","full_name":"Wiebeler, Hendrik"},{"id":"49079","full_name":"Kühne, Thomas","last_name":"Kühne","first_name":"Thomas"},{"id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"}],"doi":"10.1145/3218176.3218231","conference":{"location":"Basel, Switzerland","end_date":"2018-07-04","start_date":"2018-07-02","name":"Platform for Advanced Scientific Computing Conference (PASC)"},"publication_identifier":{"isbn":["978-1-4503-5891-0/18/07"]},"place":"New York, NY, USA","citation":{"mla":"Lass, Michael, et al. “A Massively Parallel Algorithm for the Approximate Calculation of Inverse P-Th Roots of Large Sparse Matrices.” <i>Proc. Platform for Advanced Scientific Computing (PASC) Conference</i>, ACM, 2018, doi:<a href=\"https://doi.org/10.1145/3218176.3218231\">10.1145/3218176.3218231</a>.","short":"M. Lass, S. Mohr, H. Wiebeler, T. Kühne, C. Plessl, in: Proc. Platform for Advanced Scientific Computing (PASC) Conference, ACM, New York, NY, USA, 2018.","bibtex":"@inproceedings{Lass_Mohr_Wiebeler_Kühne_Plessl_2018, place={New York, NY, USA}, title={A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices}, DOI={<a href=\"https://doi.org/10.1145/3218176.3218231\">10.1145/3218176.3218231</a>}, booktitle={Proc. Platform for Advanced Scientific Computing (PASC) Conference}, publisher={ACM}, author={Lass, Michael and Mohr, Stephan and Wiebeler, Hendrik and Kühne, Thomas and Plessl, Christian}, year={2018} }","apa":"Lass, M., Mohr, S., Wiebeler, H., Kühne, T., &#38; Plessl, C. (2018). A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices. <i>Proc. Platform for Advanced Scientific Computing (PASC) Conference</i>. Platform for Advanced Scientific Computing Conference (PASC), Basel, Switzerland. <a href=\"https://doi.org/10.1145/3218176.3218231\">https://doi.org/10.1145/3218176.3218231</a>","chicago":"Lass, Michael, Stephan Mohr, Hendrik Wiebeler, Thomas Kühne, and Christian Plessl. “A Massively Parallel Algorithm for the Approximate Calculation of Inverse P-Th Roots of Large Sparse Matrices.” In <i>Proc. Platform for Advanced Scientific Computing (PASC) Conference</i>. New York, NY, USA: ACM, 2018. <a href=\"https://doi.org/10.1145/3218176.3218231\">https://doi.org/10.1145/3218176.3218231</a>.","ieee":"M. Lass, S. Mohr, H. Wiebeler, T. Kühne, and C. Plessl, “A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices,” presented at the Platform for Advanced Scientific Computing Conference (PASC), Basel, Switzerland, 2018, doi: <a href=\"https://doi.org/10.1145/3218176.3218231\">10.1145/3218176.3218231</a>.","ama":"Lass M, Mohr S, Wiebeler H, Kühne T, Plessl C. A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices. In: <i>Proc. Platform for Advanced Scientific Computing (PASC) Conference</i>. ACM; 2018. doi:<a href=\"https://doi.org/10.1145/3218176.3218231\">10.1145/3218176.3218231</a>"},"_id":"1590","project":[{"_id":"32","name":"Performance and Efficiency in HPC with Custom Computing","grant_number":"PL 595/2-1 / 320898746"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"user_id":"15278","type":"conference","status":"public","publisher":"ACM","date_created":"2018-03-22T10:53:01Z","title":"A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices","quality_controlled":"1","year":"2018","external_id":{"arxiv":["1710.10899"]},"keyword":["approximate computing","linear algebra","matrix inversion","matrix p-th roots","numeric algorithm","parallel computing"],"language":[{"iso":"eng"}],"publication":"Proc. Platform for Advanced Scientific Computing (PASC) Conference","abstract":[{"lang":"eng","text":"We present the submatrix method, a highly parallelizable method for the approximate calculation of inverse p-th roots of large sparse symmetric matrices which are required in different scientific applications. Following the idea of Approximate Computing, we allow imprecision in the final result in order to utilize the sparsity of the input matrix and to allow massively parallel execution. For an n x n matrix, the proposed algorithm allows to distribute the calculations over n nodes with only little communication overhead. The result matrix exhibits the same sparsity pattern as the input matrix, allowing for efficient reuse of allocated data structures.\r\n\r\nWe evaluate the algorithm with respect to the error that it introduces into calculated results, as well as its performance and scalability. We demonstrate that the error is relatively limited for well-conditioned matrices and that results are still valuable for error-resilient applications like preconditioning even for ill-conditioned matrices. We discuss the execution time and scaling of the algorithm on a theoretical level and present a distributed implementation of the algorithm using MPI and OpenMP. We demonstrate the scalability of this implementation by running it on a high-performance compute cluster comprised of 1024 CPU cores, showing a speedup of 665x compared to single-threaded execution."}]},{"date_created":"2018-03-08T14:45:18Z","publisher":"ACM","title":"Automated Code Acceleration Targeting Heterogeneous OpenCL Devices","quality_controlled":"1","year":"2018","language":[{"iso":"eng"}],"keyword":["htrop"],"ddc":["000"],"publication":"Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)","file":[{"content_type":"application/pdf","relation":"main_file","success":1,"creator":"ups","date_created":"2018-11-02T14:43:37Z","date_updated":"2018-11-02T14:43:37Z","file_name":"p417-riebler.pdf","access_level":"closed","file_id":"5281","file_size":447769}],"author":[{"last_name":"Riebler","id":"8961","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"first_name":"Gavin Francis","last_name":"Vaz","full_name":"Vaz, Gavin Francis","id":"30332"},{"full_name":"Kenter, Tobias","id":"3145","last_name":"Kenter","first_name":"Tobias"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"}],"date_updated":"2023-09-26T11:47:23Z","doi":"10.1145/3178487.3178534","publication_identifier":{"isbn":["9781450349826"]},"has_accepted_license":"1","publication_status":"published","citation":{"ama":"Riebler H, Vaz GF, Kenter T, Plessl C. Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. In: <i>Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)</i>. ACM; 2018. doi:<a href=\"https://doi.org/10.1145/3178487.3178534\">10.1145/3178487.3178534</a>","ieee":"H. Riebler, G. F. Vaz, T. Kenter, and C. Plessl, “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices,” 2018, doi: <a href=\"https://doi.org/10.1145/3178487.3178534\">10.1145/3178487.3178534</a>.","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Tobias Kenter, and Christian Plessl. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” In <i>Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)</i>. ACM, 2018. <a href=\"https://doi.org/10.1145/3178487.3178534\">https://doi.org/10.1145/3178487.3178534</a>.","apa":"Riebler, H., Vaz, G. F., Kenter, T., &#38; Plessl, C. (2018). Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. <i>Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)</i>. <a href=\"https://doi.org/10.1145/3178487.3178534\">https://doi.org/10.1145/3178487.3178534</a>","short":"H. Riebler, G.F. Vaz, T. Kenter, C. Plessl, in: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018.","mla":"Riebler, Heinrich, et al. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” <i>Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)</i>, ACM, 2018, doi:<a href=\"https://doi.org/10.1145/3178487.3178534\">10.1145/3178487.3178534</a>.","bibtex":"@inproceedings{Riebler_Vaz_Kenter_Plessl_2018, title={Automated Code Acceleration Targeting Heterogeneous OpenCL Devices}, DOI={<a href=\"https://doi.org/10.1145/3178487.3178534\">10.1145/3178487.3178534</a>}, booktitle={Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)}, publisher={ACM}, author={Riebler, Heinrich and Vaz, Gavin Francis and Kenter, Tobias and Plessl, Christian}, year={2018} }"},"department":[{"_id":"27"},{"_id":"518"}],"user_id":"15278","_id":"1204","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"160364472","name":"SFB 901 - Subproject C2","_id":"14"}],"file_date_updated":"2018-11-02T14:43:37Z","type":"conference","status":"public"},{"publication":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","file":[{"date_updated":"2018-11-02T16:04:14Z","creator":"ups","date_created":"2018-11-02T16:04:14Z","file_size":2131617,"access_level":"closed","file_id":"5322","file_name":"a24-riebler.pdf","content_type":"application/pdf","success":1,"relation":"main_file"}],"abstract":[{"text":"Branch and bound (B&B) algorithms structure the search space as a tree and eliminate infeasible solutions early by pruning subtrees that cannot lead to a valid or optimal solution. Custom hardware designs significantly accelerate the execution of these algorithms. In this article, we demonstrate a high-performance B&B implementation on FPGAs. First, we identify general elements of B&B algorithms and describe their implementation as a finite state machine. Then, we introduce workers that autonomously cooperate using work stealing to allow parallel execution and full utilization of the target FPGA. Finally, we explore advantages of instance-specific designs that target a specific problem instance to improve performance.\r\n\r\nWe evaluate our concepts by applying them to a branch and bound problem, the reconstruction of corrupted AES keys obtained from cold-boot attacks. The evaluation shows that our work stealing approach is scalable with the available resources and provides speedups proportional to the number of workers. Instance-specific designs allow us to achieve an overall speedup of 47 × compared to the fastest implementation of AES key reconstruction so far. Finally, we demonstrate how instance-specific designs can be generated just-in-time such that the provided speedups outweigh the additional time required for design synthesis.","lang":"eng"}],"language":[{"iso":"eng"}],"ddc":["000"],"keyword":["coldboot"],"issue":"3","quality_controlled":"1","year":"2017","date_created":"2017-07-25T14:17:32Z","publisher":"Association for Computing Machinery (ACM)","title":"Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs","type":"journal_article","status":"public","user_id":"15278","department":[{"_id":"27"},{"_id":"518"}],"project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subproject C2"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"_id":"18","file_date_updated":"2018-11-02T16:04:14Z","publication_status":"published","publication_identifier":{"issn":["1936-7406"]},"has_accepted_license":"1","citation":{"short":"H. Riebler, M. Lass, R. Mittendorf, T. Löcke, C. Plessl, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 10 (2017) 24:1-24:23.","bibtex":"@article{Riebler_Lass_Mittendorf_Löcke_Plessl_2017, title={Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs}, volume={10}, DOI={<a href=\"https://doi.org/10.1145/3053687\">10.1145/3053687</a>}, number={3}, journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={Association for Computing Machinery (ACM)}, author={Riebler, Heinrich and Lass, Michael and Mittendorf, Robert and Löcke, Thomas and Plessl, Christian}, year={2017}, pages={24:1-24:23} }","mla":"Riebler, Heinrich, et al. “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs.” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, vol. 10, no. 3, Association for Computing Machinery (ACM), 2017, p. 24:1-24:23, doi:<a href=\"https://doi.org/10.1145/3053687\">10.1145/3053687</a>.","apa":"Riebler, H., Lass, M., Mittendorf, R., Löcke, T., &#38; Plessl, C. (2017). Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs. <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, <i>10</i>(3), 24:1-24:23. <a href=\"https://doi.org/10.1145/3053687\">https://doi.org/10.1145/3053687</a>","ama":"Riebler H, Lass M, Mittendorf R, Löcke T, Plessl C. Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs. <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>. 2017;10(3):24:1-24:23. doi:<a href=\"https://doi.org/10.1145/3053687\">10.1145/3053687</a>","ieee":"H. Riebler, M. Lass, R. Mittendorf, T. Löcke, and C. Plessl, “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs,” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, vol. 10, no. 3, p. 24:1-24:23, 2017, doi: <a href=\"https://doi.org/10.1145/3053687\">10.1145/3053687</a>.","chicago":"Riebler, Heinrich, Michael Lass, Robert Mittendorf, Thomas Löcke, and Christian Plessl. “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs.” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i> 10, no. 3 (2017): 24:1-24:23. <a href=\"https://doi.org/10.1145/3053687\">https://doi.org/10.1145/3053687</a>."},"intvolume":"        10","page":"24:1-24:23","author":[{"first_name":"Heinrich","full_name":"Riebler, Heinrich","id":"8961","last_name":"Riebler"},{"first_name":"Michael","orcid":"0000-0002-5708-7632","last_name":"Lass","full_name":"Lass, Michael","id":"24135"},{"first_name":"Robert","full_name":"Mittendorf, Robert","last_name":"Mittendorf"},{"full_name":"Löcke, Thomas","last_name":"Löcke","first_name":"Thomas"},{"id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"volume":10,"date_updated":"2023-09-26T13:23:58Z","doi":"10.1145/3053687"},{"author":[{"first_name":"Tobias","last_name":"Kenter","full_name":"Kenter, Tobias","id":"3145"},{"first_name":"Jens","id":"158","full_name":"Förstner, Jens","last_name":"Förstner","orcid":"0000-0001-7059-9862"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl"}],"date_updated":"2023-09-26T13:24:38Z","doi":"10.23919/FPL.2017.8056844","has_accepted_license":"1","citation":{"ama":"Kenter T, Förstner J, Plessl C. Flexible FPGA design for FDTD using OpenCL. In: <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>. IEEE; 2017. doi:<a href=\"https://doi.org/10.23919/FPL.2017.8056844\">10.23919/FPL.2017.8056844</a>","chicago":"Kenter, Tobias, Jens Förstner, and Christian Plessl. “Flexible FPGA Design for FDTD Using OpenCL.” In <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>. IEEE, 2017. <a href=\"https://doi.org/10.23919/FPL.2017.8056844\">https://doi.org/10.23919/FPL.2017.8056844</a>.","ieee":"T. Kenter, J. Förstner, and C. Plessl, “Flexible FPGA design for FDTD using OpenCL,” 2017, doi: <a href=\"https://doi.org/10.23919/FPL.2017.8056844\">10.23919/FPL.2017.8056844</a>.","bibtex":"@inproceedings{Kenter_Förstner_Plessl_2017, title={Flexible FPGA design for FDTD using OpenCL}, DOI={<a href=\"https://doi.org/10.23919/FPL.2017.8056844\">10.23919/FPL.2017.8056844</a>}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Kenter, Tobias and Förstner, Jens and Plessl, Christian}, year={2017} }","short":"T. Kenter, J. Förstner, C. Plessl, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2017.","mla":"Kenter, Tobias, et al. “Flexible FPGA Design for FDTD Using OpenCL.” <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2017, doi:<a href=\"https://doi.org/10.23919/FPL.2017.8056844\">10.23919/FPL.2017.8056844</a>.","apa":"Kenter, T., Förstner, J., &#38; Plessl, C. (2017). Flexible FPGA design for FDTD using OpenCL. <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>. <a href=\"https://doi.org/10.23919/FPL.2017.8056844\">https://doi.org/10.23919/FPL.2017.8056844</a>"},"department":[{"_id":"27"},{"_id":"518"},{"_id":"61"}],"user_id":"15278","_id":"1592","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"160364472","name":"SFB 901 - Subproject C2","_id":"14"},{"_id":"33","name":"HighPerMeshes","grant_number":"01|H16005A"},{"grant_number":"PL 595/2-1 / 320898746","_id":"32","name":"Performance and Efficiency in HPC with Custom Computing"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"file_date_updated":"2018-11-02T15:02:28Z","type":"conference","status":"public","date_created":"2018-03-22T11:10:23Z","publisher":"IEEE","title":"Flexible FPGA design for FDTD using OpenCL","quality_controlled":"1","year":"2017","language":[{"iso":"eng"}],"keyword":["tet_topic_hpc"],"ddc":["000"],"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","file":[{"file_size":230235,"file_id":"5291","access_level":"closed","file_name":"08056844.pdf","date_updated":"2018-11-02T15:02:28Z","date_created":"2018-11-02T15:02:28Z","creator":"ups","success":1,"relation":"main_file","content_type":"application/pdf"}],"abstract":[{"text":"Compared to classical HDL designs, generating FPGA with high-level synthesis from an OpenCL specification promises easier exploration of different design alternatives and, through ready-to-use infrastructure and common abstractions for host and memory interfaces, easier portability between different FPGA families. In this work, we evaluate the extent of this promise. To this end, we present a parameterized FDTD implementation for photonic microcavity simulations. Our design can trade-off different forms of parallelism and works for two independent OpenCL-based FPGA design flows. Hence, we can target FPGAs from different vendors and different FPGA families. We describe how we used pre-processor macros to achieve this flexibility and to work around different shortcomings of the current tools. Choosing the right design configurations, we are able to present two extremely competitive solutions for very different FPGA targets, reaching up to 172 GFLOPS sustained performance. With the portability and flexibility demonstrated, code developers not only avoid vendor lock-in, but can even make best use of real trade-offs between different architectures.","lang":"eng"}]},{"article_number":"082003","language":[{"iso":"eng"}],"_id":"1589","user_id":"15278","department":[{"_id":"27"},{"_id":"518"}],"status":"public","type":"journal_article","publication":"Journal of Physics: Conference Series","title":"High-Throughput and Low-Latency Network Communication with NetIO","doi":"10.1088/1742-6596/898/8/082003","date_updated":"2023-09-26T13:24:19Z","publisher":"IOP Publishing","date_created":"2018-03-22T10:51:20Z","author":[{"last_name":"Schumacher","full_name":"Schumacher, Jörn","first_name":"Jörn"},{"full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"full_name":"Vandelli, Wainer","last_name":"Vandelli","first_name":"Wainer"}],"volume":898,"year":"2017","citation":{"bibtex":"@article{Schumacher_Plessl_Vandelli_2017, title={High-Throughput and Low-Latency Network Communication with NetIO}, volume={898}, DOI={<a href=\"https://doi.org/10.1088/1742-6596/898/8/082003\">10.1088/1742-6596/898/8/082003</a>}, number={082003}, journal={Journal of Physics: Conference Series}, publisher={IOP Publishing}, author={Schumacher, Jörn and Plessl, Christian and Vandelli, Wainer}, year={2017} }","short":"J. Schumacher, C. Plessl, W. Vandelli, Journal of Physics: Conference Series 898 (2017).","mla":"Schumacher, Jörn, et al. “High-Throughput and Low-Latency Network Communication with NetIO.” <i>Journal of Physics: Conference Series</i>, vol. 898, 082003, IOP Publishing, 2017, doi:<a href=\"https://doi.org/10.1088/1742-6596/898/8/082003\">10.1088/1742-6596/898/8/082003</a>.","apa":"Schumacher, J., Plessl, C., &#38; Vandelli, W. (2017). High-Throughput and Low-Latency Network Communication with NetIO. <i>Journal of Physics: Conference Series</i>, <i>898</i>, Article 082003. <a href=\"https://doi.org/10.1088/1742-6596/898/8/082003\">https://doi.org/10.1088/1742-6596/898/8/082003</a>","ieee":"J. Schumacher, C. Plessl, and W. Vandelli, “High-Throughput and Low-Latency Network Communication with NetIO,” <i>Journal of Physics: Conference Series</i>, vol. 898, Art. no. 082003, 2017, doi: <a href=\"https://doi.org/10.1088/1742-6596/898/8/082003\">10.1088/1742-6596/898/8/082003</a>.","chicago":"Schumacher, Jörn, Christian Plessl, and Wainer Vandelli. “High-Throughput and Low-Latency Network Communication with NetIO.” <i>Journal of Physics: Conference Series</i> 898 (2017). <a href=\"https://doi.org/10.1088/1742-6596/898/8/082003\">https://doi.org/10.1088/1742-6596/898/8/082003</a>.","ama":"Schumacher J, Plessl C, Vandelli W. High-Throughput and Low-Latency Network Communication with NetIO. <i>Journal of Physics: Conference Series</i>. 2017;898. doi:<a href=\"https://doi.org/10.1088/1742-6596/898/8/082003\">10.1088/1742-6596/898/8/082003</a>"},"intvolume":"       898","quality_controlled":"1"},{"publication_status":"published","publication_identifier":{"isbn":["978-1-5090-2054-6"]},"citation":{"bibtex":"@inproceedings{Lass_Leibenger_Sorge_2016, title={Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension}, DOI={<a href=\"https://doi.org/10.1109/lcn.2016.11\">10.1109/lcn.2016.11</a>}, booktitle={Proc. 41st Conference on Local Computer Networks (LCN)}, publisher={IEEE}, author={Lass, Michael and Leibenger, Dominik and Sorge, Christoph}, year={2016} }","mla":"Lass, Michael, et al. “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension.” <i>Proc. 41st Conference on Local Computer Networks (LCN)</i>, IEEE, 2016, doi:<a href=\"https://doi.org/10.1109/lcn.2016.11\">10.1109/lcn.2016.11</a>.","short":"M. Lass, D. Leibenger, C. Sorge, in: Proc. 41st Conference on Local Computer Networks (LCN), IEEE, 2016.","apa":"Lass, M., Leibenger, D., &#38; Sorge, C. (2016). Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension. In <i>Proc. 41st Conference on Local Computer Networks (LCN)</i>. IEEE. <a href=\"https://doi.org/10.1109/lcn.2016.11\">https://doi.org/10.1109/lcn.2016.11</a>","ama":"Lass M, Leibenger D, Sorge C. Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension. In: <i>Proc. 41st Conference on Local Computer Networks (LCN)</i>. IEEE; 2016. doi:<a href=\"https://doi.org/10.1109/lcn.2016.11\">10.1109/lcn.2016.11</a>","ieee":"M. Lass, D. Leibenger, and C. Sorge, “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension,” in <i>Proc. 41st Conference on Local Computer Networks (LCN)</i>, 2016.","chicago":"Lass, Michael, Dominik Leibenger, and Christoph Sorge. “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension.” In <i>Proc. 41st Conference on Local Computer Networks (LCN)</i>. IEEE, 2016. <a href=\"https://doi.org/10.1109/lcn.2016.11\">https://doi.org/10.1109/lcn.2016.11</a>."},"year":"2016","date_created":"2017-07-25T14:36:16Z","author":[{"last_name":"Lass","orcid":"0000-0002-5708-7632","full_name":"Lass, Michael","id":"24135","first_name":"Michael"},{"last_name":"Leibenger","full_name":"Leibenger, Dominik","first_name":"Dominik"},{"full_name":"Sorge, Christoph","last_name":"Sorge","first_name":"Christoph"}],"date_updated":"2022-01-06T06:53:56Z","publisher":"IEEE","doi":"10.1109/lcn.2016.11","title":"Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension","type":"conference","publication":"Proc. 41st Conference on Local Computer Networks (LCN)","status":"public","abstract":[{"text":"Version Control Systems (VCS) are a valuable tool for software development\r\nand document management. Both client/server and distributed (Peer-to-Peer)\r\nmodels exist, with the latter (e.g., Git and Mercurial) becoming\r\nincreasingly popular. Their distributed nature introduces complications,\r\nespecially concerning security: it is hard to control the dissemination of\r\ncontents stored in distributed VCS as they rely on replication of complete\r\nrepositories to any involved user.\r\n\r\nWe overcome this issue by designing and implementing a concept for\r\ncryptography-enforced access control which is transparent to the user. Use\r\nof field-tested schemes (end-to-end encryption, digital signatures) allows\r\nfor strong security, while adoption of convergent encryption and\r\ncontent-defined chunking retains storage efficiency. The concept is\r\nseamlessly integrated into Mercurial---respecting its distributed storage\r\nconcept---to ensure practical usability and compatibility to existing\r\ndeployments.","lang":"eng"}],"user_id":"24135","department":[{"_id":"27"},{"_id":"518"}],"_id":"19","language":[{"iso":"eng"}],"keyword":["access control","distributed version control systems","mercurial","peer-to-peer","convergent encryption","confidentiality","authenticity"]},{"title":"Sicherheit von hybriden FPGA-Systemen in der industriellen Automatisierungstechnik -- Anforderungen und Umsetzung","date_updated":"2022-01-06T07:01:52Z","publisher":"Universität Paderborn","supervisor":[{"full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"}],"author":[{"first_name":"Christian","last_name":"Tölke","full_name":"Tölke, Christian"}],"date_created":"2018-11-07T16:10:00Z","year":"2016","citation":{"bibtex":"@book{Tölke_2016, title={Sicherheit von hybriden FPGA-Systemen in der industriellen Automatisierungstechnik -- Anforderungen und Umsetzung}, publisher={Universität Paderborn}, author={Tölke, Christian}, year={2016} }","short":"C. Tölke, Sicherheit von Hybriden FPGA-Systemen in Der Industriellen Automatisierungstechnik -- Anforderungen Und Umsetzung, Universität Paderborn, 2016.","mla":"Tölke, Christian. <i>Sicherheit von Hybriden FPGA-Systemen in Der Industriellen Automatisierungstechnik -- Anforderungen Und Umsetzung</i>. Universität Paderborn, 2016.","apa":"Tölke, C. (2016). <i>Sicherheit von hybriden FPGA-Systemen in der industriellen Automatisierungstechnik -- Anforderungen und Umsetzung</i>. Universität Paderborn.","ama":"Tölke C. <i>Sicherheit von Hybriden FPGA-Systemen in Der Industriellen Automatisierungstechnik -- Anforderungen Und Umsetzung</i>. Universität Paderborn; 2016.","ieee":"C. Tölke, <i>Sicherheit von hybriden FPGA-Systemen in der industriellen Automatisierungstechnik -- Anforderungen und Umsetzung</i>. Universität Paderborn, 2016.","chicago":"Tölke, Christian. <i>Sicherheit von Hybriden FPGA-Systemen in Der Industriellen Automatisierungstechnik -- Anforderungen Und Umsetzung</i>. Universität Paderborn, 2016."},"language":[{"iso":"eng"}],"project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"_id":"5418","user_id":"477","department":[{"_id":"27"},{"_id":"518"}],"status":"public","type":"mastersthesis"},{"language":[{"iso":"eng"}],"project":[{"name":"SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"SFB 901 - Subproject C2","_id":"14"}],"_id":"5420","user_id":"477","department":[{"_id":"27"},{"_id":"518"}],"status":"public","type":"mastersthesis","title":"Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment","date_updated":"2022-01-06T07:01:53Z","publisher":"Universität Paderborn","date_created":"2018-11-07T16:15:51Z","supervisor":[{"orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"}],"author":[{"first_name":"Gunnar","last_name":"Wüllrich","full_name":"Wüllrich, Gunnar"}],"year":"2016","citation":{"ieee":"G. Wüllrich, <i>Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment</i>. Universität Paderborn, 2016.","chicago":"Wüllrich, Gunnar. <i>Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment</i>. Universität Paderborn, 2016.","ama":"Wüllrich G. <i>Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment</i>. Universität Paderborn; 2016.","apa":"Wüllrich, G. (2016). <i>Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment</i>. Universität Paderborn.","mla":"Wüllrich, Gunnar. <i>Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment</i>. Universität Paderborn, 2016.","short":"G. Wüllrich, Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment, Universität Paderborn, 2016.","bibtex":"@book{Wüllrich_2016, title={Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment}, publisher={Universität Paderborn}, author={Wüllrich, Gunnar}, year={2016} }"}},{"has_accepted_license":"1","citation":{"apa":"Kenter, T. (2016). <i>Reconfigurable Accelerators in the World of General-Purpose Computing</i>. Universität Paderborn.","short":"T. Kenter, Reconfigurable Accelerators in the World of General-Purpose Computing, Universität Paderborn, 2016.","bibtex":"@book{Kenter_2016, title={Reconfigurable Accelerators in the World of General-Purpose Computing}, publisher={Universität Paderborn}, author={Kenter, Tobias}, year={2016} }","mla":"Kenter, Tobias. <i>Reconfigurable Accelerators in the World of General-Purpose Computing</i>. Universität Paderborn, 2016.","ieee":"T. Kenter, <i>Reconfigurable Accelerators in the World of General-Purpose Computing</i>. Universität Paderborn, 2016.","chicago":"Kenter, Tobias. <i>Reconfigurable Accelerators in the World of General-Purpose Computing</i>. Universität Paderborn, 2016.","ama":"Kenter T. <i>Reconfigurable Accelerators in the World of General-Purpose Computing</i>. Universität Paderborn; 2016."},"year":"2016","date_created":"2017-10-17T12:41:23Z","supervisor":[{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153"}],"author":[{"full_name":"Kenter, Tobias","id":"3145","last_name":"Kenter","first_name":"Tobias"}],"publisher":"Universität Paderborn","date_updated":"2022-01-06T06:52:43Z","title":"Reconfigurable Accelerators in the World of General-Purpose Computing","type":"dissertation","file":[{"date_updated":"2018-03-21T12:46:48Z","creator":"florida","date_created":"2018-03-21T12:46:48Z","file_size":5039555,"file_name":"161kenter16_diss_submission_print_16-08-26.pdf","file_id":"1545","access_level":"closed","content_type":"application/pdf","success":1,"relation":"main_file"}],"status":"public","user_id":"3145","department":[{"_id":"27"},{"_id":"518"}],"project":[{"_id":"1","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"}],"_id":"161","file_date_updated":"2018-03-21T12:46:48Z","ddc":["040"]},{"year":"2016","quality_controlled":"1","title":"ReconOS","date_created":"2017-07-26T15:07:06Z","publisher":"Springer International Publishing","abstract":[{"text":"In this chapter, we present an introduction to the ReconOS operating system for reconfigurable computing. ReconOS offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. By supporting standard POSIX operating system functions for both software and hardware threads, ReconOS particularly caters to developers with a software background, because developers can use well-known mechanisms such as semaphores, mutexes, condition variables, and message queues for developing hybrid applications with threads running on the CPU and FPGA concurrently. Through the semantic integration of hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications between different reconfigurable computing systems.","lang":"eng"}],"publication":"FPGAs for Software Programmers","language":[{"iso":"eng"}],"citation":{"mla":"Agne, Andreas, et al. “ReconOS.” <i>FPGAs for Software Programmers</i>, edited by Dirk Koch et al., Springer International Publishing, 2016, pp. 227–44, doi:<a href=\"https://doi.org/10.1007/978-3-319-26408-0_13\">10.1007/978-3-319-26408-0_13</a>.","bibtex":"@inbook{Agne_Platzner_Plessl_Happe_Lübbers_2016, place={Cham}, title={ReconOS}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-26408-0_13\">10.1007/978-3-319-26408-0_13</a>}, booktitle={FPGAs for Software Programmers}, publisher={Springer International Publishing}, author={Agne, Andreas and Platzner, Marco and Plessl, Christian and Happe, Markus and Lübbers, Enno}, editor={Koch, Dirk and Hannig, Frank and Ziener, Daniel}, year={2016}, pages={227–244} }","short":"A. Agne, M. Platzner, C. Plessl, M. Happe, E. Lübbers, in: D. Koch, F. Hannig, D. Ziener (Eds.), FPGAs for Software Programmers, Springer International Publishing, Cham, 2016, pp. 227–244.","apa":"Agne, A., Platzner, M., Plessl, C., Happe, M., &#38; Lübbers, E. (2016). ReconOS. In D. Koch, F. Hannig, &#38; D. Ziener (Eds.), <i>FPGAs for Software Programmers</i> (pp. 227–244). Springer International Publishing. <a href=\"https://doi.org/10.1007/978-3-319-26408-0_13\">https://doi.org/10.1007/978-3-319-26408-0_13</a>","ama":"Agne A, Platzner M, Plessl C, Happe M, Lübbers E. ReconOS. In: Koch D, Hannig F, Ziener D, eds. <i>FPGAs for Software Programmers</i>. Springer International Publishing; 2016:227-244. doi:<a href=\"https://doi.org/10.1007/978-3-319-26408-0_13\">10.1007/978-3-319-26408-0_13</a>","chicago":"Agne, Andreas, Marco Platzner, Christian Plessl, Markus Happe, and Enno Lübbers. “ReconOS.” In <i>FPGAs for Software Programmers</i>, edited by Dirk Koch, Frank Hannig, and Daniel Ziener, 227–44. Cham: Springer International Publishing, 2016. <a href=\"https://doi.org/10.1007/978-3-319-26408-0_13\">https://doi.org/10.1007/978-3-319-26408-0_13</a>.","ieee":"A. Agne, M. Platzner, C. Plessl, M. Happe, and E. Lübbers, “ReconOS,” in <i>FPGAs for Software Programmers</i>, D. Koch, F. Hannig, and D. Ziener, Eds. Cham: Springer International Publishing, 2016, pp. 227–244."},"page":"227-244","place":"Cham","publication_status":"published","publication_identifier":{"isbn":["978-3-319-26406-6","978-3-319-26408-0"]},"doi":"10.1007/978-3-319-26408-0_13","author":[{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"},{"full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"},{"full_name":"Happe, Markus","last_name":"Happe","first_name":"Markus"},{"first_name":"Enno","full_name":"Lübbers, Enno","last_name":"Lübbers"}],"date_updated":"2023-09-26T13:25:38Z","status":"public","editor":[{"first_name":"Dirk","last_name":"Koch","full_name":"Koch, Dirk"},{"full_name":"Hannig, Frank","last_name":"Hannig","first_name":"Frank"},{"first_name":"Daniel","full_name":"Ziener, Daniel","last_name":"Ziener"}],"type":"book_chapter","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"257906","_id":"31","name":"Engineering Proprioception in Computing Systems"}],"_id":"29"},{"user_id":"15278","department":[{"_id":"27"},{"_id":"518"}],"project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"SFB 901 - Subproject C2","_id":"14","grant_number":"160364472"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"_id":"31","language":[{"iso":"eng"}],"file_date_updated":"2019-01-11T11:56:55Z","ddc":["040"],"type":"conference","publication":"Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)","file":[{"file_id":"6626","access_level":"closed","file_name":"wrc_upb_polimi_final.pdf","file_size":394563,"creator":"deffel","date_created":"2019-01-11T11:56:55Z","date_updated":"2019-01-11T11:56:55Z","relation":"main_file","success":1,"content_type":"application/pdf"}],"status":"public","author":[{"last_name":"Riebler","id":"8961","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"last_name":"Vaz","full_name":"Vaz, Gavin Francis","id":"30332","first_name":"Gavin Francis"},{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian"},{"full_name":"Trainiti, Ettore M. G.","last_name":"Trainiti","first_name":"Ettore M. G."},{"full_name":"Durelli, Gianluca C.","last_name":"Durelli","first_name":"Gianluca C."},{"first_name":"Cristiana","full_name":"Bolchini, Cristiana","last_name":"Bolchini"}],"date_created":"2017-07-26T15:16:31Z","date_updated":"2023-09-26T13:25:59Z","title":"Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems","has_accepted_license":"1","quality_controlled":"1","citation":{"ama":"Riebler H, Vaz GF, Plessl C, Trainiti EMG, Durelli GC, Bolchini C. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: <i>Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)</i>. ; 2016.","ieee":"H. Riebler, G. F. Vaz, C. Plessl, E. M. G. Trainiti, G. C. Durelli, and C. Bolchini, “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” 2016.","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, and Cristiana Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In <i>Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)</i>, 2016.","apa":"Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., &#38; Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. <i>Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)</i>.","short":"H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, C. Bolchini, in: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.","mla":"Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” <i>Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)</i>, 2016.","bibtex":"@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, booktitle={Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Bolchini, Cristiana}, year={2016} }"},"year":"2016"},{"quality_controlled":"1","has_accepted_license":"1","citation":{"short":"T. Kenter, C. Plessl, in: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016.","bibtex":"@inproceedings{Kenter_Plessl_2016, title={Microdisk Cavity FDTD Simulation on FPGA using OpenCL}, booktitle={Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, author={Kenter, Tobias and Plessl, Christian}, year={2016} }","mla":"Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” <i>Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC)</i>, 2016.","apa":"Kenter, T., &#38; Plessl, C. (2016). Microdisk Cavity FDTD Simulation on FPGA using OpenCL. <i>Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC)</i>.","ieee":"T. Kenter and C. Plessl, “Microdisk Cavity FDTD Simulation on FPGA using OpenCL,” 2016.","chicago":"Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” In <i>Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC)</i>, 2016.","ama":"Kenter T, Plessl C. Microdisk Cavity FDTD Simulation on FPGA using OpenCL. In: <i>Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC)</i>. ; 2016."},"year":"2016","author":[{"first_name":"Tobias","last_name":"Kenter","full_name":"Kenter, Tobias","id":"3145"},{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153"}],"date_created":"2017-07-26T15:00:43Z","date_updated":"2023-09-26T13:26:17Z","title":"Microdisk Cavity FDTD Simulation on FPGA using OpenCL","publication":"Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)","type":"conference","status":"public","file":[{"date_updated":"2018-11-14T12:38:45Z","creator":"kenter","date_created":"2018-11-14T12:38:45Z","file_size":129552,"file_id":"5602","file_name":"paper_26.pdf","access_level":"closed","content_type":"application/pdf","success":1,"relation":"main_file"}],"department":[{"_id":"27"},{"_id":"518"}],"user_id":"15278","_id":"24","project":[{"grant_number":"PL 595/2-1 / 320898746","_id":"32","name":"Performance and Efficiency in HPC with Custom Computing"},{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subproject C2"}],"file_date_updated":"2018-11-14T12:38:45Z","language":[{"iso":"eng"}],"ddc":["004"]},{"_id":"25","project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"user_id":"15278","language":[{"iso":"eng"}],"publication":"Workshop on Approximate Computing (AC)","type":"conference","status":"public","date_updated":"2023-09-26T13:25:17Z","date_created":"2017-07-26T15:02:20Z","author":[{"last_name":"Lass","orcid":"0000-0002-5708-7632","id":"24135","full_name":"Lass, Michael","first_name":"Michael"},{"last_name":"Kühne","id":"49079","full_name":"Kühne, Thomas","first_name":"Thomas"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"}],"title":"Using Approximate Computing in Scientific Codes","quality_controlled":"1","year":"2016","citation":{"mla":"Lass, Michael, et al. “Using Approximate Computing in Scientific Codes.” <i>Workshop on Approximate Computing (AC)</i>, 2016.","bibtex":"@inproceedings{Lass_Kühne_Plessl_2016, title={Using Approximate Computing in Scientific Codes}, booktitle={Workshop on Approximate Computing (AC)}, author={Lass, Michael and Kühne, Thomas and Plessl, Christian}, year={2016} }","short":"M. Lass, T. Kühne, C. Plessl, in: Workshop on Approximate Computing (AC), 2016.","apa":"Lass, M., Kühne, T., &#38; Plessl, C. (2016). Using Approximate Computing in Scientific Codes. <i>Workshop on Approximate Computing (AC)</i>.","ama":"Lass M, Kühne T, Plessl C. Using Approximate Computing in Scientific Codes. In: <i>Workshop on Approximate Computing (AC)</i>. ; 2016.","chicago":"Lass, Michael, Thomas Kühne, and Christian Plessl. “Using Approximate Computing in Scientific Codes.” In <i>Workshop on Approximate Computing (AC)</i>, 2016.","ieee":"M. Lass, T. Kühne, and C. Plessl, “Using Approximate Computing in Scientific Codes,” 2016."}},{"type":"conference","publication":"Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)","abstract":[{"lang":"eng","text":"Hardware accelerators are becoming popular in academia and industry. To move one step further from the state-of-the-art multicore plus accelerator approaches, we present in this paper our innovative SAVEHSA architecture. It comprises of a heterogeneous hardware platform with three different high-end accelerators attached over PCIe (GPGPU, FPGA and Intel MIC). Such systems can process parallel workloads very efficiently whilst being more energy efficient than regular CPU systems. To leverage the heterogeneity, the workload has to be distributed among the computing units in a way that each unit is well-suited for the assigned task and executable code must be available. To tackle this problem we present two software components; the first can perform resource allocation at runtime while respecting system and application goals (in terms of throughput, energy, latency, etc.) and the second is able to analyze an application and generate executable code for an accelerator at runtime. We demonstrate the first proof-of-concept implementation of our framework on the heterogeneous platform, discuss different runtime policies and measure the introduced overheads."}],"file":[{"file_size":184334,"file_name":"138-07740545.pdf","access_level":"closed","file_id":"1560","date_updated":"2018-03-21T13:01:09Z","date_created":"2018-03-21T13:01:09Z","creator":"florida","success":1,"relation":"main_file","content_type":"application/pdf"}],"status":"public","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"_id":"138","user_id":"15278","department":[{"_id":"27"},{"_id":"518"}],"ddc":["040"],"file_date_updated":"2018-03-21T13:01:09Z","language":[{"iso":"eng"}],"quality_controlled":"1","has_accepted_license":"1","year":"2016","citation":{"short":"H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, E. Del Sozzo, M.D. Santambrogio, C. Bolchini, in: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5.","bibtex":"@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Del Sozzo_Santambrogio_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, DOI={<a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">10.1109/RTSI.2016.7740545</a>}, booktitle={Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)}, publisher={IEEE}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G.  and Durelli, Gianluca C. and Del Sozzo, Emanuele and Santambrogio, Marco D.  and Bolchini, Christina}, year={2016}, pages={1–5} }","mla":"Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” <i>Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)</i>, IEEE, 2016, pp. 1–5, doi:<a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">10.1109/RTSI.2016.7740545</a>.","apa":"Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., Del Sozzo, E., Santambrogio, M. D., &#38; Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. <i>Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)</i>, 1–5. <a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">https://doi.org/10.1109/RTSI.2016.7740545</a>","ama":"Riebler H, Vaz GF, Plessl C, et al. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: <i>Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)</i>. IEEE; 2016:1-5. doi:<a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">10.1109/RTSI.2016.7740545</a>","ieee":"H. Riebler <i>et al.</i>, “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” in <i>Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)</i>, 2016, pp. 1–5, doi: <a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">10.1109/RTSI.2016.7740545</a>.","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G.  Trainiti, Gianluca C. Durelli, Emanuele Del Sozzo, Marco D.  Santambrogio, and Christina Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In <i>Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)</i>, 1–5. IEEE, 2016. <a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">https://doi.org/10.1109/RTSI.2016.7740545</a>."},"page":"1-5","date_updated":"2023-09-26T13:28:11Z","publisher":"IEEE","author":[{"last_name":"Riebler","id":"8961","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"full_name":"Vaz, Gavin Francis","id":"30332","last_name":"Vaz","first_name":"Gavin Francis"},{"full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"},{"last_name":"Trainiti","full_name":"Trainiti, Ettore M. G. ","first_name":"Ettore M. G. "},{"first_name":"Gianluca C.","last_name":"Durelli","full_name":"Durelli, Gianluca C."},{"last_name":"Del Sozzo","full_name":"Del Sozzo, Emanuele","first_name":"Emanuele"},{"first_name":"Marco D. ","full_name":"Santambrogio, Marco D. ","last_name":"Santambrogio"},{"first_name":"Christina","last_name":"Bolchini","full_name":"Bolchini, Christina"}],"date_created":"2017-10-17T12:41:18Z","title":"Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems","doi":"10.1109/RTSI.2016.7740545"}]