Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? - Meyer, Björn; Schumacher, Jörn; Plessl, Christian; Förstner, Jens (Proc. Int. Conf. on Field Programmable Logic and Applications (FPL))
Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator. In this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort can actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like programming environment exists. As case study we use an application from computational nanophotonics. Our results show that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view.
Keywords: funding-upb-forschungspreis; funding-maxup; tet_topic_hpc

IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators - Schumacher, Tobias; Plessl, Christian; Platzner, Marco (Microprocessors and Microsystems)
Keywords: funding-altera

Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators - Happe, Markus; Hangmann, Hendrik; Agne, Andreas; Plessl, Christian (Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig))
Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices.

Pragma based parallelization - Trading hardware efficiency for ease of use? - Kenter, Tobias; Plessl, Christian; Schmitz, Henning (Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig))
One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are conﬁgured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a signiﬁcant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort.

Hardware/Software Platform for Self-aware Compute Nodes - Happe, Markus; Agne, Andreas; Plessl, Christian; Platzner, Marco (Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS))
Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method.

Turning control flow graphs into function calls: Code generation for heterogeneous architectures - Barrio, Pablo; Carreras, Carlos; Sierra, Roberto; Kenter, Tobias; Plessl, Christian (Proceedings of the International Conference on High Performance Computing and Simulation (HPCS))
Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided.

Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs - Rüthing, Christoph; Happe, Markus; Agne, Andreas; Plessl, Christian (Proceedings of the International Conference on Field Programmable Logic and Applications (FPL))
While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA.

Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux - Beisel, Tobias; Wiersema, Tobias; Plessl, Christian; Brinkmann, André (Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS))
Keywords: funding-enhance

On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors - Grad, Mariusz; Plessl, Christian (Int. Journal of Reconfigurable Computing (IJRC))

Estimation and Partitioning for CPU-Accelerator Architectures - Kenter, Tobias; Plessl, Christian; Platzner, Marco; Kauschke, Michael (Intel European Research and Innovation Conference)
Keywords: funding-intel

Hardware Virtualization on Dynamically Reconfigurable Embedded Processors - Plessl, Christian; Platzner, Marco (Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility)

Evolution of Electronic Circuits - Sekanina, Lukas; Walker, James Alfred; Kaufmann, Paul; Plessl, Christian; Platzner, Marco (Cartesian Genetic Programming)

Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend - Meyer, Björn; Plessl, Christian; Förstner, Jens (Symp. on Application Accelerators in High Performance Computing (SAAHPC))
Keywords: tet_topic_hpc

Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler - Beisel, Tobias; Wiersema, Tobias; Plessl, Christian; Brinkmann, André (Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP))

Measuring and Predicting Temperature Distributions on FPGAs at Run-Time - Happe, Markus; Agne, Andreas; Plessl, Christian (Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig))
In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time.

Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures - Kenter, Tobias; Platzner, Marco; Plessl, Christian; Kauschke, Michael (Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA))
Keywords: design space exploration; LLVM; partitioning; performance; estimation; funding-intel

FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study - Schumacher, Tobias; Süß, Tim; Plessl, Christian; Platzner, Marco (Int. Journal of Recon- figurable Computing (IJRC))
Keywords: funding-altera

Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture - Grad, Mariusz; Plessl, Christian (Proc. Reconfigurable Architectures Workshop (RAW))

Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware - Lübbers, Enno; Platzner, Marco; Plessl, Christian; Keller, Ariane; Plattner, Bernhard (Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA))

Pruning the Design Space for Just-In-Time Processor Customization - Grad, Mariusz; Plessl, Christian (Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig))

An Open Source Circuit Library with Benchmarking Facilities - Grad, Mariusz; Plessl, Christian (Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA))

Configurable Processor Architectures: History and Trends - Andrews, David; Plessl, Christian (Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA))

Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)

Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators - Beisel, Tobias; Niekamp, Manuel; Plessl, Christian (Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP))

Reconfigurable Nodes for Future Networks - Keller, Ariane; Plattner, Bernhard; Lübbers, Enno; Platzner, Marco; Plessl, Christian (Proc. IEEE Globecom Workshop on Network of the Future (FutureNet))

Rupeas: Ruby Powered Event Analysis DSL - Woehrle, Matthias; Plessl, Christian; Thiele, Lothar (Proc. Int. Conf. Networked Sensing Systems (INSS))

Performance Estimation for the Exploration of CPU-Accelerator Architectures - Kenter, Tobias; Platzner, Marco; Plessl, Christian; Kauschke, Michael (Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA))

Rupeas: Ruby Powered Event Analysis DSL - Woehrle, Matthias; Plessl, Christian; Thiele, Lothar
Wireless Sensor Networks (WSNs) are unique embedded computation systems for distributed sensing of a dispersed phenomenon. While being a strongly concurrent distributed system, its embedded aspects with severe resource limitations and the wireless communication requires a fusion of technologies and methodologies from very different fields. As WSNs are deployed in remote locations for long-term unattended operation, assurance of correct functioning of the system is of prime concern. Thus, the design and development of WSNs requires specialized tools to allow for testing and debugging the system. To this end, we present a framework for analyzing and checking WSNs based on collected events during system operation. It allows for abstracting from the event trace by means of behavioral queries and uses assertions for checking the accordance of an execution to its specification. The framework is independent from WSN test platforms, applications and logging semantics and thus generally applicable for analyzing event logs of WSN test executions.
Keywords: Rupeas; DSL; WSN; testing

IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing - Schumacher, Tobias; Plessl, Christian; Platzner, Marco (Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM))
Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator.
Keywords: IMORC; interconnect; performance

EvoCaches: Application-specific Adaptation of Cache Mapping - Kaufmann, Paul; Plessl, Christian; Platzner, Marco (Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS))
In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable.
Keywords: EvoCache; evolvable hardware; computer architecture

PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes - Beutel, Jan; Gruber, Stephan; Hasler, Andi; Lim, Roman; Meier, Andreas; Plessl, Christian; Talzi, Igor; Thiele, Lothar; Tschudin, Christian; Woehrle, Matthias; Yuecel, Mustafa (Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN))
Keywords: WSN; PermaSense

Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000 - Schumacher, Tobias; Süß, Tim; Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig))
Keywords: IMORC; graphics

An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure - Schumacher, Tobias; Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on Field Programmable Logic and Applications (FPL))
Keywords: IMORC; NOC; KNN; accelerator

Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX - Grad, Mariusz; Plessl, Christian (Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA))
In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Unit (APU) as well as the partial reconfiguration capabilities to provide dynamically reconfigurable custom instructions. We also present a hardware tool flow that automatically translates software functions into custom instructions and a software tool flow that creates binaries using these instructions. While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit.

EvAnT: Analysis and Checking of event traces for Wireless Sensor Networks - Woehrle, Matthias; Plessl, Christian; Lim, Roman; Beutel, Jan; Thiele, Lothar (IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC))
Keywords: WSN; testing; verification

A Hardware Accelerator for k-th Nearest Neighbor Thinning - Schumacher, Tobias; Meiche, Robert; Kaufmann, Paul; Lübbers, Enno; Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA))

IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers - Schumacher, Tobias; Plessl, Christian; Platzner, Marco (Many-core and Reconfigurable Supercomputing Conference (MRSC))
Keywords: IMORC; IP core; interconnect

Increasing the Reliability of Wireless Sensor Networks with a Unit Testing Framework - Beutel, Jan; Plessl, Christian; Woehrle, Matthias

Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework - Woehrle, Matthias; Plessl, Christian; Beutel, Jan; Thiele, Lothar (Proc. Workshop on Embedded Networked Sensors (EmNets))
Keywords: WSN; testing; distributed; embedded

Automated Wireless Sensor Network Testing - Beutel, Jan; Dyer, Matthias; Lim, Roman; Plessl, Christian; Woehrle, Matthias; Yuecel, Mustafa; Thiele, Lothar (Proc. Int. Conf. Networked Sensing Systems (INSS))
Keywords: WSN; testing; verification

Hardware virtualization on a coarse-grained reconfigurable processor - Plessl, Christian
In this thesis, we propose to use a reconfigurable processor as main computation element in embedded systems for applications from the multi-media and communications domain. A reconfigurable processor integrates an embedded CPU core with a Reconfigurable Processing Unit (RPU). Many of our target applications require real-time signal-processing of data streams and expose a high computational demand. The key challenge in designing embedded systems for these applications is to find an implementation that satisfies the performance goals and is adaptable to new applications, while the system cost is minimized. Implementations that solely use an embedded CPU are likely to miss the performance goals. Application-Specific Integrated Circuit (ASIC)-based coprocessors can be used for some high-volume products with fixed functions, but fall short for systems with varying applications. We argue that a reconfigurable processor with a coarse-grained, dynamically reconfigurable array of modest size provides an attractive implementation platform for our application domain. The computational intensive application kernels are executed on the RPU, while the remaining parts of the application are executed on the CPU. Reconfigurable hardware allows for implementing application specific coprocessors with a high performance, while the function of the coprocessor can still be adapted due to the programmability. So far, reconfigurable technology is used in embedded systems primarily with static configurations, e.g., for implementing glue-logic, replacing ASICs, and for implementing fixed-function coprocessors. Changing the configuration at runtime enables a number of interesting application modes, e.g., on-demand loading of coprocessors and time-multiplexed execution of coprocessors, which is commonly denoted as hardware virtualization. While the use of static configurations is well understood and supported by design-tools, the role of dynamic reconfiguration is not well investigated yet. Current application specification methods and design-tools do not provide an end-to-end tool-flow that considers dynamic reconfiguration. A key idea of our approach is to reduce system cost by keeping the size of the reconfigurable array small and to use hardware virtualization techniques to compensate for the limited hardware resources. The main contribution of this thesis is the codesign of a reconfigurable processor architecture named ZIPPY, the corresponding hardware and software implementation tools, and an application specification model which explicitly considers hardware virtualization. The ZIPPY architecture is widely parametrized and allows for specifying a whole family of processor architectures. The implementation tools are also parametrized and can target any architectural variant. We evaluate the performance of the architecture with a system-level, cycle-accurate cosimulation framework. This framework enables us to perform design-space exploration for a variety of reconfigurable processor architectures. With two case studies, we demonstrate, that hardware virtualization on the Zippy architecture is feasible and enables us to trade-off performance for area in embedded systems. Finally, we present a novel method for optimal temporal partitioning of sequential circuits, which is an important form of hardware virtualization. The method based on Slowdown and Retiming allows us to decompose any sequential circuit into a number of smaller, communicating subcircuits that can be executed on a dynamically reconfigurable architecture.
Keywords: Zippy

Optimal Temporal Partitioning based on Slowdown and Retiming - Plessl, Christian; Platzner, Marco; Thiele, Lothar (Proc. Int. Conf. on Field Programmable Technology (ICFPT))
This paper presents a novel method for optimal temporal partitioning of sequential circuits for time-multiplexed reconfigurable architectures. The method bases on slowdown and retiming and maximizes the circuit's performance during execution while restricting the size of the partitions to respect the resource constraints of the reconfigurable architecture. We provide a mixed integer linear program (MILP) formulation of the problem, which can be solved exactly. In contrast to related work, our approach optimizes performance directly, takes structural modifications of the circuit into account, and is extensible. We present the application of the new method to temporal partitioning for a coarse-grained reconfigurable architecture.
Keywords: temporal partitioning; retiming; ILP

Zippy – A coarse-grained reconfigurable array with support for hardware virtualization - Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP))
This paper motivates the use of hardware virtualization on coarse-grained reconfigurable architectures. We introduce Zippy, a coarse-grained multi-context hybrid CPU with architectural support for efficient hardware virtualization. The architectural details and the corresponding tool flow are outlined. As a case study, we compare the non-virtualized and the virtualized execution of an ADPCM decoder.
Keywords: Zippy

System-level performance evaluation of reconfigurable processors - Enzler, Rolf; Plessl, Christian; Platzner, Marco (Microprocessors and Microsystems)
Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving impact of these design decisions on the overall system performance is a challenging task. In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors.
Keywords: FPGA; reconfigurable computing; co-simulation; Zippy

Virtualization of Hardware – Introduction and Survey - Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA))
In this paper we introduce to virtualization of hardware on reconfigurable devices. We identify three main approaches denoted with temporal partitioning, virtualized execution, and virtual machine. For each virtualization approach, we discuss the application models, the required execution architectures, the design tools and the run-time systems. Then, we survey a selection of important projects in the field.
Keywords: hardware virtualization

TKDM – A Reconfigurable Co-processor in a PC's Memory Slot - Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on Field Programmable Technology (ICFPT))
This paper presents TKDM, a PC-based high-performance reconfigurable computing environment. The TKDM hardware consists of an FPGA module that uses the DIMM (dual inline memory module) bus for high-bandwidth and low-latency communication with the host CPU. The system's firmware is integrated with the Linux host operating system and offers functions for data communication and FPGA reconfiguration. The intended use of TKDM is that of a dynamically reconfigurable co-processor for data streaming applications. The system's firmware can be customized for specific application domains to facilitate simple and easy-to-use programming interfaces.
Keywords: coprocessor; DIMM; memory bus; FPGA; high performance computing

The Case for Reconfigurable Hardware in Wearable Computing - Plessl, Christian; Enzler, Rolf; Walder, Herbert; Beutel, Jan; Platzner, Marco; Thiele, Lothar; Tröster, Gerhard (Personal and Ubiquitous Computing)
Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM.

Instance-Specific Accelerators for Minimum Covering - Plessl, Christian; Platzner, Marco (Journal of Supercomputing)
This paper presents the acceleration of minimum-cost covering problems by instance-specific hardware. First, we formulate the minimum-cost covering problem and discuss a branch & bound algorithm to solve it. Then we describe instance-specific hardware architectures that implement branch & bound in 3-valued logic and use reduction techniques similar to those found in software solvers. We further present prototypical accelerator implementations and a corresponding design tool flow. Our experiments reveal significant raw speedups up to five orders of magnitude for a set of smaller unate covering problems. Provided that hardware compilation times can be reduced, we conclude that instance-specific acceleration of hard minimum-cost covering problems will lead to substantial overall speedups.
Keywords: reconfigurable computing; instance-specific acceleration; minimum covering

Virtualizing Hardware with Multi-Context Reconfigurable Arrays - Enzler, Rolf; Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on Field Programmable Logic and Applications (FPL))
In contrast to processors, current reconfigurable devices totally lack programming models that would allow for device independent compilation and forward compatibility. The key to overcome this limitation is hardware virtualization. In this paper, we resort to a macro-pipelined execution model to achieve hardware virtualization for data streaming applications. As a hardware implementation we present a hybrid multi-context architecture that attaches a coarse-grained reconfigurable array to a host CPU. A co-simulation framework enables cycle-accurate simulation of the complete architecture. As a case study we map an FIR filter to our virtualized hardware model and evaluate different designs. We discuss the impact of the number of contexts and the feature of context state on the speedup and the CPU load.
Keywords: Zippy; multi-context; FPGA

Co-simulation of a Hybrid Multi-Context Architecture - Enzler, Rolf; Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA))
Reconfigurable computing architectures aim to dynamically adapt their hardware to the application at hand. As research shows, the time it takes to reconfigure the hardware forms an overhead that can significantly impair the benefits of hardware customization. Multi-context devices are one promising approach to overcome the limitations posed by long reconfiguration times. In contrast to more traditional reconfigurable architectures, multi-context devices hold several configurations on-chip. On demand, the device can quickly switch to another context. In this paper we present a co-simulation environment to investigate design trade-offs for hybrid multi-context architectures. Our architectural model comprises a reconfigurable unit closely coupled to a CPU core. As a case study, we discuss the implementation of a FIR filter partitioned into several contexts. We outline the mapping process and present simulation results for single- and multi-context reconfigurable units coupled with both embedded and high-end CPUs.
Keywords: Zippy; co-simulation

Reconfigurable Hardware in Wearable Computing Nodes - Plessl, Christian; Enzler, Rolf; Walder, Herbert; Beutel, Jan; Platzner, Marco; Thiele, Lothar (Proc. Int. Symp. on Wearable Computers (ISWC))
Wearable computers are embedded into the mobile environment of the human body. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with low energy consumption required to maximize battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss two experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we develop and evaluate task placement techniques used in the operating system layer of WURM.
Keywords: wearable computing

Partially Reconfigurable Cores for Xilinx Virtex - Dyer, Matthias; Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on Field Programmable Logic and Applications (FPL))
Recent generations of high-density and high-speed FPGAs provide a sufficient capacity for implementing complete configurable systems on a chip (CSoCs). Hybrid CPUs that combine standard CPU cores with reconfigurable coprocessors are an important subclass of CSoCs. With partially reconfigurable FPGAs, coprocessors can be loaded on demand while the CPU remains running. However, the lack of high-level design tools for partial reconfiguration makes practical implementations a challenging task. In this paper, we introduce a design flow to implement hybrid processors on Xilinx Virtex. The design flow is based on two techniques, virtual sockets and feed-through components, and can efficiently generate partial configurations from industry-quality cores. We discuss the design flow and present a fully operational audio streaming prototype to demonstrate its feasibility.
Keywords: partial reconfiguration

Custom Computing Machines for the Set Covering Problem - Plessl, Christian; Platzner, Marco (Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM))
We present instance-specific custom computing machines for the set covering problem. Four accelerator architectures are developed that implement branch & bound in 3-valued logic and many of the deduction techniques found in software solvers. We use set covering benchmarks from two-level logic minimization and Steiner triple systems to derive and discuss experimental results. The resulting raw speedups are in the order of four magnitudes on average. Finally, we propose a hybrid solver architecture that combines the raw speed of instance-specific reconfigurable hardware with flexible bounding schemes implemented in software.

Instance-Specific Accelerators for Minimum Covering - Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA))
In this paper we present instance-specific accelerators for minimum-cost covering problems. We first define the covering problem and discuss a branch&bound algorithm to solve it. Then we describe an instance-specific hardware architecture that implements branch&bound in 3-valued logic and uses reduction techniques usually found in software solvers. Results for small unate covering problems reveal significant raw speedups.
Keywords: minimum covering; accelerator; funding-sundance

Server-Side-Techniken im Web – ein Überblick - Plessl, Christian; Wilde, Erik (iX)

Reconfigurable Accelerators for Minimum Covering - Plessl, Christian
In this report the design and implementation of an instance-specific accelerator for solving minimum covering problems will be presented. After an introduction to configurable computing in general, the minimum covering problem is defined and a branch and bound algorithm to solve it in software is presented. The remainder of the report shows how this branch and bound algorithm can be adopted to hardware. Specifically it is stressed how the various sophisticated strategies for deducing conditions for variables used by software solvers can be adopted to hardware and how a system which uses 3-valued logic to solve this problem can be designed. In addition to these considerations focusing on the architecture of the system, some important details of the actual implementation are given. A prototype has been implemented for showing the feasibility of the concept and for gaining information about speed and size of the hardware implementation. Cycle-accurate simulations for a set of benchmark problems have been done for determining the performance of the accelerator. The speed of the resulting accelerators has been compared to the time a reference software solver (espresso) needs and the resulting speedups have been calculated. I have shown that a raw speedup of several orders of maginitude can be achieved for many problems; for some problems no speedup is achieved yet. After a discussion of the results, ideas for future work are presented.

Reconfigurable Processors for Handhelds and Wearables: Application Analysis - Enzler, Rolf; Platzner, Marco; Plessl, Christian; Thiele, Lothar; Tröster, Gerhard (Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III)
In this paper, we present the analysis of applications from the domain of handheld and wearable computing. This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurable processors. We discuss the selection of representative benchmarks for handhelds and wearables and group the applications into multimedia, communications, and cryptography programs. We simulate the applications on a cycle-accurate processor simulator and gather statistical data such as instruction mix, cache hit rates and memory requirements for an embedded processor model. A breakdown of the executed cycles into different functions identifies the most compute-intensive code sections - the kernels. Then, we analyze the applications and discuss parameters that strongly influence the design of dynamically reconfigurable processors. Finally, we outline the construction of a parameterizable simulation model for a reconfigurable unit that is attached to a processor core.
Keywords: benchmark

Hardware/Software Codesign in Speech Compression Applications - Plessl, Christian; Maurer, Simon
Keywords: co-design; speech processing