TY - CONF AB - In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties. AU - Kenter, Tobias AU - Vaz, Gavin Francis AU - Plessl, Christian ID - 388 T2 - Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC) TI - Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer VL - 8405 ER - TY - JOUR AB - Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices. AU - Agne, Andreas AU - Hangmann, Hendrik AU - Happe, Markus AU - Platzner, Marco AU - Plessl, Christian ID - 363 IS - 8, Part B JF - Microprocessors and Microsystems TI - Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators VL - 38 ER - TY - CONF AB - In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates. AU - Riebler, Heinrich AU - Kenter, Tobias AU - Plessl, Christian AU - Sorge, Christoph ID - 377 KW - coldboot T2 - Proceedings of Field-Programmable Custom Computing Machines (FCCM) TI - Reconstructing AES Key Schedules from Decayed Memory with FPGAs ER - TY - JOUR AB - Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems. AU - Agne, Andreas AU - Happe, Markus AU - Lösch, Achim AU - Plessl, Christian AU - Platzner, Marco ID - 365 IS - 2 JF - ACM Transactions on Reconfigurable Technology and Systems (TRETS) TI - Self-awareness as a Model for Designing and Operating Heterogeneous Multicores VL - 7 ER - TY - JOUR AB - The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications AU - Agne, Andreas AU - Happe, Markus AU - Keller, Ariane AU - Lübbers, Enno AU - Plattner, Bernhard AU - Platzner, Marco AU - Plessl, Christian ID - 328 IS - 1 JF - IEEE Micro TI - ReconOS - An Operating System Approach for Reconfigurable Computing VL - 34 ER - TY - CONF AU - C. Durelli, Gianluca AU - Pogliani, Marcello AU - Miele, Antonio AU - Plessl, Christian AU - Riebler, Heinrich AU - Vaz, Gavin Francis AU - D. Santambrogio, Marco AU - Bolchini, Cristiana ID - 1778 T2 - Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA) TI - Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach ER - TY - CONF AB - Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes. AU - Vaz, Gavin Francis AU - Riebler, Heinrich AU - Kenter, Tobias AU - Plessl, Christian ID - 439 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Deferring Accelerator Offloading Decisions to Application Runtime ER - TY - CONF AB - Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design. AU - Kenter, Tobias AU - Schmitz, Henning AU - Plessl, Christian ID - 406 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Kernel-Centric Acceleration of High Accuracy Stereo-Matching ER - TY - CONF AU - C. Durelli, Gianluca AU - Copolla, Marcello AU - Djafarian, Karim AU - Koranaros, George AU - Miele, Antonio AU - Paolino, Michele AU - Pell, Oliver AU - Plessl, Christian AU - D. Santambrogio, Marco AU - Bolchini, Cristiana ID - 1780 T2 - Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC) TI - SAVE: Towards efficient resource management in heterogeneous system architectures ER - TY - JOUR AU - Giefers, Heiner AU - Plessl, Christian AU - Förstner, Jens ID - 1779 IS - 5 JF - ACM SIGARCH Computer Architecture News KW - funding-maxup KW - tet_topic_hpc SN - 0163-5964 TI - Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers VL - 41 ER - TY - GEN AU - Riebler, Heinrich ID - 521 KW - coldboot TI - Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs ER - TY - CONF AB - Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES. AU - Riebler, Heinrich AU - Kenter, Tobias AU - Sorge, Christoph AU - Plessl, Christian ID - 528 KW - coldboot T2 - Proceedings of the International Conference on Field-Programmable Technology (FPT) TI - FPGA-accelerated Key Search for Cold-Boot Attacks against AES ER - TY - CONF AB - In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas. AU - Happe, Markus AU - Kling, Peter AU - Plessl, Christian AU - Platzner, Marco AU - Meyer auf der Heide, Friedhelm ID - 505 T2 - Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS) TI - On-The-Fly Computing: A Novel Paradigm for Individualized IT Services ER - TY - CONF AU - Suess, Tim AU - Schoenrock, Andrew AU - Meisner, Sebastian AU - Plessl, Christian ID - 1787 SN - 978-0-7695-4979-8 T2 - Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW) TI - Parallel Macro Pipelining on the Intel SCC Many-Core Computer ER - TY - CONF AU - Grunzke, Richard AU - Birkenheuer, Georg AU - Blunk, Dirk AU - Breuers, Sebastian AU - Brinkmann, André AU - Gesing, Sandra AU - Herres-Pawlis, Sonja AU - Kohlbacher, Oliver AU - Krüger, Jens AU - Kruse, Martin AU - Müller-Pfefferkorn, Ralph AU - Schäfer, Patrick AU - Schuller, Bernd AU - Steinke, Thomas AU - Zink, Andreas ID - 2107 T2 - Proc. UNICORE Summit TI - A Data Driven Science Gateway for Computational Workflows ER - TY - GEN AU - Plessl, Christian AU - Platzner, Marco AU - Agne, Andreas AU - Happe, Markus AU - Lübbers, Enno ID - 587 TI - Programming models for reconfigurable heterogeneous multi-cores ER - TY - CONF AB - Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator. In this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort can actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like programming environment exists. As case study we use an application from computational nanophotonics. Our results show that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view. AU - Meyer, Björn AU - Schumacher, Jörn AU - Plessl, Christian AU - Förstner, Jens ID - 2106 KW - funding-upb-forschungspreis KW - funding-maxup KW - tet_topic_hpc T2 - Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) TI - Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? ER - TY - JOUR AU - Schumacher, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 2108 IS - 2 JF - Microprocessors and Microsystems KW - funding-altera SN - 0141-9331 TI - IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators VL - 36 ER - TY - CONF AB - Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices. AU - Happe, Markus AU - Hangmann, Hendrik AU - Agne, Andreas AU - Plessl, Christian ID - 615 T2 - Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig) TI - Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators ER - TY - CONF AB - One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort. AU - Kenter, Tobias AU - Plessl, Christian AU - Schmitz, Henning ID - 591 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Pragma based parallelization - Trading hardware efficiency for ease of use? ER - TY - CONF AB - Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method. AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian AU - Platzner, Marco ID - 609 T2 - Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS) TI - Hardware/Software Platform for Self-aware Compute Nodes ER - TY - CONF AB - Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided. AU - Barrio, Pablo AU - Carreras, Carlos AU - Sierra, Roberto AU - Kenter, Tobias AU - Plessl, Christian ID - 567 T2 - Proceedings of the International Conference on High Performance Computing and Simulation (HPCS) TI - Turning control flow graphs into function calls: Code generation for heterogeneous architectures ER - TY - CONF AB - While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA. AU - Rüthing, Christoph AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian ID - 612 T2 - Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) TI - Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs ER - TY - CONF AU - Beisel, Tobias AU - Wiersema, Tobias AU - Plessl, Christian AU - Brinkmann, André ID - 2180 KW - funding-enhance T2 - Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS) TI - Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux ER - TY - JOUR AU - Grad, Mariusz AU - Plessl, Christian ID - 2177 JF - Int. Journal of Reconfigurable Computing (IJRC) TI - On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors ER - TY - CONF AU - Kenter, Tobias AU - Plessl, Christian AU - Platzner, Marco AU - Kauschke, Michael ID - 2191 KW - funding-intel T2 - Intel European Research and Innovation Conference TI - Estimation and Partitioning for CPU-Accelerator Architectures ER - TY - CHAP AU - Plessl, Christian AU - Platzner, Marco ED - Khalgui, Mohamed ED - Hanisch, Hans-Michael ID - 2202 SN - 978-1-60960-086-0 T2 - Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility TI - Hardware Virtualization on Dynamically Reconfigurable Embedded Processors ER - TY - CHAP AU - Sekanina, Lukas AU - Walker, James Alfred AU - Kaufmann, Paul AU - Plessl, Christian AU - Platzner, Marco ID - 10737 T2 - Cartesian Genetic Programming TI - Evolution of Electronic Circuits ER - TY - CONF AU - Meyer, Björn AU - Plessl, Christian AU - Förstner, Jens ID - 2194 KW - tet_topic_hpc T2 - Symp. on Application Accelerators in High Performance Computing (SAAHPC) TI - Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend ER - TY - CONF AU - Beisel, Tobias AU - Wiersema, Tobias AU - Plessl, Christian AU - Brinkmann, André ID - 2193 T2 - Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) TI - Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler ER - TY - CONF AB - In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time. AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian ID - 656 T2 - Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig) TI - Measuring and Predicting Temperature Distributions on FPGAs at Run-Time ER - TY - CONF AU - Kenter, Tobias AU - Platzner, Marco AU - Plessl, Christian AU - Kauschke, Michael ID - 2200 KW - design space exploration KW - LLVM KW - partitioning KW - performance KW - estimation KW - funding-intel SN - 978-1-4503-0554-9 T2 - Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA) TI - Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures ER - TY - JOUR AU - Schumacher, Tobias AU - Süß, Tim AU - Plessl, Christian AU - Platzner, Marco ID - 2201 JF - Int. Journal of Recon- figurable Computing (IJRC) KW - funding-altera TI - FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2198 T2 - Proc. Reconfigurable Architectures Workshop (RAW) TI - Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture ER - TY - CONF AU - Lübbers, Enno AU - Platzner, Marco AU - Plessl, Christian AU - Keller, Ariane AU - Plattner, Bernhard ID - 2223 SN - 1-60132-140-6 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2216 T2 - Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig) TI - Pruning the Design Space for Just-In-Time Processor Customization ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2224 SN - 1-60132-140-6 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - An Open Source Circuit Library with Benchmarking Facilities ER - TY - CONF AU - Andrews, David AU - Plessl, Christian ID - 2220 SN - 1-60132-140-6 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Configurable Processor Architectures: History and Trends ER - TY - GEN ED - Plaks, Toomas P. ED - Andrews, David ED - DeMara, Ronald ED - Lam, Herman ED - Lee, Jooheung ED - Plessl, Christian ED - Stitt, Greg ID - 2222 SN - 1-60132-140-6 TI - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) ER - TY - CONF AU - Beisel, Tobias AU - Niekamp, Manuel AU - Plessl, Christian ID - 2226 SN - 978-1-4244-6965-9 T2 - Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) TI - Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators ER - TY - CONF AU - Keller, Ariane AU - Plattner, Bernhard AU - Lübbers, Enno AU - Platzner, Marco AU - Plessl, Christian ID - 2206 SN - 978-1-4244-8864-3 T2 - Proc. IEEE Globecom Workshop on Network of the Future (FutureNet) TI - Reconfigurable Nodes for Future Networks ER - TY - CONF AU - Woehrle, Matthias AU - Plessl, Christian AU - Thiele, Lothar ID - 2227 SN - 978-1-4244-7911-5 T2 - Proc. Int. Conf. Networked Sensing Systems (INSS) TI - Rupeas: Ruby Powered Event Analysis DSL ER - TY - CONF AU - Kenter, Tobias AU - Platzner, Marco AU - Plessl, Christian AU - Kauschke, Michael ED - Hammami, Omar ED - Larrabee, Sandra ID - 2228 T2 - Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA) TI - Performance Estimation for the Exploration of CPU-Accelerator Architectures ER - TY - GEN AB - Wireless Sensor Networks (WSNs) are unique embedded computation systems for distributed sensing of a dispersed phenomenon. While being a strongly concurrent distributed system, its embedded aspects with severe resource limitations and the wireless communication requires a fusion of technologies and methodologies from very different fields. As WSNs are deployed in remote locations for long-term unattended operation, assurance of correct functioning of the system is of prime concern. Thus, the design and development of WSNs requires specialized tools to allow for testing and debugging the system. To this end, we present a framework for analyzing and checking WSNs based on collected events during system operation. It allows for abstracting from the event trace by means of behavioral queries and uses assertions for checking the accordance of an execution to its specification. The framework is independent from WSN test platforms, applications and logging semantics and thus generally applicable for analyzing event logs of WSN test executions. AU - Woehrle, Matthias AU - Plessl, Christian AU - Thiele, Lothar ID - 2353 KW - Rupeas KW - DSL KW - WSN KW - testing TI - Rupeas: Ruby Powered Event Analysis DSL ER - TY - CONF AB - Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. AU - Schumacher, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 2350 KW - IMORC KW - interconnect KW - performance SN - 978-1-4244-4450-2 T2 - Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) TI - IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing ER - TY - CONF AB - In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. AU - Kaufmann, Paul AU - Plessl, Christian AU - Platzner, Marco ID - 2262 KW - EvoCache KW - evolvable hardware KW - computer architecture T2 - Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS) TI - EvoCaches: Application-specific Adaptation of Cache Mapping ER - TY - CONF AU - Beutel, Jan AU - Gruber, Stephan AU - Hasler, Andi AU - Lim, Roman AU - Meier, Andreas AU - Plessl, Christian AU - Talzi, Igor AU - Thiele, Lothar AU - Tschudin, Christian AU - Woehrle, Matthias AU - Yuecel, Mustafa ID - 2352 KW - WSN KW - PermaSense SN - 978-1-4244-5108-1 T2 - Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN) TI - PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes ER - TY - CONF AU - Schumacher, Tobias AU - Süß, Tim AU - Plessl, Christian AU - Platzner, Marco ID - 2238 KW - IMORC KW - graphics SN - 978-0-7695-3917-1 T2 - Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig) TI - Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000 ER - TY - CONF AU - Schumacher, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 2261 KW - IMORC KW - NOC KW - KNN KW - accelerator SN - 1946-1488 T2 - Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) TI - An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure ER - TY - CONF AB - In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Unit (APU) as well as the partial reconfiguration capabilities to provide dynamically reconfigurable custom instructions. We also present a hardware tool flow that automatically translates software functions into custom instructions and a software tool flow that creates binaries using these instructions. While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit. AU - Grad, Mariusz AU - Plessl, Christian ID - 2263 SN - 1-60132-101-5 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX ER -