---
_id: '656'
abstract:
- lang: eng
text: In the next decades, hybrid multi-cores will be the predominant architecture
for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies
are key for providing dependability in such systems. These strategies rely on
measuring the temperature distribution and redicting the thermal behavior of the
system when there are changes to the hardware and software running on the FPGA.
While there are a number of tools that use thermal models to predict temperature
distributions at design time, these tools lack the flexibility to autonomously
adjust to changing FPGA configurations. To address this problem we propose a temperature-aware
system that empowers FPGA-based reconfigurable multi-cores to autonomously predict
the on-chip temperature distribution for pro-active thread remapping. Our system
obtains temperature measurements through a self-calibrating grid of sensors and
uses area constrained heat-generating circuits in order to generate spatial and
temporal temperature gradients. The generated temperature variations are then
used to learn the free parameters of the system's thermal model. The system thus
acquires an understanding of its own thermal characteristics. We implemented an
FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T
FPGA that is aware of its thermal model. Finally, we show that the temperature
predictions vary less than 0.72 degree C on average compared to the measured temperature
distributions at run-time.
author:
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Happe M, Agne A, Plessl C. Measuring and Predicting Temperature Distributions
on FPGAs at Run-Time. In: Proceedings of the 2011 International Conference
on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2011:55-60. doi:10.1109/ReConFig.2011.59'
apa: Happe, M., Agne, A., & Plessl, C. (2011). Measuring and Predicting Temperature
Distributions on FPGAs at Run-Time. Proceedings of the 2011 International Conference
on Reconfigurable Computing and FPGAs (ReConFig), 55–60. https://doi.org/10.1109/ReConFig.2011.59
bibtex: '@inproceedings{Happe_Agne_Plessl_2011, title={Measuring and Predicting
Temperature Distributions on FPGAs at Run-Time}, DOI={10.1109/ReConFig.2011.59},
booktitle={Proceedings of the 2011 International Conference on Reconfigurable
Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Agne,
Andreas and Plessl, Christian}, year={2011}, pages={55–60} }'
chicago: Happe, Markus, Andreas Agne, and Christian Plessl. “Measuring and Predicting
Temperature Distributions on FPGAs at Run-Time.” In Proceedings of the 2011
International Conference on Reconfigurable Computing and FPGAs (ReConFig),
55–60. IEEE, 2011. https://doi.org/10.1109/ReConFig.2011.59.
ieee: 'M. Happe, A. Agne, and C. Plessl, “Measuring and Predicting Temperature Distributions
on FPGAs at Run-Time,” in Proceedings of the 2011 International Conference
on Reconfigurable Computing and FPGAs (ReConFig), 2011, pp. 55–60, doi: 10.1109/ReConFig.2011.59.'
mla: Happe, Markus, et al. “Measuring and Predicting Temperature Distributions on
FPGAs at Run-Time.” Proceedings of the 2011 International Conference on Reconfigurable
Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60, doi:10.1109/ReConFig.2011.59.
short: 'M. Happe, A. Agne, C. Plessl, in: Proceedings of the 2011 International
Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60.'
date_created: 2017-10-17T12:42:59Z
date_updated: 2023-09-26T13:46:08Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2011.59
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-14T13:49:39Z
date_updated: 2018-03-14T13:49:39Z
file_id: '1220'
file_name: 656-2011_happe_reconfig.pdf
file_size: 502244
relation: main_file
success: 1
file_date_updated: 2018-03-14T13:49:39Z
has_accepted_license: '1'
language:
- iso: eng
page: 55-60
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: Proceedings of the 2011 International Conference on Reconfigurable Computing
and FPGAs (ReConFig)
publisher: IEEE
quality_controlled: '1'
status: public
title: Measuring and Predicting Temperature Distributions on FPGAs at Run-Time
type: conference
user_id: '15278'
year: '2011'
...
---
_id: '2200'
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Michael
full_name: Kauschke, Michael
last_name: Kauschke
citation:
ama: 'Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation Framework
for Automated Exploration of CPU-Accelerator Architectures. In: Proc. Int.
Symp. on Field-Programmable Gate Arrays (FPGA). ACM; 2011:177-180. doi:10.1145/1950413.1950448'
apa: Kenter, T., Platzner, M., Plessl, C., & Kauschke, M. (2011). Performance
Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.
Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 177–180. https://doi.org/10.1145/1950413.1950448
bibtex: '@inproceedings{Kenter_Platzner_Plessl_Kauschke_2011, place={New York, NY,
USA}, title={Performance Estimation Framework for Automated Exploration of CPU-Accelerator
Architectures}, DOI={10.1145/1950413.1950448},
booktitle={Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}, publisher={ACM},
author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke,
Michael}, year={2011}, pages={177–180} }'
chicago: 'Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke.
“Performance Estimation Framework for Automated Exploration of CPU-Accelerator
Architectures.” In Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA),
177–80. New York, NY, USA: ACM, 2011. https://doi.org/10.1145/1950413.1950448.'
ieee: 'T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation
Framework for Automated Exploration of CPU-Accelerator Architectures,” in Proc.
Int. Symp. on Field-Programmable Gate Arrays (FPGA), 2011, pp. 177–180, doi:
10.1145/1950413.1950448.'
mla: Kenter, Tobias, et al. “Performance Estimation Framework for Automated Exploration
of CPU-Accelerator Architectures.” Proc. Int. Symp. on Field-Programmable Gate
Arrays (FPGA), ACM, 2011, pp. 177–80, doi:10.1145/1950413.1950448.
short: 'T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: Proc. Int. Symp. on
Field-Programmable Gate Arrays (FPGA), ACM, New York, NY, USA, 2011, pp. 177–180.'
date_created: 2018-04-03T15:08:13Z
date_updated: 2023-09-26T13:45:04Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1145/1950413.1950448
keyword:
- design space exploration
- LLVM
- partitioning
- performance
- estimation
- funding-intel
language:
- iso: eng
page: 177-180
place: New York, NY, USA
publication: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)
publication_identifier:
isbn:
- 978-1-4503-0554-9
publisher: ACM
quality_controlled: '1'
status: public
title: Performance Estimation Framework for Automated Exploration of CPU-Accelerator
Architectures
type: conference
user_id: '15278'
year: '2011'
...
---
_id: '2201'
author:
- first_name: Tobias
full_name: Schumacher, Tobias
last_name: Schumacher
- first_name: Tim
full_name: Süß, Tim
last_name: Süß
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Schumacher T, Süß T, Plessl C, Platzner M. FPGA Acceleration of Communication-bound
Streaming Applications: Architecture Modeling and a 3D Image Compositing Case
Study. Int Journal of Recon- figurable Computing (IJRC). Published online
2011. doi:10.1155/2011/760954'
apa: 'Schumacher, T., Süß, T., Plessl, C., & Platzner, M. (2011). FPGA Acceleration
of Communication-bound Streaming Applications: Architecture Modeling and a 3D
Image Compositing Case Study. Int. Journal of Recon- Figurable Computing (IJRC).
https://doi.org/10.1155/2011/760954'
bibtex: '@article{Schumacher_Süß_Plessl_Platzner_2011, title={FPGA Acceleration
of Communication-bound Streaming Applications: Architecture Modeling and a 3D
Image Compositing Case Study}, DOI={10.1155/2011/760954},
journal={Int. Journal of Recon- figurable Computing (IJRC)}, publisher={Hindawi
Publishing Corp.}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian
and Platzner, Marco}, year={2011} }'
chicago: 'Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “FPGA
Acceleration of Communication-Bound Streaming Applications: Architecture Modeling
and a 3D Image Compositing Case Study.” Int. Journal of Recon- Figurable Computing
(IJRC), 2011. https://doi.org/10.1155/2011/760954.'
ieee: 'T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “FPGA Acceleration of
Communication-bound Streaming Applications: Architecture Modeling and a 3D Image
Compositing Case Study,” Int. Journal of Recon- figurable Computing (IJRC),
2011, doi: 10.1155/2011/760954.'
mla: 'Schumacher, Tobias, et al. “FPGA Acceleration of Communication-Bound Streaming
Applications: Architecture Modeling and a 3D Image Compositing Case Study.” Int.
Journal of Recon- Figurable Computing (IJRC), Hindawi Publishing Corp., 2011,
doi:10.1155/2011/760954.'
short: T. Schumacher, T. Süß, C. Plessl, M. Platzner, Int. Journal of Recon- Figurable
Computing (IJRC) (2011).
date_created: 2018-04-03T15:09:49Z
date_updated: 2023-09-26T13:45:46Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1155/2011/760954
keyword:
- funding-altera
language:
- iso: eng
publication: Int. Journal of Recon- figurable Computing (IJRC)
publisher: Hindawi Publishing Corp.
quality_controlled: '1'
status: public
title: 'FPGA Acceleration of Communication-bound Streaming Applications: Architecture
Modeling and a 3D Image Compositing Case Study'
type: journal_article
user_id: '15278'
year: '2011'
...
---
_id: '2198'
author:
- first_name: Mariusz
full_name: Grad, Mariusz
last_name: Grad
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Grad M, Plessl C. Just-in-time Instruction Set Extension – Feasibility and
Limitations for an FPGA-based Reconfigurable ASIP Architecture. In: Proc. Reconfigurable
Architectures Workshop (RAW). IEEE Computer Society; 2011:278-285. doi:10.1109/IPDPS.2011.153'
apa: Grad, M., & Plessl, C. (2011). Just-in-time Instruction Set Extension –
Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture.
Proc. Reconfigurable Architectures Workshop (RAW), 278–285. https://doi.org/10.1109/IPDPS.2011.153
bibtex: '@inproceedings{Grad_Plessl_2011, title={Just-in-time Instruction Set Extension
– Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture},
DOI={10.1109/IPDPS.2011.153},
booktitle={Proc. Reconfigurable Architectures Workshop (RAW)}, publisher={IEEE
Computer Society}, author={Grad, Mariusz and Plessl, Christian}, year={2011},
pages={278–285} }'
chicago: Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension
– Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.”
In Proc. Reconfigurable Architectures Workshop (RAW), 278–85. IEEE Computer
Society, 2011. https://doi.org/10.1109/IPDPS.2011.153.
ieee: 'M. Grad and C. Plessl, “Just-in-time Instruction Set Extension – Feasibility
and Limitations for an FPGA-based Reconfigurable ASIP Architecture,” in Proc.
Reconfigurable Architectures Workshop (RAW), 2011, pp. 278–285, doi: 10.1109/IPDPS.2011.153.'
mla: Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension
– Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.”
Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society,
2011, pp. 278–85, doi:10.1109/IPDPS.2011.153.
short: 'M. Grad, C. Plessl, in: Proc. Reconfigurable Architectures Workshop (RAW),
IEEE Computer Society, 2011, pp. 278–285.'
date_created: 2018-04-03T15:05:52Z
date_updated: 2023-09-26T13:44:39Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/IPDPS.2011.153
language:
- iso: eng
page: 278-285
publication: Proc. Reconfigurable Architectures Workshop (RAW)
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: Just-in-time Instruction Set Extension – Feasibility and Limitations for an
FPGA-based Reconfigurable ASIP Architecture
type: conference
user_id: '15278'
year: '2011'
...
---
_id: '2223'
author:
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Ariane
full_name: Keller, Ariane
last_name: Keller
- first_name: Bernhard
full_name: Plattner, Bernhard
last_name: Plattner
citation:
ama: 'Lübbers E, Platzner M, Plessl C, Keller A, Plattner B. Towards Adaptive Networking
for Embedded Devices based on Reconfigurable Hardware. In: Proc. Int. Conf.
on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press;
2010:225-231.'
apa: Lübbers, E., Platzner, M., Plessl, C., Keller, A., & Plattner, B. (2010).
Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware.
Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
225–231.
bibtex: '@inproceedings{Lübbers_Platzner_Plessl_Keller_Plattner_2010, title={Towards
Adaptive Networking for Embedded Devices based on Reconfigurable Hardware}, booktitle={Proc.
Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA
Press}, author={Lübbers, Enno and Platzner, Marco and Plessl, Christian and Keller,
Ariane and Plattner, Bernhard}, year={2010}, pages={225–231} }'
chicago: Lübbers, Enno, Marco Platzner, Christian Plessl, Ariane Keller, and Bernhard
Plattner. “Towards Adaptive Networking for Embedded Devices Based on Reconfigurable
Hardware.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and
Algorithms (ERSA), 225–31. CSREA Press, 2010.
ieee: E. Lübbers, M. Platzner, C. Plessl, A. Keller, and B. Plattner, “Towards Adaptive
Networking for Embedded Devices based on Reconfigurable Hardware,” in Proc.
Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
2010, pp. 225–231.
mla: Lübbers, Enno, et al. “Towards Adaptive Networking for Embedded Devices Based
on Reconfigurable Hardware.” Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 225–31.
short: 'E. Lübbers, M. Platzner, C. Plessl, A. Keller, B. Plattner, in: Proc. Int.
Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press,
2010, pp. 225–231.'
date_created: 2018-04-05T16:27:13Z
date_updated: 2023-09-26T13:48:32Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
language:
- iso: eng
page: 225-231
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA)
publication_identifier:
isbn:
- 1-60132-140-6
publisher: CSREA Press
quality_controlled: '1'
status: public
title: Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2216'
author:
- first_name: Mariusz
full_name: Grad, Mariusz
last_name: Grad
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Grad M, Plessl C. Pruning the Design Space for Just-In-Time Processor Customization.
In: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig).
IEEE Computer Society; 2010:67-72. doi:10.1109/ReConFig.2010.19'
apa: Grad, M., & Plessl, C. (2010). Pruning the Design Space for Just-In-Time
Processor Customization. Proc. Int. Conf. on ReConFigurable Computing and FPGAs
(ReConFig), 67–72. https://doi.org/10.1109/ReConFig.2010.19
bibtex: '@inproceedings{Grad_Plessl_2010, place={Los Alamitos, CA, USA}, title={Pruning
the Design Space for Just-In-Time Processor Customization}, DOI={10.1109/ReConFig.2010.19},
booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)},
publisher={IEEE Computer Society}, author={Grad, Mariusz and Plessl, Christian},
year={2010}, pages={67–72} }'
chicago: 'Grad, Mariusz, and Christian Plessl. “Pruning the Design Space for Just-In-Time
Processor Customization.” In Proc. Int. Conf. on ReConFigurable Computing and
FPGAs (ReConFig), 67–72. Los Alamitos, CA, USA: IEEE Computer Society, 2010.
https://doi.org/10.1109/ReConFig.2010.19.'
ieee: 'M. Grad and C. Plessl, “Pruning the Design Space for Just-In-Time Processor
Customization,” in Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig),
2010, pp. 67–72, doi: 10.1109/ReConFig.2010.19.'
mla: Grad, Mariusz, and Christian Plessl. “Pruning the Design Space for Just-In-Time
Processor Customization.” Proc. Int. Conf. on ReConFigurable Computing and
FPGAs (ReConFig), IEEE Computer Society, 2010, pp. 67–72, doi:10.1109/ReConFig.2010.19.
short: 'M. Grad, C. Plessl, in: Proc. Int. Conf. on ReConFigurable Computing and
FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2010, pp. 67–72.'
date_created: 2018-04-05T14:48:51Z
date_updated: 2023-09-26T13:47:11Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2010.19
language:
- iso: eng
page: 67-72
place: Los Alamitos, CA, USA
publication: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: Pruning the Design Space for Just-In-Time Processor Customization
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2224'
author:
- first_name: Mariusz
full_name: Grad, Mariusz
last_name: Grad
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Grad M, Plessl C. An Open Source Circuit Library with Benchmarking Facilities.
In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA). CSREA Press; 2010:144-150.'
apa: Grad, M., & Plessl, C. (2010). An Open Source Circuit Library with Benchmarking
Facilities. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA), 144–150.
bibtex: '@inproceedings{Grad_Plessl_2010, title={An Open Source Circuit Library
with Benchmarking Facilities}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Grad, Mariusz
and Plessl, Christian}, year={2010}, pages={144–150} }'
chicago: Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with
Benchmarking Facilities.” In Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), 144–50. CSREA Press, 2010.
ieee: M. Grad and C. Plessl, “An Open Source Circuit Library with Benchmarking Facilities,”
in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA), 2010, pp. 144–150.
mla: Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with Benchmarking
Facilities.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and
Algorithms (ERSA), CSREA Press, 2010, pp. 144–50.
short: 'M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144–150.'
date_created: 2018-04-05T16:28:38Z
date_updated: 2023-09-26T13:48:59Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
language:
- iso: eng
page: 144-150
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA)
publication_identifier:
isbn:
- 1-60132-140-6
publisher: CSREA Press
quality_controlled: '1'
status: public
title: An Open Source Circuit Library with Benchmarking Facilities
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2220'
author:
- first_name: David
full_name: Andrews, David
last_name: Andrews
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Andrews D, Plessl C. Configurable Processor Architectures: History and Trends.
In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA). CSREA Press; 2010:165.'
apa: 'Andrews, D., & Plessl, C. (2010). Configurable Processor Architectures:
History and Trends. Proc. Int. Conf. on Engineering of Reconfigurable Systems
and Algorithms (ERSA), 165.'
bibtex: '@inproceedings{Andrews_Plessl_2010, title={Configurable Processor Architectures:
History and Trends}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Andrews, David
and Plessl, Christian}, year={2010}, pages={165} }'
chicago: 'Andrews, David, and Christian Plessl. “Configurable Processor Architectures:
History and Trends.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems
and Algorithms (ERSA), 165. CSREA Press, 2010.'
ieee: 'D. Andrews and C. Plessl, “Configurable Processor Architectures: History
and Trends,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and
Algorithms (ERSA), 2010, p. 165.'
mla: 'Andrews, David, and Christian Plessl. “Configurable Processor Architectures:
History and Trends.” Proc. Int. Conf. on Engineering of Reconfigurable Systems
and Algorithms (ERSA), CSREA Press, 2010, p. 165.'
short: 'D. Andrews, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), CSREA Press, 2010, p. 165.'
date_created: 2018-04-05T14:57:07Z
date_updated: 2023-09-26T13:47:33Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
language:
- iso: eng
page: '165'
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA)
publication_identifier:
isbn:
- 1-60132-140-6
publisher: CSREA Press
quality_controlled: '1'
status: public
title: 'Configurable Processor Architectures: History and Trends'
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2222'
citation:
ama: Plaks TP, Andrews D, DeMara R, et al., eds. Proc. Int. Conf. on Engineering
of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010.
apa: Plaks, T. P., Andrews, D., DeMara, R., Lam, H., Lee, J., Plessl, C., &
Stitt, G. (Eds.). (2010). Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA). CSREA Press.
bibtex: '@book{Plaks_Andrews_DeMara_Lam_Lee_Plessl_Stitt_2010, title={Proc. Int.
Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA
Press}, year={2010} }'
chicago: Plaks, Toomas P., David Andrews, Ronald DeMara, Herman Lam, Jooheung Lee,
Christian Plessl, and Greg Stitt, eds. Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA). CSREA Press, 2010.
ieee: T. P. Plaks et al., Eds., Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA). CSREA Press, 2010.
mla: Plaks, Toomas P., et al., editors. Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA). CSREA Press, 2010.
short: T.P. Plaks, D. Andrews, R. DeMara, H. Lam, J. Lee, C. Plessl, G. Stitt, eds.,
Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
CSREA Press, 2010.
date_created: 2018-04-05T15:00:49Z
date_updated: 2023-09-26T13:48:00Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
editor:
- first_name: Toomas P.
full_name: Plaks, Toomas P.
last_name: Plaks
- first_name: David
full_name: Andrews, David
last_name: Andrews
- first_name: Ronald
full_name: DeMara, Ronald
last_name: DeMara
- first_name: Herman
full_name: Lam, Herman
last_name: Lam
- first_name: Jooheung
full_name: Lee, Jooheung
last_name: Lee
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Greg
full_name: Stitt, Greg
last_name: Stitt
language:
- iso: eng
publication_identifier:
isbn:
- 1-60132-140-6
publisher: CSREA Press
quality_controlled: '1'
status: public
title: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)
type: conference_editor
user_id: '15278'
year: '2010'
...
---
_id: '2226'
author:
- first_name: Tobias
full_name: Beisel, Tobias
last_name: Beisel
- first_name: Manuel
full_name: Niekamp, Manuel
last_name: Niekamp
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Beisel T, Niekamp M, Plessl C. Using Shared Library Interposing for Transparent
Acceleration in Systems with Heterogeneous Hardware Accelerators. In: Proc.
Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP).
IEEE Computer Society; 2010:65-72. doi:10.1109/ASAP.2010.5540798'
apa: Beisel, T., Niekamp, M., & Plessl, C. (2010). Using Shared Library Interposing
for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators.
Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors
(ASAP), 65–72. https://doi.org/10.1109/ASAP.2010.5540798
bibtex: '@inproceedings{Beisel_Niekamp_Plessl_2010, title={Using Shared Library
Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware
Accelerators}, DOI={10.1109/ASAP.2010.5540798},
booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and
Processors (ASAP)}, publisher={IEEE Computer Society}, author={Beisel, Tobias
and Niekamp, Manuel and Plessl, Christian}, year={2010}, pages={65–72} }'
chicago: Beisel, Tobias, Manuel Niekamp, and Christian Plessl. “Using Shared Library
Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware
Accelerators.” In Proc. Int. Conf. on Application-Specific Systems, Architectures,
and Processors (ASAP), 65–72. IEEE Computer Society, 2010. https://doi.org/10.1109/ASAP.2010.5540798.
ieee: 'T. Beisel, M. Niekamp, and C. Plessl, “Using Shared Library Interposing for
Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators,”
in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors
(ASAP), 2010, pp. 65–72, doi: 10.1109/ASAP.2010.5540798.'
mla: Beisel, Tobias, et al. “Using Shared Library Interposing for Transparent Acceleration
in Systems with Heterogeneous Hardware Accelerators.” Proc. Int. Conf. on Application-Specific
Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010,
pp. 65–72, doi:10.1109/ASAP.2010.5540798.
short: 'T. Beisel, M. Niekamp, C. Plessl, in: Proc. Int. Conf. on Application-Specific
Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010, pp.
65–72.'
date_created: 2018-04-05T16:39:34Z
date_updated: 2023-09-26T13:49:21Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ASAP.2010.5540798
language:
- iso: eng
page: 65-72
publication: Proc. Int. Conf. on Application-Specific Systems, Architectures, and
Processors (ASAP)
publication_identifier:
isbn:
- 978-1-4244-6965-9
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: Using Shared Library Interposing for Transparent Acceleration in Systems with
Heterogeneous Hardware Accelerators
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2206'
author:
- first_name: Ariane
full_name: Keller, Ariane
last_name: Keller
- first_name: Bernhard
full_name: Plattner, Bernhard
last_name: Plattner
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Keller A, Plattner B, Lübbers E, Platzner M, Plessl C. Reconfigurable Nodes
for Future Networks. In: Proc. IEEE Globecom Workshop on Network of the Future
(FutureNet). IEEE; 2010:372-376. doi:10.1109/GLOCOMW.2010.5700341'
apa: Keller, A., Plattner, B., Lübbers, E., Platzner, M., & Plessl, C. (2010).
Reconfigurable Nodes for Future Networks. Proc. IEEE Globecom Workshop on Network
of the Future (FutureNet), 372–376. https://doi.org/10.1109/GLOCOMW.2010.5700341
bibtex: '@inproceedings{Keller_Plattner_Lübbers_Platzner_Plessl_2010, title={Reconfigurable
Nodes for Future Networks}, DOI={10.1109/GLOCOMW.2010.5700341},
booktitle={Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)},
publisher={IEEE}, author={Keller, Ariane and Plattner, Bernhard and Lübbers, Enno
and Platzner, Marco and Plessl, Christian}, year={2010}, pages={372–376} }'
chicago: Keller, Ariane, Bernhard Plattner, Enno Lübbers, Marco Platzner, and Christian
Plessl. “Reconfigurable Nodes for Future Networks.” In Proc. IEEE Globecom
Workshop on Network of the Future (FutureNet), 372–76. IEEE, 2010. https://doi.org/10.1109/GLOCOMW.2010.5700341.
ieee: 'A. Keller, B. Plattner, E. Lübbers, M. Platzner, and C. Plessl, “Reconfigurable
Nodes for Future Networks,” in Proc. IEEE Globecom Workshop on Network of the
Future (FutureNet), 2010, pp. 372–376, doi: 10.1109/GLOCOMW.2010.5700341.'
mla: Keller, Ariane, et al. “Reconfigurable Nodes for Future Networks.” Proc.
IEEE Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp.
372–76, doi:10.1109/GLOCOMW.2010.5700341.
short: 'A. Keller, B. Plattner, E. Lübbers, M. Platzner, C. Plessl, in: Proc. IEEE
Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp. 372–376.'
date_created: 2018-04-04T09:36:16Z
date_updated: 2023-09-26T13:51:00Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/GLOCOMW.2010.5700341
language:
- iso: eng
page: 372-376
publication: Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)
publication_identifier:
isbn:
- 978-1-4244-8864-3
publisher: IEEE
quality_controlled: '1'
status: public
title: Reconfigurable Nodes for Future Networks
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2227'
author:
- first_name: Matthias
full_name: Woehrle, Matthias
last_name: Woehrle
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Lothar
full_name: Thiele, Lothar
last_name: Thiele
citation:
ama: 'Woehrle M, Plessl C, Thiele L. Rupeas: Ruby Powered Event Analysis DSL. In:
Proc. Int. Conf. Networked Sensing Systems (INSS). IEEE; 2010:245-248.
doi:10.1109/INSS.2010.5572211'
apa: 'Woehrle, M., Plessl, C., & Thiele, L. (2010). Rupeas: Ruby Powered Event
Analysis DSL. Proc. Int. Conf. Networked Sensing Systems (INSS), 245–248.
https://doi.org/10.1109/INSS.2010.5572211'
bibtex: '@inproceedings{Woehrle_Plessl_Thiele_2010, title={Rupeas: Ruby Powered
Event Analysis DSL}, DOI={10.1109/INSS.2010.5572211},
booktitle={Proc. Int. Conf. Networked Sensing Systems (INSS)}, publisher={IEEE},
author={Woehrle, Matthias and Plessl, Christian and Thiele, Lothar}, year={2010},
pages={245–248} }'
chicago: 'Woehrle, Matthias, Christian Plessl, and Lothar Thiele. “Rupeas: Ruby
Powered Event Analysis DSL.” In Proc. Int. Conf. Networked Sensing Systems
(INSS), 245–48. IEEE, 2010. https://doi.org/10.1109/INSS.2010.5572211.'
ieee: 'M. Woehrle, C. Plessl, and L. Thiele, “Rupeas: Ruby Powered Event Analysis
DSL,” in Proc. Int. Conf. Networked Sensing Systems (INSS), 2010, pp. 245–248,
doi: 10.1109/INSS.2010.5572211.'
mla: 'Woehrle, Matthias, et al. “Rupeas: Ruby Powered Event Analysis DSL.” Proc.
Int. Conf. Networked Sensing Systems (INSS), IEEE, 2010, pp. 245–48, doi:10.1109/INSS.2010.5572211.'
short: 'M. Woehrle, C. Plessl, L. Thiele, in: Proc. Int. Conf. Networked Sensing
Systems (INSS), IEEE, 2010, pp. 245–248.'
date_created: 2018-04-05T16:41:02Z
date_updated: 2023-09-26T13:49:38Z
department:
- _id: '27'
- _id: '518'
doi: 10.1109/INSS.2010.5572211
extern: '1'
language:
- iso: eng
page: 245-248
publication: Proc. Int. Conf. Networked Sensing Systems (INSS)
publication_identifier:
isbn:
- 978-1-4244-7911-5
publisher: IEEE
quality_controlled: '1'
status: public
title: 'Rupeas: Ruby Powered Event Analysis DSL'
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2228'
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Michael
full_name: Kauschke, Michael
last_name: Kauschke
citation:
ama: 'Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation for the
Exploration of CPU-Accelerator Architectures. In: Hammami O, Larrabee S, eds.
Proc. Workshop on Architectural Research Prototyping (WARP), International
Symposium on Computer Architecture (ISCA). ; 2010.'
apa: Kenter, T., Platzner, M., Plessl, C., & Kauschke, M. (2010). Performance
Estimation for the Exploration of CPU-Accelerator Architectures. In O. Hammami
& S. Larrabee (Eds.), Proc. Workshop on Architectural Research Prototyping
(WARP), International Symposium on Computer Architecture (ISCA).
bibtex: '@inproceedings{Kenter_Platzner_Plessl_Kauschke_2010, title={Performance
Estimation for the Exploration of CPU-Accelerator Architectures}, booktitle={Proc.
Workshop on Architectural Research Prototyping (WARP), International Symposium
on Computer Architecture (ISCA)}, author={Kenter, Tobias and Platzner, Marco and
Plessl, Christian and Kauschke, Michael}, editor={Hammami, Omar and Larrabee,
Sandra}, year={2010} }'
chicago: Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke.
“Performance Estimation for the Exploration of CPU-Accelerator Architectures.”
In Proc. Workshop on Architectural Research Prototyping (WARP), International
Symposium on Computer Architecture (ISCA), edited by Omar Hammami and Sandra
Larrabee, 2010.
ieee: T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation
for the Exploration of CPU-Accelerator Architectures,” in Proc. Workshop on
Architectural Research Prototyping (WARP), International Symposium on Computer
Architecture (ISCA), 2010.
mla: Kenter, Tobias, et al. “Performance Estimation for the Exploration of CPU-Accelerator
Architectures.” Proc. Workshop on Architectural Research Prototyping (WARP),
International Symposium on Computer Architecture (ISCA), edited by Omar Hammami
and Sandra Larrabee, 2010.
short: 'T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: O. Hammami, S. Larrabee
(Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International
Symposium on Computer Architecture (ISCA), 2010.'
date_created: 2018-04-05T16:43:04Z
date_updated: 2023-09-26T13:50:04Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
editor:
- first_name: Omar
full_name: Hammami, Omar
last_name: Hammami
- first_name: Sandra
full_name: Larrabee, Sandra
last_name: Larrabee
language:
- iso: eng
publication: Proc. Workshop on Architectural Research Prototyping (WARP), International
Symposium on Computer Architecture (ISCA)
quality_controlled: '1'
status: public
title: Performance Estimation for the Exploration of CPU-Accelerator Architectures
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2353'
abstract:
- lang: eng
text: 'Wireless Sensor Networks (WSNs) are unique embedded computation systems for
distributed sensing of a dispersed phenomenon. While being a strongly concurrent
distributed system, its embedded aspects with severe resource limitations and
the wireless communication requires a fusion of technologies and methodologies
from very different fields. As WSNs are deployed in remote locations for long-term
unattended operation, assurance of correct functioning of the system is of prime
concern. Thus, the design and development of WSNs requires specialized tools to
allow for testing and debugging the system. To this end, we present a framework
for analyzing and checking WSNs based on collected events during system operation.
It allows for abstracting from the event trace by means of behavioral queries
and uses assertions for checking the accordance of an execution to its specification.
The framework is independent from WSN test platforms, applications and logging
semantics and thus generally applicable for analyzing event logs of WSN test executions. '
author:
- first_name: Matthias
full_name: Woehrle, Matthias
last_name: Woehrle
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Lothar
full_name: Thiele, Lothar
last_name: Thiele
citation:
ama: 'Woehrle M, Plessl C, Thiele L. Rupeas: Ruby Powered Event Analysis DSL.
Computer Engineering and Networks Lab, ETH Zurich; 2009.'
apa: 'Woehrle, M., Plessl, C., & Thiele, L. (2009). Rupeas: Ruby Powered
Event Analysis DSL. Computer Engineering and Networks Lab, ETH Zurich.'
bibtex: '@book{Woehrle_Plessl_Thiele_2009, place={Computer Engineering and Networks
Lab, ETH Zurich}, title={Rupeas: Ruby Powered Event Analysis DSL}, author={Woehrle,
Matthias and Plessl, Christian and Thiele, Lothar}, year={2009} }'
chicago: 'Woehrle, Matthias, Christian Plessl, and Lothar Thiele. Rupeas: Ruby
Powered Event Analysis DSL. Computer Engineering and Networks Lab, ETH Zurich,
2009.'
ieee: 'M. Woehrle, C. Plessl, and L. Thiele, Rupeas: Ruby Powered Event Analysis
DSL. Computer Engineering and Networks Lab, ETH Zurich, 2009.'
mla: 'Woehrle, Matthias, et al. Rupeas: Ruby Powered Event Analysis DSL.
2009.'
short: 'M. Woehrle, C. Plessl, L. Thiele, Rupeas: Ruby Powered Event Analysis DSL,
Computer Engineering and Networks Lab, ETH Zurich, 2009.'
date_created: 2018-04-16T15:09:19Z
date_updated: 2022-01-06T06:55:56Z
department:
- _id: '27'
- _id: '518'
extern: '1'
keyword:
- Rupeas
- DSL
- WSN
- testing
language:
- iso: eng
place: Computer Engineering and Networks Lab, ETH Zurich
report_number: TIK-Report 290
status: public
title: 'Rupeas: Ruby Powered Event Analysis DSL'
type: report
user_id: '16153'
year: '2009'
...
---
_id: '2350'
abstract:
- lang: eng
text: 'Mapping applications that consist of a collection of cores to FPGA accelerators
and optimizing their performance is a challenging task in high performance reconfigurable
computing. We present IMORC, an architectural template and highly versatile on-chip
interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which
allows for flexibly composing accelerators from cores running at full speed within
their own clock domains, thus facilitating the re-use of cores and portability.
Further, IMORC inserts performance counters for monitoring runtime data. In this
paper, we first introduce the IMORC architectural template and the on-chip interconnect,
and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor
thinning problem on an XD1000 reconfigurable computing system. Using IMORC''s
monitoring infrastructure, we gain insights into the data-dependent behavior of
the application which, in turn, allow for optimizing the accelerator. '
author:
- first_name: Tobias
full_name: Schumacher, Tobias
last_name: Schumacher
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Schumacher T, Plessl C, Platzner M. IMORC: Application Mapping, Monitoring
and Optimization for High-Performance Reconfigurable Computing. In: Proc. Int.
Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer
Society; 2009:275-278. doi:10.1109/FCCM.2009.25'
apa: 'Schumacher, T., Plessl, C., & Platzner, M. (2009). IMORC: Application
Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.
Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM),
275–278. https://doi.org/10.1109/FCCM.2009.25'
bibtex: '@inproceedings{Schumacher_Plessl_Platzner_2009, title={IMORC: Application
Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing},
DOI={10.1109/FCCM.2009.25},
booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)},
publisher={IEEE Computer Society}, author={Schumacher, Tobias and Plessl, Christian
and Platzner, Marco}, year={2009}, pages={275–278} }'
chicago: 'Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: Application
Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.”
In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM),
275–78. IEEE Computer Society, 2009. https://doi.org/10.1109/FCCM.2009.25.'
ieee: 'T. Schumacher, C. Plessl, and M. Platzner, “IMORC: Application Mapping, Monitoring
and Optimization for High-Performance Reconfigurable Computing,” in Proc. Int.
Symp. on Field-Programmable Custom Computing Machines (FCCM), 2009, pp. 275–278,
doi: 10.1109/FCCM.2009.25.'
mla: 'Schumacher, Tobias, et al. “IMORC: Application Mapping, Monitoring and Optimization
for High-Performance Reconfigurable Computing.” Proc. Int. Symp. on Field-Programmable
Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–78,
doi:10.1109/FCCM.2009.25.'
short: 'T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable
Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–278.'
date_created: 2018-04-16T15:05:52Z
date_updated: 2023-09-26T13:51:44Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/FCCM.2009.25
keyword:
- IMORC
- interconnect
- performance
language:
- iso: eng
page: 275-278
publication: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)
publication_identifier:
isbn:
- 978-1-4244-4450-2
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: 'IMORC: Application Mapping, Monitoring and Optimization for High-Performance
Reconfigurable Computing'
type: conference
user_id: '15278'
year: '2009'
...
---
_id: '2262'
abstract:
- lang: eng
text: 'In this work we present EvoCache, a novel approach for implementing application-specific
caches. The key innovation of EvoCache is to make the function that maps memory
addresses from the CPU address space to cache indices programmable. We support
arbitrary Boolean mapping functions that are implemented within a small reconfigurable
logic fabric. For finding suitable cache mapping functions we rely on techniques
from the evolvable hardware domain and utilize an evolutionary optimization procedure.
We evaluate the use of EvoCache in an embedded processor for two specific applications
(JPEG and BZIP2 compression) with respect to execution time, cache miss rate and
energy consumption. We show that the evolvable hardware approach for optimizing
the cache functions not only significantly improves the cache performance for
the training data used during optimization, but that the evolved mapping functions
generalize very well. Compared to a conventional cache architecture, EvoCache
applied to test data achieves a reduction in execution time of up to 14.31% for
JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70%
for BZIP2). We also discuss the integration of EvoCache into the operating system
and show that the area and delay overheads introduced by EvoCache are acceptable. '
author:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Kaufmann P, Plessl C, Platzner M. EvoCaches: Application-specific Adaptation
of Cache Mapping. In: Proc. NASA/ESA Conference on Adaptive Hardware and Systems
(AHS). IEEE Computer Society; 2009:11-18.'
apa: 'Kaufmann, P., Plessl, C., & Platzner, M. (2009). EvoCaches: Application-specific
Adaptation of Cache Mapping. Proc. NASA/ESA Conference on Adaptive Hardware
and Systems (AHS), 11–18.'
bibtex: '@inproceedings{Kaufmann_Plessl_Platzner_2009, place={Los Alamitos, CA,
USA}, title={EvoCaches: Application-specific Adaptation of Cache Mapping}, booktitle={Proc.
NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}, publisher={IEEE Computer
Society}, author={Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2009},
pages={11–18} }'
chicago: 'Kaufmann, Paul, Christian Plessl, and Marco Platzner. “EvoCaches: Application-Specific
Adaptation of Cache Mapping.” In Proc. NASA/ESA Conference on Adaptive Hardware
and Systems (AHS), 11–18. Los Alamitos, CA, USA: IEEE Computer Society, 2009.'
ieee: 'P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific
Adaptation of Cache Mapping,” in Proc. NASA/ESA Conference on Adaptive Hardware
and Systems (AHS), 2009, pp. 11–18.'
mla: 'Kaufmann, Paul, et al. “EvoCaches: Application-Specific Adaptation of Cache
Mapping.” Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS),
IEEE Computer Society, 2009, pp. 11–18.'
short: 'P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive
Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009,
pp. 11–18.'
date_created: 2018-04-06T15:18:24Z
date_updated: 2023-09-26T13:53:11Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
keyword:
- EvoCache
- evolvable hardware
- computer architecture
language:
- iso: eng
page: 11-18
place: Los Alamitos, CA, USA
publication: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: 'EvoCaches: Application-specific Adaptation of Cache Mapping'
type: conference
user_id: '15278'
year: '2009'
...
---
_id: '2352'
author:
- first_name: Jan
full_name: Beutel, Jan
last_name: Beutel
- first_name: Stephan
full_name: Gruber, Stephan
last_name: Gruber
- first_name: Andi
full_name: Hasler, Andi
last_name: Hasler
- first_name: Roman
full_name: Lim, Roman
last_name: Lim
- first_name: Andreas
full_name: Meier, Andreas
last_name: Meier
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Igor
full_name: Talzi, Igor
last_name: Talzi
- first_name: Lothar
full_name: Thiele, Lothar
last_name: Thiele
- first_name: Christian
full_name: Tschudin, Christian
last_name: Tschudin
- first_name: Matthias
full_name: Woehrle, Matthias
last_name: Woehrle
- first_name: Mustafa
full_name: Yuecel, Mustafa
last_name: Yuecel
citation:
ama: 'Beutel J, Gruber S, Hasler A, et al. PermaDAQ: A Scientific Instrument for
Precision Sensing and Data Recovery in Environmental Extremes. In: Proc. Int.
Conf. on Information Processing in Sensor Networks (IPSN). IEEE Computer Society;
2009:265-276.'
apa: 'Beutel, J., Gruber, S., Hasler, A., Lim, R., Meier, A., Plessl, C., Talzi,
I., Thiele, L., Tschudin, C., Woehrle, M., & Yuecel, M. (2009). PermaDAQ:
A Scientific Instrument for Precision Sensing and Data Recovery in Environmental
Extremes. Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN),
265–276.'
bibtex: '@inproceedings{Beutel_Gruber_Hasler_Lim_Meier_Plessl_Talzi_Thiele_Tschudin_Woehrle_et
al._2009, place={Washington, DC, USA}, title={PermaDAQ: A Scientific Instrument
for Precision Sensing and Data Recovery in Environmental Extremes}, booktitle={Proc.
Int. Conf. on Information Processing in Sensor Networks (IPSN)}, publisher={IEEE
Computer Society}, author={Beutel, Jan and Gruber, Stephan and Hasler, Andi and
Lim, Roman and Meier, Andreas and Plessl, Christian and Talzi, Igor and Thiele,
Lothar and Tschudin, Christian and Woehrle, Matthias and et al.}, year={2009},
pages={265–276} }'
chicago: 'Beutel, Jan, Stephan Gruber, Andi Hasler, Roman Lim, Andreas Meier, Christian
Plessl, Igor Talzi, et al. “PermaDAQ: A Scientific Instrument for Precision Sensing
and Data Recovery in Environmental Extremes.” In Proc. Int. Conf. on Information
Processing in Sensor Networks (IPSN), 265–76. Washington, DC, USA: IEEE Computer
Society, 2009.'
ieee: 'J. Beutel et al., “PermaDAQ: A Scientific Instrument for Precision
Sensing and Data Recovery in Environmental Extremes,” in Proc. Int. Conf. on
Information Processing in Sensor Networks (IPSN), 2009, pp. 265–276.'
mla: 'Beutel, Jan, et al. “PermaDAQ: A Scientific Instrument for Precision Sensing
and Data Recovery in Environmental Extremes.” Proc. Int. Conf. on Information
Processing in Sensor Networks (IPSN), IEEE Computer Society, 2009, pp. 265–76.'
short: 'J. Beutel, S. Gruber, A. Hasler, R. Lim, A. Meier, C. Plessl, I. Talzi,
L. Thiele, C. Tschudin, M. Woehrle, M. Yuecel, in: Proc. Int. Conf. on Information
Processing in Sensor Networks (IPSN), IEEE Computer Society, Washington, DC, USA,
2009, pp. 265–276.'
date_created: 2018-04-16T15:08:07Z
date_updated: 2023-09-26T13:52:01Z
department:
- _id: '27'
- _id: '518'
extern: '1'
keyword:
- WSN
- PermaSense
language:
- iso: eng
page: 265-276
place: Washington, DC, USA
publication: Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)
publication_identifier:
isbn:
- 978-1-4244-5108-1
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: 'PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery
in Environmental Extremes'
type: conference
user_id: '15278'
year: '2009'
...
---
_id: '2238'
author:
- first_name: Tobias
full_name: Schumacher, Tobias
last_name: Schumacher
- first_name: Tim
full_name: Süß, Tim
last_name: Süß
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Schumacher T, Süß T, Plessl C, Platzner M. Communication Performance Characterization
for Reconfigurable Accelerator Design on the XD1000. In: Proc. Int. Conf. on
ReConFigurable Computing and FPGAs (ReConFig). IEEE Computer Society; 2009:119-124.
doi:10.1109/ReConFig.2009.32'
apa: Schumacher, T., Süß, T., Plessl, C., & Platzner, M. (2009). Communication
Performance Characterization for Reconfigurable Accelerator Design on the XD1000.
Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–124.
https://doi.org/10.1109/ReConFig.2009.32
bibtex: '@inproceedings{Schumacher_Süß_Plessl_Platzner_2009, place={Los Alamitos,
CA, USA}, title={Communication Performance Characterization for Reconfigurable
Accelerator Design on the XD1000}, DOI={10.1109/ReConFig.2009.32},
booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)},
publisher={IEEE Computer Society}, author={Schumacher, Tobias and Süß, Tim and
Plessl, Christian and Platzner, Marco}, year={2009}, pages={119–124} }'
chicago: 'Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “Communication
Performance Characterization for Reconfigurable Accelerator Design on the XD1000.”
In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–24.
Los Alamitos, CA, USA: IEEE Computer Society, 2009. https://doi.org/10.1109/ReConFig.2009.32.'
ieee: 'T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “Communication Performance
Characterization for Reconfigurable Accelerator Design on the XD1000,” in Proc.
Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 2009, pp. 119–124,
doi: 10.1109/ReConFig.2009.32.'
mla: Schumacher, Tobias, et al. “Communication Performance Characterization for
Reconfigurable Accelerator Design on the XD1000.” Proc. Int. Conf. on ReConFigurable
Computing and FPGAs (ReConFig), IEEE Computer Society, 2009, pp. 119–24, doi:10.1109/ReConFig.2009.32.
short: 'T. Schumacher, T. Süß, C. Plessl, M. Platzner, in: Proc. Int. Conf. on ReConFigurable
Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA,
2009, pp. 119–124.'
date_created: 2018-04-05T17:11:28Z
date_updated: 2023-09-26T13:52:32Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2009.32
keyword:
- IMORC
- graphics
language:
- iso: eng
page: 119-124
place: Los Alamitos, CA, USA
publication: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)
publication_identifier:
isbn:
- 978-0-7695-3917-1
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: Communication Performance Characterization for Reconfigurable Accelerator Design
on the XD1000
type: conference
user_id: '15278'
year: '2009'
...
---
_id: '2261'
author:
- first_name: Tobias
full_name: Schumacher, Tobias
last_name: Schumacher
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Schumacher T, Plessl C, Platzner M. An Accelerator for k-th Nearest Neighbor
Thinning Based on the IMORC Infrastructure. In: Proc. Int. Conf. on Field Programmable
Logic and Applications (FPL). IEEE; 2009:338-344.'
apa: Schumacher, T., Plessl, C., & Platzner, M. (2009). An Accelerator for k-th
Nearest Neighbor Thinning Based on the IMORC Infrastructure. Proc. Int. Conf.
on Field Programmable Logic and Applications (FPL), 338–344.
bibtex: '@inproceedings{Schumacher_Plessl_Platzner_2009, title={An Accelerator for
k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}, booktitle={Proc.
Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE},
author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009},
pages={338–344} }'
chicago: Schumacher, Tobias, Christian Plessl, and Marco Platzner. “An Accelerator
for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” In Proc.
Int. Conf. on Field Programmable Logic and Applications (FPL), 338–44. IEEE,
2009.
ieee: T. Schumacher, C. Plessl, and M. Platzner, “An Accelerator for k-th Nearest
Neighbor Thinning Based on the IMORC Infrastructure,” in Proc. Int. Conf. on
Field Programmable Logic and Applications (FPL), 2009, pp. 338–344.
mla: Schumacher, Tobias, et al. “An Accelerator for K-Th Nearest Neighbor Thinning
Based on the IMORC Infrastructure.” Proc. Int. Conf. on Field Programmable
Logic and Applications (FPL), IEEE, 2009, pp. 338–44.
short: 'T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable
Logic and Applications (FPL), IEEE, 2009, pp. 338–344.'
date_created: 2018-04-06T15:15:47Z
date_updated: 2023-09-26T13:52:52Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
keyword:
- IMORC
- NOC
- KNN
- accelerator
language:
- iso: eng
page: 338-344
publication: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)
publication_identifier:
isbn:
- 978-1-4244-3892-1
issn:
- 1946-1488
publisher: IEEE
quality_controlled: '1'
status: public
title: An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure
type: conference
user_id: '15278'
year: '2009'
...
---
_id: '2263'
abstract:
- lang: eng
text: 'In this paper, we introduce the Woolcano reconfigurable processor architecture.
The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary
Processing Unit (APU) as well as the partial reconfiguration capabilities to provide
dynamically reconfigurable custom instructions. We also present a hardware tool
flow that automatically translates software functions into custom instructions
and a software tool flow that creates binaries using these instructions. While
previous research on processors with reconfigurable functional units has been
performed predominantly with simulation, the Woolcano architecture allows for
exploring dynamic instruction set extension with commercially available hardware.
Finally, we present a case study demonstrating a custom floating-point instruction
generated with our approach, which achieves a 40x speedup over software-emulated
floating-point operations and a 21% speedup over the Xilinx hardware floating-point
unit. '
author:
- first_name: Mariusz
full_name: Grad, Mariusz
last_name: Grad
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Grad M, Plessl C. Woolcano: An Architecture and Tool Flow for Dynamic Instruction
Set Extension on Xilinx Virtex-4 FX. In: Proc. Int. Conf. on Engineering of
Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2009:319-322.'
apa: 'Grad, M., & Plessl, C. (2009). Woolcano: An Architecture and Tool Flow
for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. Proc. Int. Conf.
on Engineering of Reconfigurable Systems and Algorithms (ERSA), 319–322.'
bibtex: '@inproceedings{Grad_Plessl_2009, place={USA}, title={Woolcano: An Architecture
and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX}, booktitle={Proc.
Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA
Press}, author={Grad, Mariusz and Plessl, Christian}, year={2009}, pages={319–322}
}'
chicago: 'Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool
Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” In Proc.
Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
319–22. USA: CSREA Press, 2009.'
ieee: 'M. Grad and C. Plessl, “Woolcano: An Architecture and Tool Flow for Dynamic
Instruction Set Extension on Xilinx Virtex-4 FX,” in Proc. Int. Conf. on Engineering
of Reconfigurable Systems and Algorithms (ERSA), 2009, pp. 319–322.'
mla: 'Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow
for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” Proc. Int. Conf.
on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press,
2009, pp. 319–22.'
short: 'M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), CSREA Press, USA, 2009, pp. 319–322.'
date_created: 2018-04-06T15:19:51Z
date_updated: 2023-09-26T13:53:30Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
language:
- iso: eng
page: 319-322
place: USA
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA)
publication_identifier:
isbn:
- 1-60132-101-5
publisher: CSREA Press
quality_controlled: '1'
status: public
title: 'Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension
on Xilinx Virtex-4 FX'
type: conference
user_id: '15278'
year: '2009'
...