---
_id: '53663'
abstract:
- lang: eng
text: 'Noctua 2 is a supercomputer operated at the Paderborn Center for Parallel
Computing (PC2) at Paderborn University in Germany. Noctua 2 was inaugurated in
2022 and is an Atos BullSequana XH2000 system. It consists mainly of three node
types: 1) CPU Compute nodes with AMD EPYC processors in different main memory
configurations, 2) GPU nodes with NVIDIA A100 GPUs, and 3) FPGA nodes with Xilinx
Alveo U280 and Intel Stratix 10 FPGA cards. While CPUs and GPUs are known off-the-shelf
components in HPC systems, the operation of a large number of FPGA cards from
different vendors and a dedicated FPGA-to-FPGA network are unique characteristics
of Noctua 2. This paper describes in detail the overall setup of Noctua 2 and
gives insights into the operation of the cluster from a hardware, software and
facility perspective.'
article_type: original
author:
- first_name: Carsten
full_name: Bauer, Carsten
id: '90082'
last_name: Bauer
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Michael
full_name: Lass, Michael
id: '24135'
last_name: Lass
orcid: 0000-0002-5708-7632
- first_name: Lukas
full_name: Mazur, Lukas
id: '90492'
last_name: Mazur
orcid: ' 0000-0001-6304-7082'
- first_name: Marius
full_name: Meyer, Marius
id: '40778'
last_name: Meyer
- first_name: Holger
full_name: Nitsche, Holger
id: '15272'
last_name: Nitsche
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Robert
full_name: Schade, Robert
id: '75963'
last_name: Schade
orcid: 0000-0002-6268-5397
- first_name: Michael
full_name: Schwarz, Michael
id: '5312'
last_name: Schwarz
- first_name: Nils
full_name: Winnwa, Nils
id: '61189'
last_name: Winnwa
- first_name: Alex
full_name: Wiens, Alex
id: '23522'
last_name: Wiens
orcid: 0000-0003-1764-9773
- first_name: Xin
full_name: Wu, Xin
id: '77439'
last_name: Wu
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Jens
full_name: Simon, Jens
id: '15273'
last_name: Simon
citation:
ama: Bauer C, Kenter T, Lass M, et al. Noctua 2 Supercomputer. Journal of large-scale
research facilities. 2024;9. doi:10.17815/jlsrf-8-187
apa: Bauer, C., Kenter, T., Lass, M., Mazur, L., Meyer, M., Nitsche, H., Riebler,
H., Schade, R., Schwarz, M., Winnwa, N., Wiens, A., Wu, X., Plessl, C., &
Simon, J. (2024). Noctua 2 Supercomputer. Journal of Large-Scale Research Facilities,
9. https://doi.org/10.17815/jlsrf-8-187
bibtex: '@article{Bauer_Kenter_Lass_Mazur_Meyer_Nitsche_Riebler_Schade_Schwarz_Winnwa_et
al._2024, title={Noctua 2 Supercomputer}, volume={9}, DOI={10.17815/jlsrf-8-187 }, journal={Journal of large-scale research facilities},
author={Bauer, Carsten and Kenter, Tobias and Lass, Michael and Mazur, Lukas and
Meyer, Marius and Nitsche, Holger and Riebler, Heinrich and Schade, Robert and
Schwarz, Michael and Winnwa, Nils and et al.}, year={2024} }'
chicago: Bauer, Carsten, Tobias Kenter, Michael Lass, Lukas Mazur, Marius Meyer,
Holger Nitsche, Heinrich Riebler, et al. “Noctua 2 Supercomputer.” Journal
of Large-Scale Research Facilities 9 (2024). https://doi.org/10.17815/jlsrf-8-187 .
ieee: 'C. Bauer et al., “Noctua 2 Supercomputer,” Journal of large-scale
research facilities, vol. 9, 2024, doi: 10.17815/jlsrf-8-187 .'
mla: Bauer, Carsten, et al. “Noctua 2 Supercomputer.” Journal of Large-Scale
Research Facilities, vol. 9, 2024, doi:10.17815/jlsrf-8-187 .
short: C. Bauer, T. Kenter, M. Lass, L. Mazur, M. Meyer, H. Nitsche, H. Riebler,
R. Schade, M. Schwarz, N. Winnwa, A. Wiens, X. Wu, C. Plessl, J. Simon, Journal
of Large-Scale Research Facilities 9 (2024).
date_created: 2024-04-26T07:39:41Z
date_updated: 2024-04-26T08:44:30Z
ddc:
- '004'
department:
- _id: '27'
- _id: '518'
doi: '10.17815/jlsrf-8-187 '
file:
- access_level: open_access
content_type: application/pdf
creator: deffel
date_created: 2024-04-26T07:30:20Z
date_updated: 2024-04-26T08:35:17Z
file_id: '53664'
file_name: Noctua2_Supercomputer.pdf
file_size: 3825480
relation: main_file
file_date_updated: 2024-04-26T08:35:17Z
has_accepted_license: '1'
intvolume: ' 9'
keyword:
- Noctua 2
- Supercomputer
- FPGA
- PC2
- Paderborn Center for Parallel Computing
language:
- iso: eng
oa: '1'
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: Journal of large-scale research facilities
publication_status: published
status: public
title: Noctua 2 Supercomputer
type: journal_article
user_id: '8961'
volume: 9
year: '2024'
...
---
_id: '56606'
abstract:
- lang: eng
text: AbstractMost FPGA boards in the HPC domain
are well-suited for parallel scaling because of the direct integration of versatile
and high-throughput network ports. However, the utilization of their network capabilities is
often challenging and error-prone because the whole network stack and communication
patterns have to be implemented and managed on the FPGAs. Also, this approach
conceptually involves a trade-off between the performance potential of improved
communication and the impact of resource consumption for communication infrastructure,
since the utilized resources on the FPGAs could otherwise be used for computations.
In this work, we investigate this trade-off, firstly, by using synthetic benchmarks
to evaluate the different configuration options of the communication framework
ACCL and their impact on communication latency and throughput. Finally, we use
our findings to implement a shallow water simulation whose scalability heavily
depends on low-latency communication. With a suitable configuration of ACCL, good
scaling behavior can be shown to all 48 FPGAs installed in the system. Overall,
the results show that the availability of inter-FPGA communication frameworks
as well as the configurability of framework and network stack are crucial to achieve
the best application performance with low latency communication.
author:
- first_name: Marius
full_name: Meyer, Marius
last_name: Meyer
- first_name: Tobias
full_name: Kenter, Tobias
last_name: Kenter
- first_name: Lucian
full_name: Petrica, Lucian
last_name: Petrica
- first_name: Kenneth
full_name: O’Brien, Kenneth
last_name: O’Brien
- first_name: Michaela
full_name: Blott, Michaela
last_name: Blott
- first_name: Christian
full_name: Plessl, Christian
last_name: Plessl
citation:
ama: 'Meyer M, Kenter T, Petrica L, O’Brien K, Blott M, Plessl C. Optimizing Communication
for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL. In: Lecture
Notes in Computer Science. Springer Nature Switzerland; 2024. doi:10.1007/978-3-031-69766-1_9'
apa: Meyer, M., Kenter, T., Petrica, L., O’Brien, K., Blott, M., & Plessl, C.
(2024). Optimizing Communication for Latency Sensitive HPC Applications on up
to 48 FPGAs Using ACCL. In Lecture Notes in Computer Science. Springer
Nature Switzerland. https://doi.org/10.1007/978-3-031-69766-1_9
bibtex: '@inbook{Meyer_Kenter_Petrica_O’Brien_Blott_Plessl_2024, place={Cham}, title={Optimizing
Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL},
DOI={10.1007/978-3-031-69766-1_9},
booktitle={Lecture Notes in Computer Science}, publisher={Springer Nature Switzerland},
author={Meyer, Marius and Kenter, Tobias and Petrica, Lucian and O’Brien, Kenneth
and Blott, Michaela and Plessl, Christian}, year={2024} }'
chicago: 'Meyer, Marius, Tobias Kenter, Lucian Petrica, Kenneth O’Brien, Michaela
Blott, and Christian Plessl. “Optimizing Communication for Latency Sensitive HPC
Applications on up to 48 FPGAs Using ACCL.” In Lecture Notes in Computer Science.
Cham: Springer Nature Switzerland, 2024. https://doi.org/10.1007/978-3-031-69766-1_9.'
ieee: 'M. Meyer, T. Kenter, L. Petrica, K. O’Brien, M. Blott, and C. Plessl, “Optimizing
Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL,”
in Lecture Notes in Computer Science, Cham: Springer Nature Switzerland,
2024.'
mla: Meyer, Marius, et al. “Optimizing Communication for Latency Sensitive HPC Applications
on up to 48 FPGAs Using ACCL.” Lecture Notes in Computer Science, Springer
Nature Switzerland, 2024, doi:10.1007/978-3-031-69766-1_9.
short: 'M. Meyer, T. Kenter, L. Petrica, K. O’Brien, M. Blott, C. Plessl, in: Lecture
Notes in Computer Science, Springer Nature Switzerland, Cham, 2024.'
date_created: 2024-10-14T07:51:51Z
date_updated: 2024-10-14T07:55:50Z
department:
- _id: '27'
- _id: '518'
doi: 10.1007/978-3-031-69766-1_9
language:
- iso: eng
main_file_link:
- open_access: '1'
oa: '1'
place: Cham
publication: Lecture Notes in Computer Science
publication_identifier:
isbn:
- '9783031697654'
- '9783031697661'
issn:
- 0302-9743
- 1611-3349
publication_status: published
publisher: Springer Nature Switzerland
quality_controlled: '1'
status: public
title: Optimizing Communication for Latency Sensitive HPC Applications on up to 48
FPGAs Using ACCL
type: book_chapter
user_id: '3145'
year: '2024'
...
---
_id: '56605'
author:
- first_name: Jan-Oliver
full_name: Opdenhövel, Jan-Oliver
id: '73960'
last_name: Opdenhövel
orcid: 0000-0003-2314-2784
- first_name: Christoph
full_name: Alt, Christoph
id: '100625'
last_name: Alt
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
citation:
ama: 'Opdenhövel J-O, Alt C, Plessl C, Kenter T. StencilStream: A SYCL-based Stencil
Simulation Framework Targeting FPGAs. In: 2024 34th International Conference
on Field-Programmable Logic and Applications (FPL). IEEE; 2024. doi:10.1109/fpl64840.2024.00023'
apa: 'Opdenhövel, J.-O., Alt, C., Plessl, C., & Kenter, T. (2024). StencilStream:
A SYCL-based Stencil Simulation Framework Targeting FPGAs. 2024 34th International
Conference on Field-Programmable Logic and Applications (FPL). https://doi.org/10.1109/fpl64840.2024.00023'
bibtex: '@inproceedings{Opdenhövel_Alt_Plessl_Kenter_2024, title={StencilStream:
A SYCL-based Stencil Simulation Framework Targeting FPGAs}, DOI={10.1109/fpl64840.2024.00023},
booktitle={2024 34th International Conference on Field-Programmable Logic and
Applications (FPL)}, publisher={IEEE}, author={Opdenhövel, Jan-Oliver and Alt,
Christoph and Plessl, Christian and Kenter, Tobias}, year={2024} }'
chicago: 'Opdenhövel, Jan-Oliver, Christoph Alt, Christian Plessl, and Tobias Kenter.
“StencilStream: A SYCL-Based Stencil Simulation Framework Targeting FPGAs.” In
2024 34th International Conference on Field-Programmable Logic and Applications
(FPL). IEEE, 2024. https://doi.org/10.1109/fpl64840.2024.00023.'
ieee: 'J.-O. Opdenhövel, C. Alt, C. Plessl, and T. Kenter, “StencilStream: A SYCL-based
Stencil Simulation Framework Targeting FPGAs,” 2024, doi: 10.1109/fpl64840.2024.00023.'
mla: 'Opdenhövel, Jan-Oliver, et al. “StencilStream: A SYCL-Based Stencil Simulation
Framework Targeting FPGAs.” 2024 34th International Conference on Field-Programmable
Logic and Applications (FPL), IEEE, 2024, doi:10.1109/fpl64840.2024.00023.'
short: 'J.-O. Opdenhövel, C. Alt, C. Plessl, T. Kenter, in: 2024 34th International
Conference on Field-Programmable Logic and Applications (FPL), IEEE, 2024.'
date_created: 2024-10-14T07:49:24Z
date_updated: 2024-10-14T07:56:26Z
department:
- _id: '27'
- _id: '518'
doi: 10.1109/fpl64840.2024.00023
language:
- iso: eng
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: 2024 34th International Conference on Field-Programmable Logic and Applications
(FPL)
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: 'StencilStream: A SYCL-based Stencil Simulation Framework Targeting FPGAs'
type: conference
user_id: '3145'
year: '2024'
...
---
_id: '56607'
author:
- first_name: Abdul Rehman
full_name: Tareen, Abdul Rehman
id: '76938'
last_name: Tareen
- first_name: Marius
full_name: Meyer, Marius
id: '40778'
last_name: Meyer
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
citation:
ama: 'Tareen AR, Meyer M, Plessl C, Kenter T. HiHiSpMV: Sparse Matrix Vector Multiplication
with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory. In: 2024
IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing
Machines (FCCM). Vol 35. IEEE; 2024. doi:10.1109/fccm60383.2024.00014'
apa: 'Tareen, A. R., Meyer, M., Plessl, C., & Kenter, T. (2024). HiHiSpMV: Sparse
Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High
Bandwidth Memory. 2024 IEEE 32nd Annual International Symposium on Field-Programmable
Custom Computing Machines (FCCM), 35. https://doi.org/10.1109/fccm60383.2024.00014'
bibtex: '@inproceedings{Tareen_Meyer_Plessl_Kenter_2024, title={HiHiSpMV: Sparse
Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High
Bandwidth Memory}, volume={35}, DOI={10.1109/fccm60383.2024.00014},
booktitle={2024 IEEE 32nd Annual International Symposium on Field-Programmable
Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Tareen, Abdul Rehman
and Meyer, Marius and Plessl, Christian and Kenter, Tobias}, year={2024} }'
chicago: 'Tareen, Abdul Rehman, Marius Meyer, Christian Plessl, and Tobias Kenter.
“HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions
on FPGAs with High Bandwidth Memory.” In 2024 IEEE 32nd Annual International
Symposium on Field-Programmable Custom Computing Machines (FCCM), Vol. 35.
IEEE, 2024. https://doi.org/10.1109/fccm60383.2024.00014.'
ieee: 'A. R. Tareen, M. Meyer, C. Plessl, and T. Kenter, “HiHiSpMV: Sparse Matrix
Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth
Memory,” in 2024 IEEE 32nd Annual International Symposium on Field-Programmable
Custom Computing Machines (FCCM), 2024, vol. 35, doi: 10.1109/fccm60383.2024.00014.'
mla: 'Tareen, Abdul Rehman, et al. “HiHiSpMV: Sparse Matrix Vector Multiplication
with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory.” 2024
IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing
Machines (FCCM), vol. 35, IEEE, 2024, doi:10.1109/fccm60383.2024.00014.'
short: 'A.R. Tareen, M. Meyer, C. Plessl, T. Kenter, in: 2024 IEEE 32nd Annual International
Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2024.'
date_created: 2024-10-14T07:59:08Z
date_updated: 2024-10-14T12:27:55Z
department:
- _id: '27'
- _id: '518'
doi: 10.1109/fccm60383.2024.00014
intvolume: ' 35'
language:
- iso: eng
publication: 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom
Computing Machines (FCCM)
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: 'HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions
on FPGAs with High Bandwidth Memory'
type: conference
user_id: '3145'
volume: 35
year: '2024'
...
---
_id: '56609'
abstract:
- lang: eng
text: 'The computation of electron repulsion integrals (ERIs) is a key component
for quantum chemical methods. The intensive computation and bandwidth demand for
ERI evaluation presents a significant challenge for quantum-mechanics-based atomistic
simulations with hybrid density functional theory: due to the tens of trillions
of ERI computations in each time step, practical applications are usually limited
to thousands of atoms. In this work, we propose SERI, a high-throughput streaming
accelerator for ERI computation on HBM-based FPGAs. In contrast to prior buffer-based
designs, SERI proposes a novel streaming architecture to address the on-chip buffer
limitation and the floorplanning challenge, and leverages the high-bandwidth memory
to overcome the bandwidth bottleneck in prior designs. Moreover, to meet the varying
computation, bandwidth, and floorplanning requirements between the 55 canonical
quartet classes in ERI calculation, we design an automation tool, together with
an accurate performance model, to automatically customize the architecture and
floorplanning strategy for each canonical quartet class to maximize their throughput.
Our performance evaluation on the AMD/Xilinx Alveo U280 FPGA board shows that,
SERI achieves an average speedup of 9.80 x over the previous best-performing FPGA
design, a 3.21x speedup over a 64-core AMD EPYC 7713 CPU, and a 15.64x speedup
over an Nvidia A40 GPU. It reaches a peak throughput of 23.8 GERIS ($10^9$ ERIs
per second) on one Alveo U280 FPGA. SERI will be released soon at https://github.com/SFU-HiAccel/SERI.'
author:
- first_name: Philip
full_name: Stachura, Philip
last_name: Stachura
- first_name: Guanyu
full_name: Li, Guanyu
last_name: Li
- first_name: Xin
full_name: Wu, Xin
id: '77439'
last_name: Wu
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Zhenman
full_name: Fang, Zhenman
last_name: Fang
citation:
ama: 'Stachura P, Li G, Wu X, Plessl C, Fang Z. SERI: High-Throughput Streaming
Acceleration of Electron Repulsion Integral Computation in Quantum Chemistry using
HBM-based FPGAs. In: 2024 34th International Conference on Field-Programmable
Logic and Applications (FPL). IEEE; 2024:60-68. doi:10.1109/fpl64840.2024.00018'
apa: 'Stachura, P., Li, G., Wu, X., Plessl, C., & Fang, Z. (2024). SERI: High-Throughput
Streaming Acceleration of Electron Repulsion Integral Computation in Quantum Chemistry
using HBM-based FPGAs. 2024 34th International Conference on Field-Programmable
Logic and Applications (FPL), 60–68. https://doi.org/10.1109/fpl64840.2024.00018'
bibtex: '@inproceedings{Stachura_Li_Wu_Plessl_Fang_2024, title={SERI: High-Throughput
Streaming Acceleration of Electron Repulsion Integral Computation in Quantum Chemistry
using HBM-based FPGAs}, DOI={10.1109/fpl64840.2024.00018},
booktitle={2024 34th International Conference on Field-Programmable Logic and
Applications (FPL)}, publisher={IEEE}, author={Stachura, Philip and Li, Guanyu
and Wu, Xin and Plessl, Christian and Fang, Zhenman}, year={2024}, pages={60–68}
}'
chicago: 'Stachura, Philip, Guanyu Li, Xin Wu, Christian Plessl, and Zhenman Fang.
“SERI: High-Throughput Streaming Acceleration of Electron Repulsion Integral Computation
in Quantum Chemistry Using HBM-Based FPGAs.” In 2024 34th International Conference
on Field-Programmable Logic and Applications (FPL), 60–68. IEEE, 2024. https://doi.org/10.1109/fpl64840.2024.00018.'
ieee: 'P. Stachura, G. Li, X. Wu, C. Plessl, and Z. Fang, “SERI: High-Throughput
Streaming Acceleration of Electron Repulsion Integral Computation in Quantum Chemistry
using HBM-based FPGAs,” in 2024 34th International Conference on Field-Programmable
Logic and Applications (FPL), 2024, pp. 60–68, doi: 10.1109/fpl64840.2024.00018.'
mla: 'Stachura, Philip, et al. “SERI: High-Throughput Streaming Acceleration of
Electron Repulsion Integral Computation in Quantum Chemistry Using HBM-Based FPGAs.”
2024 34th International Conference on Field-Programmable Logic and Applications
(FPL), IEEE, 2024, pp. 60–68, doi:10.1109/fpl64840.2024.00018.'
short: 'P. Stachura, G. Li, X. Wu, C. Plessl, Z. Fang, in: 2024 34th International
Conference on Field-Programmable Logic and Applications (FPL), IEEE, 2024, pp.
60–68.'
date_created: 2024-10-14T08:44:44Z
date_updated: 2024-10-15T08:37:27Z
department:
- _id: '27'
- _id: '518'
doi: 10.1109/fpl64840.2024.00018
language:
- iso: eng
main_file_link:
- url: https://ieeexplore.ieee.org/document/10705609
page: 60-68
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: 2024 34th International Conference on Field-Programmable Logic and Applications
(FPL)
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: 'SERI: High-Throughput Streaming Acceleration of Electron Repulsion Integral
Computation in Quantum Chemistry using HBM-based FPGAs'
type: conference
user_id: '77439'
year: '2024'
...
---
_id: '62067'
abstract:
- lang: eng
text: Most FPGA boards in the HPC domain are well-suited for parallel scaling because
of the direct integration of versatile and high-throughput network ports. However,
the utilization of their network capabilities is often challenging and error-prone
because the whole network stack and communication patterns have to be implemented
and managed on the FPGAs. Also, this approach conceptually involves a trade-off
between the performance potential of improved communication and the impact of
resource consumption for communication infrastructure, since the utilized resources
on the FPGAs could otherwise be used for computations. In this work, we investigate
this trade-off, firstly, by using synthetic benchmarks to evaluate the different
configuration options of the communication framework ACCL and their impact on
communication latency and throughput. Finally, we use our findings to implement
a shallow water simulation whose scalability heavily depends on low-latency communication.
With a suitable configuration of ACCL, good scaling behavior can be shown to all
48 FPGAs installed in the system. Overall, the results show that the availability
of inter-FPGA communication frameworks as well as the configurability of framework and
network stack are crucial to achieve the best application performance with low
latency communication.
author:
- first_name: Marius
full_name: Meyer, Marius
id: '40778'
last_name: Meyer
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Lucian
full_name: Petrica, Lucian
last_name: Petrica
- first_name: Kenneth
full_name: O’Brien, Kenneth
last_name: O’Brien
- first_name: Michaela
full_name: Blott, Michaela
last_name: Blott
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Meyer M, Kenter T, Petrica L, O’Brien K, Blott M, Plessl C. Optimizing Communication
for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL. In: Lecture
Notes in Computer Science. Springer Nature Switzerland; 2024. doi:10.1007/978-3-031-69766-1_9'
apa: Meyer, M., Kenter, T., Petrica, L., O’Brien, K., Blott, M., & Plessl, C.
(2024). Optimizing Communication for Latency Sensitive HPC Applications on up
to 48 FPGAs Using ACCL. In Lecture Notes in Computer Science. Springer
Nature Switzerland. https://doi.org/10.1007/978-3-031-69766-1_9
bibtex: '@inbook{Meyer_Kenter_Petrica_O’Brien_Blott_Plessl_2024, place={Cham}, title={Optimizing
Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL},
DOI={10.1007/978-3-031-69766-1_9},
booktitle={Lecture Notes in Computer Science}, publisher={Springer Nature Switzerland},
author={Meyer, Marius and Kenter, Tobias and Petrica, Lucian and O’Brien, Kenneth
and Blott, Michaela and Plessl, Christian}, year={2024} }'
chicago: 'Meyer, Marius, Tobias Kenter, Lucian Petrica, Kenneth O’Brien, Michaela
Blott, and Christian Plessl. “Optimizing Communication for Latency Sensitive HPC
Applications on up to 48 FPGAs Using ACCL.” In Lecture Notes in Computer Science.
Cham: Springer Nature Switzerland, 2024. https://doi.org/10.1007/978-3-031-69766-1_9.'
ieee: 'M. Meyer, T. Kenter, L. Petrica, K. O’Brien, M. Blott, and C. Plessl, “Optimizing
Communication for Latency Sensitive HPC Applications on up to 48 FPGAs Using ACCL,”
in Lecture Notes in Computer Science, Cham: Springer Nature Switzerland,
2024.'
mla: Meyer, Marius, et al. “Optimizing Communication for Latency Sensitive HPC Applications
on up to 48 FPGAs Using ACCL.” Lecture Notes in Computer Science, Springer
Nature Switzerland, 2024, doi:10.1007/978-3-031-69766-1_9.
short: 'M. Meyer, T. Kenter, L. Petrica, K. O’Brien, M. Blott, C. Plessl, in: Lecture
Notes in Computer Science, Springer Nature Switzerland, Cham, 2024.'
date_created: 2025-11-04T09:50:24Z
date_updated: 2025-11-04T09:51:22Z
department:
- _id: '27'
- _id: '518'
doi: 10.1007/978-3-031-69766-1_9
language:
- iso: eng
main_file_link:
- open_access: '1'
oa: '1'
place: Cham
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Lecture Notes in Computer Science
publication_identifier:
isbn:
- '9783031697654'
- '9783031697661'
issn:
- 0302-9743
- 1611-3349
publication_status: published
publisher: Springer Nature Switzerland
quality_controlled: '1'
status: public
title: Optimizing Communication for Latency Sensitive HPC Applications on up to 48
FPGAs Using ACCL
type: book_chapter
user_id: '3145'
year: '2024'
...
---
_id: '56604'
abstract:
- lang: eng
text: This manuscript makes the claim of having computed the 9th Dedekind number,
D(9). This was done by accelerating the core operation of the process with an
efficient FPGA design that outperforms an optimized 64-core CPU reference by 95x.
The FPGA execution was parallelized on the Noctua 2 supercomputer at Paderborn
University. The resulting value for D(9) is 286386577668298411128469151667598498812366.
This value can be verified in two steps. We have made the data file containing
the 490 M results available, each of which can be verified separately on CPU,
and the whole file sums to our proposed value. The paper explains the mathematical
approach in the first part, before putting the focus on a deep dive into the FPGA
accelerator implementation followed by a performance analysis. The FPGA implementation
was done in Register-Transfer Level using a dual-clock architecture and shows
how we achieved an impressive FMax of 450 MHz on the targeted Stratix 10 GX 2,800
FPGAs. The total compute time used was 47,000 FPGA hours.
author:
- first_name: Lennart
full_name: Van Hirtum, Lennart
id: '100210'
last_name: Van Hirtum
- first_name: Patrick
full_name: De Causmaecker, Patrick
last_name: De Causmaecker
- first_name: Jens
full_name: Goemaere, Jens
last_name: Goemaere
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Michael
full_name: Lass, Michael
id: '24135'
last_name: Lass
orcid: 0000-0002-5708-7632
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Van Hirtum L, De Causmaecker P, Goemaere J, et al. A Computation of the Ninth
Dedekind Number Using FPGA Supercomputing. ACM Transactions on Reconfigurable
Technology and Systems. 2024;17(3):1-28. doi:10.1145/3674147
apa: Van Hirtum, L., De Causmaecker, P., Goemaere, J., Kenter, T., Riebler, H.,
Lass, M., & Plessl, C. (2024). A Computation of the Ninth Dedekind Number
Using FPGA Supercomputing. ACM Transactions on Reconfigurable Technology and
Systems, 17(3), 1–28. https://doi.org/10.1145/3674147
bibtex: '@article{Van Hirtum_De Causmaecker_Goemaere_Kenter_Riebler_Lass_Plessl_2024,
title={A Computation of the Ninth Dedekind Number Using FPGA Supercomputing},
volume={17}, DOI={10.1145/3674147},
number={3}, journal={ACM Transactions on Reconfigurable Technology and Systems},
publisher={Association for Computing Machinery (ACM)}, author={Van Hirtum, Lennart
and De Causmaecker, Patrick and Goemaere, Jens and Kenter, Tobias and Riebler,
Heinrich and Lass, Michael and Plessl, Christian}, year={2024}, pages={1–28} }'
chicago: 'Van Hirtum, Lennart, Patrick De Causmaecker, Jens Goemaere, Tobias Kenter,
Heinrich Riebler, Michael Lass, and Christian Plessl. “A Computation of the Ninth
Dedekind Number Using FPGA Supercomputing.” ACM Transactions on Reconfigurable
Technology and Systems 17, no. 3 (2024): 1–28. https://doi.org/10.1145/3674147.'
ieee: 'L. Van Hirtum et al., “A Computation of the Ninth Dedekind Number
Using FPGA Supercomputing,” ACM Transactions on Reconfigurable Technology and
Systems, vol. 17, no. 3, pp. 1–28, 2024, doi: 10.1145/3674147.'
mla: Van Hirtum, Lennart, et al. “A Computation of the Ninth Dedekind Number Using
FPGA Supercomputing.” ACM Transactions on Reconfigurable Technology and Systems,
vol. 17, no. 3, Association for Computing Machinery (ACM), 2024, pp. 1–28, doi:10.1145/3674147.
short: L. Van Hirtum, P. De Causmaecker, J. Goemaere, T. Kenter, H. Riebler, M.
Lass, C. Plessl, ACM Transactions on Reconfigurable Technology and Systems 17
(2024) 1–28.
date_created: 2024-10-14T07:38:29Z
date_updated: 2025-11-04T09:53:26Z
department:
- _id: '27'
- _id: '518'
doi: 10.1145/3674147
intvolume: ' 17'
issue: '3'
language:
- iso: eng
main_file_link:
- open_access: '1'
oa: '1'
page: 1-28
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: ACM Transactions on Reconfigurable Technology and Systems
publication_identifier:
issn:
- 1936-7406
- 1936-7414
publication_status: published
publisher: Association for Computing Machinery (ACM)
quality_controlled: '1'
status: public
title: A Computation of the Ninth Dedekind Number Using FPGA Supercomputing
type: journal_article
user_id: '3145'
volume: 17
year: '2024'
...
---
_id: '53503'
author:
- first_name: Kaan
full_name: Olgu, Kaan
last_name: Olgu
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Jose
full_name: Nunez-Yanez, Jose
last_name: Nunez-Yanez
- first_name: Simon
full_name: Mcintosh-Smith, Simon
last_name: Mcintosh-Smith
citation:
ama: 'Olgu K, Kenter T, Nunez-Yanez J, Mcintosh-Smith S. Optimisation and Evaluation
of Breadth First Search with oneAPI/SYCL on Intel FPGAs: from Describing Algorithms
to Describing Architectures. In: Proceedings of the 12th International Workshop
on OpenCL and SYCL. ACM; 2024. doi:10.1145/3648115.3648134'
apa: 'Olgu, K., Kenter, T., Nunez-Yanez, J., & Mcintosh-Smith, S. (2024). Optimisation
and Evaluation of Breadth First Search with oneAPI/SYCL on Intel FPGAs: from Describing
Algorithms to Describing Architectures. Proceedings of the 12th International
Workshop on OpenCL and SYCL. https://doi.org/10.1145/3648115.3648134'
bibtex: '@inproceedings{Olgu_Kenter_Nunez-Yanez_Mcintosh-Smith_2024, title={Optimisation
and Evaluation of Breadth First Search with oneAPI/SYCL on Intel FPGAs: from Describing
Algorithms to Describing Architectures}, DOI={10.1145/3648115.3648134},
booktitle={Proceedings of the 12th International Workshop on OpenCL and SYCL},
publisher={ACM}, author={Olgu, Kaan and Kenter, Tobias and Nunez-Yanez, Jose and
Mcintosh-Smith, Simon}, year={2024} }'
chicago: 'Olgu, Kaan, Tobias Kenter, Jose Nunez-Yanez, and Simon Mcintosh-Smith.
“Optimisation and Evaluation of Breadth First Search with OneAPI/SYCL on Intel
FPGAs: From Describing Algorithms to Describing Architectures.” In Proceedings
of the 12th International Workshop on OpenCL and SYCL. ACM, 2024. https://doi.org/10.1145/3648115.3648134.'
ieee: 'K. Olgu, T. Kenter, J. Nunez-Yanez, and S. Mcintosh-Smith, “Optimisation
and Evaluation of Breadth First Search with oneAPI/SYCL on Intel FPGAs: from Describing
Algorithms to Describing Architectures,” 2024, doi: 10.1145/3648115.3648134.'
mla: 'Olgu, Kaan, et al. “Optimisation and Evaluation of Breadth First Search with
OneAPI/SYCL on Intel FPGAs: From Describing Algorithms to Describing Architectures.”
Proceedings of the 12th International Workshop on OpenCL and SYCL, ACM,
2024, doi:10.1145/3648115.3648134.'
short: 'K. Olgu, T. Kenter, J. Nunez-Yanez, S. Mcintosh-Smith, in: Proceedings of
the 12th International Workshop on OpenCL and SYCL, ACM, 2024.'
date_created: 2024-04-15T07:41:21Z
date_updated: 2025-11-04T09:53:59Z
department:
- _id: '27'
- _id: '518'
doi: 10.1145/3648115.3648134
language:
- iso: eng
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: Proceedings of the 12th International Workshop on OpenCL and SYCL
publication_status: published
publisher: ACM
quality_controlled: '1'
status: public
title: 'Optimisation and Evaluation of Breadth First Search with oneAPI/SYCL on Intel
FPGAs: from Describing Algorithms to Describing Architectures'
type: conference
user_id: '3145'
year: '2024'
...
---
_id: '54312'
article_number: '11'
author:
- first_name: Markus
full_name: Büttner, Markus
last_name: Büttner
- first_name: Christoph
full_name: Alt, Christoph
id: '100625'
last_name: Alt
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Harald
full_name: Köstler, Harald
last_name: Köstler
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Vadym
full_name: Aizinger, Vadym
last_name: Aizinger
citation:
ama: 'Büttner M, Alt C, Kenter T, Köstler H, Plessl C, Aizinger V. Enabling Performance
Portability for Shallow Water Equations on CPUs, GPUs, and FPGAs with SYCL. In:
Proceedings of the Platform for Advanced Scientific Computing Conference (PASC).
ACM; 2024. doi:10.1145/3659914.3659925'
apa: Büttner, M., Alt, C., Kenter, T., Köstler, H., Plessl, C., & Aizinger,
V. (2024). Enabling Performance Portability for Shallow Water Equations on CPUs,
GPUs, and FPGAs with SYCL. Proceedings of the Platform for Advanced Scientific
Computing Conference (PASC), Article 11. https://doi.org/10.1145/3659914.3659925
bibtex: '@inproceedings{Büttner_Alt_Kenter_Köstler_Plessl_Aizinger_2024, title={Enabling
Performance Portability for Shallow Water Equations on CPUs, GPUs, and FPGAs with
SYCL}, DOI={10.1145/3659914.3659925},
number={11}, booktitle={Proceedings of the Platform for Advanced Scientific Computing
Conference (PASC)}, publisher={ACM}, author={Büttner, Markus and Alt, Christoph
and Kenter, Tobias and Köstler, Harald and Plessl, Christian and Aizinger, Vadym},
year={2024} }'
chicago: Büttner, Markus, Christoph Alt, Tobias Kenter, Harald Köstler, Christian
Plessl, and Vadym Aizinger. “Enabling Performance Portability for Shallow Water
Equations on CPUs, GPUs, and FPGAs with SYCL.” In Proceedings of the Platform
for Advanced Scientific Computing Conference (PASC). ACM, 2024. https://doi.org/10.1145/3659914.3659925.
ieee: 'M. Büttner, C. Alt, T. Kenter, H. Köstler, C. Plessl, and V. Aizinger, “Enabling
Performance Portability for Shallow Water Equations on CPUs, GPUs, and FPGAs with
SYCL,” 2024, doi: 10.1145/3659914.3659925.'
mla: Büttner, Markus, et al. “Enabling Performance Portability for Shallow Water
Equations on CPUs, GPUs, and FPGAs with SYCL.” Proceedings of the Platform
for Advanced Scientific Computing Conference (PASC), 11, ACM, 2024, doi:10.1145/3659914.3659925.
short: 'M. Büttner, C. Alt, T. Kenter, H. Köstler, C. Plessl, V. Aizinger, in: Proceedings
of the Platform for Advanced Scientific Computing Conference (PASC), ACM, 2024.'
date_created: 2024-05-16T13:24:49Z
date_updated: 2024-11-27T22:50:19Z
department:
- _id: '27'
- _id: '518'
doi: 10.1145/3659914.3659925
language:
- iso: eng
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: Proceedings of the Platform for Advanced Scientific Computing Conference
(PASC)
publication_status: published
publisher: ACM
quality_controlled: '1'
status: public
title: Enabling Performance Portability for Shallow Water Equations on CPUs, GPUs,
and FPGAs with SYCL
type: conference
user_id: '16153'
year: '2024'
...
---
_id: '43439'
abstract:
- lang: eng
text: "This preprint makes the claim of having computed the $9^{th}$ Dedekind\r\nNumber.
This was done by building an efficient FPGA Accelerator for the core\r\noperation
of the process, and parallelizing it on the Noctua 2 Supercluster at\r\nPaderborn
University. The resulting value is\r\n286386577668298411128469151667598498812366.
This value can be verified in two\r\nsteps. We have made the data file containing
the 490M results available, each\r\nof which can be verified separately on CPU,
and the whole file sums to our\r\nproposed value."
author:
- first_name: Lennart
full_name: Van Hirtum, Lennart
last_name: Van Hirtum
- first_name: Patrick
full_name: De Causmaecker, Patrick
last_name: De Causmaecker
- first_name: Jens
full_name: Goemaere, Jens
last_name: Goemaere
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Michael
full_name: Lass, Michael
id: '24135'
last_name: Lass
orcid: 0000-0002-5708-7632
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Van Hirtum L, De Causmaecker P, Goemaere J, et al. A computation of D(9) using
FPGA Supercomputing. arXiv:230403039. Published online 2023.
apa: Van Hirtum, L., De Causmaecker, P., Goemaere, J., Kenter, T., Riebler, H.,
Lass, M., & Plessl, C. (2023). A computation of D(9) using FPGA Supercomputing.
In arXiv:2304.03039.
bibtex: '@article{Van Hirtum_De Causmaecker_Goemaere_Kenter_Riebler_Lass_Plessl_2023,
title={A computation of D(9) using FPGA Supercomputing}, journal={arXiv:2304.03039},
author={Van Hirtum, Lennart and De Causmaecker, Patrick and Goemaere, Jens and
Kenter, Tobias and Riebler, Heinrich and Lass, Michael and Plessl, Christian},
year={2023} }'
chicago: Van Hirtum, Lennart, Patrick De Causmaecker, Jens Goemaere, Tobias Kenter,
Heinrich Riebler, Michael Lass, and Christian Plessl. “A Computation of D(9) Using
FPGA Supercomputing.” ArXiv:2304.03039, 2023.
ieee: L. Van Hirtum et al., “A computation of D(9) using FPGA Supercomputing,”
arXiv:2304.03039. 2023.
mla: Van Hirtum, Lennart, et al. “A Computation of D(9) Using FPGA Supercomputing.”
ArXiv:2304.03039, 2023.
short: L. Van Hirtum, P. De Causmaecker, J. Goemaere, T. Kenter, H. Riebler, M.
Lass, C. Plessl, ArXiv:2304.03039 (2023).
date_created: 2023-04-08T11:05:29Z
date_updated: 2024-01-22T09:56:42Z
department:
- _id: '27'
- _id: '518'
external_id:
arxiv:
- '2304.03039'
language:
- iso: eng
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: arXiv:2304.03039
status: public
title: A computation of D(9) using FPGA Supercomputing
type: preprint
user_id: '3145'
year: '2023'
...
---
_id: '46188'
author:
- first_name: Jennifer
full_name: Faj, Jennifer
id: '78722'
last_name: Faj
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Sara
full_name: Faghih-Naini, Sara
last_name: Faghih-Naini
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Vadym
full_name: Aizinger, Vadym
last_name: Aizinger
citation:
ama: 'Faj J, Kenter T, Faghih-Naini S, Plessl C, Aizinger V. Scalable Multi-FPGA
Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured Meshes.
In: Proceedings of the Platform for Advanced Scientific Computing Conference
(PASC). ACM; 2023. doi:10.1145/3592979.3593407'
apa: Faj, J., Kenter, T., Faghih-Naini, S., Plessl, C., & Aizinger, V. (2023).
Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on
Unstructured Meshes. Proceedings of the Platform for Advanced Scientific Computing
Conference (PASC). https://doi.org/10.1145/3592979.3593407
bibtex: '@inproceedings{Faj_Kenter_Faghih-Naini_Plessl_Aizinger_2023, title={Scalable
Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured
Meshes}, DOI={10.1145/3592979.3593407},
booktitle={Proceedings of the Platform for Advanced Scientific Computing Conference
(PASC)}, publisher={ACM}, author={Faj, Jennifer and Kenter, Tobias and Faghih-Naini,
Sara and Plessl, Christian and Aizinger, Vadym}, year={2023} }'
chicago: Faj, Jennifer, Tobias Kenter, Sara Faghih-Naini, Christian Plessl, and
Vadym Aizinger. “Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water
Model on Unstructured Meshes.” In Proceedings of the Platform for Advanced
Scientific Computing Conference (PASC). ACM, 2023. https://doi.org/10.1145/3592979.3593407.
ieee: 'J. Faj, T. Kenter, S. Faghih-Naini, C. Plessl, and V. Aizinger, “Scalable
Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured
Meshes,” 2023, doi: 10.1145/3592979.3593407.'
mla: Faj, Jennifer, et al. “Scalable Multi-FPGA Design of a Discontinuous Galerkin
Shallow-Water Model on Unstructured Meshes.” Proceedings of the Platform for
Advanced Scientific Computing Conference (PASC), ACM, 2023, doi:10.1145/3592979.3593407.
short: 'J. Faj, T. Kenter, S. Faghih-Naini, C. Plessl, V. Aizinger, in: Proceedings
of the Platform for Advanced Scientific Computing Conference (PASC), ACM, 2023.'
date_created: 2023-07-28T09:42:14Z
date_updated: 2024-04-17T08:09:39Z
department:
- _id: '27'
- _id: '518'
doi: 10.1145/3592979.3593407
language:
- iso: eng
main_file_link:
- url: https://dl.acm.org/doi/pdf/10.1145/3592979.3593407
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: Proceedings of the Platform for Advanced Scientific Computing Conference
(PASC)
publication_status: published
publisher: ACM
quality_controlled: '1'
related_material:
link:
- description: Open Access available via this link.
relation: other
url: https://www.sighpc.org/for-our-community/acm-open-tocs/pasc23-open-toc
status: public
title: Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model
on Unstructured Meshes
type: conference
user_id: '3145'
year: '2023'
...
---
_id: '46189'
author:
- first_name: Charles
full_name: Prouveur, Charles
last_name: Prouveur
- first_name: Matthieu
full_name: Haefele, Matthieu
last_name: Haefele
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Nils
full_name: Voss, Nils
last_name: Voss
citation:
ama: 'Prouveur C, Haefele M, Kenter T, Voss N. FPGA Acceleration for HPC Supercapacitor
Simulations. In: Proceedings of the Platform for Advanced Scientific Computing
Conference (PASC). ACM; 2023. doi:10.1145/3592979.3593419'
apa: Prouveur, C., Haefele, M., Kenter, T., & Voss, N. (2023). FPGA Acceleration
for HPC Supercapacitor Simulations. Proceedings of the Platform for Advanced
Scientific Computing Conference (PASC). https://doi.org/10.1145/3592979.3593419
bibtex: '@inproceedings{Prouveur_Haefele_Kenter_Voss_2023, title={FPGA Acceleration
for HPC Supercapacitor Simulations}, DOI={10.1145/3592979.3593419},
booktitle={Proceedings of the Platform for Advanced Scientific Computing Conference
(PASC)}, publisher={ACM}, author={Prouveur, Charles and Haefele, Matthieu and
Kenter, Tobias and Voss, Nils}, year={2023} }'
chicago: Prouveur, Charles, Matthieu Haefele, Tobias Kenter, and Nils Voss. “FPGA
Acceleration for HPC Supercapacitor Simulations.” In Proceedings of the Platform
for Advanced Scientific Computing Conference (PASC). ACM, 2023. https://doi.org/10.1145/3592979.3593419.
ieee: 'C. Prouveur, M. Haefele, T. Kenter, and N. Voss, “FPGA Acceleration for HPC
Supercapacitor Simulations,” 2023, doi: 10.1145/3592979.3593419.'
mla: Prouveur, Charles, et al. “FPGA Acceleration for HPC Supercapacitor Simulations.”
Proceedings of the Platform for Advanced Scientific Computing Conference (PASC),
ACM, 2023, doi:10.1145/3592979.3593419.
short: 'C. Prouveur, M. Haefele, T. Kenter, N. Voss, in: Proceedings of the Platform
for Advanced Scientific Computing Conference (PASC), ACM, 2023.'
date_created: 2023-07-28T09:46:25Z
date_updated: 2024-04-17T08:10:51Z
department:
- _id: '27'
- _id: '518'
doi: 10.1145/3592979.3593419
language:
- iso: eng
main_file_link:
- url: https://dl.acm.org/doi/pdf/10.1145/3592979.3593419
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: Proceedings of the Platform for Advanced Scientific Computing Conference
(PASC)
publication_status: published
publisher: ACM
quality_controlled: '1'
related_material:
link:
- description: Open Access available via this link.
relation: other
url: ' https://www.sighpc.org/for-our-community/acm-open-tocs/pasc23-open-toc '
status: public
title: FPGA Acceleration for HPC Supercapacitor Simulations
type: conference
user_id: '3145'
year: '2023'
...
---
_id: '45893'
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Marius
full_name: Meyer, Marius
id: '40778'
last_name: Meyer
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Hansmeier T, Kenter T, Meyer M, Riebler H, Platzner M, Plessl C. Compute Centers
I: Heterogeneous Execution Environments. In: Haake C-J, Meyer auf der Heide F,
Platzner M, Wachsmuth H, Wehrheim H, eds. On-The-Fly Computing -- Individualized
IT-Services in Dynamic Markets. Vol 412. Verlagsschriftenreihe des Heinz Nixdorf
Instituts. Heinz Nixdorf Institut, Universität Paderborn; 2023:165-182. doi:10.5281/zenodo.8068642'
apa: 'Hansmeier, T., Kenter, T., Meyer, M., Riebler, H., Platzner, M., & Plessl,
C. (2023). Compute Centers I: Heterogeneous Execution Environments. In C.-J. Haake,
F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, & H. Wehrheim (Eds.), On-The-Fly
Computing -- Individualized IT-services in dynamic markets (Vol. 412, pp.
165–182). Heinz Nixdorf Institut, Universität Paderborn. https://doi.org/10.5281/zenodo.8068642'
bibtex: '@inbook{Hansmeier_Kenter_Meyer_Riebler_Platzner_Plessl_2023, place={Paderborn},
series={Verlagsschriftenreihe des Heinz Nixdorf Instituts}, title={Compute Centers
I: Heterogeneous Execution Environments}, volume={412}, DOI={10.5281/zenodo.8068642},
booktitle={On-The-Fly Computing -- Individualized IT-services in dynamic markets},
publisher={Heinz Nixdorf Institut, Universität Paderborn}, author={Hansmeier,
Tim and Kenter, Tobias and Meyer, Marius and Riebler, Heinrich and Platzner, Marco
and Plessl, Christian}, editor={Haake, Claus-Jochen and Meyer auf der Heide, Friedhelm
and Platzner, Marco and Wachsmuth, Henning and Wehrheim, Heike}, year={2023},
pages={165–182}, collection={Verlagsschriftenreihe des Heinz Nixdorf Instituts}
}'
chicago: 'Hansmeier, Tim, Tobias Kenter, Marius Meyer, Heinrich Riebler, Marco Platzner,
and Christian Plessl. “Compute Centers I: Heterogeneous Execution Environments.”
In On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets,
edited by Claus-Jochen Haake, Friedhelm Meyer auf der Heide, Marco Platzner, Henning
Wachsmuth, and Heike Wehrheim, 412:165–82. Verlagsschriftenreihe Des Heinz Nixdorf
Instituts. Paderborn: Heinz Nixdorf Institut, Universität Paderborn, 2023. https://doi.org/10.5281/zenodo.8068642.'
ieee: 'T. Hansmeier, T. Kenter, M. Meyer, H. Riebler, M. Platzner, and C. Plessl,
“Compute Centers I: Heterogeneous Execution Environments,” in On-The-Fly Computing
-- Individualized IT-services in dynamic markets, vol. 412, C.-J. Haake, F.
Meyer auf der Heide, M. Platzner, H. Wachsmuth, and H. Wehrheim, Eds. Paderborn:
Heinz Nixdorf Institut, Universität Paderborn, 2023, pp. 165–182.'
mla: 'Hansmeier, Tim, et al. “Compute Centers I: Heterogeneous Execution Environments.”
On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets,
edited by Claus-Jochen Haake et al., vol. 412, Heinz Nixdorf Institut, Universität
Paderborn, 2023, pp. 165–82, doi:10.5281/zenodo.8068642.'
short: 'T. Hansmeier, T. Kenter, M. Meyer, H. Riebler, M. Platzner, C. Plessl, in:
C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, H. Wehrheim (Eds.),
On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets, Heinz Nixdorf
Institut, Universität Paderborn, Paderborn, 2023, pp. 165–182.'
date_created: 2023-07-07T08:15:45Z
date_updated: 2024-05-02T10:33:00Z
ddc:
- '004'
department:
- _id: '7'
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.5281/zenodo.8068642
editor:
- first_name: Claus-Jochen
full_name: Haake, Claus-Jochen
last_name: Haake
- first_name: Friedhelm
full_name: Meyer auf der Heide, Friedhelm
last_name: Meyer auf der Heide
- first_name: Marco
full_name: Platzner, Marco
last_name: Platzner
- first_name: Henning
full_name: Wachsmuth, Henning
last_name: Wachsmuth
- first_name: Heike
full_name: Wehrheim, Heike
last_name: Wehrheim
file:
- access_level: open_access
content_type: application/pdf
creator: florida
date_created: 2023-07-07T08:15:35Z
date_updated: 2023-07-07T11:17:33Z
file_id: '45894'
file_name: C2-Chapter-SFB-Buch-Final.pdf
file_size: 2288788
relation: main_file
file_date_updated: 2023-07-07T11:17:33Z
has_accepted_license: '1'
intvolume: ' 412'
language:
- iso: eng
oa: '1'
page: 165-182
place: Paderborn
project:
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
- _id: '4'
name: 'SFB 901 - C: SFB 901 - Project Area C'
- _id: '14'
grant_number: '160364472'
name: 'SFB 901 - C2: SFB 901 - On-The-Fly Compute Centers I: Heterogene Ausführungsumgebungen
(Subproject C2)'
publication: On-The-Fly Computing -- Individualized IT-services in dynamic markets
publisher: Heinz Nixdorf Institut, Universität Paderborn
series_title: Verlagsschriftenreihe des Heinz Nixdorf Instituts
status: public
title: 'Compute Centers I: Heterogeneous Execution Environments'
type: book_chapter
user_id: '398'
volume: 412
year: '2023'
...
---
_id: '38041'
abstract:
- lang: eng
text: "While FPGA accelerator boards and their respective high-level design
tools are maturing, there is still a lack of multi-FPGA applications, libraries,
and not least, benchmarks and reference implementations towards sustained HPC
usage of these devices. As in the early days of GPUs in HPC, for workloads that
can reasonably be decoupled into loosely coupled working sets, multi-accelerator
support can be achieved by using standard communication interfaces like MPI on
the host side. However, for performance and productivity, some applications can
profit from a tighter coupling of the accelerators. FPGAs offer unique opportunities
here when extending the dataflow characteristics to their communication interfaces.\r\n
\ In this work, we extend the HPCC FPGA benchmark suite by multi-FPGA
support and three missing benchmarks that particularly characterize or stress
inter-device communication: b_eff, PTRANS, and LINPACK. With all benchmarks implemented
for current boards with Intel and Xilinx FPGAs, we established a baseline for
multi-FPGA performance. Additionally, for the communication-centric benchmarks,
we explored the potential of direct FPGA-to-FPGA communication with a circuit-switched
inter-FPGA network that is currently only available for one of the boards. The
evaluation with parallel execution on up to 26 FPGA boards makes use of one of
the largest academic FPGA installations."
author:
- first_name: Marius
full_name: Meyer, Marius
id: '40778'
last_name: Meyer
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Meyer M, Kenter T, Plessl C. Multi-FPGA Designs and Scaling of HPC Challenge
Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks. ACM Transactions
on Reconfigurable Technology and Systems. Published online 2023. doi:10.1145/3576200
apa: Meyer, M., Kenter, T., & Plessl, C. (2023). Multi-FPGA Designs and Scaling
of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks.
ACM Transactions on Reconfigurable Technology and Systems. https://doi.org/10.1145/3576200
bibtex: '@article{Meyer_Kenter_Plessl_2023, title={Multi-FPGA Designs and Scaling
of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks},
DOI={10.1145/3576200}, journal={ACM
Transactions on Reconfigurable Technology and Systems}, publisher={Association
for Computing Machinery (ACM)}, author={Meyer, Marius and Kenter, Tobias and Plessl,
Christian}, year={2023} }'
chicago: Meyer, Marius, Tobias Kenter, and Christian Plessl. “Multi-FPGA Designs
and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA
Networks.” ACM Transactions on Reconfigurable Technology and Systems, 2023.
https://doi.org/10.1145/3576200.
ieee: 'M. Meyer, T. Kenter, and C. Plessl, “Multi-FPGA Designs and Scaling of HPC
Challenge Benchmarks via MPI and Circuit-Switched Inter-FPGA Networks,” ACM
Transactions on Reconfigurable Technology and Systems, 2023, doi: 10.1145/3576200.'
mla: Meyer, Marius, et al. “Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks
via MPI and Circuit-Switched Inter-FPGA Networks.” ACM Transactions on Reconfigurable
Technology and Systems, Association for Computing Machinery (ACM), 2023, doi:10.1145/3576200.
short: M. Meyer, T. Kenter, C. Plessl, ACM Transactions on Reconfigurable Technology
and Systems (2023).
date_created: 2023-01-23T08:40:42Z
date_updated: 2023-07-28T08:02:05Z
department:
- _id: '27'
- _id: '518'
doi: 10.1145/3576200
keyword:
- General Computer Science
language:
- iso: eng
main_file_link:
- open_access: '1'
url: https://dl.acm.org/doi/10.1145/3576200
oa: '1'
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
- _id: '4'
name: 'SFB 901 - C: SFB 901 - Project Area C'
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901'
- _id: '14'
grant_number: '160364472'
name: 'SFB 901 - C2: SFB 901 - Subproject C2'
publication: ACM Transactions on Reconfigurable Technology and Systems
publication_identifier:
issn:
- 1936-7406
- 1936-7414
publication_status: published
publisher: Association for Computing Machinery (ACM)
quality_controlled: '1'
status: public
title: Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-Switched
Inter-FPGA Networks
type: journal_article
user_id: '24135'
year: '2023'
...
---
_id: '43228'
abstract:
- lang: eng
text: "The computation of electron repulsion integrals (ERIs) over Gaussian-type
orbitals (GTOs) is a challenging problem in quantum-mechanics-based atomistic
simulations. In practical simulations, several trillions of ERIs may have to be\r\ncomputed
for every time step.\r\nIn this work, we investigate FPGAs as accelerators for
the ERI computation. We use template parameters, here within the Intel oneAPI
tool flow, to create customized designs for 256 different ERI quartet classes,
based on their orbitals. To maximize data reuse, all intermediates are buffered
in FPGA on-chip memory with customized layout. The pre-calculation of intermediates
also helps to overcome data dependencies caused by multi-dimensional recurrence\r\nrelations.
The involved loop structures are partially or even fully unrolled for high throughput
of FPGA kernels. Furthermore, a lossy compression algorithm utilizing arbitrary
bitwidth integers is integrated in the FPGA kernels. To our\r\nbest knowledge,
this is the first work on ERI computation on FPGAs that supports more than just
the single most basic quartet class. Also, the integration of ERI computation
and compression it a novelty that is not even covered by CPU or GPU libraries
so far.\r\nOur evaluation shows that using 16-bit integer for the ERI compression,
the fastest FPGA kernels exceed the performance of 10 GERIS ($10 \\times 10^9$
ERIs per second) on one Intel Stratix 10 GX 2800 FPGA, with maximum absolute errors
around $10^{-7}$ - $10^{-5}$ Hartree. The measured throughput can be accurately
explained by a performance model. The FPGA kernels deployed on 2 FPGAs outperform
similar computations using the widely used libint reference on a two-socket server
with 40 Xeon Gold 6148 CPU cores of the same process technology by factors up
to 6.0x and on a new two-socket server with 128 EPYC 7713 CPU cores by up to 1.9x."
author:
- first_name: Xin
full_name: Wu, Xin
id: '77439'
last_name: Wu
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Robert
full_name: Schade, Robert
id: '75963'
last_name: Schade
orcid: 0000-0002-6268-539
- first_name: Thomas
full_name: Kühne, Thomas
id: '49079'
last_name: Kühne
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Wu X, Kenter T, Schade R, Kühne T, Plessl C. Computing and Compressing Electron
Repulsion Integrals on FPGAs. In: 2023 IEEE 31st Annual International Symposium
on Field-Programmable Custom Computing Machines (FCCM). ; 2023:162-173. doi:10.1109/FCCM57271.2023.00026'
apa: Wu, X., Kenter, T., Schade, R., Kühne, T., & Plessl, C. (2023). Computing
and Compressing Electron Repulsion Integrals on FPGAs. 2023 IEEE 31st Annual
International Symposium on Field-Programmable Custom Computing Machines (FCCM),
162–173. https://doi.org/10.1109/FCCM57271.2023.00026
bibtex: '@inproceedings{Wu_Kenter_Schade_Kühne_Plessl_2023, title={Computing and
Compressing Electron Repulsion Integrals on FPGAs}, DOI={10.1109/FCCM57271.2023.00026},
booktitle={2023 IEEE 31st Annual International Symposium on Field-Programmable
Custom Computing Machines (FCCM)}, author={Wu, Xin and Kenter, Tobias and Schade,
Robert and Kühne, Thomas and Plessl, Christian}, year={2023}, pages={162–173}
}'
chicago: Wu, Xin, Tobias Kenter, Robert Schade, Thomas Kühne, and Christian Plessl.
“Computing and Compressing Electron Repulsion Integrals on FPGAs.” In 2023
IEEE 31st Annual International Symposium on Field-Programmable Custom Computing
Machines (FCCM), 162–73, 2023. https://doi.org/10.1109/FCCM57271.2023.00026.
ieee: 'X. Wu, T. Kenter, R. Schade, T. Kühne, and C. Plessl, “Computing and Compressing
Electron Repulsion Integrals on FPGAs,” in 2023 IEEE 31st Annual International
Symposium on Field-Programmable Custom Computing Machines (FCCM), 2023, pp.
162–173, doi: 10.1109/FCCM57271.2023.00026.'
mla: Wu, Xin, et al. “Computing and Compressing Electron Repulsion Integrals on
FPGAs.” 2023 IEEE 31st Annual International Symposium on Field-Programmable
Custom Computing Machines (FCCM), 2023, pp. 162–73, doi:10.1109/FCCM57271.2023.00026.
short: 'X. Wu, T. Kenter, R. Schade, T. Kühne, C. Plessl, in: 2023 IEEE 31st Annual
International Symposium on Field-Programmable Custom Computing Machines (FCCM),
2023, pp. 162–173.'
date_created: 2023-03-30T11:15:40Z
date_updated: 2023-08-02T15:05:42Z
department:
- _id: '27'
- _id: '518'
doi: 10.1109/FCCM57271.2023.00026
external_id:
arxiv:
- '2303.13632'
language:
- iso: eng
main_file_link:
- url: https://ieeexplore.ieee.org/document/10171537
page: 162-173
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom
Computing Machines (FCCM)
quality_controlled: '1'
status: public
title: Computing and Compressing Electron Repulsion Integrals on FPGAs
type: conference
user_id: '75963'
year: '2023'
...
---
_id: '45361'
abstract:
- lang: eng
text: The non-orthogonal local submatrix method applied to electronic structure–based
molecular dynamics simulations is shown to exceed 1.1 EFLOP/s in FP16/FP32-mixed
floating-point arithmetic when using 4400 NVIDIA A100 GPUs of the Perlmutter system.
This is enabled by a modification of the original method that pushes the sustained
fraction of the peak performance to about 80%. Example calculations are performed
for SARS-CoV-2 spike proteins with up to 83 million atoms.
article_number: '109434202311776'
article_type: original
author:
- first_name: Robert
full_name: Schade, Robert
id: '75963'
last_name: Schade
orcid: 0000-0002-6268-539
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Hossam
full_name: Elgabarty, Hossam
id: '60250'
last_name: Elgabarty
orcid: 0000-0002-4945-1481
- first_name: Michael
full_name: Lass, Michael
id: '24135'
last_name: Lass
orcid: 0000-0002-5708-7632
- first_name: Thomas
full_name: Kühne, Thomas
id: '49079'
last_name: Kühne
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Schade R, Kenter T, Elgabarty H, Lass M, Kühne T, Plessl C. Breaking the exascale
barrier for the electronic structure problem in ab-initio molecular dynamics.
The International Journal of High Performance Computing Applications. Published
online 2023. doi:10.1177/10943420231177631
apa: Schade, R., Kenter, T., Elgabarty, H., Lass, M., Kühne, T., & Plessl, C.
(2023). Breaking the exascale barrier for the electronic structure problem in
ab-initio molecular dynamics. The International Journal of High Performance
Computing Applications, Article 109434202311776. https://doi.org/10.1177/10943420231177631
bibtex: '@article{Schade_Kenter_Elgabarty_Lass_Kühne_Plessl_2023, title={Breaking
the exascale barrier for the electronic structure problem in ab-initio molecular
dynamics}, DOI={10.1177/10943420231177631},
number={109434202311776}, journal={The International Journal of High Performance
Computing Applications}, publisher={SAGE Publications}, author={Schade, Robert
and Kenter, Tobias and Elgabarty, Hossam and Lass, Michael and Kühne, Thomas and
Plessl, Christian}, year={2023} }'
chicago: Schade, Robert, Tobias Kenter, Hossam Elgabarty, Michael Lass, Thomas Kühne,
and Christian Plessl. “Breaking the Exascale Barrier for the Electronic Structure
Problem in Ab-Initio Molecular Dynamics.” The International Journal of High
Performance Computing Applications, 2023. https://doi.org/10.1177/10943420231177631.
ieee: 'R. Schade, T. Kenter, H. Elgabarty, M. Lass, T. Kühne, and C. Plessl, “Breaking
the exascale barrier for the electronic structure problem in ab-initio molecular
dynamics,” The International Journal of High Performance Computing Applications,
Art. no. 109434202311776, 2023, doi: 10.1177/10943420231177631.'
mla: Schade, Robert, et al. “Breaking the Exascale Barrier for the Electronic Structure
Problem in Ab-Initio Molecular Dynamics.” The International Journal of High
Performance Computing Applications, 109434202311776, SAGE Publications, 2023,
doi:10.1177/10943420231177631.
short: R. Schade, T. Kenter, H. Elgabarty, M. Lass, T. Kühne, C. Plessl, The International
Journal of High Performance Computing Applications (2023).
date_created: 2023-05-30T09:19:09Z
date_updated: 2023-08-02T15:04:53Z
department:
- _id: '27'
- _id: '518'
doi: 10.1177/10943420231177631
keyword:
- Hardware and Architecture
- Theoretical Computer Science
- Software
language:
- iso: eng
main_file_link:
- open_access: '1'
url: https://journals.sagepub.com/doi/10.1177/10943420231177631
oa: '1'
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: The International Journal of High Performance Computing Applications
publication_identifier:
issn:
- 1094-3420
- 1741-2846
publication_status: published
publisher: SAGE Publications
quality_controlled: '1'
status: public
title: Breaking the exascale barrier for the electronic structure problem in ab-initio
molecular dynamics
type: journal_article
user_id: '75963'
year: '2023'
...
---
_id: '46191'
author:
- first_name: Christoph
full_name: Alt, Christoph
id: '100625'
last_name: Alt
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Sara
full_name: Faghih-Naini, Sara
last_name: Faghih-Naini
- first_name: Jennifer
full_name: Faj, Jennifer
id: '78722'
last_name: Faj
- first_name: Jan-Oliver
full_name: Opdenhövel, Jan-Oliver
id: '73960'
last_name: Opdenhövel
orcid: 0000-0003-2314-2784
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Vadym
full_name: Aizinger, Vadym
last_name: Aizinger
- first_name: Jan
full_name: Hönig, Jan
last_name: Hönig
- first_name: Harald
full_name: Köstler, Harald
last_name: Köstler
citation:
ama: 'Alt C, Kenter T, Faghih-Naini S, et al. Shallow Water DG Simulations on FPGAs:
Design and Comparison of a Novel Code Generation Pipeline. In: Lecture Notes
in Computer Science. Springer Nature Switzerland; 2023. doi:10.1007/978-3-031-32041-5_5'
apa: 'Alt, C., Kenter, T., Faghih-Naini, S., Faj, J., Opdenhövel, J.-O., Plessl,
C., Aizinger, V., Hönig, J., & Köstler, H. (2023). Shallow Water DG Simulations
on FPGAs: Design and Comparison of a Novel Code Generation Pipeline. In Lecture
Notes in Computer Science. Springer Nature Switzerland. https://doi.org/10.1007/978-3-031-32041-5_5'
bibtex: '@inbook{Alt_Kenter_Faghih-Naini_Faj_Opdenhövel_Plessl_Aizinger_Hönig_Köstler_2023,
place={Cham}, title={Shallow Water DG Simulations on FPGAs: Design and Comparison
of a Novel Code Generation Pipeline}, DOI={10.1007/978-3-031-32041-5_5},
booktitle={Lecture Notes in Computer Science}, publisher={Springer Nature Switzerland},
author={Alt, Christoph and Kenter, Tobias and Faghih-Naini, Sara and Faj, Jennifer
and Opdenhövel, Jan-Oliver and Plessl, Christian and Aizinger, Vadym and Hönig,
Jan and Köstler, Harald}, year={2023} }'
chicago: 'Alt, Christoph, Tobias Kenter, Sara Faghih-Naini, Jennifer Faj, Jan-Oliver
Opdenhövel, Christian Plessl, Vadym Aizinger, Jan Hönig, and Harald Köstler. “Shallow
Water DG Simulations on FPGAs: Design and Comparison of a Novel Code Generation
Pipeline.” In Lecture Notes in Computer Science. Cham: Springer Nature
Switzerland, 2023. https://doi.org/10.1007/978-3-031-32041-5_5.'
ieee: 'C. Alt et al., “Shallow Water DG Simulations on FPGAs: Design and Comparison
of a Novel Code Generation Pipeline,” in Lecture Notes in Computer Science,
Cham: Springer Nature Switzerland, 2023.'
mla: 'Alt, Christoph, et al. “Shallow Water DG Simulations on FPGAs: Design and Comparison
of a Novel Code Generation Pipeline.” Lecture Notes in Computer Science,
Springer Nature Switzerland, 2023, doi:10.1007/978-3-031-32041-5_5.'
short: 'C. Alt, T. Kenter, S. Faghih-Naini, J. Faj, J.-O. Opdenhövel, C. Plessl,
V. Aizinger, J. Hönig, H. Köstler, in: Lecture Notes in Computer Science, Springer
Nature Switzerland, Cham, 2023.'
date_created: 2023-07-28T09:53:21Z
date_updated: 2025-11-04T09:32:49Z
department:
- _id: '27'
- _id: '518'
doi: 10.1007/978-3-031-32041-5_5
language:
- iso: eng
place: Cham
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: Lecture Notes in Computer Science
publication_identifier:
isbn:
- '9783031320408'
- '9783031320415'
issn:
- 0302-9743
- 1611-3349
publication_status: published
publisher: Springer Nature Switzerland
quality_controlled: '1'
status: public
title: 'Shallow Water DG Simulations on FPGAs: Design and Comparison of a Novel Code
Generation Pipeline'
type: book_chapter
user_id: '3145'
year: '2023'
...
---
_id: '46190'
author:
- first_name: Jan-Oliver
full_name: Opdenhövel, Jan-Oliver
id: '73960'
last_name: Opdenhövel
orcid: 0000-0003-2314-2784
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
citation:
ama: 'Opdenhövel J-O, Plessl C, Kenter T. Mutation Tree Reconstruction of Tumor
Cells on FPGAs Using a Bit-Level Matrix Representation. In: Proceedings of
the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable
Technologies (HEART). ACM; 2023. doi:10.1145/3597031.3597050'
apa: Opdenhövel, J.-O., Plessl, C., & Kenter, T. (2023). Mutation Tree Reconstruction
of Tumor Cells on FPGAs Using a Bit-Level Matrix Representation. Proceedings
of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable
Technologies (HEART). https://doi.org/10.1145/3597031.3597050
bibtex: '@inproceedings{Opdenhövel_Plessl_Kenter_2023, title={Mutation Tree Reconstruction
of Tumor Cells on FPGAs Using a Bit-Level Matrix Representation}, DOI={10.1145/3597031.3597050},
booktitle={Proceedings of the 13th International Symposium on Highly Efficient
Accelerators and Reconfigurable Technologies (HEART)}, publisher={ACM}, author={Opdenhövel,
Jan-Oliver and Plessl, Christian and Kenter, Tobias}, year={2023} }'
chicago: Opdenhövel, Jan-Oliver, Christian Plessl, and Tobias Kenter. “Mutation
Tree Reconstruction of Tumor Cells on FPGAs Using a Bit-Level Matrix Representation.”
In Proceedings of the 13th International Symposium on Highly Efficient Accelerators
and Reconfigurable Technologies (HEART). ACM, 2023. https://doi.org/10.1145/3597031.3597050.
ieee: 'J.-O. Opdenhövel, C. Plessl, and T. Kenter, “Mutation Tree Reconstruction
of Tumor Cells on FPGAs Using a Bit-Level Matrix Representation,” 2023, doi: 10.1145/3597031.3597050.'
mla: Opdenhövel, Jan-Oliver, et al. “Mutation Tree Reconstruction of Tumor Cells
on FPGAs Using a Bit-Level Matrix Representation.” Proceedings of the 13th
International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies
(HEART), ACM, 2023, doi:10.1145/3597031.3597050.
short: 'J.-O. Opdenhövel, C. Plessl, T. Kenter, in: Proceedings of the 13th International
Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART),
ACM, 2023.'
date_created: 2023-07-28T09:49:23Z
date_updated: 2025-11-04T09:32:30Z
department:
- _id: '27'
- _id: '518'
doi: 10.1145/3597031.3597050
language:
- iso: eng
main_file_link:
- open_access: '1'
url: https://dl.acm.org/doi/pdf/10.1145/3597031.3597050
oa: '1'
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: Proceedings of the 13th International Symposium on Highly Efficient Accelerators
and Reconfigurable Technologies (HEART)
publication_status: published
publisher: ACM
quality_controlled: '1'
status: public
title: Mutation Tree Reconstruction of Tumor Cells on FPGAs Using a Bit-Level Matrix
Representation
type: conference
user_id: '3145'
year: '2023'
...
---
_id: '32414'
author:
- first_name: Michael
full_name: Lass, Michael
id: '24135'
last_name: Lass
orcid: 0000-0002-5708-7632
citation:
ama: Lass M. Bringing Massive Parallelism and Hardware Acceleration to Linear
Scaling Density Functional Theory Through Targeted Approximations. Universität
Paderborn; 2022. doi:10.17619/UNIPB/1-1281
apa: Lass, M. (2022). Bringing Massive Parallelism and Hardware Acceleration
to Linear Scaling Density Functional Theory Through Targeted Approximations.
Universität Paderborn. https://doi.org/10.17619/UNIPB/1-1281
bibtex: '@book{Lass_2022, place={Paderborn}, title={Bringing Massive Parallelism
and Hardware Acceleration to Linear Scaling Density Functional Theory Through
Targeted Approximations}, DOI={10.17619/UNIPB/1-1281},
publisher={Universität Paderborn}, author={Lass, Michael}, year={2022} }'
chicago: 'Lass, Michael. Bringing Massive Parallelism and Hardware Acceleration
to Linear Scaling Density Functional Theory Through Targeted Approximations.
Paderborn: Universität Paderborn, 2022. https://doi.org/10.17619/UNIPB/1-1281.'
ieee: 'M. Lass, Bringing Massive Parallelism and Hardware Acceleration to Linear
Scaling Density Functional Theory Through Targeted Approximations. Paderborn:
Universität Paderborn, 2022.'
mla: Lass, Michael. Bringing Massive Parallelism and Hardware Acceleration to
Linear Scaling Density Functional Theory Through Targeted Approximations.
Universität Paderborn, 2022, doi:10.17619/UNIPB/1-1281.
short: M. Lass, Bringing Massive Parallelism and Hardware Acceleration to Linear
Scaling Density Functional Theory Through Targeted Approximations, Universität
Paderborn, Paderborn, 2022.
date_created: 2022-07-25T18:13:51Z
date_updated: 2022-07-25T18:14:23Z
department:
- _id: '27'
- _id: '518'
doi: 10.17619/UNIPB/1-1281
language:
- iso: eng
place: Paderborn
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
title: Bringing Massive Parallelism and Hardware Acceleration to Linear Scaling Density
Functional Theory Through Targeted Approximations
type: dissertation
user_id: '24135'
year: '2022'
...
---
_id: '33493'
abstract:
- lang: eng
text: "Electronic structure calculations have been instrumental in providing many\r\nimportant
insights into a range of physical and chemical properties of various\r\nmolecular
and solid-state systems. Their importance to various fields,\r\nincluding materials
science, chemical sciences, computational chemistry and\r\ndevice physics, is
underscored by the large fraction of available public\r\nsupercomputing resources
devoted to these calculations. As we enter the\r\nexascale era, exciting new opportunities
to increase simulation numbers, sizes,\r\nand accuracies present themselves. In
order to realize these promises, the\r\ncommunity of electronic structure software
developers will however first have\r\nto tackle a number of challenges pertaining
to the efficient use of new\r\narchitectures that will rely heavily on massive
parallelism and hardware\r\naccelerators. This roadmap provides a broad overview
of the state-of-the-art in\r\nelectronic structure calculations and of the various
new directions being\r\npursued by the community. It covers 14 electronic structure
codes, presenting\r\ntheir current status, their development priorities over the
next five years,\r\nand their plans towards tackling the challenges and leveraging
the\r\nopportunities presented by the advent of exascale computing."
author:
- first_name: Vikram
full_name: Gavini, Vikram
last_name: Gavini
- first_name: Stefano
full_name: Baroni, Stefano
last_name: Baroni
- first_name: Volker
full_name: Blum, Volker
last_name: Blum
- first_name: David R.
full_name: Bowler, David R.
last_name: Bowler
- first_name: Alexander
full_name: Buccheri, Alexander
last_name: Buccheri
- first_name: James R.
full_name: Chelikowsky, James R.
last_name: Chelikowsky
- first_name: Sambit
full_name: Das, Sambit
last_name: Das
- first_name: William
full_name: Dawson, William
last_name: Dawson
- first_name: Pietro
full_name: Delugas, Pietro
last_name: Delugas
- first_name: Mehmet
full_name: Dogan, Mehmet
last_name: Dogan
- first_name: Claudia
full_name: Draxl, Claudia
last_name: Draxl
- first_name: Giulia
full_name: Galli, Giulia
last_name: Galli
- first_name: Luigi
full_name: Genovese, Luigi
last_name: Genovese
- first_name: Paolo
full_name: Giannozzi, Paolo
last_name: Giannozzi
- first_name: Matteo
full_name: Giantomassi, Matteo
last_name: Giantomassi
- first_name: Xavier
full_name: Gonze, Xavier
last_name: Gonze
- first_name: Marco
full_name: Govoni, Marco
last_name: Govoni
- first_name: Andris
full_name: Gulans, Andris
last_name: Gulans
- first_name: François
full_name: Gygi, François
last_name: Gygi
- first_name: John M.
full_name: Herbert, John M.
last_name: Herbert
- first_name: Sebastian
full_name: Kokott, Sebastian
last_name: Kokott
- first_name: Thomas
full_name: Kühne, Thomas
id: '49079'
last_name: Kühne
- first_name: Kai-Hsin
full_name: Liou, Kai-Hsin
last_name: Liou
- first_name: Tsuyoshi
full_name: Miyazaki, Tsuyoshi
last_name: Miyazaki
- first_name: Phani
full_name: Motamarri, Phani
last_name: Motamarri
- first_name: Ayako
full_name: Nakata, Ayako
last_name: Nakata
- first_name: John E.
full_name: Pask, John E.
last_name: Pask
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Laura E.
full_name: Ratcliff, Laura E.
last_name: Ratcliff
- first_name: Ryan M.
full_name: Richard, Ryan M.
last_name: Richard
- first_name: Mariana
full_name: Rossi, Mariana
last_name: Rossi
- first_name: Robert
full_name: Schade, Robert
id: '75963'
last_name: Schade
orcid: 0000-0002-6268-539
- first_name: Matthias
full_name: Scheffler, Matthias
last_name: Scheffler
- first_name: Ole
full_name: Schütt, Ole
last_name: Schütt
- first_name: Phanish
full_name: Suryanarayana, Phanish
last_name: Suryanarayana
- first_name: Marc
full_name: Torrent, Marc
last_name: Torrent
- first_name: Lionel
full_name: Truflandier, Lionel
last_name: Truflandier
- first_name: Theresa L.
full_name: Windus, Theresa L.
last_name: Windus
- first_name: Qimen
full_name: Xu, Qimen
last_name: Xu
- first_name: Victor W. -Z.
full_name: Yu, Victor W. -Z.
last_name: Yu
- first_name: Danny
full_name: Perez, Danny
last_name: Perez
citation:
ama: Gavini V, Baroni S, Blum V, et al. Roadmap on Electronic Structure Codes in
the Exascale Era. arXiv:220912747. Published online 2022.
apa: Gavini, V., Baroni, S., Blum, V., Bowler, D. R., Buccheri, A., Chelikowsky,
J. R., Das, S., Dawson, W., Delugas, P., Dogan, M., Draxl, C., Galli, G., Genovese,
L., Giannozzi, P., Giantomassi, M., Gonze, X., Govoni, M., Gulans, A., Gygi, F.,
… Perez, D. (2022). Roadmap on Electronic Structure Codes in the Exascale Era.
In arXiv:2209.12747.
bibtex: '@article{Gavini_Baroni_Blum_Bowler_Buccheri_Chelikowsky_Das_Dawson_Delugas_Dogan_et
al._2022, title={Roadmap on Electronic Structure Codes in the Exascale Era}, journal={arXiv:2209.12747},
author={Gavini, Vikram and Baroni, Stefano and Blum, Volker and Bowler, David
R. and Buccheri, Alexander and Chelikowsky, James R. and Das, Sambit and Dawson,
William and Delugas, Pietro and Dogan, Mehmet and et al.}, year={2022} }'
chicago: Gavini, Vikram, Stefano Baroni, Volker Blum, David R. Bowler, Alexander
Buccheri, James R. Chelikowsky, Sambit Das, et al. “Roadmap on Electronic Structure
Codes in the Exascale Era.” ArXiv:2209.12747, 2022.
ieee: V. Gavini et al., “Roadmap on Electronic Structure Codes in the Exascale
Era,” arXiv:2209.12747. 2022.
mla: Gavini, Vikram, et al. “Roadmap on Electronic Structure Codes in the Exascale
Era.” ArXiv:2209.12747, 2022.
short: V. Gavini, S. Baroni, V. Blum, D.R. Bowler, A. Buccheri, J.R. Chelikowsky,
S. Das, W. Dawson, P. Delugas, M. Dogan, C. Draxl, G. Galli, L. Genovese, P. Giannozzi,
M. Giantomassi, X. Gonze, M. Govoni, A. Gulans, F. Gygi, J.M. Herbert, S. Kokott,
T. Kühne, K.-H. Liou, T. Miyazaki, P. Motamarri, A. Nakata, J.E. Pask, C. Plessl,
L.E. Ratcliff, R.M. Richard, M. Rossi, R. Schade, M. Scheffler, O. Schütt, P.
Suryanarayana, M. Torrent, L. Truflandier, T.L. Windus, Q. Xu, V.W.-Z. Yu, D.
Perez, ArXiv:2209.12747 (2022).
date_created: 2022-09-28T05:25:10Z
date_updated: 2023-07-28T08:03:41Z
department:
- _id: '27'
- _id: '518'
external_id:
arxiv:
- '2209.12747'
language:
- iso: eng
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: arXiv:2209.12747
status: public
title: Roadmap on Electronic Structure Codes in the Exascale Era
type: preprint
user_id: '24135'
year: '2022'
...