---
_id: '2201'
author:
- first_name: Tobias
  full_name: Schumacher, Tobias
  last_name: Schumacher
- first_name: Tim
  full_name: Süß, Tim
  last_name: Süß
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Schumacher T, Süß T, Plessl C, Platzner M. FPGA Acceleration of Communication-bound
    Streaming Applications: Architecture Modeling and a 3D Image Compositing Case
    Study. <i>Int Journal of Recon- figurable Computing (IJRC)</i>. Published online
    2011. doi:<a href="https://doi.org/10.1155/2011/760954">10.1155/2011/760954</a>'
  apa: 'Schumacher, T., Süß, T., Plessl, C., &#38; Platzner, M. (2011). FPGA Acceleration
    of Communication-bound Streaming Applications: Architecture Modeling and a 3D
    Image Compositing Case Study. <i>Int. Journal of Recon- Figurable Computing (IJRC)</i>.
    <a href="https://doi.org/10.1155/2011/760954">https://doi.org/10.1155/2011/760954</a>'
  bibtex: '@article{Schumacher_Süß_Plessl_Platzner_2011, title={FPGA Acceleration
    of Communication-bound Streaming Applications: Architecture Modeling and a 3D
    Image Compositing Case Study}, DOI={<a href="https://doi.org/10.1155/2011/760954">10.1155/2011/760954</a>},
    journal={Int. Journal of Recon- figurable Computing (IJRC)}, publisher={Hindawi
    Publishing Corp.}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian
    and Platzner, Marco}, year={2011} }'
  chicago: 'Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “FPGA
    Acceleration of Communication-Bound Streaming Applications: Architecture Modeling
    and a 3D Image Compositing Case Study.” <i>Int. Journal of Recon- Figurable Computing
    (IJRC)</i>, 2011. <a href="https://doi.org/10.1155/2011/760954">https://doi.org/10.1155/2011/760954</a>.'
  ieee: 'T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “FPGA Acceleration of
    Communication-bound Streaming Applications: Architecture Modeling and a 3D Image
    Compositing Case Study,” <i>Int. Journal of Recon- figurable Computing (IJRC)</i>,
    2011, doi: <a href="https://doi.org/10.1155/2011/760954">10.1155/2011/760954</a>.'
  mla: 'Schumacher, Tobias, et al. “FPGA Acceleration of Communication-Bound Streaming
    Applications: Architecture Modeling and a 3D Image Compositing Case Study.” <i>Int.
    Journal of Recon- Figurable Computing (IJRC)</i>, Hindawi Publishing Corp., 2011,
    doi:<a href="https://doi.org/10.1155/2011/760954">10.1155/2011/760954</a>.'
  short: T. Schumacher, T. Süß, C. Plessl, M. Platzner, Int. Journal of Recon- Figurable
    Computing (IJRC) (2011).
date_created: 2018-04-03T15:09:49Z
date_updated: 2023-09-26T13:45:46Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1155/2011/760954
keyword:
- funding-altera
language:
- iso: eng
publication: Int. Journal of Recon- figurable Computing (IJRC)
publisher: Hindawi Publishing Corp.
quality_controlled: '1'
status: public
title: 'FPGA Acceleration of Communication-bound Streaming Applications: Architecture
  Modeling and a 3D Image Compositing Case Study'
type: journal_article
user_id: '15278'
year: '2011'
...
---
_id: '2198'
author:
- first_name: Mariusz
  full_name: Grad, Mariusz
  last_name: Grad
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
citation:
  ama: 'Grad M, Plessl C. Just-in-time Instruction Set Extension – Feasibility and
    Limitations for an FPGA-based Reconfigurable ASIP Architecture. In: <i>Proc. Reconfigurable
    Architectures Workshop (RAW)</i>. IEEE Computer Society; 2011:278-285. doi:<a
    href="https://doi.org/10.1109/IPDPS.2011.153">10.1109/IPDPS.2011.153</a>'
  apa: Grad, M., &#38; Plessl, C. (2011). Just-in-time Instruction Set Extension –
    Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture.
    <i>Proc. Reconfigurable Architectures Workshop (RAW)</i>, 278–285. <a href="https://doi.org/10.1109/IPDPS.2011.153">https://doi.org/10.1109/IPDPS.2011.153</a>
  bibtex: '@inproceedings{Grad_Plessl_2011, title={Just-in-time Instruction Set Extension
    – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture},
    DOI={<a href="https://doi.org/10.1109/IPDPS.2011.153">10.1109/IPDPS.2011.153</a>},
    booktitle={Proc. Reconfigurable Architectures Workshop (RAW)}, publisher={IEEE
    Computer Society}, author={Grad, Mariusz and Plessl, Christian}, year={2011},
    pages={278–285} }'
  chicago: Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension
    – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.”
    In <i>Proc. Reconfigurable Architectures Workshop (RAW)</i>, 278–85. IEEE Computer
    Society, 2011. <a href="https://doi.org/10.1109/IPDPS.2011.153">https://doi.org/10.1109/IPDPS.2011.153</a>.
  ieee: 'M. Grad and C. Plessl, “Just-in-time Instruction Set Extension – Feasibility
    and Limitations for an FPGA-based Reconfigurable ASIP Architecture,” in <i>Proc.
    Reconfigurable Architectures Workshop (RAW)</i>, 2011, pp. 278–285, doi: <a href="https://doi.org/10.1109/IPDPS.2011.153">10.1109/IPDPS.2011.153</a>.'
  mla: Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension
    – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.”
    <i>Proc. Reconfigurable Architectures Workshop (RAW)</i>, IEEE Computer Society,
    2011, pp. 278–85, doi:<a href="https://doi.org/10.1109/IPDPS.2011.153">10.1109/IPDPS.2011.153</a>.
  short: 'M. Grad, C. Plessl, in: Proc. Reconfigurable Architectures Workshop (RAW),
    IEEE Computer Society, 2011, pp. 278–285.'
date_created: 2018-04-03T15:05:52Z
date_updated: 2023-09-26T13:44:39Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/IPDPS.2011.153
language:
- iso: eng
page: 278-285
publication: Proc. Reconfigurable Architectures Workshop (RAW)
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: Just-in-time Instruction Set Extension – Feasibility and Limitations for an
  FPGA-based Reconfigurable ASIP Architecture
type: conference
user_id: '15278'
year: '2011'
...
---
_id: '2223'
author:
- first_name: Enno
  full_name: Lübbers, Enno
  last_name: Lübbers
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Ariane
  full_name: Keller, Ariane
  last_name: Keller
- first_name: Bernhard
  full_name: Plattner, Bernhard
  last_name: Plattner
citation:
  ama: 'Lübbers E, Platzner M, Plessl C, Keller A, Plattner B. Towards Adaptive Networking
    for Embedded Devices based on Reconfigurable Hardware. In: <i>Proc. Int. Conf.
    on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press;
    2010:225-231.'
  apa: Lübbers, E., Platzner, M., Plessl, C., Keller, A., &#38; Plattner, B. (2010).
    Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware.
    <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>,
    225–231.
  bibtex: '@inproceedings{Lübbers_Platzner_Plessl_Keller_Plattner_2010, title={Towards
    Adaptive Networking for Embedded Devices based on Reconfigurable Hardware}, booktitle={Proc.
    Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA
    Press}, author={Lübbers, Enno and Platzner, Marco and Plessl, Christian and Keller,
    Ariane and Plattner, Bernhard}, year={2010}, pages={225–231} }'
  chicago: Lübbers, Enno, Marco Platzner, Christian Plessl, Ariane Keller, and Bernhard
    Plattner. “Towards Adaptive Networking for Embedded Devices Based on Reconfigurable
    Hardware.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and
    Algorithms (ERSA)</i>, 225–31. CSREA Press, 2010.
  ieee: E. Lübbers, M. Platzner, C. Plessl, A. Keller, and B. Plattner, “Towards Adaptive
    Networking for Embedded Devices based on Reconfigurable Hardware,” in <i>Proc.
    Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>,
    2010, pp. 225–231.
  mla: Lübbers, Enno, et al. “Towards Adaptive Networking for Embedded Devices Based
    on Reconfigurable Hardware.” <i>Proc. Int. Conf. on Engineering of Reconfigurable
    Systems and Algorithms (ERSA)</i>, CSREA Press, 2010, pp. 225–31.
  short: 'E. Lübbers, M. Platzner, C. Plessl, A. Keller, B. Plattner, in: Proc. Int.
    Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press,
    2010, pp. 225–231.'
date_created: 2018-04-05T16:27:13Z
date_updated: 2023-09-26T13:48:32Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
language:
- iso: eng
page: 225-231
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
  (ERSA)
publication_identifier:
  isbn:
  - 1-60132-140-6
publisher: CSREA Press
quality_controlled: '1'
status: public
title: Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2216'
author:
- first_name: Mariusz
  full_name: Grad, Mariusz
  last_name: Grad
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
citation:
  ama: 'Grad M, Plessl C. Pruning the Design Space for Just-In-Time Processor Customization.
    In: <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>.
    IEEE Computer Society; 2010:67-72. doi:<a href="https://doi.org/10.1109/ReConFig.2010.19">10.1109/ReConFig.2010.19</a>'
  apa: Grad, M., &#38; Plessl, C. (2010). Pruning the Design Space for Just-In-Time
    Processor Customization. <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs
    (ReConFig)</i>, 67–72. <a href="https://doi.org/10.1109/ReConFig.2010.19">https://doi.org/10.1109/ReConFig.2010.19</a>
  bibtex: '@inproceedings{Grad_Plessl_2010, place={Los Alamitos, CA, USA}, title={Pruning
    the Design Space for Just-In-Time Processor Customization}, DOI={<a href="https://doi.org/10.1109/ReConFig.2010.19">10.1109/ReConFig.2010.19</a>},
    booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)},
    publisher={IEEE Computer Society}, author={Grad, Mariusz and Plessl, Christian},
    year={2010}, pages={67–72} }'
  chicago: 'Grad, Mariusz, and Christian Plessl. “Pruning the Design Space for Just-In-Time
    Processor Customization.” In <i>Proc. Int. Conf. on ReConFigurable Computing and
    FPGAs (ReConFig)</i>, 67–72. Los Alamitos, CA, USA: IEEE Computer Society, 2010.
    <a href="https://doi.org/10.1109/ReConFig.2010.19">https://doi.org/10.1109/ReConFig.2010.19</a>.'
  ieee: 'M. Grad and C. Plessl, “Pruning the Design Space for Just-In-Time Processor
    Customization,” in <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>,
    2010, pp. 67–72, doi: <a href="https://doi.org/10.1109/ReConFig.2010.19">10.1109/ReConFig.2010.19</a>.'
  mla: Grad, Mariusz, and Christian Plessl. “Pruning the Design Space for Just-In-Time
    Processor Customization.” <i>Proc. Int. Conf. on ReConFigurable Computing and
    FPGAs (ReConFig)</i>, IEEE Computer Society, 2010, pp. 67–72, doi:<a href="https://doi.org/10.1109/ReConFig.2010.19">10.1109/ReConFig.2010.19</a>.
  short: 'M. Grad, C. Plessl, in: Proc. Int. Conf. on ReConFigurable Computing and
    FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2010, pp. 67–72.'
date_created: 2018-04-05T14:48:51Z
date_updated: 2023-09-26T13:47:11Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2010.19
language:
- iso: eng
page: 67-72
place: Los Alamitos, CA, USA
publication: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: Pruning the Design Space for Just-In-Time Processor Customization
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2224'
author:
- first_name: Mariusz
  full_name: Grad, Mariusz
  last_name: Grad
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
citation:
  ama: 'Grad M, Plessl C. An Open Source Circuit Library with Benchmarking Facilities.
    In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
    (ERSA)</i>. CSREA Press; 2010:144-150.'
  apa: Grad, M., &#38; Plessl, C. (2010). An Open Source Circuit Library with Benchmarking
    Facilities. <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
    (ERSA)</i>, 144–150.
  bibtex: '@inproceedings{Grad_Plessl_2010, title={An Open Source Circuit Library
    with Benchmarking Facilities}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable
    Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Grad, Mariusz
    and Plessl, Christian}, year={2010}, pages={144–150} }'
  chicago: Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with
    Benchmarking Facilities.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable
    Systems and Algorithms (ERSA)</i>, 144–50. CSREA Press, 2010.
  ieee: M. Grad and C. Plessl, “An Open Source Circuit Library with Benchmarking Facilities,”
    in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
    (ERSA)</i>, 2010, pp. 144–150.
  mla: Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with Benchmarking
    Facilities.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and
    Algorithms (ERSA)</i>, CSREA Press, 2010, pp. 144–50.
  short: 'M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable
    Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144–150.'
date_created: 2018-04-05T16:28:38Z
date_updated: 2023-09-26T13:48:59Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
language:
- iso: eng
page: 144-150
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
  (ERSA)
publication_identifier:
  isbn:
  - 1-60132-140-6
publisher: CSREA Press
quality_controlled: '1'
status: public
title: An Open Source Circuit Library with Benchmarking Facilities
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2220'
author:
- first_name: David
  full_name: Andrews, David
  last_name: Andrews
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
citation:
  ama: 'Andrews D, Plessl C. Configurable Processor Architectures: History and Trends.
    In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
    (ERSA)</i>. CSREA Press; 2010:165.'
  apa: 'Andrews, D., &#38; Plessl, C. (2010). Configurable Processor Architectures:
    History and Trends. <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems
    and Algorithms (ERSA)</i>, 165.'
  bibtex: '@inproceedings{Andrews_Plessl_2010, title={Configurable Processor Architectures:
    History and Trends}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable
    Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Andrews, David
    and Plessl, Christian}, year={2010}, pages={165} }'
  chicago: 'Andrews, David, and Christian Plessl. “Configurable Processor Architectures:
    History and Trends.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems
    and Algorithms (ERSA)</i>, 165. CSREA Press, 2010.'
  ieee: 'D. Andrews and C. Plessl, “Configurable Processor Architectures: History
    and Trends,” in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and
    Algorithms (ERSA)</i>, 2010, p. 165.'
  mla: 'Andrews, David, and Christian Plessl. “Configurable Processor Architectures:
    History and Trends.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems
    and Algorithms (ERSA)</i>, CSREA Press, 2010, p. 165.'
  short: 'D. Andrews, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable
    Systems and Algorithms (ERSA), CSREA Press, 2010, p. 165.'
date_created: 2018-04-05T14:57:07Z
date_updated: 2023-09-26T13:47:33Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
language:
- iso: eng
page: '165'
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
  (ERSA)
publication_identifier:
  isbn:
  - 1-60132-140-6
publisher: CSREA Press
quality_controlled: '1'
status: public
title: 'Configurable Processor Architectures: History and Trends'
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2222'
citation:
  ama: Plaks TP, Andrews D, DeMara R, et al., eds. <i>Proc. Int. Conf. on Engineering
    of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2010.
  apa: Plaks, T. P., Andrews, D., DeMara, R., Lam, H., Lee, J., Plessl, C., &#38;
    Stitt, G. (Eds.). (2010). <i>Proc. Int. Conf. on Engineering of Reconfigurable
    Systems and Algorithms (ERSA)</i>. CSREA Press.
  bibtex: '@book{Plaks_Andrews_DeMara_Lam_Lee_Plessl_Stitt_2010, title={Proc. Int.
    Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA
    Press}, year={2010} }'
  chicago: Plaks, Toomas P., David Andrews, Ronald DeMara, Herman Lam, Jooheung Lee,
    Christian Plessl, and Greg Stitt, eds. <i>Proc. Int. Conf. on Engineering of Reconfigurable
    Systems and Algorithms (ERSA)</i>. CSREA Press, 2010.
  ieee: T. P. Plaks <i>et al.</i>, Eds., <i>Proc. Int. Conf. on Engineering of Reconfigurable
    Systems and Algorithms (ERSA)</i>. CSREA Press, 2010.
  mla: Plaks, Toomas P., et al., editors. <i>Proc. Int. Conf. on Engineering of Reconfigurable
    Systems and Algorithms (ERSA)</i>. CSREA Press, 2010.
  short: T.P. Plaks, D. Andrews, R. DeMara, H. Lam, J. Lee, C. Plessl, G. Stitt, eds.,
    Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
    CSREA Press, 2010.
date_created: 2018-04-05T15:00:49Z
date_updated: 2023-09-26T13:48:00Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
editor:
- first_name: Toomas P.
  full_name: Plaks, Toomas P.
  last_name: Plaks
- first_name: David
  full_name: Andrews, David
  last_name: Andrews
- first_name: Ronald
  full_name: DeMara, Ronald
  last_name: DeMara
- first_name: Herman
  full_name: Lam, Herman
  last_name: Lam
- first_name: Jooheung
  full_name: Lee, Jooheung
  last_name: Lee
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Greg
  full_name: Stitt, Greg
  last_name: Stitt
language:
- iso: eng
publication_identifier:
  isbn:
  - 1-60132-140-6
publisher: CSREA Press
quality_controlled: '1'
status: public
title: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)
type: conference_editor
user_id: '15278'
year: '2010'
...
---
_id: '2226'
author:
- first_name: Tobias
  full_name: Beisel, Tobias
  last_name: Beisel
- first_name: Manuel
  full_name: Niekamp, Manuel
  last_name: Niekamp
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
citation:
  ama: 'Beisel T, Niekamp M, Plessl C. Using Shared Library Interposing for Transparent
    Acceleration in Systems with Heterogeneous Hardware Accelerators. In: <i>Proc.
    Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>.
    IEEE Computer Society; 2010:65-72. doi:<a href="https://doi.org/10.1109/ASAP.2010.5540798">10.1109/ASAP.2010.5540798</a>'
  apa: Beisel, T., Niekamp, M., &#38; Plessl, C. (2010). Using Shared Library Interposing
    for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators.
    <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors
    (ASAP)</i>, 65–72. <a href="https://doi.org/10.1109/ASAP.2010.5540798">https://doi.org/10.1109/ASAP.2010.5540798</a>
  bibtex: '@inproceedings{Beisel_Niekamp_Plessl_2010, title={Using Shared Library
    Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware
    Accelerators}, DOI={<a href="https://doi.org/10.1109/ASAP.2010.5540798">10.1109/ASAP.2010.5540798</a>},
    booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and
    Processors (ASAP)}, publisher={IEEE Computer Society}, author={Beisel, Tobias
    and Niekamp, Manuel and Plessl, Christian}, year={2010}, pages={65–72} }'
  chicago: Beisel, Tobias, Manuel Niekamp, and Christian Plessl. “Using Shared Library
    Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware
    Accelerators.” In <i>Proc. Int. Conf. on Application-Specific Systems, Architectures,
    and Processors (ASAP)</i>, 65–72. IEEE Computer Society, 2010. <a href="https://doi.org/10.1109/ASAP.2010.5540798">https://doi.org/10.1109/ASAP.2010.5540798</a>.
  ieee: 'T. Beisel, M. Niekamp, and C. Plessl, “Using Shared Library Interposing for
    Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators,”
    in <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors
    (ASAP)</i>, 2010, pp. 65–72, doi: <a href="https://doi.org/10.1109/ASAP.2010.5540798">10.1109/ASAP.2010.5540798</a>.'
  mla: Beisel, Tobias, et al. “Using Shared Library Interposing for Transparent Acceleration
    in Systems with Heterogeneous Hardware Accelerators.” <i>Proc. Int. Conf. on Application-Specific
    Systems, Architectures, and Processors (ASAP)</i>, IEEE Computer Society, 2010,
    pp. 65–72, doi:<a href="https://doi.org/10.1109/ASAP.2010.5540798">10.1109/ASAP.2010.5540798</a>.
  short: 'T. Beisel, M. Niekamp, C. Plessl, in: Proc. Int. Conf. on Application-Specific
    Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010, pp.
    65–72.'
date_created: 2018-04-05T16:39:34Z
date_updated: 2023-09-26T13:49:21Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ASAP.2010.5540798
language:
- iso: eng
page: 65-72
publication: Proc. Int. Conf. on Application-Specific Systems, Architectures, and
  Processors (ASAP)
publication_identifier:
  isbn:
  - 978-1-4244-6965-9
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: Using Shared Library Interposing for Transparent Acceleration in Systems with
  Heterogeneous Hardware Accelerators
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2206'
author:
- first_name: Ariane
  full_name: Keller, Ariane
  last_name: Keller
- first_name: Bernhard
  full_name: Plattner, Bernhard
  last_name: Plattner
- first_name: Enno
  full_name: Lübbers, Enno
  last_name: Lübbers
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
citation:
  ama: 'Keller A, Plattner B, Lübbers E, Platzner M, Plessl C. Reconfigurable Nodes
    for Future Networks. In: <i>Proc. IEEE Globecom Workshop on Network of the Future
    (FutureNet)</i>. IEEE; 2010:372-376. doi:<a href="https://doi.org/10.1109/GLOCOMW.2010.5700341">10.1109/GLOCOMW.2010.5700341</a>'
  apa: Keller, A., Plattner, B., Lübbers, E., Platzner, M., &#38; Plessl, C. (2010).
    Reconfigurable Nodes for Future Networks. <i>Proc. IEEE Globecom Workshop on Network
    of the Future (FutureNet)</i>, 372–376. <a href="https://doi.org/10.1109/GLOCOMW.2010.5700341">https://doi.org/10.1109/GLOCOMW.2010.5700341</a>
  bibtex: '@inproceedings{Keller_Plattner_Lübbers_Platzner_Plessl_2010, title={Reconfigurable
    Nodes for Future Networks}, DOI={<a href="https://doi.org/10.1109/GLOCOMW.2010.5700341">10.1109/GLOCOMW.2010.5700341</a>},
    booktitle={Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)},
    publisher={IEEE}, author={Keller, Ariane and Plattner, Bernhard and Lübbers, Enno
    and Platzner, Marco and Plessl, Christian}, year={2010}, pages={372–376} }'
  chicago: Keller, Ariane, Bernhard Plattner, Enno Lübbers, Marco Platzner, and Christian
    Plessl. “Reconfigurable Nodes for Future Networks.” In <i>Proc. IEEE Globecom
    Workshop on Network of the Future (FutureNet)</i>, 372–76. IEEE, 2010. <a href="https://doi.org/10.1109/GLOCOMW.2010.5700341">https://doi.org/10.1109/GLOCOMW.2010.5700341</a>.
  ieee: 'A. Keller, B. Plattner, E. Lübbers, M. Platzner, and C. Plessl, “Reconfigurable
    Nodes for Future Networks,” in <i>Proc. IEEE Globecom Workshop on Network of the
    Future (FutureNet)</i>, 2010, pp. 372–376, doi: <a href="https://doi.org/10.1109/GLOCOMW.2010.5700341">10.1109/GLOCOMW.2010.5700341</a>.'
  mla: Keller, Ariane, et al. “Reconfigurable Nodes for Future Networks.” <i>Proc.
    IEEE Globecom Workshop on Network of the Future (FutureNet)</i>, IEEE, 2010, pp.
    372–76, doi:<a href="https://doi.org/10.1109/GLOCOMW.2010.5700341">10.1109/GLOCOMW.2010.5700341</a>.
  short: 'A. Keller, B. Plattner, E. Lübbers, M. Platzner, C. Plessl, in: Proc. IEEE
    Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp. 372–376.'
date_created: 2018-04-04T09:36:16Z
date_updated: 2023-09-26T13:51:00Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/GLOCOMW.2010.5700341
language:
- iso: eng
page: 372-376
publication: Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)
publication_identifier:
  isbn:
  - 978-1-4244-8864-3
publisher: IEEE
quality_controlled: '1'
status: public
title: Reconfigurable Nodes for Future Networks
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2227'
author:
- first_name: Matthias
  full_name: Woehrle, Matthias
  last_name: Woehrle
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Lothar
  full_name: Thiele, Lothar
  last_name: Thiele
citation:
  ama: 'Woehrle M, Plessl C, Thiele L. Rupeas: Ruby Powered Event Analysis DSL. In:
    <i>Proc. Int. Conf. Networked Sensing Systems (INSS)</i>. IEEE; 2010:245-248.
    doi:<a href="https://doi.org/10.1109/INSS.2010.5572211">10.1109/INSS.2010.5572211</a>'
  apa: 'Woehrle, M., Plessl, C., &#38; Thiele, L. (2010). Rupeas: Ruby Powered Event
    Analysis DSL. <i>Proc. Int. Conf. Networked Sensing Systems (INSS)</i>, 245–248.
    <a href="https://doi.org/10.1109/INSS.2010.5572211">https://doi.org/10.1109/INSS.2010.5572211</a>'
  bibtex: '@inproceedings{Woehrle_Plessl_Thiele_2010, title={Rupeas: Ruby Powered
    Event Analysis DSL}, DOI={<a href="https://doi.org/10.1109/INSS.2010.5572211">10.1109/INSS.2010.5572211</a>},
    booktitle={Proc. Int. Conf. Networked Sensing Systems (INSS)}, publisher={IEEE},
    author={Woehrle, Matthias and Plessl, Christian and Thiele, Lothar}, year={2010},
    pages={245–248} }'
  chicago: 'Woehrle, Matthias, Christian Plessl, and Lothar Thiele. “Rupeas: Ruby
    Powered Event Analysis DSL.” In <i>Proc. Int. Conf. Networked Sensing Systems
    (INSS)</i>, 245–48. IEEE, 2010. <a href="https://doi.org/10.1109/INSS.2010.5572211">https://doi.org/10.1109/INSS.2010.5572211</a>.'
  ieee: 'M. Woehrle, C. Plessl, and L. Thiele, “Rupeas: Ruby Powered Event Analysis
    DSL,” in <i>Proc. Int. Conf. Networked Sensing Systems (INSS)</i>, 2010, pp. 245–248,
    doi: <a href="https://doi.org/10.1109/INSS.2010.5572211">10.1109/INSS.2010.5572211</a>.'
  mla: 'Woehrle, Matthias, et al. “Rupeas: Ruby Powered Event Analysis DSL.” <i>Proc.
    Int. Conf. Networked Sensing Systems (INSS)</i>, IEEE, 2010, pp. 245–48, doi:<a
    href="https://doi.org/10.1109/INSS.2010.5572211">10.1109/INSS.2010.5572211</a>.'
  short: 'M. Woehrle, C. Plessl, L. Thiele, in: Proc. Int. Conf. Networked Sensing
    Systems (INSS), IEEE, 2010, pp. 245–248.'
date_created: 2018-04-05T16:41:02Z
date_updated: 2023-09-26T13:49:38Z
department:
- _id: '27'
- _id: '518'
doi: 10.1109/INSS.2010.5572211
extern: '1'
language:
- iso: eng
page: 245-248
publication: Proc. Int. Conf. Networked Sensing Systems (INSS)
publication_identifier:
  isbn:
  - 978-1-4244-7911-5
publisher: IEEE
quality_controlled: '1'
status: public
title: 'Rupeas: Ruby Powered Event Analysis DSL'
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2228'
author:
- first_name: Tobias
  full_name: Kenter, Tobias
  id: '3145'
  last_name: Kenter
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Michael
  full_name: Kauschke, Michael
  last_name: Kauschke
citation:
  ama: 'Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation for the
    Exploration of CPU-Accelerator Architectures. In: Hammami O, Larrabee S, eds.
    <i>Proc. Workshop on Architectural Research Prototyping (WARP), International
    Symposium on Computer Architecture (ISCA)</i>. ; 2010.'
  apa: Kenter, T., Platzner, M., Plessl, C., &#38; Kauschke, M. (2010). Performance
    Estimation for the Exploration of CPU-Accelerator Architectures. In O. Hammami
    &#38; S. Larrabee (Eds.), <i>Proc. Workshop on Architectural Research Prototyping
    (WARP), International Symposium on Computer Architecture (ISCA)</i>.
  bibtex: '@inproceedings{Kenter_Platzner_Plessl_Kauschke_2010, title={Performance
    Estimation for the Exploration of CPU-Accelerator Architectures}, booktitle={Proc.
    Workshop on Architectural Research Prototyping (WARP), International Symposium
    on Computer Architecture (ISCA)}, author={Kenter, Tobias and Platzner, Marco and
    Plessl, Christian and Kauschke, Michael}, editor={Hammami, Omar and Larrabee,
    Sandra}, year={2010} }'
  chicago: Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke.
    “Performance Estimation for the Exploration of CPU-Accelerator Architectures.”
    In <i>Proc. Workshop on Architectural Research Prototyping (WARP), International
    Symposium on Computer Architecture (ISCA)</i>, edited by Omar Hammami and Sandra
    Larrabee, 2010.
  ieee: T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation
    for the Exploration of CPU-Accelerator Architectures,” in <i>Proc. Workshop on
    Architectural Research Prototyping (WARP), International Symposium on Computer
    Architecture (ISCA)</i>, 2010.
  mla: Kenter, Tobias, et al. “Performance Estimation for the Exploration of CPU-Accelerator
    Architectures.” <i>Proc. Workshop on Architectural Research Prototyping (WARP),
    International Symposium on Computer Architecture (ISCA)</i>, edited by Omar Hammami
    and Sandra Larrabee, 2010.
  short: 'T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: O. Hammami, S. Larrabee
    (Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International
    Symposium on Computer Architecture (ISCA), 2010.'
date_created: 2018-04-05T16:43:04Z
date_updated: 2023-09-26T13:50:04Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
editor:
- first_name: Omar
  full_name: Hammami, Omar
  last_name: Hammami
- first_name: Sandra
  full_name: Larrabee, Sandra
  last_name: Larrabee
language:
- iso: eng
publication: Proc. Workshop on Architectural Research Prototyping (WARP), International
  Symposium on Computer Architecture (ISCA)
quality_controlled: '1'
status: public
title: Performance Estimation for the Exploration of CPU-Accelerator Architectures
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2353'
abstract:
- lang: eng
  text: 'Wireless Sensor Networks (WSNs) are unique embedded computation systems for
    distributed sensing of a dispersed phenomenon. While being a strongly concurrent
    distributed system, its embedded aspects with severe resource limitations and
    the wireless communication requires a fusion of technologies and methodologies
    from very different fields. As WSNs are deployed in remote locations for long-term
    unattended operation, assurance of correct functioning of the system is of prime
    concern. Thus, the design and development of WSNs requires specialized tools to
    allow for testing and debugging the system. To this end, we present a framework
    for analyzing and checking WSNs based on collected events during system operation.
    It allows for abstracting from the event trace by means of behavioral queries
    and uses assertions for checking the accordance of an execution to its specification.
    The framework is independent from WSN test platforms, applications and logging
    semantics and thus generally applicable for analyzing event logs of WSN test executions. '
author:
- first_name: Matthias
  full_name: Woehrle, Matthias
  last_name: Woehrle
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Lothar
  full_name: Thiele, Lothar
  last_name: Thiele
citation:
  ama: 'Woehrle M, Plessl C, Thiele L. <i>Rupeas: Ruby Powered Event Analysis DSL</i>.
    Computer Engineering and Networks Lab, ETH Zurich; 2009.'
  apa: 'Woehrle, M., Plessl, C., &#38; Thiele, L. (2009). <i>Rupeas: Ruby Powered
    Event Analysis DSL</i>. Computer Engineering and Networks Lab, ETH Zurich.'
  bibtex: '@book{Woehrle_Plessl_Thiele_2009, place={Computer Engineering and Networks
    Lab, ETH Zurich}, title={Rupeas: Ruby Powered Event Analysis DSL}, author={Woehrle,
    Matthias and Plessl, Christian and Thiele, Lothar}, year={2009} }'
  chicago: 'Woehrle, Matthias, Christian Plessl, and Lothar Thiele. <i>Rupeas: Ruby
    Powered Event Analysis DSL</i>. Computer Engineering and Networks Lab, ETH Zurich,
    2009.'
  ieee: 'M. Woehrle, C. Plessl, and L. Thiele, <i>Rupeas: Ruby Powered Event Analysis
    DSL</i>. Computer Engineering and Networks Lab, ETH Zurich, 2009.'
  mla: 'Woehrle, Matthias, et al. <i>Rupeas: Ruby Powered Event Analysis DSL</i>.
    2009.'
  short: 'M. Woehrle, C. Plessl, L. Thiele, Rupeas: Ruby Powered Event Analysis DSL,
    Computer Engineering and Networks Lab, ETH Zurich, 2009.'
date_created: 2018-04-16T15:09:19Z
date_updated: 2022-01-06T06:55:56Z
department:
- _id: '27'
- _id: '518'
extern: '1'
keyword:
- Rupeas
- DSL
- WSN
- testing
language:
- iso: eng
place: Computer Engineering and Networks Lab, ETH Zurich
report_number: TIK-Report 290
status: public
title: 'Rupeas: Ruby Powered Event Analysis DSL'
type: report
user_id: '16153'
year: '2009'
...
---
_id: '2350'
abstract:
- lang: eng
  text: 'Mapping applications that consist of a collection of cores to FPGA accelerators
    and optimizing their performance is a challenging task in high performance reconfigurable
    computing. We present IMORC, an architectural template and highly versatile on-chip
    interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which
    allows for flexibly composing accelerators from cores running at full speed within
    their own clock domains, thus facilitating the re-use of cores and portability.
    Further, IMORC inserts performance counters for monitoring runtime data. In this
    paper, we first introduce the IMORC architectural template and the on-chip interconnect,
    and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor
    thinning problem on an XD1000 reconfigurable computing system. Using IMORC''s
    monitoring infrastructure, we gain insights into the data-dependent behavior of
    the application which, in turn, allow for optimizing the accelerator. '
author:
- first_name: Tobias
  full_name: Schumacher, Tobias
  last_name: Schumacher
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Schumacher T, Plessl C, Platzner M. IMORC: Application Mapping, Monitoring
    and Optimization for High-Performance Reconfigurable Computing. In: <i>Proc. Int.
    Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>. IEEE Computer
    Society; 2009:275-278. doi:<a href="https://doi.org/10.1109/FCCM.2009.25">10.1109/FCCM.2009.25</a>'
  apa: 'Schumacher, T., Plessl, C., &#38; Platzner, M. (2009). IMORC: Application
    Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.
    <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>,
    275–278. <a href="https://doi.org/10.1109/FCCM.2009.25">https://doi.org/10.1109/FCCM.2009.25</a>'
  bibtex: '@inproceedings{Schumacher_Plessl_Platzner_2009, title={IMORC: Application
    Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing},
    DOI={<a href="https://doi.org/10.1109/FCCM.2009.25">10.1109/FCCM.2009.25</a>},
    booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)},
    publisher={IEEE Computer Society}, author={Schumacher, Tobias and Plessl, Christian
    and Platzner, Marco}, year={2009}, pages={275–278} }'
  chicago: 'Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: Application
    Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.”
    In <i>Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>,
    275–78. IEEE Computer Society, 2009. <a href="https://doi.org/10.1109/FCCM.2009.25">https://doi.org/10.1109/FCCM.2009.25</a>.'
  ieee: 'T. Schumacher, C. Plessl, and M. Platzner, “IMORC: Application Mapping, Monitoring
    and Optimization for High-Performance Reconfigurable Computing,” in <i>Proc. Int.
    Symp. on Field-Programmable Custom Computing Machines (FCCM)</i>, 2009, pp. 275–278,
    doi: <a href="https://doi.org/10.1109/FCCM.2009.25">10.1109/FCCM.2009.25</a>.'
  mla: 'Schumacher, Tobias, et al. “IMORC: Application Mapping, Monitoring and Optimization
    for High-Performance Reconfigurable Computing.” <i>Proc. Int. Symp. on Field-Programmable
    Custom Computing Machines (FCCM)</i>, IEEE Computer Society, 2009, pp. 275–78,
    doi:<a href="https://doi.org/10.1109/FCCM.2009.25">10.1109/FCCM.2009.25</a>.'
  short: 'T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable
    Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–278.'
date_created: 2018-04-16T15:05:52Z
date_updated: 2023-09-26T13:51:44Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/FCCM.2009.25
keyword:
- IMORC
- interconnect
- performance
language:
- iso: eng
page: 275-278
publication: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)
publication_identifier:
  isbn:
  - 978-1-4244-4450-2
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: 'IMORC: Application Mapping, Monitoring and Optimization for High-Performance
  Reconfigurable Computing'
type: conference
user_id: '15278'
year: '2009'
...
---
_id: '2262'
abstract:
- lang: eng
  text: 'In this work we present EvoCache, a novel approach for implementing application-specific
    caches. The key innovation of EvoCache is to make the function that maps memory
    addresses from the CPU address space to cache indices programmable. We support
    arbitrary Boolean mapping functions that are implemented within a small reconfigurable
    logic fabric. For finding suitable cache mapping functions we rely on techniques
    from the evolvable hardware domain and utilize an evolutionary optimization procedure.
    We evaluate the use of EvoCache in an embedded processor for two specific applications
    (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and
    energy consumption. We show that the evolvable hardware approach for optimizing
    the cache functions not only significantly improves the cache performance for
    the training data used during optimization, but that the evolved mapping functions
    generalize very well. Compared to a conventional cache architecture, EvoCache
    applied to test data achieves a reduction in execution time of up to 14.31% for
    JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70%
    for BZIP2). We also discuss the integration of EvoCache into the operating system
    and show that the area and delay overheads introduced by EvoCache are acceptable. '
author:
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Kaufmann P, Plessl C, Platzner M. EvoCaches: Application-specific Adaptation
    of Cache Mapping. In: <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems
    (AHS)</i>. IEEE Computer Society; 2009:11-18.'
  apa: 'Kaufmann, P., Plessl, C., &#38; Platzner, M. (2009). EvoCaches: Application-specific
    Adaptation of Cache Mapping. <i>Proc. NASA/ESA Conference on Adaptive Hardware
    and Systems (AHS)</i>, 11–18.'
  bibtex: '@inproceedings{Kaufmann_Plessl_Platzner_2009, place={Los Alamitos, CA,
    USA}, title={EvoCaches: Application-specific Adaptation of Cache Mapping}, booktitle={Proc.
    NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}, publisher={IEEE Computer
    Society}, author={Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2009},
    pages={11–18} }'
  chicago: 'Kaufmann, Paul, Christian Plessl, and Marco Platzner. “EvoCaches: Application-Specific
    Adaptation of Cache Mapping.” In <i>Proc. NASA/ESA Conference on Adaptive Hardware
    and Systems (AHS)</i>, 11–18. Los Alamitos, CA, USA: IEEE Computer Society, 2009.'
  ieee: 'P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific
    Adaptation of Cache Mapping,” in <i>Proc. NASA/ESA Conference on Adaptive Hardware
    and Systems (AHS)</i>, 2009, pp. 11–18.'
  mla: 'Kaufmann, Paul, et al. “EvoCaches: Application-Specific Adaptation of Cache
    Mapping.” <i>Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)</i>,
    IEEE Computer Society, 2009, pp. 11–18.'
  short: 'P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive
    Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009,
    pp. 11–18.'
date_created: 2018-04-06T15:18:24Z
date_updated: 2023-09-26T13:53:11Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
keyword:
- EvoCache
- evolvable hardware
- computer architecture
language:
- iso: eng
page: 11-18
place: Los Alamitos, CA, USA
publication: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: 'EvoCaches: Application-specific Adaptation of Cache Mapping'
type: conference
user_id: '15278'
year: '2009'
...
---
_id: '2352'
author:
- first_name: Jan
  full_name: Beutel, Jan
  last_name: Beutel
- first_name: Stephan
  full_name: Gruber, Stephan
  last_name: Gruber
- first_name: Andi
  full_name: Hasler, Andi
  last_name: Hasler
- first_name: Roman
  full_name: Lim, Roman
  last_name: Lim
- first_name: Andreas
  full_name: Meier, Andreas
  last_name: Meier
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Igor
  full_name: Talzi, Igor
  last_name: Talzi
- first_name: Lothar
  full_name: Thiele, Lothar
  last_name: Thiele
- first_name: Christian
  full_name: Tschudin, Christian
  last_name: Tschudin
- first_name: Matthias
  full_name: Woehrle, Matthias
  last_name: Woehrle
- first_name: Mustafa
  full_name: Yuecel, Mustafa
  last_name: Yuecel
citation:
  ama: 'Beutel J, Gruber S, Hasler A, et al. PermaDAQ: A Scientific Instrument for
    Precision Sensing and Data Recovery in Environmental Extremes. In: <i>Proc. Int.
    Conf. on Information Processing in Sensor Networks (IPSN)</i>. IEEE Computer Society;
    2009:265-276.'
  apa: 'Beutel, J., Gruber, S., Hasler, A., Lim, R., Meier, A., Plessl, C., Talzi,
    I., Thiele, L., Tschudin, C., Woehrle, M., &#38; Yuecel, M. (2009). PermaDAQ:
    A Scientific Instrument for Precision Sensing and Data Recovery in Environmental
    Extremes. <i>Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)</i>,
    265–276.'
  bibtex: '@inproceedings{Beutel_Gruber_Hasler_Lim_Meier_Plessl_Talzi_Thiele_Tschudin_Woehrle_et
    al._2009, place={Washington, DC, USA}, title={PermaDAQ: A Scientific Instrument
    for Precision Sensing and Data Recovery in Environmental Extremes}, booktitle={Proc.
    Int. Conf. on Information Processing in Sensor Networks (IPSN)}, publisher={IEEE
    Computer Society}, author={Beutel, Jan and Gruber, Stephan and Hasler, Andi and
    Lim, Roman and Meier, Andreas and Plessl, Christian and Talzi, Igor and Thiele,
    Lothar and Tschudin, Christian and Woehrle, Matthias and et al.}, year={2009},
    pages={265–276} }'
  chicago: 'Beutel, Jan, Stephan Gruber, Andi Hasler, Roman Lim, Andreas Meier, Christian
    Plessl, Igor Talzi, et al. “PermaDAQ: A Scientific Instrument for Precision Sensing
    and Data Recovery in Environmental Extremes.” In <i>Proc. Int. Conf. on Information
    Processing in Sensor Networks (IPSN)</i>, 265–76. Washington, DC, USA: IEEE Computer
    Society, 2009.'
  ieee: 'J. Beutel <i>et al.</i>, “PermaDAQ: A Scientific Instrument for Precision
    Sensing and Data Recovery in Environmental Extremes,” in <i>Proc. Int. Conf. on
    Information Processing in Sensor Networks (IPSN)</i>, 2009, pp. 265–276.'
  mla: 'Beutel, Jan, et al. “PermaDAQ: A Scientific Instrument for Precision Sensing
    and Data Recovery in Environmental Extremes.” <i>Proc. Int. Conf. on Information
    Processing in Sensor Networks (IPSN)</i>, IEEE Computer Society, 2009, pp. 265–76.'
  short: 'J. Beutel, S. Gruber, A. Hasler, R. Lim, A. Meier, C. Plessl, I. Talzi,
    L. Thiele, C. Tschudin, M. Woehrle, M. Yuecel, in: Proc. Int. Conf. on Information
    Processing in Sensor Networks (IPSN), IEEE Computer Society, Washington, DC, USA,
    2009, pp. 265–276.'
date_created: 2018-04-16T15:08:07Z
date_updated: 2023-09-26T13:52:01Z
department:
- _id: '27'
- _id: '518'
extern: '1'
keyword:
- WSN
- PermaSense
language:
- iso: eng
page: 265-276
place: Washington, DC, USA
publication: Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)
publication_identifier:
  isbn:
  - 978-1-4244-5108-1
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: 'PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery
  in Environmental Extremes'
type: conference
user_id: '15278'
year: '2009'
...
---
_id: '2238'
author:
- first_name: Tobias
  full_name: Schumacher, Tobias
  last_name: Schumacher
- first_name: Tim
  full_name: Süß, Tim
  last_name: Süß
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Schumacher T, Süß T, Plessl C, Platzner M. Communication Performance Characterization
    for Reconfigurable Accelerator Design on the XD1000. In: <i>Proc. Int. Conf. on
    ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE Computer Society; 2009:119-124.
    doi:<a href="https://doi.org/10.1109/ReConFig.2009.32">10.1109/ReConFig.2009.32</a>'
  apa: Schumacher, T., Süß, T., Plessl, C., &#38; Platzner, M. (2009). Communication
    Performance Characterization for Reconfigurable Accelerator Design on the XD1000.
    <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, 119–124.
    <a href="https://doi.org/10.1109/ReConFig.2009.32">https://doi.org/10.1109/ReConFig.2009.32</a>
  bibtex: '@inproceedings{Schumacher_Süß_Plessl_Platzner_2009, place={Los Alamitos,
    CA, USA}, title={Communication Performance Characterization for Reconfigurable
    Accelerator Design on the XD1000}, DOI={<a href="https://doi.org/10.1109/ReConFig.2009.32">10.1109/ReConFig.2009.32</a>},
    booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)},
    publisher={IEEE Computer Society}, author={Schumacher, Tobias and Süß, Tim and
    Plessl, Christian and Platzner, Marco}, year={2009}, pages={119–124} }'
  chicago: 'Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “Communication
    Performance Characterization for Reconfigurable Accelerator Design on the XD1000.”
    In <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, 119–24.
    Los Alamitos, CA, USA: IEEE Computer Society, 2009. <a href="https://doi.org/10.1109/ReConFig.2009.32">https://doi.org/10.1109/ReConFig.2009.32</a>.'
  ieee: 'T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “Communication Performance
    Characterization for Reconfigurable Accelerator Design on the XD1000,” in <i>Proc.
    Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2009, pp. 119–124,
    doi: <a href="https://doi.org/10.1109/ReConFig.2009.32">10.1109/ReConFig.2009.32</a>.'
  mla: Schumacher, Tobias, et al. “Communication Performance Characterization for
    Reconfigurable Accelerator Design on the XD1000.” <i>Proc. Int. Conf. on ReConFigurable
    Computing and FPGAs (ReConFig)</i>, IEEE Computer Society, 2009, pp. 119–24, doi:<a
    href="https://doi.org/10.1109/ReConFig.2009.32">10.1109/ReConFig.2009.32</a>.
  short: 'T. Schumacher, T. Süß, C. Plessl, M. Platzner, in: Proc. Int. Conf. on ReConFigurable
    Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA,
    2009, pp. 119–124.'
date_created: 2018-04-05T17:11:28Z
date_updated: 2023-09-26T13:52:32Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2009.32
keyword:
- IMORC
- graphics
language:
- iso: eng
page: 119-124
place: Los Alamitos, CA, USA
publication: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)
publication_identifier:
  isbn:
  - 978-0-7695-3917-1
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: Communication Performance Characterization for Reconfigurable Accelerator Design
  on the XD1000
type: conference
user_id: '15278'
year: '2009'
...
---
_id: '2261'
author:
- first_name: Tobias
  full_name: Schumacher, Tobias
  last_name: Schumacher
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Schumacher T, Plessl C, Platzner M. An Accelerator for k-th Nearest Neighbor
    Thinning Based on the IMORC Infrastructure. In: <i>Proc. Int. Conf. on Field Programmable
    Logic and Applications (FPL)</i>. IEEE; 2009:338-344.'
  apa: Schumacher, T., Plessl, C., &#38; Platzner, M. (2009). An Accelerator for k-th
    Nearest Neighbor Thinning Based on the IMORC Infrastructure. <i>Proc. Int. Conf.
    on Field Programmable Logic and Applications (FPL)</i>, 338–344.
  bibtex: '@inproceedings{Schumacher_Plessl_Platzner_2009, title={An Accelerator for
    k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}, booktitle={Proc.
    Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE},
    author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009},
    pages={338–344} }'
  chicago: Schumacher, Tobias, Christian Plessl, and Marco Platzner. “An Accelerator
    for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” In <i>Proc.
    Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 338–44. IEEE,
    2009.
  ieee: T. Schumacher, C. Plessl, and M. Platzner, “An Accelerator for k-th Nearest
    Neighbor Thinning Based on the IMORC Infrastructure,” in <i>Proc. Int. Conf. on
    Field Programmable Logic and Applications (FPL)</i>, 2009, pp. 338–344.
  mla: Schumacher, Tobias, et al. “An Accelerator for K-Th Nearest Neighbor Thinning
    Based on the IMORC Infrastructure.” <i>Proc. Int. Conf. on Field Programmable
    Logic and Applications (FPL)</i>, IEEE, 2009, pp. 338–44.
  short: 'T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable
    Logic and Applications (FPL), IEEE, 2009, pp. 338–344.'
date_created: 2018-04-06T15:15:47Z
date_updated: 2023-09-26T13:52:52Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
keyword:
- IMORC
- NOC
- KNN
- accelerator
language:
- iso: eng
page: 338-344
publication: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)
publication_identifier:
  isbn:
  - 978-1-4244-3892-1
  issn:
  - 1946-1488
publisher: IEEE
quality_controlled: '1'
status: public
title: An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure
type: conference
user_id: '15278'
year: '2009'
...
---
_id: '2263'
abstract:
- lang: eng
  text: 'In this paper, we introduce the Woolcano reconfigurable processor architecture.
    The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary
    Processing Unit (APU) as well as the partial reconfiguration capabilities to provide
    dynamically reconfigurable custom instructions. We also present a hardware tool
    flow that automatically translates software functions into custom instructions
    and a software tool flow that creates binaries using these instructions. While
    previous research on processors with reconfigurable functional units has been
    performed predominantly with simulation, the Woolcano architecture allows for
    exploring dynamic instruction set extension with commercially available hardware.
    Finally, we present a case study demonstrating a custom floating-point instruction
    generated with our approach, which achieves a 40x speedup over software-emulated
    floating-point operations and a 21% speedup over the Xilinx hardware floating-point
    unit. '
author:
- first_name: Mariusz
  full_name: Grad, Mariusz
  last_name: Grad
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
citation:
  ama: 'Grad M, Plessl C. Woolcano: An Architecture and Tool Flow for Dynamic Instruction
    Set Extension on Xilinx Virtex-4 FX. In: <i>Proc. Int. Conf. on Engineering of
    Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2009:319-322.'
  apa: 'Grad, M., &#38; Plessl, C. (2009). Woolcano: An Architecture and Tool Flow
    for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. <i>Proc. Int. Conf.
    on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 319–322.'
  bibtex: '@inproceedings{Grad_Plessl_2009, place={USA}, title={Woolcano: An Architecture
    and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX}, booktitle={Proc.
    Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA
    Press}, author={Grad, Mariusz and Plessl, Christian}, year={2009}, pages={319–322}
    }'
  chicago: 'Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool
    Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” In <i>Proc.
    Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>,
    319–22. USA: CSREA Press, 2009.'
  ieee: 'M. Grad and C. Plessl, “Woolcano: An Architecture and Tool Flow for Dynamic
    Instruction Set Extension on Xilinx Virtex-4 FX,” in <i>Proc. Int. Conf. on Engineering
    of Reconfigurable Systems and Algorithms (ERSA)</i>, 2009, pp. 319–322.'
  mla: 'Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow
    for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” <i>Proc. Int. Conf.
    on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press,
    2009, pp. 319–22.'
  short: 'M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable
    Systems and Algorithms (ERSA), CSREA Press, USA, 2009, pp. 319–322.'
date_created: 2018-04-06T15:19:51Z
date_updated: 2023-09-26T13:53:30Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
language:
- iso: eng
page: 319-322
place: USA
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
  (ERSA)
publication_identifier:
  isbn:
  - 1-60132-101-5
publisher: CSREA Press
quality_controlled: '1'
status: public
title: 'Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension
  on Xilinx Virtex-4 FX'
type: conference
user_id: '15278'
year: '2009'
...
---
_id: '2370'
author:
- first_name: Matthias
  full_name: Woehrle, Matthias
  last_name: Woehrle
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Roman
  full_name: Lim, Roman
  last_name: Lim
- first_name: Jan
  full_name: Beutel, Jan
  last_name: Beutel
- first_name: Lothar
  full_name: Thiele, Lothar
  last_name: Thiele
citation:
  ama: 'Woehrle M, Plessl C, Lim R, Beutel J, Thiele L. EvAnT: Analysis and Checking
    of event traces for Wireless Sensor Networks. In: <i>IEEE Int. Conf. on Sensor
    Networks, Ubiquitous, and Trustworthy Computing (SUTC)</i>. IEEE Computer Society;
    2008:201-208. doi:<a href="https://doi.org/10.1109/SUTC.2008.24">10.1109/SUTC.2008.24</a>'
  apa: 'Woehrle, M., Plessl, C., Lim, R., Beutel, J., &#38; Thiele, L. (2008). EvAnT:
    Analysis and Checking of event traces for Wireless Sensor Networks. <i>IEEE Int.
    Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC)</i>, 201–208.
    <a href="https://doi.org/10.1109/SUTC.2008.24">https://doi.org/10.1109/SUTC.2008.24</a>'
  bibtex: '@inproceedings{Woehrle_Plessl_Lim_Beutel_Thiele_2008, place={Los Alamitos,
    CA, USA}, title={EvAnT: Analysis and Checking of event traces for Wireless Sensor
    Networks}, DOI={<a href="https://doi.org/10.1109/SUTC.2008.24">10.1109/SUTC.2008.24</a>},
    booktitle={IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing
    (SUTC)}, publisher={IEEE Computer Society}, author={Woehrle, Matthias and Plessl,
    Christian and Lim, Roman and Beutel, Jan and Thiele, Lothar}, year={2008}, pages={201–208}
    }'
  chicago: 'Woehrle, Matthias, Christian Plessl, Roman Lim, Jan Beutel, and Lothar
    Thiele. “EvAnT: Analysis and Checking of Event Traces for Wireless Sensor Networks.”
    In <i>IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing
    (SUTC)</i>, 201–8. Los Alamitos, CA, USA: IEEE Computer Society, 2008. <a href="https://doi.org/10.1109/SUTC.2008.24">https://doi.org/10.1109/SUTC.2008.24</a>.'
  ieee: 'M. Woehrle, C. Plessl, R. Lim, J. Beutel, and L. Thiele, “EvAnT: Analysis
    and Checking of event traces for Wireless Sensor Networks,” in <i>IEEE Int. Conf.
    on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC)</i>, 2008, pp.
    201–208, doi: <a href="https://doi.org/10.1109/SUTC.2008.24">10.1109/SUTC.2008.24</a>.'
  mla: 'Woehrle, Matthias, et al. “EvAnT: Analysis and Checking of Event Traces for
    Wireless Sensor Networks.” <i>IEEE Int. Conf. on Sensor Networks, Ubiquitous,
    and Trustworthy Computing (SUTC)</i>, IEEE Computer Society, 2008, pp. 201–08,
    doi:<a href="https://doi.org/10.1109/SUTC.2008.24">10.1109/SUTC.2008.24</a>.'
  short: 'M. Woehrle, C. Plessl, R. Lim, J. Beutel, L. Thiele, in: IEEE Int. Conf.
    on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC), IEEE Computer
    Society, Los Alamitos, CA, USA, 2008, pp. 201–208.'
date_created: 2018-04-17T12:03:20Z
date_updated: 2023-09-26T13:55:02Z
department:
- _id: '27'
- _id: '518'
doi: 10.1109/SUTC.2008.24
keyword:
- WSN
- testing
- verification
language:
- iso: eng
page: 201-208
place: Los Alamitos, CA, USA
publication: IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing
  (SUTC)
publication_identifier:
  isbn:
  - 978-0-7695-3158-8
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: 'EvAnT: Analysis and Checking of event traces for Wireless Sensor Networks'
type: conference
user_id: '15278'
year: '2008'
...
---
_id: '2364'
author:
- first_name: Tobias
  full_name: Schumacher, Tobias
  last_name: Schumacher
- first_name: Robert
  full_name: Meiche, Robert
  last_name: Meiche
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Enno
  full_name: Lübbers, Enno
  last_name: Lübbers
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Schumacher T, Meiche R, Kaufmann P, Lübbers E, Plessl C, Platzner M. A Hardware
    Accelerator for k-th Nearest Neighbor Thinning. In: <i>Proc. Int. Conf. on Engineering
    of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2008:245-251.'
  apa: Schumacher, T., Meiche, R., Kaufmann, P., Lübbers, E., Plessl, C., &#38; Platzner,
    M. (2008). A Hardware Accelerator for k-th Nearest Neighbor Thinning. <i>Proc.
    Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>,
    245–251.
  bibtex: '@inproceedings{Schumacher_Meiche_Kaufmann_Lübbers_Plessl_Platzner_2008,
    title={A Hardware Accelerator for k-th Nearest Neighbor Thinning}, booktitle={Proc.
    Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA
    Press}, author={Schumacher, Tobias and Meiche, Robert and Kaufmann, Paul and Lübbers,
    Enno and Plessl, Christian and Platzner, Marco}, year={2008}, pages={245–251}
    }'
  chicago: Schumacher, Tobias, Robert Meiche, Paul Kaufmann, Enno Lübbers, Christian
    Plessl, and Marco Platzner. “A Hardware Accelerator for K-Th Nearest Neighbor
    Thinning.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and
    Algorithms (ERSA)</i>, 245–51. CSREA Press, 2008.
  ieee: T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, and M. Platzner,
    “A Hardware Accelerator for k-th Nearest Neighbor Thinning,” in <i>Proc. Int.
    Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2008,
    pp. 245–251.
  mla: Schumacher, Tobias, et al. “A Hardware Accelerator for K-Th Nearest Neighbor
    Thinning.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
    (ERSA)</i>, CSREA Press, 2008, pp. 245–51.
  short: 'T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, M. Platzner,
    in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
    CSREA Press, 2008, pp. 245–251.'
date_created: 2018-04-17T11:33:32Z
date_updated: 2023-09-26T13:54:24Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
language:
- iso: eng
page: 245-251
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
  (ERSA)
publication_identifier:
  isbn:
  - 1-60132-064-7
publisher: CSREA Press
quality_controlled: '1'
status: public
title: A Hardware Accelerator for k-th Nearest Neighbor Thinning
type: conference
user_id: '15278'
year: '2008'
...