---
_id: '2430'
abstract:
- lang: eng
  text: In this report the design and implementation of an instance-specific accelerator
    for solving minimum covering problems will be presented. After an introduction
    to configurable computing in general, the minimum covering problem is defined
    and a branch and bound algorithm to solve it in software is presented. The remainder
    of the report shows how this branch and bound algorithm can be adopted to hardware.
    Specifically it is stressed how the various sophisticated strategies for deducing
    conditions for variables used by software solvers can be adopted to hardware and
    how a system which uses 3-valued logic to solve this problem can be designed.
    In addition to these considerations focusing on the architecture of the system,
    some important details of the actual implementation are given. A prototype has
    been implemented for showing the feasibility of the concept and for gaining information
    about speed and size of the hardware implementation. Cycle-accurate simulations
    for a set of benchmark problems have been done for determining the performance
    of the accelerator. The speed of the resulting accelerators has been compared
    to the time a reference software solver (espresso) needs and the resulting speedups
    have been calculated. I have shown that a raw speedup of several orders of maginitude
    can be achieved for many problems; for some problems no speedup is achieved yet.
    After a discussion of the results, ideas for future work are presented.
author:
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
citation:
  ama: Plessl C. <i>Reconfigurable Accelerators for Minimum Covering</i>. Computer
    Engineering and Networks Lab, ETH Zurich, Switzerland; 2001.
  apa: Plessl, C. (2001). <i>Reconfigurable Accelerators for Minimum Covering</i>.
    Computer Engineering and Networks Lab, ETH Zurich, Switzerland.
  bibtex: '@book{Plessl_2001, title={Reconfigurable Accelerators for Minimum Covering},
    publisher={Computer Engineering and Networks Lab, ETH Zurich, Switzerland}, author={Plessl,
    Christian}, year={2001} }'
  chicago: Plessl, Christian. <i>Reconfigurable Accelerators for Minimum Covering</i>.
    Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2001.
  ieee: C. Plessl, <i>Reconfigurable Accelerators for Minimum Covering</i>. Computer
    Engineering and Networks Lab, ETH Zurich, Switzerland, 2001.
  mla: Plessl, Christian. <i>Reconfigurable Accelerators for Minimum Covering</i>.
    Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2001.
  short: C. Plessl, Reconfigurable Accelerators for Minimum Covering, Computer Engineering
    and Networks Lab, ETH Zurich, Switzerland, 2001.
date_created: 2018-04-17T15:47:26Z
date_updated: 2022-01-06T06:56:17Z
department:
- _id: '518'
publisher: Computer Engineering and Networks Lab, ETH Zurich, Switzerland
status: public
title: Reconfigurable Accelerators for Minimum Covering
type: mastersthesis
user_id: '24135'
year: '2001'
...
---
_id: '2432'
abstract:
- lang: eng
  text: In this paper, we present the analysis of applications from the domain of
    handheld and wearable computing. This analysis is the first step to derive and
    evaluate design parameters for dynamically reconfigurable processors. We discuss
    the selection of representative benchmarks for handhelds and wearables and group
    the applications into multimedia, communications, and cryptography programs. We
    simulate the applications on a cycle-accurate processor simulator and gather statistical
    data such as instruction mix, cache hit rates and memory requirements for an embedded
    processor model. A breakdown of the executed cycles into different functions identifies
    the most compute-intensive code sections - the kernels. Then, we analyze the applications
    and discuss parameters that strongly influence the design of dynamically reconfigurable
    processors. Finally, we outline the construction of a parameterizable simulation
    model for a reconfigurable unit that is attached to a processor core.
author:
- first_name: Rolf
  full_name: Enzler, Rolf
  last_name: Enzler
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Lothar
  full_name: Thiele, Lothar
  last_name: Thiele
- first_name: Gerhard
  full_name: Tröster, Gerhard
  last_name: Tröster
citation:
  ama: 'Enzler R, Platzner M, Plessl C, Thiele L, Tröster G. Reconfigurable Processors
    for Handhelds and Wearables: Application Analysis. In: <i>Reconfigurable Technology:
    FPGAs and Reconfigurable Processors for Computing and Communications III</i>.
    Vol 4525. Proc. SPIE. ; 2001:135-146. doi:<a href="https://doi.org/10.1117/12.434376">10.1117/12.434376</a>'
  apa: 'Enzler, R., Platzner, M., Plessl, C., Thiele, L., &#38; Tröster, G. (2001).
    Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In
    <i>Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing
    and Communications III</i> (Vol. 4525, pp. 135–146). <a href="https://doi.org/10.1117/12.434376">https://doi.org/10.1117/12.434376</a>'
  bibtex: '@inproceedings{Enzler_Platzner_Plessl_Thiele_Tröster_2001, series={Proc.
    SPIE}, title={Reconfigurable Processors for Handhelds and Wearables: Application
    Analysis}, volume={4525}, DOI={<a href="https://doi.org/10.1117/12.434376">10.1117/12.434376</a>},
    booktitle={Reconfigurable Technology: FPGAs and Reconfigurable Processors for
    Computing and Communications III}, author={Enzler, Rolf and Platzner, Marco and
    Plessl, Christian and Thiele, Lothar and Tröster, Gerhard}, year={2001}, pages={135–146},
    collection={Proc. SPIE} }'
  chicago: 'Enzler, Rolf, Marco Platzner, Christian Plessl, Lothar Thiele, and Gerhard
    Tröster. “Reconfigurable Processors for Handhelds and Wearables: Application Analysis.”
    In <i>Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing
    and Communications III</i>, 4525:135–46. Proc. SPIE, 2001. <a href="https://doi.org/10.1117/12.434376">https://doi.org/10.1117/12.434376</a>.'
  ieee: 'R. Enzler, M. Platzner, C. Plessl, L. Thiele, and G. Tröster, “Reconfigurable
    Processors for Handhelds and Wearables: Application Analysis,” in <i>Reconfigurable
    Technology: FPGAs and Reconfigurable Processors for Computing and Communications
    III</i>, 2001, vol. 4525, pp. 135–146.'
  mla: 'Enzler, Rolf, et al. “Reconfigurable Processors for Handhelds and Wearables:
    Application Analysis.” <i>Reconfigurable Technology: FPGAs and Reconfigurable
    Processors for Computing and Communications III</i>, vol. 4525, 2001, pp. 135–46,
    doi:<a href="https://doi.org/10.1117/12.434376">10.1117/12.434376</a>.'
  short: 'R. Enzler, M. Platzner, C. Plessl, L. Thiele, G. Tröster, in: Reconfigurable
    Technology: FPGAs and Reconfigurable Processors for Computing and Communications
    III, 2001, pp. 135–146.'
date_created: 2018-04-17T15:51:39Z
date_updated: 2022-01-06T06:56:17Z
department:
- _id: '518'
- _id: '78'
doi: 10.1117/12.434376
intvolume: '      4525'
keyword:
- benchmark
page: 135-146
publication: 'Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing
  and Communications III'
series_title: Proc. SPIE
status: public
title: 'Reconfigurable Processors for Handhelds and Wearables: Application Analysis'
type: conference
user_id: '24135'
volume: 4525
year: '2001'
...
---
_id: '2433'
author:
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Simon
  full_name: Maurer, Simon
  last_name: Maurer
citation:
  ama: Plessl C, Maurer S. <i>Hardware/Software Codesign in Speech Compression Applications</i>.
    Computer Engineering and Networks Lab, ETH Zurich, Switzerland; 2000.
  apa: Plessl, C., &#38; Maurer, S. (2000). <i>Hardware/Software Codesign in Speech
    Compression Applications</i>. Computer Engineering and Networks Lab, ETH Zurich,
    Switzerland.
  bibtex: '@book{Plessl_Maurer_2000, title={Hardware/Software Codesign in Speech Compression
    Applications}, publisher={Computer Engineering and Networks Lab, ETH Zurich, Switzerland},
    author={Plessl, Christian and Maurer, Simon}, year={2000} }'
  chicago: Plessl, Christian, and Simon Maurer. <i>Hardware/Software Codesign in Speech
    Compression Applications</i>. Computer Engineering and Networks Lab, ETH Zurich,
    Switzerland, 2000.
  ieee: C. Plessl and S. Maurer, <i>Hardware/Software Codesign in Speech Compression
    Applications</i>. Computer Engineering and Networks Lab, ETH Zurich, Switzerland,
    2000.
  mla: Plessl, Christian, and Simon Maurer. <i>Hardware/Software Codesign in Speech
    Compression Applications</i>. Computer Engineering and Networks Lab, ETH Zurich,
    Switzerland, 2000.
  short: C. Plessl, S. Maurer, Hardware/Software Codesign in Speech Compression Applications,
    Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2000.
date_created: 2018-04-17T15:56:00Z
date_updated: 2022-01-06T06:56:17Z
department:
- _id: '518'
keyword:
- co-design
- speech processing
publisher: Computer Engineering and Networks Lab, ETH Zurich, Switzerland
status: public
title: Hardware/Software Codesign in Speech Compression Applications
type: mastersthesis
user_id: '24135'
year: '2000'
...