@article{23476, author = {{Weizel, Maxim and Scheytt, J. Christoph and Kärtner, Franz X. and Witzens, Jeremy}}, issn = {{1094-4087}}, journal = {{Optics Express}}, title = {{{Optically clocked switched-emitter-follower THA in a photonic SiGe BiCMOS technology}}}, doi = {{10.1364/oe.425710}}, year = {{2021}}, } @inproceedings{24022, abstract = {{In this paper we propose a novel low-power receiver architecture which uses a direct-detection receiver in combination with a 2.44 GHz 13 bit Barker Code SAW correlator for improvement of co-channel interference. Furthermore, to improve receiver sensitivity, a narrowband baseband correlator which uses pulse position modulation (PPM) is proposed. The receiver can be used as a Wake-up Receiver (WuRx) in Wireless Sensor Networks (WSN) to minimize the power dissipation and provide asynchronous and on-demand data communication. We present a rigorous analysis of the receiver. It shows that the RF front-end (SAW correlator and envelope detector) alone suffers from poor sensitivity due to the high baseband bandwidth and the absence of an RF low noise amplifier. However, by adding the narrowband correlator with an innovative Pulse Position Modulation (PPM) scheme, the overall sensitivity of the receiver reaches -63.1 dB with an improvement of 17.7 dB due to the use of the narrowband correlator that reduces the baseband bandwidth from 50 to 0.84 MHz. By scaling the narrowband correlator bandwidth further down, the receiver sensitivity can be further improved.}}, author = {{Abughannam, Saed and Scheytt, Christoph}}, booktitle = {{IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC 2020) }}, publisher = {{IEEE}}, title = {{{Sensitivity Analysis of a Low-Power Wake-Up Receiver Using an RF Barker Code SAW Correlator and a Baseband Narrowband Correlator}}}, doi = {{10.1109/PIMRC48278.2020.9217198}}, year = {{2020}}, } @inproceedings{24027, abstract = {{Fault effect simulation is a well-established technique for the qualification of robust embedded software and hardware as required by different safety standards. Our article introduces a Virtual Prototype based approach for the fault analysis and fast simulation of a set of automatically generated and target compiled software programs. The approach scales to different RISC-V ISA standard subset configurations and is based on an instruction and hardware register coverage for automatic fault injections of permanent and transient bitflips. The analysis of each software binary evaluates its opcode type and register access coverage including the addressed memory space. Based on this information dedicated sets of fault injected hardware models, i.e., mutants, are generated. The simulation of all mutants conducted with the different binaries finally identifies the cases with a normal termination though executed on a faulty hardware model. They are identified as a subject for further investigations and improvements by the implementation of additional hardware or software safety countermeasures. Our final evaluation results with automatic C code generation, compilation, analysis, and simulation show that QEMU provides an adequate efficient platform, which also scales to more complex scenarios.}}, author = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}}, booktitle = {{MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop}}, title = {{{A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures}}}, year = {{2020}}, } @inproceedings{24030, abstract = {{Low-power receivers use direct-detection receiver architecture for its design simplicity and its low power dissipation. However, the direct-detection based receivers suffer from co-channel interference which significantly degrades the communication reliability. Co-channel interference robustness can be improved by using a BPSK Barker code modulated Surface Acoustic Wave (SAW) correlator as a prior stage to the RF direct detection circuit. This paper reports in details the design, fabrication and measurements of a 2.45 GHz SAW correlator with 13 bits length Barker code. The device is fabricated on Lithium Niobate LiNbO3 substrate and it is composed of an input non-coded Inter Digital Transducers (IDT), a Piezoelectric substrate and an output coded IDT. The device wavelength λ is set to 1.6 μm, considering a phase velocity of the wave equal to 3970 m.s-1. Several configurations of the device were designed and fabricated, particularly varying the aperture and the non-coded IDT length to find out the optimal device configuration. All devices were found to operate with Insertion Loss (IL) ranging from 12 to 15 dB at 2.45 GHz with a tip probing measurement setup, while a packaged sample has an IL of 12.45 dB at 2.44 GHz mounted on a PCB with external 50 Ω LC matching network. Additionally, time-domain measurement for the packaged device shows that the output has a correlation peak with a peak-to-side-lobe (PSL) ratio of 4:1 for a -0.5 dBm input BPSK Barker code signal.}}, author = {{Ballandras, Sylvain and Abughannam, Saed and Courjon, Emilie and Scheytt, Christoph}}, booktitle = {{GeMiC 2020 - German Microwave Conference}}, title = {{{Design and Fabrication of Barker Coded Surface Acoustic Wave (SAW) Correlator at 2.45 GHz for Low-Power Wake-up Receivers}}}, year = {{2020}}, } @inproceedings{24020, abstract = {{Novel analog-to-digital converter (ADC) architectures are motivated by the demand for rising sampling rates and effective number of bits (ENOB). The main limitation on ENOB in purely electrical ADCs lies in the relatively high jitter of oscillators, in the order of a few tens of fs for state-of-the-art components. When compared to the extremely low jitter obtained with best-in-class Ti:sapphire mode-locked lasers (MLL), in the attosecond range, it is apparent that a mixed electrical-optical architecture could significantly improve the converters' ENOB. We model and analyze the ENOB limitations arising from optical sources in optically enabled, spectrally sliced ADCs, after discussing the system architecture and implementation details. The phase noise of the optical carrier, serving for electro-optic signal transduction, is shown not to propagate to the reconstructed digitized signal and therefore not to represent a fundamental limit. The optical phase noise of the MLL used to generate reference tones for individual slices also does not fundamentally impact the converted signal, so long as it remains correlated among all the comb lines. On the other hand, the timing jitter of the MLL, as also reflected in its RF linewidth, is fundamentally limiting the ADC performance, since it is directly mapped as jitter to the converted signal. The hybrid nature of a photonically enabled, spectrally sliced ADC implies the utilization of a number of reduced bandwidth electrical ADCs to convert parallel slices, resulting in the propagation of jitter from the electrical oscillator supplying their clock. Due to the reduced sampling rate of the electrical ADCs, as compared to the overall system, the overall noise performance of the presented architecture is substantially improved with respect to a fully electrical ADC.}}, author = {{Zazzi, Andrea and Müller, Juliana and Gudyriev, Sergiy and Marin-Palomo, Pablo and Fang, Dengyang and Scheytt, Christoph and Koos, Christian and Witzens, Jeremy}}, booktitle = {{21. ITG-Fachtagung Photonische Netze}}, publisher = {{VDE-Verlag}}, title = {{{Mode-locked laser timing jitter limitation in optically enabled frequency-sliced ADCs}}}, year = {{2020}}, } @article{24025, abstract = {{The effect of phase noise introduced by optical sources in spectrally-sliced optically enabled DACs and ADCs is modeled and analyzed in detail. In both data converter architectures, a mode-locked laser is assumed to provide an optical comb whose lines are used to either synthesize or analyze individual spectral slices. While the optical phase noise of the central MLL line as well as of other optical carriers used in the analyzed system architectures have a minor impact on the system performance, the RF phase noise of the MLL fundamentally limits it. In particular, the corresponding jitter of the MLL pulse train is transferred almost one-to-one to the system-level timing jitter of the data converters. While MLL phase noise can in principle be tracked and removed by electronic signal processing, this results in electric oscillator phase noise replacing the MLL jitter and is not conducive in systems leveraging the ultra-low jitter of low-noise mode-locked lasers. Precise analytical models are derived and validated by detailed numerical simulations.}}, author = {{Zazzi, Andrea and Müller, Juliana and Gudyriev, Sergiy and Marin-Palomo, Pablo and Fang, Dengyang and Scheytt, Christoph and Koos, Christian and Witzens, Jeremy}}, journal = {{Opt. Express}}, title = {{{Fundamental limitations of spectrally-sliced optically enabled data converters arising from MLL timing jitter}}}, doi = {{10.1364/OE.382832}}, volume = {{28}}, year = {{2020}}, } @inproceedings{24028, abstract = {{A 28 Gbps NRZ bang-bang clock and data recovery (CDR) chip for 100G PSM4 is presented. It exhibits an adaptable loop filter transfer function with independently tunable proportional and integral parameters. This allows to optimize the jitter transfer, jitter tolerance, and locking range of the CDR according to system requirements. The CDR represents a key component for a single-chip 8-channel electronic-photonic PSM4 transceiver. A CDR chip was manufactured in a 0.25 μm monolithic photonic BiCMOS technology. The core chip area is 0.51 mm 2 and it dissipates 330 mW from 2.5 V and 3.3 V power supplies.}}, author = {{Iftekhar, Mohammed and Gudyriev, Sergiy and Scheytt, Christoph}}, booktitle = {{2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)}}, publisher = {{IEEE}}, title = {{{28 Gbps Bang-Bang CDR for 100G PSM4 with Independently Tunable Proportional and Integral Parameters of the Loop Filter in 0.25 µm Photonic BiCMOS Technology}}}, doi = {{10.1109/SIRF46766.2020.9040190}}, year = {{2020}}, } @inproceedings{24024, abstract = {{Recently it has been demonstrated that an optoelectronic phase-locked loop (OEPLL) using a mode-locked laser as a reference oscillator achieves significantly lower phase noise than conventional electronic frequency synthesizers. In this paper a concept for an OEPLL-based frequency synthesizer is presented and it is investigated how it can be used as a local oscillator (LO) for THz transceivers in order to improve the signal quality in THz wireless communications. The concept of the OEPLL is presented and it's measured phase noise is compared to the phase noise of a laboratory-grade electronic frequency synthesizer. The measured phase noise spectra of both synthesizers at 10 GHz are then used to model LO phase noise at 320 GHz. Based on models of generic zero-IF transmit and receive frontends, THz signals with different modulation formats and Baud rates are simulated at system level using the modeled LO phase noise for the two LO approaches. Finally, the results are compared.}}, author = {{Scheytt, Christoph and Wrana, Dominik and Bahmanian, Meysam and Kallfass, Ingmar}}, booktitle = {{2020 Third International Workshop on Mobile Terahertz Systems (IWMTS)}}, location = {{Essen, Germany }}, title = {{{Ultra-Low Phase Noise Frequency Synthesis for THz Communications Using Optoelectronic PLLs}}}, doi = {{10.1109/IWMTS49292.2020.9166347}}, year = {{2020}}, } @inproceedings{24023, abstract = {{This paper presents an ultra-wideband and ultra-low noise frequency synthesizer using a mode-locked laser as its reference. The frequency synthesizer can lock in the frequency range from 2 GHz to 20 GHz on any harmonic of a mode-locked laser optical pulse train. The integrated rms-jitter (1 kHz-100 MHz) of the synthesizer is less than 5 fs in the frequency range from 4 GHz to 20 GHz with a typical value of 4 fs and a minimum of 3 fs. This is the first reported wideband phase locked loop achieving sub-10 fs rms-jitter for offset frequencies larger than 1 kHz.}}, author = {{Bahmanian, Meysam and Fard, Saeed and Koppelmann, Bastian and Scheytt, Christoph}}, booktitle = {{ 2020 IEEE/MTT-S International Microwave Symposium (IMS)}}, publisher = {{IEEE}}, title = {{{Wide-Band Frequency Synthesizer with Ultra-Low Phase Noise Using an Optical Clock Source}}}, doi = {{10.1109/IMS30576.2020.9224118}}, year = {{2020}}, } @inproceedings{24021, abstract = {{This paper presents a broadband track-and-hold amplifier (THA) based on switched-emitter-follower (SEF) topology. The THA exhibits both large- and small-signal bandwidth exeeding 60 GHz. It achieves an effective number of bits (ENOB) of 7 bit at 34 GHz input frequency and an ENOB of >5 bit over the whole input frequency bandwidth at sampling rate of 10 GS/s. Much higher sampling rates are possible but lead to somewhat worse performance. The chip was fabricated in a 130 nm SiGe BiCMOS technology from IHP (SG13G2). It draws 78 mA from a -4.8 V supply voltage, dissipating 375 mW.}}, author = {{Wu, Liang and Weizel, Maxim and Scheytt, Christoph}}, booktitle = {{2020 IEEE International Symposium on Circuits and Systems (ISCAS)}}, isbn = {{978-1-7281-3320-1}}, issn = {{2158-1525 }}, publisher = {{IEEE}}, title = {{{Above 60 GHz Bandwidth 10 GS/s Sampling Rate Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology}}}, doi = {{10.1109/ISCAS45731.2020.9180947}}, year = {{2020}}, } @article{24029, abstract = {{In this paper we present the system and circuit level analysis and feasibility study of applying microwave Radio Frequency Identification (RFID) systems with multipleinput multiple-output (MIMO) reader technology for tracking machining tools in multipath fading conditions of production environments. In the proposed system the MIMO reader interrogates single-antenna tags, and a high RFID frequency of 5.8 GHz is chosen to reduce the size of the reader's antenna array. According to the requirements dictated by the performed system analysis at 5.8 GHz, a low power fully integrated analog frontend (AFE) is designed and fabricated in a standard 65-nm CMOS technology for low power passive transponders. Performance of the Differential Drive Rectifier (DDR) topology as the core of the energy harvesting unit is investigated in detail. A multi-stage DDR power scavenging unit is dimensioned to provide a 1.2 V rectified voltage for 20-30 kQ load range, with a high power conversion efficiency (PCE) for high frequency and low input power level signals. The rectified voltage is then converted to a 1 V regulated voltage for the AFE and the baseband processor with 30 to 50 μW of estimated power consumption. Transistors with standard threshold voltage (VT) have been used for implementation. Measurements of the fabricated multi-stage configuration of the circuit show a maximum PCE of 68.8% at -12.46 dBm, and an input quality factor (Q-factor) of approximately 10. Amplitude-shift keying (ASK) demodulator and backscattering modulator with 80% modulation index, operating according to EPC-C1G2 protocol are applied for data transfer. The AFE consumes less than 1 μW in the reading mode. The AFE tag chip is 0.55 × 0.58 mm 2 .}}, author = {{Haddadian, Sanaz and Scheytt, Christoph}}, journal = {{IEEE Journal of Radio Frequency Identification}}, pages = {{1--1}}, title = {{{Analysis, Design and Implementation of a Fully Integrated Analog Front-End for Microwave RFIDs at 5.8 GHz to be Used with Compact MIMO Readers}}}, doi = {{10.1109/JRFID.2020.3009741}}, year = {{2020}}, } @inproceedings{24026, abstract = {{In this paper we present a new system concept for an optoelectronic wireless phased array system. Like in a conventional phased array system with optical carrier distribution, optical fibers are used to distribute the carrier from the basestation to the wireless frontends. However in contrast to prior concepts, we propose to use an optical IQ return path from the wireless frontends back to the basestation. Furthermore, we reuse the optical carrier signal for the IQ return path which allows to avoid local oscillator lasers in the wireless frontends and reduces the hardware effort significantly. The system concept allows to integrate all components of an optoelectronic wireless frontend in a single chip using silicon photonics technology.}}, author = {{Kruse, Stephan and Kress, Christian and Scheytt, Christoph and Kurz, Heiko G. and Schneider, Thomas}}, booktitle = {{GeMiC 2020 - German Microwave Conference}}, title = {{{Analysis and Simulation of a Wireless Phased Array System with Optical Carrier Distribution and an Optical IQ Return Path}}}, year = {{2020}}, } @inproceedings{23479, author = {{Weizel, Maxim and Kaertner, Franz X. and Witzens, Jeremy and Scheytt, J. Christoph}}, booktitle = {{Photonic Networks; 21th ITG-Symposium}}, location = {{Online}}, pages = {{1--6}}, publisher = {{VDE}}, title = {{{Photonic Analog-to-Digital-Converters – Comparison of a MZM-Sampler with an Optoelectronic Switched-Emitter-Follower Sampler}}}, year = {{2020}}, } @inproceedings{24053, abstract = {{We overview the 3-year Meteracom project which will provide traceability to the SI for THz communication measurement parameters. The key objectives are to develop new metrological methods to characterize the measurement systems, system components and propagation channels. The final objective is to develop metrology for functionality and signal integrity of THz communication systems; particularly device discovery and beam tracking, determination of physical layer parameters for digital transmission and real-time performance evaluation.}}, author = {{Humphreys, David and Berekovic, Mladen and Kallfass, Ingmar and Scheytt, Christoph and Kuerner, Thomas and Jukan, Admela and Schneider, Thomas and Kleine-Ostmann, Thomas and Koch, Martin and Thomae, Reiner}}, booktitle = {{Proc. 43-nd Meeting of the Wireless World Research Forum (WWRF)",}}, title = {{{An overview of the Meteracom Project}}}, year = {{2019}}, } @inproceedings{24058, abstract = {{Embedded systems require a high energy efficiency in combination with an optimized performance. As such, Bit Manipulation Instructions (BMIs) were introduced for x86 and ARMv8 to improve the runtime efficiency and power dissipation of the compiled software for various applications. Though the RISC-V platform is meanwhile widely accepted for embedded systems application, its instruction set architecture (ISA) currently still supports only two basic BMIs.We introduce ten advanced BMIs for the RISC-V ISA and implemented them on Berkeley's Rocket CPU [1], which we synthesized for the Artix-7 FPGA and the TSMC 65nm cell library. Our RISC-V BMI definitions are based on an analysis and combination of existing x86 and ARMv8 BMIs. Our Rocket CPU hardware extensions show that RISC-V BMI extensions have no negative impact on the critical path of the execution pipeline. Our software evaluations show that we can, for example, expect a significant impact for time and power consuming cryptographic applications.}}, author = {{Koppelmann, Bastian and Adelt, Peer and Müller, Wolfgang and Scheytt, Christoph}}, booktitle = {{29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)}}, title = {{{RISC-V Extensions for Bit Manipulation Instructions}}}, doi = {{10.1109/PATMOS.2019.8862170}}, year = {{2019}}, } @inproceedings{24060, abstract = {{In diesem Artikel stellen wir eine Methode zur nicht-invasiven dynamischen Speicher- und IO-Analyse mit QEMU für sicherheitskritische eingebettete Software für die RISC-V Befehlssatzarchitektur vor. Die Implementierung basiert auf einer Erweiterung des Tiny Code Generator (TCG) des quelloffenen CPU-Emulators QEMU um die dynamische Identifikation von Zugriffen auf Datenspeicher sowie auf an die CPU angeschlossene IO-Geräte. Wir demonstrieren die Funktionalität der Methode anhand eines Versuchsaufbaus, bei dem eine Schließsystemkontrolle mittels serieller UART-Schnittstelle an einen RISC-V-Prozessor angebunden ist. Dieses Szenario zeigt, dass ein unberechtigter Zugriff auf die UART-Schnittstelle frühzeitig aufgedeckt und ein Angriff auf eine Zugangskontrolle somit endeckt werden kann. }}, author = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}}, booktitle = {{MBMV 2019-22.Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2019)}}, isbn = {{978-3-8007-4945-4}}, title = {{{Analyse sicherheitskritischer Software für RISC-V Prozessoren}}}, year = {{2019}}, } @inproceedings{24061, author = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph and Driessen, Benedikt}}, booktitle = {{ 2nd International Workshop on Embedded Software for Industrial IoT in conjunction with DATE 2019}}, pages = {{32--34}}, title = {{{QEMU for Dynamic Memory Analysis of Security Sensitive Software}}}, year = {{2019}}, } @article{24063, abstract = {{It its current Version 3.1.0 QEMU supports RISC-V RV32GC and RV64GC software emulation in user and full system mode. We will first give an overview of the current state of the QEMU RISC-V implementation. Thereafter, we will present the DecodeTree tool, which will be available with the next QEMU release. DecodeTree is a code generator included in QEMU that can generate the program logic for extracting and decoding opcodes and operands from a formal instruction list of the target architecture. This enables the structured implementation of just-in-time compilations to guarantee that the QEMU implementation meets the ISA specification. As such, we completely replaced the existing RISC-V RV32GC and RV64GC implementations by DecodeTree generations in the next official QEMU release, which is expected in spring 2019. We will demonstrate the DecodeTree applications by the example of RISC-V ISA subset configurations.}}, author = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}}, journal = {{2nd International Workshop on RISC-V Research Activities}}, title = {{{QEMU Support for RISC-V: Current State and Future Releases}}}, volume = {{(Presentation)}}, year = {{2019}}, } @inproceedings{24055, abstract = {{An octave-band voltage-controlled oscillator is phase-locked on the envelope of the pulse train from a mode-locked laser. The locking scheme employs a balanced Mach-Zehnder modulator with two photodiodes as a phase detector. The phase.locked loop has a loop bandwidth of approximately 1MHz and an in-band phase noise of approximately -135dBc/Hz at all frequencies. The integrated jitter from 1kHz to 100MHz is 21fs, 18.3fs and 13.8fs at 5.016GHz, 7.6GHz and 10.032GHz carrier frequencies, respectively. To the authors' knowledge, this is the best jitter performance reported for a PLL with MZM-based phase detection and the first reported PLL of this type featuring an octave-band frequency range.}}, author = {{Bahmanian, Meysam and Tiedau, Johannes and Silberhorn, Christine and Scheytt, Christoph}}, booktitle = {{2019 International Topical Meeting on Microwave Photonics (MWP)}}, pages = {{1--4}}, title = {{{Octave-Band Microwave Frequency Synthesizer Using Mode-Locked Laser as a Reference}}}, doi = {{10.1109/MWP.2019.8892046}}, year = {{2019}}, } @book{53596, editor = {{Bringmann, Oliver and Ecker, Wolfgang and Müller, Wolfgang and Müller-Gridschneder, Daniel}}, title = {{{Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT}}}, year = {{2019}}, }