@misc{24792, author = {{Bahmanian, Meysam and Scheytt, Christoph}}, title = {{{Theory of an Optoelectronic Microwave Phase-locked Loop based on a MLL reference and MZM-based Optoelectronic Phase Detection}}}, year = {{2019}}, } @inproceedings{24051, abstract = {{Using direct-detection architecture in Radio Frequency (RF) receivers allows for ultra-low power dissipation and is often used in Wake-Up receivers. Unfortunately direct-detection receivers suffer from high sensitivity to co-channel interference which reduces the communication performance and reliability. In this paper, it is shown that co-channel interference robustness of direct-detection receivers is improved by using Binary Phase Shift Keying (BPSK) Barker code modulated Surface Acoustic Wave (SAW) correlator as a prior stage to the RF envelope detector. Replacing the band select filter with SAW correlator does not result in higher receiver hardware cost. In our receiver, the SAW correlator functions as a passive signal processor, providing gain for a BPSK Barker code modulated signal, while suppressing in-band interferers. This improves the co-channel interference robustness of the direct-detection receiver while preserving its advantage of power efficiency. The concept is verified by means of a direct-detection receiver with discrete components on an RF PCB including an SAW Barker Code correlator at a center frequency of 2.44 GHz fabricated on Lithium Niobate substrate. Measurements with WiFi signals demonstrate that the interference robustness is improved by more than 10 dB compared to a conventional direct-detection receiver.}}, author = {{Abughannam, Saed and Fard, Saeed and Scheytt, Christoph}}, booktitle = {{Asia-Pacific Microwave Conference (APMC)}}, location = {{ Singapore }}, title = {{{Improving Co-Channel Interference Robustness In Direct Detection Receivers Using A Surface Acoustic Wave (SAW) Correlator }}}, doi = {{10.1109/APMC46564.2019.9038186}}, year = {{2019}}, } @inproceedings{24052, abstract = {{This paper presents a broadband track-and-hold amplifier (THA) based on switched-emitter-follower (SEF) topology. The THA exhibits a record 3dB small-signal bandwidth of 70 GHz. With the high sampling rate of 40 GS/s, it achieves an effective number of bits (ENOB) of 7.5 bit at 1 GHz input frequency and an ENOB of >5 bit up to 15 GHz input frequency. The chip was fabricated in a 130 nm SiGe BiCMOS technology from IHP (SG13G2). It draws 110 mA from a -4 V supply voltage, dissipating 440 mW.}}, author = {{Wu, Liang and Weizel, Maxim and Scheytt, Christoph}}, booktitle = {{26th IEEE International Conference on Electronics Circuits and Systems (ICECS)}}, title = {{{A 70 GHz Small-signal Bandwidth 40 GS/s Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology}}}, doi = {{10.1109/ICECS46596.2019.8965046}}, year = {{2019}}, } @inproceedings{24049, abstract = {{This paper presents a broadband sampler IC using a current-mode integrated-and-hold-circuit (IHC) as sampling circuit. The sampler IC exhibits 1dB large-signal bandwidth of 70 GHz and excellent signal integrity on hold-mode. With a sampling rate of 5 GS/s, it achieves effective number of bits (ENOB) of 6 bit at 9.9 GHz input frequency. The chip was fabricated in a 130 nm SiGe BiCMOS technology from IHP.}}, author = {{Wu, Liang and Weizel, Maxim and Scheytt, Christoph}}, booktitle = {{Asia-Pacific Microwave Conference (APMC)}}, location = {{Singapore }}, title = {{{70 GHz Large-signal Bandwidth Sampler Using Current-mode Integrate-and-Hold Circuit in 130 nm SiGe BiCMOS Technology}}}, doi = {{10.1109/APMC46564.2019.9038239}}, year = {{2019}}, } @inproceedings{24057, abstract = {{Targeting the feasible application of microwave RFID systems with MIMO reader technology for tracking small objects in multipath fading conditions, we present a fully integrated Analog Front-End (AFE) designed and fabricated in a standard 65-nm CMOS technology for low power passive RFID tags in the 5.8 GHz ISM band. A differential drive power scavenging unit is dimensioned to provide a 1.2 V rectified voltage resulting in a 1 V regulated voltage for the AFE while supplying a 50 μW load. Transistors with standard threshold voltage (V th ) have been used for implementation. Measurements of the fabricated circuits show a maximum Power Conversion Efficiency (PCE) of 71.8% at -12.5 dBm, and an input quality factor (Q-factor) of approximately 10.}}, author = {{Haddadian, Sanaz and Scheytt, Christoph}}, booktitle = {{IEEE International Conference on RFID Technology & Application (RFID-TA) }}, title = {{{A 5.8 GHz CMOS Analog Front-End Targeting RF Energy Harvesting for Microwave RFIDs with MIMO Reader}}}, doi = {{10.1109/RFID-TA.2019.8892037}}, year = {{2019}}, } @inproceedings{24059, abstract = {{We present a complete Visible Light Communication (VLC) system for experimental Vehicular VLC (V-VLC) research activities. Visible light is becoming an important technology complementing existing Radio Frequency (RF) technologies such as Cellular V2X (C-V2X) and Dedicated Short Range Communication (DSRC). In this scope, first works helped introducing new simulation models to explore V-VLC capabilities, technologies, and algorithms. Yet, experimental prototypes are still in an early phase. We aim bridging this gap with our system, which integrates a custom-made driver hardware, commercial vehicle light modules, and an Open Source signal processing implementation in GNU Radio, which explicitly offers rapid prototyping. Our system supports OFDM with a variety of Modulation and Coding Schemes (MCS) and is compliant to IEEE 802.11; this is in line with the upcoming IEEE 802.11 LC standard as well. In an extensive series of experiments, we assessed the communication performance by looking at realistic inter vehicle distances. Our results clearly show that our system supports even higher order MCS with very low error rates over long distances.}}, author = {{Amjad, Muhammad Sohaib and Tebruegge, Claas and Memedi, Agon and Kruse, Stephan and Kress, Christian and Scheytt, Christoph and Dressler, Falko}}, booktitle = {{IEEE International Conference on Communications (ICC)}}, pages = {{1--6}}, publisher = {{ICC 2019 - 2019 IEEE International Conference on Communications (ICC)}}, title = {{{An IEEE 802.11 Compliant SDR-Based System for Vehicular Visible Light Communications}}}, doi = {{10.1109/ICC.2019.8761960}}, year = {{2019}}, } @inproceedings{24048, abstract = {{This paper presents an area-efficient 19.25 GHz to 77 GHz frequency quadrupler for automotive radar applications. To reduce chip area, the delay lines of each doubler stage have been drastically shrunk by means of meandering, slow wave structures, and capacitive loading. Additional circuit techniques were applied to further reduce chip area. Compared to previously published Gilbert cell frequency multipliers the presented quadrupler achieves the shortest electrical length of the delay lines reported so far allowing for compact, low-cost radar transceivers. The chip was implemented in a IHP 130nm SiGe BiCMOS technology (f T /f max =240/340GHz). It dissipates 91.5mW from a 3.3V supply.}}, author = {{Kruse, Stephan}}, booktitle = {{IEEE MTT-S International Microwave and RF Conference 2019}}, publisher = {{IEEE}}, title = {{{An Area Efficient 19.25 GHz to 77 GHz Gilbert Cell Frequency Quadrupler with 55% Shrinked Delay Lines in 130nm SiGe BiCMOS }}}, doi = {{10.1109/IMaRC45935.2019.9118726}}, year = {{2019}}, } @article{24056, abstract = {{Source-free all optical sampling, based on the convolution of the signal spectrum with a frequency comb in an electronic-photonic, co-integrated silicon device will be presented for the first time, to the best of our knowledge. The method has the potential to achieve very high precision, requires only low power and can be fully tunable in the electrical domain. Sampling rates of three and four times the RF bandwidths of the photonics and electronics can be achieved. Thus, the presented method might lead to low-footprint, fully-integrated, precise, electrically tunable, photonic ADCs with very high-analog bandwidths for the digital infrastructure of tomorrow.}}, author = {{Misra, Arijit and Kress, Christian and Singh, Karanveer and Preussler, Stefan and Scheytt, Christoph and Schneider, Thomas}}, journal = {{Opt. Express}}, number = {{21}}, pages = {{29972--29984}}, title = {{{Integrated source-free all optical sampling with a sampling rate of up to three times the RF bandwidth of silicon photonic MZM}}}, doi = {{10.1364/OE.27.029972}}, volume = {{27}}, year = {{2019}}, } @inproceedings{24054, abstract = {{Optical sampling of pseudo random microwave signals with sinc-shaped Nyquist pulse sequences has been demonstrated in an integrated silicon photonics platform. An electronic-photonic, co-integrated depletion type silicon intensity modulator with high extinction ratio has been used to sample the microwave signal with a sampling rate, which corresponds to three times its RF bandwidth. Thus, a sampling rate of 21 GSa/s is achieved with a 7 GHz modulator, with 3 dBm of differential input power.}}, author = {{Misra, Arijit and Kress, Christian and Singh, Karanveer and Preussler, Stefan and Scheytt, Christoph and Schneider, Thomas}}, booktitle = {{2019 International Topical Meeting on Microwave Photonics (MWP)}}, pages = {{1--4}}, title = {{{Integrated All Optical Sampling of Microwave Signals in Silicon Photonics}}}, doi = {{10.1109/MWP.2019.8892128}}, year = {{2019}}, } @inproceedings{24186, abstract = {{A 2nd transconductance subharmonic receiver for 245 GHz spectroscopy sensor applications has been proposed. The receiver consists of a 245 GHz on-chip folded dipole antenna, a CB (common base) LNA, a 2nd transconductance SHM (subharmonic mixer), and a 120 GHz push-push VCO with 1/64 divider. The receiver is fabricated in fT/fmax = 300/500 GHz SiGe:C BiCMOS technology. The receiver dissipates a low power of 288 mW. Integrated with the on-chip antenna, the receiver is measured on-chip with a conversion gain of 15 dB, a bandwidth of 15 GHz, and the chip will be utilized in PCB board design for gas spectroscopy sensor application.}}, author = {{Mao, Yanfei and Shiju, E. and Schmalz, Klaus and Scheytt, Christoph}}, booktitle = {{Journal of Semiconductors}}, title = {{{245 GHz Subharmonic Receiver With Onchip Antenna for Gas Spectroscopy Application}}}, year = {{2018}}, } @inproceedings{24192, abstract = {{The terahertz frequency range provides abundant bandwidth (25GHz ~ 50 GHz) to achieve ultra-high-speed wireless communication and enables data rates up to and above 100 Gbps. We choose Parallel Sequence Spread Spectrum (PSSS) as an analog friendly modulation and coding scheme that allows for an efficient mixed-signal implementation of a 100 Gbps wireless communication system. In our system design, we require a DAC (Digital to Analog converters) running at 1.67 G symbols/sec. The optimization of the bit resolution of this DAC will considerably reduce the hardware implementation efforts. In this work, we presented the analytical model for PSSS modulation and deduced a mathematical formula to calculate the number of discrete level amplitudes along with their probability distribution appearing at the output of the PSSS modulated signal. The analytical analysis assists in predicting the number of the quantization level of the DAC needed at the PSSS transmitter. The theoretical analysis shows that there are in total 225 discrete levels at the output of the PSSS encoder which leads to an 8-bit resolution of DAC. In this paper, we analyzed the variation of BER (Bit Error Rate) to the clipping of low probability amplitude levels and found that there is an only slight increase of the BER when we clip off the low probability amplitude levels. Thus, there is a tradeoff involved in a minor growth of BER concerning the reduction of the DAC bit resolution. Finally, we can reduce the DAC bit resolution from 8 bits to 7 bits and thus simplify the hardware implementation efforts of DAC operating at 1.67 Gbps.}}, author = {{Karthik, KrishneGowda and Wimmer, Lara and Javed, Abdul Rehman and Wolf, Andreas and Scheytt, Christoph and Kraemer, Rolf}}, booktitle = {{15th International Symposium on Wireless Communication Systems (ISWCS) }}, location = {{Lisbon, Portugal }}, publisher = {{IEEE}}, title = {{{Analysis of PSSS modulation for optimization of DAC bit resolution for 100 Gbps systems}}}, doi = {{10.1109/ISWCS.2018.8491216}}, year = {{2018}}, } @article{24194, author = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang}}, journal = {{International Workshop on RISC-V Research Activities}}, location = {{Munich, DE}}, title = {{{Current and Future RISC-V Activities for Virtual Prototyping and Chip Design}}}, volume = {{Presentation}}, year = {{2018}}, } @inproceedings{24195, abstract = {{This paper demonstrates system level analysis of an energy efficient Radio Frequency (RF) receiver. The receiver is based on a Surface Acoustic Wave (SAW) correlator which is used for highly linear demodulation and interferer suppression in conjunction with envelope detection for ultra-low power dissipation and hardware efficiency. The receiver is to be used in Wireless Sensor Networks (WSN) as a Wake-up Receiver (WuR) to reduce the network nodes power dissipation and provide asynchronous data communication. Low latency and high interference robustness makes this scheme interesting for industrial real-time applications. In this paper, the SAW correlator transfer function is derived, which functions as a Matched Filter (MF). Since the receiver uses envelope detection and based on the characteristic of the SAW, the receiver sensitivity is analyzed by means of a non-linear approach.}}, author = {{Abughannam, Saed and Scheytt, Christoph}}, booktitle = {{2nd URSI AT-RASC}}, pages = {{1--4}}, publisher = {{IEEE}}, title = {{{System Analysis of a Wake-Up Receiver Based on Surface Acoustic Wave Correlator}}}, doi = {{10.23919/URSI-AT-RASC.2018.8471531}}, year = {{2018}}, } @inproceedings{24196, abstract = {{This paper presents an approach for analog fault effect simulation automation based on random fault selection with a high fault coverage of the circuit under test by means of fault injection and simulation based on advanced sampling techniques. The random fault selection utilizes the likelihood of the fault occurrence of different electrical components in the circuit with a confidence level. Defect models of different devices are analyzed for the calculation of the fault probability. A case study with our implemented tool demonstrates that likelihood calculation and fault simulation provides means for efficient fault effect simulation automation.}}, author = {{Wu, Liang and Hussain, Mohammad Khizer and Abughannam, Saed and Müller, Wolfgang and Scheytt, Christoph and Ecker, Wolfgang}}, booktitle = {{2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)) }}, publisher = {{IEEE}}, title = {{{Analog fault simulation automation at schematic level with random sampling techniques}}}, doi = {{10.1109/DTIS.2018.8368549}}, year = {{2018}}, } @misc{24198, author = {{Scheytt, Christoph and Wu, Liang}}, title = {{{Integrier‐ und Halte‐Schaltung }}}, year = {{2018}}, } @inproceedings{24199, abstract = {{This work describes a dielectric sensing system applying a 120 GHz electrical interferometer for contactless permittivity measurements. The applied IC was fabricated in a 130 nm SiGe process featuring an ft and fmax of 240 GHz and 330 GHz. The on-chip system contains a 120 GHz VCO with a tuning range of 7 GHz featuring a divide-by-64 circuit to enable external PLL operation. An important feature of the IC is high-precision and high-resolution phase shifting based on a slow-wave transmission lines approach with digital control. This allows for direct digital readout ability. The on chip power detector provides DC output signals giving the opportunity to record transfer functions of the interferometer. It enables sample emulation capability by phase shift inducement in the measurement as well as a reference transmission line. The motherboard of the system provides PLL stabilization for frequency sweeps. The proposed approach is capable of automated dielectric monitoring by phase compensation.}}, author = {{Wessel, Jan and Schmalz, Klaus and Scheytt, Christoph and Kissinger, Dietmar}}, booktitle = {{2018 IEEE Radio and Wireless Symposium (RWS)}}, issn = {{2164-2974 }}, publisher = {{IEEE}}, title = {{{Sensitive permittivity detector for dielectric samples at 120 GHz}}}, doi = {{10.1109/RWS.2018.8304967}}, year = {{2018}}, } @inproceedings{24197, abstract = {{A monolithically integrated coherent receiver in silicon photonic technology is presented along with measurement results for constellation diagrams up to 64GBd and bandwidth of 34 GHz. To our knowledge this is the fastest single-chip coherent receiver.}}, author = {{Kress, Christian and Gudyriev, Sergiy and Zwickel, Heiner and Kemal, Juned N. and Lischke, Stefan and Zimmermann, Lars and Koos, Christian and Scheytt, Christoph}}, booktitle = {{Optical Fiber Communication Conference 2018, San Diego}}, location = {{San Diego, CA, USA }}, title = {{{64 GBd Monolithically Integrated Coherent QPSK Single Polarization Receiver in 0.25 µm SiGe-Photonic Technology}}}, volume = {{Th4A.6}}, year = {{2018}}, } @inproceedings{24189, author = {{Gudyriev, Sergiy and Kress, Christian and Scheytt, Christoph}}, booktitle = {{10th Sino-German Joint Symposium on Opto- and Microelectronic Devices and Circuits (SODC 2018)}}, publisher = {{IEEE}}, title = {{{Electronic Photonic Integrated Circuits for Coherent and Non-Coherent Receivers}}}, year = {{2018}}, } @inproceedings{24188, author = {{Scheytt, Christoph}}, booktitle = {{10th Sino-German Joint Symposium on Opto- and Microelectronic Devices and Circuits (SODC 2018)}}, publisher = {{IEEE}}, title = {{{Ultra‐broadband Signal Processing by means of Electronic‐Photonic Integration}}}, year = {{2018}}, } @inproceedings{24191, author = {{Gudyriev, Sergiy and Kress, Christian and Scheytt, Christoph}}, booktitle = {{DFG Priority Programme SPP2111}}, title = {{{Electronic‐Photonic Integrated Systems for Ultrafast Signal Processing}}}, year = {{2018}}, }