@inproceedings{24222, abstract = {{This paper focuses on the design of a high efficiency cross-connected differential drive rectifier for next-generation passive RFID tags. To provide a realistic estimation of the transponders’power and efficiency requirements at 5.8 GHz, detailed link/power-budget analysis for various blocks of the tag chip is carried out. From link budget analysis realistic RF power levels are obtained and a rectifier with high conversion efficiency at low power levels is designed. Simulations based on a commercial 65nm CMOS technology investigate the suitability of the harvesting circuit for 5.8 GHz RFID tags.}}, author = {{Haddadian, Sanaz and Scheytt, Christoph and Kramer, Roland}}, booktitle = {{ANALOG 2017; 16th ITG/GMM-Symposium}}, pages = {{18}}, publisher = {{Technische Universität Berlin}}, title = {{{Energy Harvesting Analysis for Next Generation Passive RFID Tags}}}, year = {{2017}}, } @inproceedings{24264, abstract = {{Electronic systems, like they are embedded in road vehicles, have to be compliant to functional safety standards like ISO 26262 [1], which limit the impacts of malfunctions for safety critical systems. ISO 26262, for instance, defines different safety levels for road vehicles, which require different means and measures for a safety compliant system and its development process like risk analysis and fault effect simulation. For fault effect simulation it is important to investigate the impact of physical and hardware related effects to the correct function of a system. This article first studies code and model mutations for fault injection in the context of fault effect simulation through different system abstraction levels. It demonstrates how high level mutations correlate to bit flips of software binaries by examples from the TriCore™ instruction set and finally presents a virtual platform based implementation for automated injection of bit flip based mutations into software binaries. Experimental results demonstrate the efficiency of the implemented approach.}}, author = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Becker, Markus and Kleinjohann, Bernd and Scheytt, Christoph}}, booktitle = {{Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC)}}, issn = {{2324-8440}}, title = {{{Fast Dynamic Fault Injection for Virtual Microcontroller Platforms}}}, doi = {{10.1109/VLSI-SoC.2016.7753545}}, year = {{2016}}, } @inproceedings{24265, abstract = {{This paper presents a four stage all-transmission-line 220 GHz differential LNA in SiGe BiCMOS technology. Cascode topology is chosen for each stage. The amplifier takes advantage of microstrip transmission lines to realize the inductive load, Marshand balun, input, output, and inter-stage matching of the LNA. The LNA has a gain of 21 dB at 224 GHz, a 3 dB bandwidth of more than 6 GHz. It has a supply voltage of 3V and power dissipation of 234 mW. The amplifier is intended for the use in communication, security scanning, imaging and remote sensing at 220 GHz.}}, author = {{Mao, Yanfei and Schmalz, Klaus and Scheytt, Christoph and Shiju, E.}}, booktitle = {{IEEE International Symposium on Radio-Frequency Integration Technology}}, title = {{{An all-transmission-line 220 GHz differential LNA in SiGe BiCMOS}}}, doi = {{10.1109/RFIT.2016.7578132}}, year = {{2016}}, } @inproceedings{24263, abstract = {{The design of safety critical systems requires an efficient methodology for an effective fault effect simulation for analog and digital circuits where analog fault injection and fault effect simulation is currently a field of active research and commercial tools are not available yet. This article begins by discussing fault injection strategies for analog circuits applied on a case study with two topologies of a Voltage Controlled Oscillator (VCO). In the second part it performs on the basis of the example of a Wireless Sensor Network (WSN) node, how far different mixed level implementations with Verilog-A and SPICE can affect the simulation time and points out which component consumes the major part of the simulation time.}}, author = {{Abughannam, Saed and Wu, Liang and Müller, Wolfgang and Scheytt, Christoph and Ecker, Wolfgang and Novello, Christiano}}, booktitle = {{Analog 2016 - VDE}}, isbn = {{978-3-8007-4265-3}}, title = {{{Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study}}}, year = {{2016}}, } @inproceedings{24262, abstract = {{Currently, all drone manufactures face the same problem: flight safety utility will become mandatory to obtain the legal admission for broad commercial use of drones. This means that on-board obstacle detection and collision avoidance is a must-have in order to overcome existing legal barriers and acceptance issues. Some of the currently available sensors are too large, too heavy, or can be poorly integrated into existing systems. During the exhibition a demonstration of a novel micro-sensor operating at 120 GHz will be given and participants will have the chance to experience the device first-hand.}}, author = {{Nava, Federico and Genschow, Dieter and Scheytt, Christoph}}, booktitle = {{DRONE Berlin 2016}}, title = {{{Obstacle detection using a miniaturized radar sensor operating at 120GHz ISM band}}}, year = {{2016}}, } @inproceedings{24271, abstract = {{An ultra-broadband analog correlator consisting of a four-quadrant multiplier and an ultra-fast resettable integrator using only NPN transistors was designed, fabricated, and measured. For the integrator, a cross-coupled transistor pair is used as a negative resistance generator. A novel ultra-fast reset circuit is implemented which allows to reset the integrator within very short time of 120 ps. The chip was fabricated using 130 nm SiGe BiCMOS technology with fT of 250 GHz and f max of 300 GHz. In the measurements carried out on printed circuit board, the correlator operated without noticeable performance degradation with inputs up to 33 Gbps which correspond to a bandwidth of more than 24 GHz. The correlator exhibits high linearity with output P1dB of more than 9.9 dBm (700 mV diff ) for both inputs. It dissipates 122.5 mW for the core circuit excluding the 50 Ω output driver. To the knowledge of the authors, the circuit represents the fastest analog correlator published so far. It can be used for spread spectrum communication, radar signal processing, and measurement applications.}}, author = {{Javed, Abdul Rehman and Scheytt, Christoph and Von der Ahe, Uwe}}, booktitle = {{IEEE Bipolar/BiCMOS Circuits and Technology Meeting}}, issn = {{https://ieeexplore.ieee.org/document/7738962}}, publisher = {{IEEE}}, title = {{{Linear ultra-broadband NPN-only analog correlator at 33 Gbps in 130nm SiGe BiCMOS technology}}}, doi = {{ 10.1109/BCTM.2016.7738962}}, year = {{2016}}, } @inproceedings{24269, abstract = {{Today's increasing number of sensors and computation nodes covered by cyber physical systems (CPS) results in rising complexity. For instance, computation results are based on measured data whose quality strongly depends on their age. CPS therefore have real-time requirements on computation results and communication to keep temporal dependency between measured inputs and computed outputs. In addition, today's CPS shall be modular to enable flexibility and scalability, e.g., postulated for production systems in context of Industry 4.0. Enabling CPS to easily integrate components by some Plug-and-Produce mechanism is desired.In this paper, we aim at enabling Plug-and-Produce in CPS using hypervisor-based virtualization. This implies hierarchical scheduling of dependent real-time systems. Here, dependencies are given by precedence constraints of tasks. Based on an approach for detection of new components added to a real-time network, in this paper we focus on integration of enabled applications into the current schedule of a computation node. Here, enabled application refers to an application software that just got executable by plugging some component to the CPS. Applications are encapsulated by virtual machines and provide a self-description including information about required and provided data as well as timing behavior. This self-description is used to adjust global scheduling and thus include new functionality to the CPS.}}, author = {{Jatzkowski, Jan and Adelt, Peer and Rettberg, Achim}}, booktitle = {{3rd International Conference on System-integrated Intelligence: New Challenges for Product and Production Engineering}}, pages = {{227--234}}, publisher = {{Elsevier}}, title = {{{Hierarchical Scheduling for Plug-and-Produce}}}, doi = {{ 10.1016/j.protcy.2016.08.031}}, year = {{2016}}, } @inproceedings{24270, abstract = {{In this paper a prototype of an ultra-compact continuous-wave (CW) and frequency-modulated continuous-wave (FMCW) radar system using a highly-integrated radar chip and in-package antennas will be presented. An introduction will be given on the concept of antenna integration for millimeter-wave radar and the advantages of such systems. The radar then will be described in its main components, a 122 GHz Integrated Circuit including in-package antennas as well as the acquisition and processing system realized using flexible printed circuit board (FLEX PCB) technology. Furthermore initial measurements of the radar system will be presented and explained. }}, author = {{Nava, Federico and Scheytt, Christoph and Zwick, Thomas and Pauli, Mario and Goettel, B. and Winkler, Wolfgang}}, booktitle = {{ 3rd International Conference on System-Integrated Intelligence}}, title = {{{Ultra-compact 122GHz Radar Sensor for Autonomous Aircrafts}}}, doi = {{ 10.1016/j.protcy.2016.08.051}}, year = {{2016}}, } @inproceedings{24266, abstract = {{Recently electronic-photonic integrated circuits (EPIC) technology platforms became available [1] which allow fabrication of very compact and fast monolithic receivers. However, although the cointegration of electronics and photonics on the same chip allows for novel circuit topologies which could help to improve circuit performance quite often transmitter and receiver circuit design is using more or less conventional approaches. We propose a novel architecture that effectively utilizes the benefits of the EPIC technology such as: very short interconnects between the photodiode and the amplifier, symmetrical and compact photodiode structure with low operating voltages. Our architecture shown in Fig. 1 features fully-differential input stage, automatic biasing of the photodiode, DC coupling between diode and transimpedance amplifier (TIA) and very small footprint.}}, author = {{Gudyriev, Sergiy and Scheytt, Christoph and Meister, Stefan and Knoll, Dieter and Lischke, Stefan and Zimmermann, Lars and Meuer, Christian}}, booktitle = {{IEEE Group IV Photonics Conference}}, title = {{{ Low-Power, Ultra-compact, Fully-differential 40Gbps Direct Detection Receiver in 0.25μm Photonic BiCMOS SiGe Technology}}}, doi = {{10.1109/GROUP4.2016.7739126}}, year = {{2016}}, } @inproceedings{24267, author = {{Scheytt, Christoph}}, booktitle = {{Microelectronics Seminar}}, title = {{{Recent Advances in Millimeter-Wave-and Electronic-Photonic System-on-Chip Design}}}, year = {{2016}}, } @inproceedings{24287, abstract = {{Terahertz frequency band of 0.06 - 10 THz is especially interesting for ultra-high-speed wireless communication to achieve data rates of 100 Gbps or higher. To accommodate this demand, advanced terahertz signal processing techniques need to be investigated. Parallel Sequence Spread Spectrum (PSSS) is a physical layer (PHY) baseband technology that seems to be suited for being used for ultra-high speed wireless communication since the receiver architecture is especially simple and can be implemented almost completely in analog hardware. In this paper, a PSSS modulated signal at a chip rate of 20 Gcps with a spectral efficiency of (only) 1 bit/s/Hz is transmitted using a linearity limited 240 GHz wireless frontend. PSSS transceiver models are realized offline in MATLAB/Simulink. The PSSS transmitter generates the PSSS modulated symbols that are loaded onto an Arbitrary Waveform generator (AWG) and then transmitted using the available 240 GHz wireless frontend. A Digital Storage Oscilloscope (DSO) samples and stores the received signal. The PSSS receiver performs synchronization, channel estimation and demodulation. For a coded data rate of 20 Gbps, an eye opening of 40% and a BER of 5.4·10 -5 has been measured. These results are highly promising to achieve data rates of up to 100 Gbps with PSSS modulation using a RF-frontend having higher linear operating range and thus allowing increasing the bandwidth efficiency to 4 b/s/Hz.}}, author = {{KrishneGowda, Karthik and Messinger, Tobias and Wolf, Andreas and Kraemer, Rolf and Kallfass, Ingmar and Scheytt, Christoph}}, booktitle = {{ICUWB 2015}}, title = {{{Towards 100 Gbps Wireless Communication in THz Band with PSSS Modulation: A Promising Hardware in the Loop Experiment}}}, doi = {{10.1109/ICUWB.2015.7324520}}, year = {{2015}}, } @inproceedings{24286, author = {{Scheytt, Christoph and Javed, Abdul Rehman}}, booktitle = {{Workshop on Approximate Computing}}, location = {{Paderborn}}, title = {{{Shifting the Analog-Digital Boundary in Signal Processing: Should We Use Mixed-Signal "Approximate" Computing?}}}, year = {{2015}}, } @misc{24288, author = {{Adelt, Peer}}, publisher = {{Universität Paderborn, Fakultät EIM}}, title = {{{Analyse von Ausführungszeiten durch Integration einer statischen WCET-Analyse mit einer dynamischen Befehlssatzsimulation am Beispiel der TriCore-Architektur}}}, year = {{2015}}, } @inproceedings{24291, abstract = {{In this paper, a miniaturized 122 GHz ISM band FMCW radar is used to achieve micrometer accuracy. The radar consists of a SiGe single chip radar sensor and LCP off-chip antennas. The antennas are integrated in a QFN package. To increase the gain of the radar, an additional lens is used. A combined frequency and phase evaluation algorithm provides micrometer accuracy. The influence of the lens phase center on the beat frequency phase and hence, the overall accuracy is shown. Furthermore, accuracy limitations of the radar system over larger measurement distances are investigated. Accuracies of 200 μm and 2 μm are achieved over a distance of 1.9 m and 5 mm, respectively.}}, author = {{Scherr, Steffen and Göttel, Benjamin and Ayhan, Serdal and Bhutani, Akanksha and Pauli, Mario and Winkler, Wolfgang and Scheytt, Christoph and Zwick, Thomas}}, booktitle = {{European Microwave Week 2015}}, title = {{{Miniaturized 122 GHz ISM Band FMCW Radar with Micrometer Accuracy}}}, doi = {{10.1109/EuRAD.2015.7346291}}, year = {{2015}}, } @inproceedings{24289, author = {{Müller, Wolfgang and Wu, Liang and Scheytt, Christoph and Becker, Markus and Schoenberg, Sven}}, booktitle = {{Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014)}}, editor = {{Mueller-Gritschneder, Daniel and Müller, Wolfgang and Mitra, Subhasish}}, title = {{{On the Correlation of HW Faults and SW Errors}}}, year = {{2015}}, } @phdthesis{24298, abstract = {{This thesis investigates the design and realization of integrated planar antennas for millimeter-wave applications. The state-of-the-art antenna integration and packaging technologies are extensively studied, and an antenna design flow is proposed. A number of integrated antenna designs by applying different integration approaches and technologies, i.e. on printed circuit board (PCB), on-chip and in Benzocyclobutene (BCB) above-wafer process, are presented. The designs target not only high performance, but also the practical considerations of low-cost, feasibility, better reliability, and good reproducibility. They cover the industrial, medical, and scientific (ISM) bands of 60 GHz, 122 GHz, and 245 GHz in the millimeter-wave range with outstanding performance in a low-cost fashion by applying innovative, appropriate integration methods and sophisticated design. By applying the localized backside etching (LBE) process the presented on-chip antennas achieve measured peak gains of 6–8.4 dBi for above 100 GHz applications with simulated efficiencies of 54–75%. These figures are comparable to that of on-board or in-package antennas. To the best of my knowledge, the achieved gain of 7.5–8.4 dBi in the band of 124–134 GHz for the 130 GHz on-chip double folded dipole antenna is the highest reported result to date for planar on-chip antennas based on low-resistivity silicon technologies. System demonstrators with integrated antennas are realized and measured. The 60 GHz demonstrator with on-PCB differential bunny-ear antenna and a novel bond-wire compensation scheme achieves a data rate of 3.6 Gbit/s over a 15-meter distance, which was the best reported analog front-end without beamforming function in silicon technology regarding both the data rate and transmission distance at the time of its publication. A 245 GHz single-channel transmitter and a single-channel receiver with integrated on-chip antennas are also demonstrated. An effective isotropic radiated power (EIRP) of 7–8 dBm is achieved for the transmitter, which is the highest reported value at 245 GHz for a SiGe transmitter with a single antenna so far. Furthermore, the receiver has the highest reported integration level for any 245 GHz SiGe receiver. A 245 GHz 4-channel-transmitter array with integrated on-chip antenna array is also realized to achieve spatial power combining, which offers 11 dB higher EIRP than a single-channel transmitter. From the presented results of the thesis it is feasible to realize high performance integrated planar antennas in the entire millimeter-wave range and beyond in a cost-effective fashion. }}, author = {{Wang, Ruoyu}}, publisher = {{Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}}, title = {{{Integrated Planar Antenna Designs and Technologies for Millimeter-Wave Applications}}}, volume = {{338}}, year = {{2015}}, } @inproceedings{24294, abstract = {{Parallel Sequence Spread Spectrum (PSSS) is a physical layer (PHY) baseband technology which is gaining interest for both wireless and wired multi-gigabit communication systems. PSSS is well suited for mixed signal transceiver implementation including channel equalization and allows for a reduction in power dissipation by avoiding high speed data converters. The architecture of a mixed signal baseband processor for 100 Gbps wireless communication is described that reduces the implementation complexity and results in a consequent reduction in power dissipation and chip area.}}, author = {{Javed, Abdul Rehman and Scheytt, Christoph and KrishneGowda, Karthik and Kraemer, Rolf}}, booktitle = {{Wireless and Microwave Technology Conference (WAMICON)}}, pages = {{1--4}}, publisher = {{IEEE}}, title = {{{System Design Considerations for a PSSS transceiver for 100Gbps wireless communication with emphasis on mixed Signal implementation}}}, doi = {{10.1109/WAMICON.2015.7120419}}, year = {{2015}}, } @inproceedings{24293, abstract = {{Parallel Sequence Spread Spectrum (PSSS) is a physical layer baseband technology wherein parallel data streams are transmitted simultaneously by spreading them using orthogonal codes. PSSS was selected for the wireless sensor network standard IEEE802.15.4-2006 to increase data rate and improve performance in fading channels for frequency bands below 1 GHz. Since then it has gained interest for both wireless and wired communication links.}}, author = {{Javed, Abdul Rehman and Scheytt, Christoph}}, booktitle = {{1st URSI Atlantic Radio Science Conference (URSI AT-RASC 2015)}}, title = {{{System Design and Simulation of a PSSS Based Mixed Signal Transceiver for a 20 Gbps Bandwidth Limited Communication Link}}}, doi = {{10.1109/URSI-AT-RASC.2015.7302987}}, year = {{2015}}, } @inproceedings{24292, author = {{Scheytt, Christoph and Javed, Abdul Rehman}}, booktitle = {{European Microwave Week 2015}}, title = {{{Mixed-Signal Baseband Processing for 100 Gbit/s Communications}}}, year = {{2015}}, } @inproceedings{24297, author = {{Javed, Abdul Rehman and Scheytt, Christoph and Kraemer, Rolf and Messinger, Tobias and Kallfass, Ingmar}}, location = {{Nürnberg, Germany}}, title = {{{Mixed-mode Baseband for 100 Gbit/s Wireless Communications}}}, year = {{2015}}, }