@inproceedings{24296, author = {{Javed, Abdul Rehman}}, location = {{Nürnberg, Germany}}, title = {{{PSSS baseband receiver circuit design}}}, year = {{2015}}, } @misc{24295, author = {{Scheytt, Christoph and Javed, Abdul Rehman}}, booktitle = {{ForschungsForum Paderborn}}, number = {{18}}, pages = {{25--30}}, title = {{{100 Gigabit pro Sekunde und mehr für das drahtlose Hochgeschwindigkeits-Internet}}}, year = {{2015}}, } @inproceedings{24290, abstract = {{The recent rapid development of silicon photonics technology has spurred the process of on-chip integration of all kinds of opto-electronic components. One of the most common components of such type is the opto-electrical receiver. The monolithic implementation of the receiver could potentially have lower power consumption, higher sensitivity and bandwidth due to very short diode to amplifier connection length, which has very low parasitic capacitance and series resistance. The SiGe photodiode itself is also very compact, thus lowering the junction capacitance and improving its bandwidth. Among the different optical communication systems, coherent transmission lately received a lot of attention due to the rising requirements of the optical link capacity, and it was shown that this particular approach could benefit greatly from the monolithic integration, since the major component required for the demodulation on the receiver side – 90° optical hybrid – could be implemented fully passive and directly on the same chip as the receiver itself, together with digital post-processing circuitry. Despite the initial complexity of the modulation scheme, advanced silicon photonics components like this optical hybrid could make coherent transmission attractive even for short-range optical links. I would like to present the actual designs, implementation and measurement results of 90° fully passive optical hybrids, implemented in the IHP SG25PIC (passive photonics IC) technology. One of the designs is based on 4x4 multimode interferometer (MMI). The other one is based on two separate 2x2 MMIs with additional delay element. The final designs didn’t require any additional tuning after fabrication and have shown sufficient precision and performance for a coherent system design. The results of this work were later used for the design of monolithic coherent receiver.}}, author = {{Gudyriev, Sergiy and Scheytt, Christoph}}, booktitle = {{Kleinheubacher Tagung 2015}}, pages = {{18}}, title = {{{Silicon photonics 90° optical hybrid design for coherent receivers}}}, year = {{2015}}, } @book{53590, editor = {{Müller-Gridschneder, Daniel and Müller, Wolfgang and Mitra, Subhasish}}, title = {{{Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems}}}, year = {{2015}}, } @inproceedings{24300, author = {{Wessel, Jan and Schmalz, Klaus and Cahill, Brian and Scheytt, Christoph}}, booktitle = {{Elektrotechnisches Kolloquium}}, title = {{{Design of an Electrical Interferometer at 120 GHz for Contactless Permittivity Characterization}}}, year = {{2014}}, } @inproceedings{24305, abstract = {{Energy efficiency drives the development of more and more complex low-power designs. Based on dynamic power management techniques, multiple voltage islands as well as a huge amount of power states are specified that have to be tested carefully. In this context, low-power design should start at an early stage using state-of-the-art system-level modeling and simulation techniques. However, there is neither a programming language nor any modeling standard that reflects variable power together with its functional side effects in a well-suited abstract manner. To overcome this limitation, we present a modeling approach on top of SystemC TLM to capture low-power design characteristics at electronic system-level. We demonstrate the usability by means of an existing open-source low-power design. The experimental results show that appropriate TLM instrumentation cause only minimal simulation overhead, but offer sufficient details to identify common low-power design errors.}}, author = {{Mischkalla, Fabian and Müller, Wolfgang}}, booktitle = {{Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)}}, publisher = {{IEEE}}, title = {{{Architectural Low-Power Design Using Transaction-Based System Modeling and Simulation}}}, doi = {{10.1109/SAMOS.2014.6893219}}, year = {{2014}}, } @inproceedings{24308, abstract = {{A 115 GHz slow wave transmission line intended for phase detection based integrated biosensors is presented. The structure was fabricated in a 130 nm SiGe process. It achieved the targeted overall phase shift of 1° at 115 GHz. Moreover, the phase can be adjusted by 16 switches using Heterojunction Bipolar (HBT) transistors leading to a phase resolution of 0.125°. The change in input and output matching over all configurations of the switches is not higher than 0.8 dB and the transmission S 21 varies with less than 0.7 dB. To the authors knowledge, it is the first switchable slow wave structure using microstrip transmission lines along with a bipolar switch circuitry. Moreover, the presented structure provides a very powerful solution for real-time digital read-outs in integrated biosensors, without need of additional signal processing steps.}}, author = {{Wessel, Jan and Schmalz, Klaus and Scheytt, Christoph and Meliani, Chafik}}, booktitle = {{Microwave Symposium (IMS), 2014 IEEE MTT-S International}}, pages = {{1 -- 3}}, publisher = {{IEEE}}, title = {{{ Switchable slow wave transmission line in 130 nm SiGe technology at 115 GHz for phase detection based biosensors}}}, doi = {{10.1109/MWSYM.2014.6848446}}, year = {{2014}}, } @inproceedings{24303, abstract = {{A calibration technique as well as measurement results for a 7 GHz Biosensor are presented. It is shown that the applied sensor structure can be calibrated by adjusting the phase of a sensing element's transmission S21. This is realized by slowing down the wave traveling a microstrip line serving as a reference in the differential sensor structure. The dielectric properties along with certain physical boundaries of an obstacle covering parts of the microstrip line evoke that effect. Measurements with an ethanol serious along with simulation results showed that sensitivity can be increased substantially with this calibration technique. A change of the real part of the sample's permittivity of 48 leads to a 18 MHz frequency shift.}}, author = {{Wessel, Jan and Schmalz, Klaus and Scheytt, Christoph and Meliani, Chafik and Cahill, Brian}}, booktitle = {{European Microwave Conference (EuMC)}}, pages = {{699 -- 702}}, publisher = {{IEEE}}, title = {{{A 7 GHz biosensor for permittivity change with enhanced sensitivity through phase compensation}}}, doi = {{10.1109/EuMC.2014.6986530}}, volume = {{44th}}, year = {{2014}}, } @inproceedings{24307, abstract = {{There is a continuous increase of bandwidth-demanding services such as ultra HDTV, 3D TV, etc. which will require data rates up to 100-400 Gb/s for short range wireless communication. This paper introduces a novel mixed-mode design where both analog and digital domain design is considered, which helps in the reduction of power consumption. Parallel Sequence Spread Spectrum (PSSS) is used for physical layer (PHY) baseband technology, which considerably alleviates both transmitter and receiver design.}}, author = {{Kraemer, Rolf and Wolf, Andreas and Scheytt, Christoph and Kallfass, Ingmar and KrishneGowda, Karthik}}, booktitle = {{2014 IEEE 15th Annual IEEE Wireless and Microwave Technology Conference (WAMICON)}}, publisher = {{IEEE}}, title = {{{Wireless 100 Gb/s: PHY layer Overview and Challenges in THz freqency band}}}, doi = {{10.1109/WAMICON.2014.6857743}}, year = {{2014}}, } @article{24302, abstract = {{In this paper, we present an efficient approach to virtual platform modeling for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666 Standard SystemC simulation. For evaluation we consider Infineon's recently introduced AURIX processor family as a target platform, which utilizes multiple CPU cores operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals. For SoC prototyping, we integrate the fast and open instruction accurate QEMU software emulator with the TLMu library for SystemC co-verification. This article reports our most recent efforts of the implementation of the TriCore instruction set for QEMU. The experimental results demonstrate the functional correctness and performance of our TriCore implementation.}}, author = {{Koppelmann, Bastian and Messidat, Bernd and Becker, Markus and Kuznik, Christoph and Müller, Wolfgang and Scheytt, Christoph}}, journal = {{Design and Verification Conference (DVCON EUROPE)}}, location = {{München, Germany}}, title = {{{Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}}}, year = {{2014}}, } @article{24309, abstract = {{Verific-MM is an approach to systematize and accelerate the coverage plan engineering as well as the verification environment’s (functional) metric code generation -- usually a time-consuming and error-prone task -- in particular by (i) improving automation via assisted model-based approaches, utilizing recent industry standards such as UCIS and (ii) a supporting methodology suitable for various target (functional coverage) languages (IEEE-1800 SystemVerilog, IEEE-1647 e, IEEE-1666 SystemC).}}, author = {{Kuznik, Christoph and Müller, Wolfgang}}, journal = {{Design, Automation and Test in Europe DATE, University Booth, Dresden}}, title = {{{Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure}}}, year = {{2014}}, } @inproceedings{24304, author = {{Scheytt, Christoph}}, booktitle = {{Analog 2014,14. Fachtagung der Gesellschaft für Mikroelektronik, Mikrosystemtechnik und Feinwerktechnik des VDE und VDI}}, title = {{{System-on-Chip Design für Funkfrequenzen oberhalb von 100 GHz-Herausforderungen und potenzielle Anwendungen}}}, year = {{2014}}, } @article{24306, author = {{Elkhouly, Mohamed and Mao, Yanfei and Meliani, Chafik and Scheytt, Christoph and Ellinger, Frank}}, journal = {{IEEE JOURNAL OF SOLID-STATE CIRCUITS}}, number = {{9}}, title = {{{A -Band Four-Element Butler Matrix in 0.13 µm SiGe BiCMOS Technology}}}, volume = {{49}}, year = {{2014}}, } @inproceedings{24311, abstract = {{Intelligent automotive electronics significantly improved driving safety in the last decades. With the increasing complexity of automotive systems, dependability of the electronic components themselves and of their interaction must be assured to avoid any risk to driving safety due to unexpected failures caused by internal or external faults. Additionally, Virtual Prototypes (VPs) have been accepted in many areas of system development processes in the automotive industry as platforms for SW development, verification, and design space exploration. We believe that VPs will significantly contribute to the analysis of safety conditions for automotive electronics. This paper shows the advantages of such a methodology based on today's industrial needs, presents the current state of the art in this field, and outlines upcoming research challenges that need to be addressed to make this vision a reality.}}, author = {{Oetjens, Jan-Hendrik and Becker, Markus and Kuznik, Christoph and Müller, Wolfgang and Bannow, Nico and Brinkmann, Oliver and Burger, Andreas and Chaari, Moomen and Chakraborty, Samarjit and Drechsler, R. and Ecker, Wolfgang and Grüttner, Kim and Kruse, Thomas and Le, Hoang M and Mauderer, M. and Mueller-Gritschneider, Daniel and Poppen, Frank and Post, Hendrik and Reiter, SEbastian and Rosenstiel, Wolfgang and Roth, S. and Schlichtmann, Ulf and Von Schwerin, Andreas and Tabacaru, Bogdan Andrei and Viehl, Alexander}}, booktitle = {{Design Automation Conference (DAC)}}, title = {{{Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges}}}, doi = {{10.1145/2593069.2602976}}, year = {{2014}}, } @inproceedings{24301, author = {{Scheytt, Christoph}}, booktitle = {{Fakultätskolloquium der Fakultät für Elektrotechnik und Informationstechnik}}, title = {{{mm-Wellen- und Electronic-Photonic System-on-Chip Design}}}, year = {{2014}}, } @inproceedings{25120, author = {{Mischkalla, Fabian and Müller, Wolfgang}}, booktitle = {{Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)}}, location = {{Greece, Sep. 2014, IEEE}}, publisher = {{IEEE}}, title = {{{Architectural Low-Power Design Using Transaction-Based System Simulation}}}, year = {{2014}}, } @inproceedings{25146, author = {{Joy, M. tech. Mabel Mary and Müller, Wolfgang and Rammig, Franz-Josef}}, booktitle = {{12th IEEE International conference on Embedded Computing}}, title = {{{Source code annotated memory leak detection for soft real time embedded systems with resource constraints}}}, year = {{2014}}, } @inproceedings{25144, author = {{Mischkalla, Fabian and Müller, Wolfgang}}, booktitle = {{PATMOS 2014}}, title = {{{Advanced SoC Virtual Prototyping for System-Level Power Planning and Validation}}}, year = {{2014}}, } @inproceedings{36918, abstract = {{This paper presents an advanced eight levels spanning SystemC based virtual platform methodology and framework - referred to as HeroeS 3 - providing smooth application to platform mapping and continuous co-refinement of a virtual prototype with its physical environment model. For heterogeneity support, various SystemC extensions are combined covering continuous/discrete models of computation and different communication abstractions, such as analog mixed-signal models, abstract RTOS/HAL/middleware models, TLM bus models, and QEMU wrappers. We enable dependability assessment by Fault Effect Modeling (FEM) at the virtual prototype in order to avoid risking physical injury or damage. Also, simulation results are deterministic and can be evaluated interactively or offline. We apply FEM to both the physical environment model and the different abstractions of the virtual prototype. Currently, we focus on sensor failures and application control flow errors.}}, author = {{Becker, Markus and Kuznik, Christoph and Müller, Wolfgang}}, keywords = {{Computational modeling, Finite element analysis, Prototypes, Abstracts, Software, Fault tolerance, Fault tolerant systems}}, location = {{Berlin}}, publisher = {{IEEE}}, title = {{{Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems}}}, doi = {{10.1109/ICCPS.2014.6843726}}, year = {{2014}}, } @inproceedings{36917, abstract = {{The ever-increasing complexity of heterogeneous electronic systems demand for intensified abstraction and automation efforts to improve design, verification and validation productivity, especially in earlier phases of system engineering. Within the verification activity various metrics can be applied to determine functional correctness or the overall progress. Here, a supporting verification methodology defining high-level verification planning down to the actual metric code development is essential. Moreover, an advanced assistance for the designer, such as a tooling infrastructure to automatize and accelerate the metric code implementation, is needed to minimize the influence of errorprone manual coding. In this article we present a single-source verification metric code-generation methodology for improved coverage automation. We determine (i) a suitable metric model for model-based capture of verification metrics as well as (ii) an assisted model-based processing and generation flow of the verification environment and metric skeletons. We apply our method to a SystemC case-study, in doing so, targeting metric code implementation productivity and consistency enhancement.}}, author = {{Kuznik, Christoph and Müller, Wolfgang and Defo, Gilles Bertrand}}, keywords = {{System Design, Verification}}, title = {{{An Assisted Single Source Verification Metric Model Code Generation Methodology}}}, year = {{2014}}, }