@inproceedings{24311,
  abstract     = {{Intelligent automotive electronics significantly improved driving safety in the last decades. With the increasing complexity of automotive systems, dependability of the electronic components themselves and of their interaction must be assured to avoid any risk to driving safety due to unexpected failures caused by internal or external faults. Additionally, Virtual Prototypes (VPs) have been accepted in many areas of system development processes in the automotive industry as platforms for SW development, verification, and design space exploration. We believe that VPs will significantly contribute to the analysis of safety conditions for automotive electronics. This paper shows the advantages of such a methodology based on today's industrial needs, presents the current state of the art in this field, and outlines upcoming research challenges that need to be addressed to make this vision a reality.}},
  author       = {{Oetjens, Jan-Hendrik and Becker, Markus and Kuznik, Christoph and Müller, Wolfgang and Bannow, Nico and Brinkmann, Oliver and Burger, Andreas and Chaari, Moomen and Chakraborty, Samarjit and Drechsler, R. and Ecker, Wolfgang and Grüttner, Kim and Kruse, Thomas and Le, Hoang M and Mauderer, M. and Mueller-Gritschneider, Daniel and Poppen, Frank and Post, Hendrik and Reiter, SEbastian and Rosenstiel, Wolfgang and Roth, S.  and Schlichtmann, Ulf and Von Schwerin, Andreas and Tabacaru, Bogdan Andrei and Viehl, Alexander}},
  booktitle    = {{Design Automation Conference (DAC)}},
  title        = {{{Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges}}},
  doi          = {{10.1145/2593069.2602976}},
  year         = {{2014}},
}

@inproceedings{24301,
  author       = {{Scheytt, Christoph}},
  booktitle    = {{Fakultätskolloquium der Fakultät für Elektrotechnik und Informationstechnik}},
  title        = {{{mm-Wellen- und Electronic-Photonic System-on-Chip Design}}},
  year         = {{2014}},
}

@inproceedings{25120,
  author       = {{Mischkalla, Fabian and Müller, Wolfgang}},
  booktitle    = {{Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)}},
  location     = {{Greece, Sep. 2014, IEEE}},
  publisher    = {{IEEE}},
  title        = {{{Architectural Low-Power Design Using Transaction-Based System Simulation}}},
  year         = {{2014}},
}

@inproceedings{25146,
  author       = {{Joy, M. tech. Mabel Mary and Müller, Wolfgang and Rammig, Franz-Josef}},
  booktitle    = {{12th IEEE International conference on Embedded Computing}},
  title        = {{{Source code annotated memory leak detection for soft real time embedded systems with resource constraints}}},
  year         = {{2014}},
}

@inproceedings{25144,
  author       = {{Mischkalla, Fabian and Müller, Wolfgang}},
  booktitle    = {{PATMOS 2014}},
  title        = {{{Advanced SoC Virtual Prototyping for System-Level Power Planning and Validation}}},
  year         = {{2014}},
}

@inproceedings{36918,
  abstract     = {{This paper presents an advanced eight levels spanning SystemC based virtual platform methodology and framework - referred to as HeroeS 3 - providing smooth application to platform mapping and continuous co-refinement of a virtual prototype with its physical environment model. For heterogeneity support, various SystemC extensions are combined covering continuous/discrete models of computation and different communication abstractions, such as analog mixed-signal models, abstract RTOS/HAL/middleware models, TLM bus models, and QEMU wrappers. We enable dependability assessment by Fault Effect Modeling (FEM) at the virtual prototype in order to avoid risking physical injury or damage. Also, simulation results are deterministic and can be evaluated interactively or offline. We apply FEM to both the physical environment model and the different abstractions of the virtual prototype. Currently, we focus on sensor failures and application control flow errors.}},
  author       = {{Becker, Markus and Kuznik, Christoph and Müller, Wolfgang}},
  keywords     = {{Computational modeling, Finite element analysis, Prototypes, Abstracts, Software, Fault tolerance, Fault tolerant systems}},
  location     = {{Berlin}},
  publisher    = {{IEEE}},
  title        = {{{Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems}}},
  doi          = {{10.1109/ICCPS.2014.6843726}},
  year         = {{2014}},
}

@inproceedings{36917,
  abstract     = {{The ever-increasing complexity of heterogeneous electronic systems demand for intensified abstraction and automation efforts to improve design, verification and validation productivity, especially in earlier phases of system engineering. Within the verification activity various metrics can be applied to determine functional correctness or the overall progress. Here, a supporting verification methodology defining high-level verification planning down to the actual metric code development is essential. Moreover, an advanced assistance for the designer, such as a tooling infrastructure to automatize and accelerate the metric code implementation, is needed to minimize the influence of errorprone manual coding. In this article we present a single-source verification metric code-generation methodology for improved coverage automation. We determine (i) a suitable metric model for model-based capture of verification metrics as well as (ii) an assisted model-based processing and generation flow of the verification environment and metric skeletons. We apply our method to a SystemC case-study, in doing so, targeting metric code implementation productivity and consistency enhancement.}},
  author       = {{Kuznik, Christoph and Müller, Wolfgang and Defo, Gilles Bertrand}},
  keywords     = {{System Design, Verification}},
  title        = {{{An Assisted Single Source Verification Metric Model Code Generation Methodology}}},
  year         = {{2014}},
}

@inproceedings{25166,
  abstract     = {{Zur Sicherstellung hoher Zuverlässigkeits- und Fehlertoleranzwerte von Schaltungen und ganzen Systemen finden vermehrt Test- und Verifikationsmethoden Anwendung die einen virtuellen Prototypen (VP) des Systems bereits frühzeitig im Entwurfsablauf einem Stresstest unterziehen. Hierbei werden speziell für die Domäne relevante Fehlerinjektoren verwendet (Digital, Mixed-Signal, Mechanik) die anhand von Fehlermodellen geeignete Testfälle erzeugen und in das System über Stimuli bzw. direkt injizieren. Jede effektive Anwendung einer Methode bedingt jedoch auch das Vorhandensein einer zugrundeliegenden Methodik. In diesem Beitrag wird die System Verification Methodology (SVM) vorgestellt werden, eine universell einsetzbare und erweiterbare Infrastruktur zur Beschreibung von Testumgebungen auf Basis der SystemC Sprache und Simulationskernels.}},
  author       = {{Kuznik, Christoph and Müller, Wolfgang}},
  booktitle    = {{26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen}},
  title        = {{{Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM}}},
  year         = {{2014}},
}

@inproceedings{25163,
  author       = {{Kuznik, Christoph and Defo, Bertrand Gilles and Müller, Wolfgang}},
  booktitle    = {{17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) }},
  title        = {{{Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung}}},
  year         = {{2014}},
}

@article{25151,
  author       = {{Kuznik, Christoph and Defo, Bertrand Gilles and Müller, Wolfgang}},
  journal      = {{Electronic System Level Synthesis Conference (ESLSyn)}},
  title        = {{{An Assisted Single Source Verification Metric Model Code Generation Methodology}}},
  year         = {{2014}},
}

@article{24310,
  abstract     = {{A millimeter wave frequency mixed-signal design of a 1-tap half-rate look-ahead decision feedback equalizer for 80 Gb/s short-reach optical communication systems is presented. On-wafer tests are developed to determine the maximum operating bit rate of the equalizer. Results are also presented for intersymbol interference mitigation at 80 Gb/s for a 20 GHz bandwidth-limited channel. Further improvements on the architecture of the 80 Gb/s equalizer are discussed and used in the design and on-wafer measurement of a 110 Gb/s equalizer. The equalizers are designed in a 0.13 μm SiGe:C BiCMOS technology. The 80 and 110 Gb/s versions dissipate 4 and 5.75 W, respectively and occupy 2 and 2.56 mm 2 , respectively.}},
  author       = {{Awny, Ahmed and Möller, Lothar and Junio, Josef and Scheytt, Christoph and Thiede, Andreas}},
  issn         = {{1558-173X}},
  journal      = {{IEEE JOURNAL OF SOLID-STATE CIRCUITS}},
  number       = {{No.2}},
  pages        = {{452--470}},
  title        = {{{Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer}}},
  doi          = {{10.1109/JSSC.2013.2285385}},
  volume       = {{Vol.49}},
  year         = {{2014}},
}

@inproceedings{34585,
  abstract     = {{In this paper, we present an efficient approach to virtual platform modeling for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666 Standard SystemC simulation.  For evaluation we consider Infineon's recently introduced AURIX processor family as a target platform, which utilizes multiple CPU cores operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals. For SoC prototyping, we integrate the fast and open instruction accurate QEMU software emulator with the TLMu library for SystemC co-verification. This article reports our most recent efforts of the implementation of the TriCore instruction set for QEMU. The experimental results demonstrate the functional correctness and performance of our TriCore implementation.}},
  author       = {{Koppelmann, Bastian and Messidat, Bernd and Becker, Markus and Müller, Wolfgang and Scheytt, J. Christoph}},
  booktitle    = {{Proceedings of the Design and Verification Conference Europe (DVCON Europe)}},
  keywords     = {{System Design, Verification}},
  title        = {{{Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}}},
  year         = {{2014}},
}

@inproceedings{34583,
  abstract     = {{In this paper, we present an efficient approach to virtual platform modeling for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666 Standard SystemC simulation.  For evaluation we consider Infineon's recently introduced AURIX processor family as a target platform, which utilizes multiple CPU cores operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals. For SoC prototyping, we integrate the fast and open instruction accurate QEMU software emulator with the TLMu library for SystemC co-verification. This article reports our most recent efforts of the implementation of the TriCore instruction set for QEMU. The experimental results demonstrate the functional correctness and performance of our TriCore implementation.}},
  author       = {{Koppelmann, Bastian and Messidat, Bernd and Kuznik, Christoph and Müller, Wolfgang and Becker, Markus and Scheytt, J. Christoph}},
  booktitle    = {{Proceedings of the Design and Verification Conference Europe (DVCON Europe)}},
  keywords     = {{System Design, Verification}},
  title        = {{{Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}}},
  year         = {{2014}},
}

@inproceedings{24356,
  abstract     = {{A fully integrated six-port receiver front-end at 120 GHz center frequency including a low-noise-amplifier, a passive six-port network, a VCO, and four direct converters is presented in this publication. The overall architecture of the designed six-port receiver is analyzed and fundamental theory of the receiver given. The design of the six-port building blocks is described and measurement results are presented. All circuits have been fabricated in a 0.13μm 300-GHz f T SiGe BiCMOS technology. The fully integrated receiver consumes 85.9 rnA from a 3.3-V supply and occupies an area of 1.03mm 2 . The receiver includes a VCO with a center frequency of 117.15 GHz, a tuning range of 2.7 GHz, and a phase noise of -86 dBc/Hz at 1 MHz offset. The LNA shows a gain of 12 dB, a 3-dB bandwidth of 30 GHz at a power consumption of 9.2 rnA. The six-port core has a conversion gain of 3.6 dB, a P 1dB of -12 dBm, and a power consumption of 28 rnA. The overall receiver shows a conversion gain of 2.4 dB at 120 GHz and P 1dB of -17 dBm.}},
  author       = {{Laemmle, Benjamin and Schmalz, Klaus and Borngräber, Johannes and Scheytt, Christoph and Weigel, Robert and Koelpin, Alexander and Kissinger, Dietmar}},
  booktitle    = {{Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on}},
  title        = {{{A fully integrated 120-GHz six-port receiver front-end in a 130-nm SiGe BiCMOS technology}}},
  doi          = {{10.1109/SiRF.2013.6489455}},
  year         = {{2013}},
}

@inproceedings{24355,
  abstract     = {{Impulse-radio ultra-wideband systems (IR-UWB) provide short-range wireless communication and precise localization simultaneously. Especially non-coherent IR-UWB reduces the system complexity which enables the design of low-power receivers. This paper presents an integrating digitizer which integrates rectified baseband pulses of an IR-UWB signal and provides the digitized data to the digital baseband of the receiver. The integrator is composed of two time-interleaved (TI) operational amplifiers with capacitive feedback. With this structure, the integrator can be periodically reset without introducing a dead time between two integration periods. The analog-to-digital conversion is performed by a 6 bit 62.4 MS/s successive approximation register analog-to-digital converter (SAR ADC). The integrating digitizer chip is realized in a 250 nm SiGe:C BiCMOS technology from IHP.}},
  author       = {{Digel, Johannes and Masini, Michelangelo and Grözing, Markus and Berroth, Manfred and Fischer, Gunter and Olonbayar, Sonom and Gustat, Hans and Scheytt, Christoph}},
  booktitle    = {{Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on}},
  pages        = {{93--95}},
  title        = {{{Integrator and digitizer for a non-coherent IR-UWB receiver}}},
  doi          = {{10.1109/SiRF.2013.6489443}},
  year         = {{2013}},
}

@inproceedings{24353,
  abstract     = {{This paper presents an integrated mixed-signal 120GHz FMCW/CW radar chipset in a 0.13μm SiGe BiCMOS technology. It features on-chip MMW built-in-self-test (BIST) circuits, a harmonic transceiver, software linearization (SWL) circuits and a digital interface. This chipset has been tested in a low-cost package, where the antennas are integrated. Above 100GHz, our transceiver has achieved state-ofthe-art integration level and receiver linearity, and DC power consumption.}},
  author       = {{Sun, Yaoming and Marinkovic, Miroslav and Fischer, Gunter and Winkler, Wolfgang and Debski, Wojciech and Beer, Stefan and Zwick, Thomas and Girma, Mekdes Gebresilassie and Hasch, Jürgen and Scheytt, Christoph}},
  booktitle    = {{Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International}},
  pages        = {{148--149}},
  title        = {{{A low-cost miniature 120GHz SiP FMCW/CW radar sensor with software linearization}}},
  doi          = {{10.1109/ISSCC.2013.6487676}},
  year         = {{2013}},
}

@inproceedings{24357,
  abstract     = {{Complex integrated 122 and 245 GHz SiGe BiCMOS transceiver ICs as well as an efficient broadband on-chip antenna are presented. The ICs target radar and sensing applications for the ISM bands at 122 and 245 GHz. Due to high level of integration and basic mm-wave self-testing production as well as test cost are dramatically reduced. Furthermore a compact and efficient on-chip antenna allows for chip-on-board mounting without RF interfaces.}},
  author       = {{Scheytt, Christoph and Sun, Yaoming and Schmalz, Klaus and Mao, Yanfei and Wang, Ruoyu and Debski, Wojciech and Winkler, Wolfgang}},
  booktitle    = {{Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on}},
  pages        = {{246--248}},
  title        = {{{Towards mm-wave System-On-Chip with integrated antennas for low-cost 122 and 245 GHz radar sensors}}},
  doi          = {{10.1109/SiRF.2013.6489494}},
  year         = {{2013}},
}

@inproceedings{24354,
  abstract     = {{In this paper, a 6-bit true modular programmable frequency divider with division ratios ranging from 64 to 127 is reported. It is composed of a divider chain of 6 divide-by-2/3 cells, and ECL stages that are introduced as synchronization circuits for programming inputs. The synchronization circuits have CMOS input for compatibility with programming circuits. The stand-alone divider chain is functional up to an input clock frequency of 49 GHz. The combination of the divider chain with synchronization circuits is functional up to 44 GHz. The 6 stage divider draws 34 mA current from a 2.7 V supply. The synchronization circuits draw 30 mA from a 3 V supply. The circuit is fabricated in a 0.13 μm SiGe BiCMOS technology, and is well suited for millimeter-wave phase-locked loop (PLL) circuits which require fine frequency resolution.}},
  author       = {{Ergintav, Arzu and Sun, Yaoming and Scheytt, Christoph and Gürbüz, Yasar}},
  booktitle    = {{Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on}},
  title        = {{{49 GHz 6-bit programmable divider in SiGe BiCMOS}}},
  doi          = {{10.1109/SiRF.2013.6489451}},
  year         = {{2013}},
}

@inproceedings{24361,
  abstract     = {{Two subharmonic receivers for 245 GHz spectroscopy sensor applications in the 245 GHz ISM band have been proposed. One receiver consists of an 2nd APDP (antiparallel diode pair) passive SHM (subharmonic mixer), a 120 GHz push-push VCO with 1/64 divider, and a 120 GHz PA (power amplifier). The other consists of a single-ended four-stage CB (common base) LNA, an 2 nd APDP passive SHM, an IF amplifier, a 120 GHz push-push VCO with 1/64 divider, and a 120 GHz PA. The receivers are fabricated in a SiGe:C BiCMOS technology with f T /f max =300/500 GHz. The measured conversion gain are -17 dB rsp. 10.6 dB at 245 GHz with 3-dB bandwidths of 13 GHz rsp. 14 GHz, and the single-side band noise figure are 17 dB rsp. 20 dB; the two receivers dissipates a power of 213 mW and 312 mW, respectively.}},
  author       = {{Mao, Yanfei and Schmalz, Klaus and Borngräber, Johannes and Scheytt, Christoph}},
  booktitle    = {{2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium}},
  title        = {{{245 GHz subharmonic receivers in SiGe}}},
  doi          = {{10.1109/RFIC.2013.6569533}},
  year         = {{2013}},
}

@inproceedings{24358,
  abstract     = {{A 240 GHz direct conversion IQ receiver manufactured in 0.13 SiGe BiCMOS technology with f T /f max of 300/500 GHz is presented. The receiver consists of a four stage LNA, an active power divider, an LO IQ generation network, and direct down-conversion fundamental mixers. The integrated IQ receiver yields a conversion gain of 18 dB, an 18 dB simulated DSB NF, and a 3 dB bandwidth of 25 GHz. The required 245 GHz LO power is in the order of -10 dBm. The receiver exhibits an IQ amplitude and phase imbalance of 1 dB and 3° respectively. It draws 135 mA from the 3.5 V supply and 20 mA from 2 V.}},
  author       = {{Elkhouly, Mohamed and Mao, Yanfei and Meliani, Chafik and Ellinger, Frank and Scheytt, Christoph}},
  booktitle    = {{2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium,}},
  title        = {{{A 240 GHz Direct Conversion IQ Receiver in 0.13 µm SiGe BiCMOS technology}}},
  doi          = {{10.1109/RFIC.2013.6569589}},
  year         = {{2013}},
}