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Sie führt die Anschlüsse über weitere Leiterbahnen zum Rand des Chips und wird dort zu Kontaktflecken (“Pads”) aufgeweitet, die als Anschluss für die Verbindungsdrähte zwischen Chip und Gehäuse oder zum Aufsetzen von Messsonden für die Parametererfassung zum Schaltungstest auf ungesägten Scheiben dienen.","lang":"eng"}],"page":"131–151","publisher":"Vieweg+Teubner Verlag","_id":"39875","language":[{"iso":"eng"}],"doi":"10.1007/978-3-322-94119-0_8","user_id":"20179","status":"public","year":"2002","title":"Metallisierung und Kontakte","publication_identifier":{"isbn":["978-3-322-94119-0"]},"author":[{"id":"20179","first_name":"Ulrich","last_name":"Hilleringmann","full_name":"Hilleringmann, Ulrich"}],"date_updated":"2023-03-21T10:03:35Z"},{"status":"public","title":"Nanometer Scale Lateral Structures of MOS Type Layers","year":"2000","author":[{"id":"20179","last_name":"Hilleringmann","first_name":"Ulrich","full_name":"Hilleringmann, Ulrich"},{"full_name":"Vieregge, T","last_name":"Vieregge","first_name":"T"},{"full_name":"Horstmann, JT","last_name":"Horstmann","first_name":"JT"}],"date_updated":"2023-03-21T09:59:50Z","page":"49–53","language":[{"iso":"eng"}],"_id":"39884","user_id":"20179","publication":"Proceedings Micro. tec","citation":{"bibtex":"@inproceedings{Hilleringmann_Vieregge_Horstmann_2000, title={Nanometer Scale Lateral Structures of MOS Type Layers}, booktitle={Proceedings Micro. tec}, author={Hilleringmann, Ulrich and Vieregge, T and Horstmann, JT}, year={2000}, pages={49–53} }","ama":"Hilleringmann U, Vieregge T, Horstmann J. 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