@inproceedings{37048, abstract = {{We introduce a structured methodology for the generation of executable test environments from textual requirement specifications via UML class diagrams and the application of the classification tree methodology for embedded systems. The first phase is a stepwise transformation from unstructured English text into a textual normal form (TNF), which is automatically translated into UML class diagrams. After annotations of the class diagrams and the definition of test cases by sequence diagrams, both are converted into classification trees. From the classification trees we can finally generate SystemVerilog code. The methodology is introduced and evaluated by the example of an Adaptive Cruise Controller.}}, author = {{Müller, Wolfgang and Bol, Alexander and Krupp, Alexander and Lundkvist, Ola}}, editor = {{Kleinjohann, L. and Kleinjohann, B.}}, isbn = {{978-3-642-15233-7}}, keywords = {{Natural Language UML SystemVerilog Testbenches}}, publisher = {{Springer Verlag}}, title = {{{Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems}}}, doi = {{10.1007/978-3-642-15234-4_9}}, year = {{2010}}, } @inproceedings{37049, author = {{Xie, Tao and Letombe, Florian and Müller, Wolfgang}}, editor = {{Kleinjohann, L. and Kleinjohann, B.}}, publisher = {{Springer Verlag}}, title = {{{Mutation-Analysis Directed Constrained Random Verification}}}, year = {{2010}}, } @inproceedings{37051, author = {{Xie, Tao and Defo, Gilles B. and Müller, Wolfgang}}, location = {{Paris}}, title = {{{An Eclipse-based Framework for the IP-XACT-enabled Assembly of Mixed-Level IPs}}}, year = {{2010}}, } @inproceedings{37057, abstract = {{Many heterogeneous embedded systems, for example industrial automation and automotive applications, require hard-real time constraints to be exhaustively verified - which is a challenging task for the verification engineer. To cope with complexity, verification techniques working on different abstraction levels are best practice. SystemC is a versatile C++ based design and verification language, offering various mechanisms and constructs required for embedded systems modeling. Using the add-on SystemC Verification Library (SCV) elemental constrained-random stimuli techniques may be used for verification. However, SCV has several drawbacks such as lack of functional coverage. In this paper we present a functional coverage library that implements parts of the IEEE 1800-2005 SystemVerilog standard and allows capturing functional coverage throughout the design and verification process with SystemC. Moreover, we will demonstrate the usability of the approach with a case study working on a CAN bus model written in SystemC.}}, author = {{Defo, Gilles B. and Müller, Wolfgang and Kuznik, Christoph}}, booktitle = {{Proceedings of SIES 2010}}, keywords = {{Libraries, Generators, Transfer functions, Monitoring, Computational modeling, Driver circuits, Adaptation model}}, location = {{ Trento, Italy}}, publisher = {{IEEE}}, title = {{{Verification of a CAN Bus Model in SystemC with Functional Coverage}}}, doi = {{10.1109/SIES.2010.5551379}}, year = {{2010}}, } @inproceedings{37056, abstract = {{In this paper we present an approach to increase the fault tolerance in FlexRay networks by introducing backup nodes to replace defect ECUs (Electronic Control Units). In order to reduce the memory requirements of such backup nodes, we distribute redundant tasks over different nodes and propose the distributed coordinated migration of tasks of the defect ECU to the backup node at runtime. This approach enhances our former work in, where we extended the FlexRay bus schedule by redundant slots to consider changes in the communication/slot assignment and investigated and evaluated different solutions to migrate the redundant tasks to the backup node using the static and/or dynamic segment of the communication cycle for transmissions. We present the approach of distributed coordination for migration and communication instead of additional dedicated coordinator nodes to further increase the fault tolerance. With this approach we improve the safety of FlexRay networks by avoiding a possible single point of failure due to a dedicated coordinator node also minimizing the necessary time needed for a reconfiguration after an ECU failure. Furthermore, we reduce the overhead within the communication and the demand for additional hardware components.}}, author = {{Klobedanz, Kay and Defo, Gilles B. and Müller, Wolfgang and Kerstan, Timo}}, booktitle = {{Proceedings of SIES 2010}}, keywords = {{Fault tolerant systems, Protocols, Redundancy, Runtime, Payloads, Schedules}}, title = {{{Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks}}}, doi = {{10.1109/SIES.2010.5551384}}, year = {{2010}}, } @inproceedings{37053, abstract = {{Seamless HW/SW codesign flows support early verification of hardware and Hardware-dependent Software (HdS) like drivers, operating systems, and firmware. For early estimation and verification, the application of SystemC in combination with Instruction Set Simulators and Software Emulators like QEMU is widely accepted. In this article, we present an advanced design flow for HW, (RT)OS and HdS refinement and verification with focus on the transition from abstract RTOS verification to full system RTOS/HdS emulation. In the context of assertion-based verification, we introduce a set of generic real-time properties which can be reused and verified at different abstraction levels and discuss their application. The properties are presented by the means of IEEE standard PSL assertions which are applied for mixed SystemC/HdS models.}}, author = {{Müller, Wolfgang and da S. Oliveira, Marcio F. and Zabel, Henning and Becker, Markus}}, booktitle = {{Proceedings of HLDVT2010}}, keywords = {{Hardware, Microprogramming, Application software, Timing, Protocols, Virtual prototyping, Real time systems, Sampling methods, Operating systems, Emulation}}, location = {{Anaheim, FL, USA}}, publisher = {{IEEE}}, title = {{{Verification of Real-Time Properties for Hardware-Dependant Software}}}, year = {{2010}}, } @inproceedings{37060, author = {{Oliveira, Marcio F. S. and do Nascimento, Francisco Assis M. and Müller, Wolfgang}}, booktitle = {{Proceedings of MoMPES 2010}}, title = {{{Design Space Abstraction and Metamodeling for Embedded Systems Design Space Exploration}}}, year = {{2010}}, } @inbook{33813, abstract = {{Today, mobile and embedded real-time systems have to cope with the migration and allocation of multiple software tasks running on top of a real-time operating system (RTOS) residing on one or several system processors. Each RTOS has to be configured towards the individual needs of the application and environment. For this, different scheduling strategies and task priorities have to be evaluated in order to keep execution and response times for a given task set. Abstract RTOS simulation is applied to analyze different parameters in early design phases. This chapter presents a SystemC RTOS library for abstract yet accurate RTOS sim- ulation, supporting modeling of preemption in the presence of prioritized and nested interrupts. After introducing basic principles of abstract RTOS simula- tion, we present our SystemC library in detail. Thereafter, we discuss related approaches and close with applications in electronic automotive systems design and some evaluations.}}, author = {{Zabel, Henning and Müller, Wolfgang and Gerstlauer, Andreas}}, booktitle = {{Hardware Dependent Software - Principles and Practice}}, editor = {{Ecker, Wolfgang and Müller, Wolfgang and Dömer, Rainer}}, isbn = {{978-1-4020-9435-4}}, keywords = {{RTOS Modelling, RTOS Simulation, SystemC, Task Scheduling, Interrupt Analysis}}, pages = {{233--260}}, publisher = {{Springer Verlag}}, title = {{{Accurate RTOS Modelling and Analysis with SystemC}}}, doi = {{10.1007/978-1-4020-9436-1_9}}, year = {{2009}}, } @inbook{33814, abstract = {{Rapidly rising system complexity has created a growing productivity gap in the design of electronic systems. One critical component is Hardware-dependent Software (HdS), the importance of which is often underestimated. In this chap- ter, we introduce HdS and illustrate its role in the overall system design context. We also provide a brief overview and define a basic HdS terminology and con- clude with a brief outlook over the following chapters in this book.}}, author = {{Ecker, Wolfgang and Müller, Wolfgang and Dömer, Rainer}}, booktitle = {{Hardware Dependent Software - Principles and Practice}}, editor = {{Ecker, Wolfgang and Müller, Wolfgang and Dömer, Rainer}}, isbn = {{978-1-4020-9435-4}}, keywords = {{Hardware-dependent Software, Systems Complexity, Productivity Gap}}, pages = {{1--14}}, publisher = {{Springer Verlag}}, title = {{{Hardware-dependent Software - Introduction and Overview}}}, doi = {{10.1007/978-1-4020-9436-1_1}}, year = {{2009}}, } @inproceedings{37067, abstract = {{IP-XACT is a well accepted standard for the exchange of IP components at Electronic System and Register Transfer Level. Still, the creation and manipulation of these descriptions at the XML level can be time-consuming and error-prone. In this paper, we show that the UML can be consistently applied as an efficient and comprehensible frontend for IP-XACT-based IP description and integration. For this, we present an IP-XACT UML profile that enables UML-based descriptions covering the same information as a corresponding IP-XACT description. This enables the automated generation of IP-XACT component and design descriptions from respective UML models. In particular, it also allows the integration of existing IPs with UML. To illustrate our approach, we present an application example based on the IBM PowerPC Evaluation Kit.}}, author = {{Schattkowsky, Tim and Xie, Tao and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE'09}}, isbn = {{978-1-4244-3781-8}}, keywords = {{Unified modeling language, XML, Power system modeling, Application software, Master-slave, Power system management, Acceleration, Scattering, Software engineering, Software standards}}, publisher = {{IEEE}}, title = {{{A UML Frontend for IP-XACT-based IP Management}}}, doi = {{10.1109/DATE.2009.5090664}}, year = {{2009}}, } @inproceedings{37066, abstract = {{Today, mobile and embedded real-time systems have to cope with the migration and allocation of multiple software tasks running on top of a real-time operating system (RTOS) residing on one or multiple system processors. Abstract RTOS simulations and timing analysis applies for fast and early estimation to configure it towards the individual needs of the application and environment. In this context, a high accuracy of the simulation compared to an instruction set simulation (ISS) is of key importance. In this paper, we investigate the accuracy of abstract RTOS simulation and compare it to ISS and the behavior of the physical system. We show that we can reach an increased accuracy of the simulation when we inject noise into the time model. Our results indicate that it is sufficient to inject uniformly distributed random time values to the RTOS real-time clock.}}, author = {{Zabel, Henning and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE'09}}, isbn = {{978-1-4244-3781-8}}, keywords = {{Timing, Analytical models, Clocks, Performance analysis, Scheduling, Operating systems, Delay, Real time systems, Application software, Context modeling}}, title = {{{Increased Accuracy through Noise Injection in Abstract RTOS Simulation}}}, doi = {{10.1109/DATE.2009.5090925}}, year = {{2009}}, } @inproceedings{37063, abstract = {{Safety-critical automotive systems must fulfill hard real-time constraints to guarantee their reliability and safety requirements. In the context of network-based electronics systems, high-level timing requirements have to be carefully mastered and traced throughout the whole development process. In this paper, we outline the management of scheduling-specific timing information by the application of a steer-by-wire design example. We apply the principles of the AUTOSAR-compliant Timing Augmented Description Language (TADL) following the methodology introduced by the TIMMO project[2]. Focus of the example will be the identification of end-to-end timing constraints and their refinement by means of stimuli-response event chains.}}, author = {{Klobedanz, Kay and Kuznik, Christoph and Elfeky, Ahmed and Müller, Wolfgang}}, booktitle = {{Proceedings of IESS09}}, isbn = {{978-3-642-04283-6}}, keywords = {{Abstraction Level Controller Area Network High Abstraction Level Event Chain Automotive System}}, publisher = {{Springer Verlag}}, title = {{{Development of Automotive Communication Based Real-Time Systems - A Steer-by-Wire Case Study}}}, doi = {{10.1007/978-3-642-04284-3_20}}, year = {{2009}}, } @inproceedings{37064, author = {{Becker, Markus and Zabel, Henning and Müller, Wolfgang}}, location = {{Berlin}}, title = {{{Integration abstrakter RTOS-Simulation in den Entwurf eingebetteter automobiler E/E-Systeme}}}, year = {{2009}}, } @inproceedings{37061, author = {{Krupp, Alexander and Müller, Wolfgang}}, booktitle = {{Proceedings of IESS09}}, title = {{{Systematic Model-in-the-Loop Test of Embedded Control Systems}}}, year = {{2009}}, } @inproceedings{37068, author = {{Doemer, R. and Gerstlauer, A. and Müller, Wolfgang}}, booktitle = {{Proceedings of ASP-DAC'09}}, title = {{{Hardware-dependent Software for Multi- and Many-Core Embedded Systems}}}, year = {{2009}}, } @article{34563, abstract = {{UML has been widely accepted by the software community for several years. As electronic systems design can no longer be seen as an isolated hardware design activity, UML becomes of significant interest as a unification language for systems description combining both HW and SW components. This article provides a comprehensive view of the UML applied to System-on-Chip (SoC) and hardware-related embedded systems design. The modeling concepts in the UML language are first introduced, including major diagrams for the representation of the behavior and the structure of systems. The principles behind application specific UML customizations (UML profiles) are summarized, and several examples relevant for SoC design are given, such as the SysML (System Modeling Language) and the SoC Profile. Thereafter, various approaches associating UML with existing HW/SW design languages are presented. Beyond language aspects, the article addresses the question of UML-based design flows, and shows how UML can be applied concretely to the development of electronic-based systems. The current situation about tool support constitutes the last focus of the article. In particular, we show how UML tools can be combined with well-known simulation environments, such as MATLAB.}}, author = {{Vanderperren, Yves and Müller, Wolfgang and Dahaene, Wim}}, journal = {{Design Automation for Embedded Systems}}, keywords = {{UML SysML Model-based design System specification Modelling languages}}, pages = {{261--292}}, publisher = {{Springer-Verlag}}, title = {{{UML for Electronic Systems Design – A Comprehensive Overview}}}, doi = {{10.1007/s10617-008-9028-9}}, volume = {{12}}, year = {{2008}}, } @article{34564, abstract = {{To provide user interfaces for a rich set of devices and interaction modalities, we follow a model-based development methodology. We devised an architecture which deploys user interfaces specified as dialogue models with abstract interaction objects and allows context-based adaptations by means of an external transcoding process. For the validation of the applicability of this methodology for developing usable multimodal multi-device systems, we present two case studies based on proof-of-concept implementations and assessed them with a large set of established design principles and different types of modality cooperation.}}, author = {{Schäfer, Robbie and Müller, Wolfgang}}, journal = {{Journal on Multimodal User Interfaces}}, keywords = {{Interaction architecture Abstract interaction objects Dialogue model Transformations Multimodality Multi-device Design principles}}, number = {{1}}, pages = {{25--41}}, publisher = {{Springer-Verlag}}, title = {{{Assessment of a Multimodal Interaction and Rendering System against Established Design Principles}}}, doi = {{10.1007/s12193-008-0003-3}}, volume = {{2}}, year = {{2008}}, } @inbook{33815, abstract = {{Test processes in the automotive industry are tool-intensive and affected by technologically heterogeneous test infrastructures. In the industrial practice a product has to pass tests at several levels of abstraction such as Model-in-the-Loop (MIL), Software-in-the-Loop (SIL) and Hardware-in-the-Loop (HIL) tests. Different test systems are applied for this purpose (e.g. dSPACE MTest, dSPACE Automation Desk, National Instruments Teststand) and almost each test system requests its own proprietary test description language. The exchange of tests between different test systems and the reuse of tests between different test levels is normally not possible. Efforts to integrate these heterogeneous test environments, to address test exchange in a general manner and to standardize and harmonize the existing language environment are still at the beginning and not tailored towards the requirements of the automotive domain. To keep the whole development and test process efficient and manageable, the definition of an integrated and seamless approach is required. TestML – the test exchange language we present in this article – is defined to overcome the technological obstacles (different test language syntax and semantics, different data formats and interface descriptions) that almost automatically accompany the application of heterogeneous test tools and test infrastructures. TestML supports the exchange of tests between different test notations in a heterogeneous tool environment. In this paper, we introduce the XML schema of TestML and demonstrate the efficiency of the interchange format by giving examples from the model-based development of electronic control units. Tool support is illustrated by an application with Simulink/Stateflow.}}, author = {{Großmann, Jürgen and Fey, Ines and Krupp, Alexander and Conrad, Mirko and Wewetzer, Christian and Müller, Wolfgang}}, booktitle = {{ASWSD 2006: Model-Driven Development of Reliable Automotive Services}}, editor = {{Broy, Manfred and Krüger, Ingolf H. and Meisinger, Michael}}, isbn = {{978-3-540-70929-9}}, keywords = {{Test Behavior, Test Exchange, System Under Test, Hybrid Automaton, Test Execution}}, pages = {{98--117}}, publisher = {{Springer Verlag}}, title = {{{TestML – A Test Exchange Language for Model-based Testing of Embedded Software}}}, doi = {{10.1007/978-3-540-70930-5_7}}, year = {{2008}}, } @inproceedings{37075, abstract = {{Complex control oriented embedded systems with hard real-time constraints require real-time operation system (RTOS) for predictable timing behavior. To support the evaluation of different scheduling strategies and task priorities, we use an abstract RTOS model based on SystemC. In this article, we present an annotation method for time estimation that supports flexible simulation and validation of real-time-constraints for task migration between different target processors without loss of simulation performance and less memory overhead.}}, author = {{Zabel, Henning and Müller, Wolfgang}}, editor = {{Kleinjohann, L. and Kleinjohann, B.}}, isbn = {{978-0-387-09660-5}}, keywords = {{Execution Time Schedule Strategy Simulation Speed Task Migration Atomic Block}}, publisher = {{Springer Verlag}}, title = {{{An Efficient Time Annotation Technique in Abstract RTOS Simulations for Multiprocessor Task Migration}}}, doi = {{10.1007/978-0-387-09661-2_18}}, volume = {{271}}, year = {{2008}}, } @inproceedings{37072, abstract = {{Bei der Simulation von eingebetteten Echtzeit Systemen zur Analyse von Ausführungs- zeiten und Scheduling gibt es immer einen Kompromiss zwischen zyklengenauen Ergebnis- sen und der Laufzeit der Simulation. Mithilfe von abstrakten RTOS Modellen auf Basis von SystemC wird versucht diese Lücke zu schließen. Aktuelle Arbeiten besitzen allerdings nur unzureichende Möglichkeiten zur Modellierung von Interrupt Scheduling und ihren hard- wareabhängigen Prioritäten. Unser Ansatz verwendet zwei getrennte Scheduler für Softwa- re Task und Interrupt Service Routinen. Diese Trennung erlaubt die präzise Modellierung von Interrupt Prioritäten und Interrupt Scheduling unabhängig von dem eigentlichen RTOS Scheduler.}}, author = {{Zabel, Henning and Müller, Wolfgang}}, booktitle = {{Methoden und Beschreibungs-sprachen zur Modellierung und Verifikation von Schaltungen und System}}, editor = {{Scholl, Ch. and Disch, S.}}, publisher = {{Shaker Verlag}}, title = {{{Präzises Interrupt Scheduling in abstrakten RTOS Modellen in SystemC}}}, year = {{2008}}, }