@phdthesis{34711, author = {{Terhörst, Philipp}}, publisher = {{Technical University of Darmstadt, Germany}}, title = {{{Mitigating Soft-Biometric Driven Bias and Privacy Concerns in Face Recognition Systems}}}, year = {{2021}}, } @article{34712, author = {{Terhörst, Philipp and Fährmann, Daniel and Damer, Naser and Kirchbuchner, Florian and Kuijper, Arjan}}, journal = {{IEEE Trans. Biom. Behav. Identity Sci.}}, number = {{4}}, pages = {{519–534}}, title = {{{On Soft-Biometric Information Stored in Biometric Face Embeddings}}}, doi = {{10.1109/TBIOM.2021.3093920}}, volume = {{3}}, year = {{2021}}, } @article{27841, abstract = {{Verification of software and processor hardware usually proceeds separately, software analysis relying on the correctness of processors executing machine instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption. In this paper we present a novel formal approach for hardware/software co-verification targeting processors with custom instruction set extensions. We detail two different approaches for checking whether the hardware fulfills the requirements expected by the software analysis. The approaches are designed to explore a trade-off between generality of the verification and computational effort. Then, we describe the integration of software and hardware analyses for both techniques and describe a fully automated tool chain implementing the approaches. Finally, we demonstrate and compare the two approaches on example source code with custom instructions, using state-of-the-art software analysis and hardware verification techniques.}}, author = {{Jakobs, Marie-Christine and Pauck, Felix and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}}, journal = {{IEEE Access}}, keywords = {{Software Analysis, Abstract Interpretation, Custom Instruction, Hardware Verification}}, publisher = {{IEEE}}, title = {{{Software/Hardware Co-Verification for Custom Instruction Set Processors}}}, doi = {{10.1109/ACCESS.2021.3131213}}, year = {{2021}}, } @inproceedings{21238, author = {{Pauck, Felix and Wehrheim, Heike}}, booktitle = {{Software Engineering 2021}}, editor = {{Koziolek, Anne and Schaefer, Ina and Seidl, Christoph}}, pages = {{ 83--84 }}, publisher = {{Gesellschaft für Informatik e.V.}}, title = {{{Cooperative Android App Analysis with CoDiDroid}}}, doi = {{10.18420/SE2021_30 }}, year = {{2021}}, } @article{37404, author = {{Menzefricke, Jörn Steffen and Wiederkehr, Ingrid and Koldewey, Christian and Dumitrescu, Roman}}, issn = {{2212-8271}}, journal = {{Procedia CIRP}}, keywords = {{General Medicine}}, pages = {{241--246}}, publisher = {{Elsevier BV}}, title = {{{Maturity-based Development of Strategic Thrusts for Socio-technical Risks}}}, doi = {{10.1016/j.procir.2021.11.041}}, volume = {{104}}, year = {{2021}}, } @misc{32402, author = {{Böttger, Meret Amalia Elisabeth}}, title = {{{IND-CCA Secure PKE Schemes - Based on Lattices}}}, year = {{2021}}, } @article{29710, author = {{Podworny, Susanne and Höper, Lukas and Fleischer, Yannik and Hüsing, Sven and Schulte, Carsten}}, journal = {{INFOS 2021–19. GI-Fachtagung Informatik und Schule}}, publisher = {{Gesellschaft für Informatik, Bonn}}, title = {{{Data Science ab Klasse 5–Konkrete Unterrichtsvorschläge für künstliche Intelligenz unplugged und Datenbewusstsein}}}, year = {{2021}}, } @article{29712, author = {{Höper, Lukas and Podworny, Susanne and Hüsing, Sven and Schulte, Carsten and Fleischer, Yannik and Biehler, Rolf and Frischemeier, Daniel and Malatyali, Hülya}}, journal = {{INFOS 2021–19. GI-Fachtagung Informatik und Schule}}, publisher = {{Gesellschaft für Informatik, Bonn}}, title = {{{Zur neuen Bedeutung von Daten in Data Science und künstlicher Intelligenz}}}, year = {{2021}}, } @article{40512, author = {{Hüsing, Sven and Weiser, Niklas and Biehler, Rolf}}, journal = {{mathematik lehren}}, number = {{228}}, pages = {{23–27}}, publisher = {{Friedrich Verlag}}, title = {{{Faszination 3D-Film: Entwicklung einer 3D-Konstruktion}}}, volume = {{2021}}, year = {{2021}}, } @article{29780, abstract = {{A central tenet of theoretical cryptography is the study of the minimal assumptions required to implement a given cryptographic primitive. One such primitive is the one-time memory (OTM), introduced by Goldwasser, Kalai, and Rothblum [CRYPTO 2008], which is a classical functionality modeled after a non-interactive 1-out-of-2 oblivious transfer, and which is complete for one-time classical and quantum programs. It is known that secure OTMs do not exist in the standard model in both the classical and quantum settings. Here, we propose a scheme for using quantum information, together with the assumption of stateless (i.e., reusable) hardware tokens, to build statistically secure OTMs. Via the semidefinite programming-based quantum games framework of Gutoski and Watrous [STOC 2007], we prove security for a malicious receiver making at most 0.114n adaptive queries to the token (for n the key size), in the quantum universal composability framework, but leave open the question of security against a polynomial amount of queries. Compared to alternative schemes derived from the literature on quantum money, our scheme is technologically simple since it is of the "prepare-and-measure" type. We also give two impossibility results showing certain assumptions in our scheme cannot be relaxed.}}, author = {{Broadbent, Anne and Gharibian, Sevag and Zhou, Hong-Sheng}}, issn = {{2521-327X}}, journal = {{Quantum}}, keywords = {{Physics and Astronomy (miscellaneous), Atomic and Molecular Physics, and Optics}}, publisher = {{Verein zur Forderung des Open Access Publizierens in den Quantenwissenschaften}}, title = {{{Towards Quantum One-Time Memories from Stateless Hardware}}}, doi = {{10.22331/q-2021-04-08-429}}, volume = {{5}}, year = {{2021}}, } @inproceedings{29138, author = {{Ahmed, Qazi Arbab}}, booktitle = {{2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)}}, title = {{{Hardware Trojans in Reconfigurable Computing}}}, doi = {{10.1109/vlsi-soc53125.2021.9606974}}, year = {{2021}}, } @misc{44234, author = {{Berger, Thilo Frederik}}, title = {{{Combining Mobility, Heterogeneity, and Leasing Approaches for Online Resource Allocation}}}, year = {{2021}}, } @misc{44233, author = {{Pranger, Sebastian}}, title = {{{Online k-Facility Reallocation using k-Server Algorithms}}}, year = {{2021}}, } @inproceedings{20681, abstract = {{The battle of developing hardware Trojans and corresponding countermeasures has taken adversaries towards ingenious ways of compromising hardware designs by circumventing even advanced testing and verification methods. Besides conventional methods of inserting Trojans into a design by a malicious entity, the design flow for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised to assist the attacker to perform a successful malfunctioning or information leakage attack. The advanced stealthy malicious look-up-table (LUT) attack activates a Trojan only when generating the FPGA bitstream and can thus not be detected by register transfer and gate level testing and verification. However, also this attack was recently revealed by a bitstream-level proof-carrying hardware (PCH) approach. In this paper, we present a novel attack that leverages malicious routing of the inserted Trojan circuit to acquire a dormant state even in the generated and transmitted bitstream. The Trojan's payload is connected to primary inputs/outputs of the FPGA via a programmable interconnect point (PIP). The Trojan is detached from inputs/outputs during place-and-route and re-connected only when the FPGA is being programmed, thus activating the Trojan circuit without any need for a trigger logic. Since the Trojan is injected in a post-synthesis step and remains unconnected in the bitstream, the presented attack can currently neither be prevented by conventional testing and verification methods nor by recent bitstream-level verification techniques.}}, author = {{Ahmed, Qazi Arbab and Wiersema, Tobias and Platzner, Marco}}, booktitle = {{2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)}}, location = {{Alpexpo | Grenoble, France}}, publisher = {{2021 Design, Automation and Test in Europe Conference (DATE)}}, title = {{{Malicious Routing: Circumventing Bitstream-level Verification for FPGAs}}}, doi = {{10.23919/DATE51398.2021.9474026}}, year = {{2021}}, } @misc{45236, author = {{N., N.}}, title = {{{Design and Implementation of a Crowd-based Prototype Validation Platform}}}, year = {{2021}}, } @misc{45237, author = {{N., N.}}, title = {{{Model-based Continuous Experimentation for Software Product Prototypes}}}, year = {{2021}}, } @misc{45239, author = {{N., N.}}, title = {{{Lightweight Process Engine for Situation-specific Development of Business Models for Digital Platforms}}}, year = {{2021}}, } @misc{45240, author = {{N., N.}}, title = {{{Development and Evaluation of a Multi Platform Approach for Augmented Reality Product Configuration}}}, year = {{2021}}, } @misc{45238, author = {{N., N.}}, title = {{{Model-based Feature Backlog Synchronization for Dual-Track Development Methods}}}, year = {{2021}}, } @misc{45254, author = {{Anonymous, Anonymous}}, title = {{{Device-Independent Security Proofs Via Entropy Accumulation}}}, year = {{2021}}, }