@inproceedings{15422, author = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{World Congress on Nature and Biologically Inspired Computing (NaBIC)}}, publisher = {{Springer}}, title = {{{Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor}}}, year = {{2019}}, } @phdthesis{15430, author = {{Yigitbas, Enes}}, title = {{{Model-Driven Engineering of Self-Adaptive User Interfaces}}}, year = {{2019}}, } @inproceedings{15478, abstract = {{Stratix 10 FPGA cards have a good potential for the acceleration of HPC workloads since the Stratix 10 product line introduces devices with a large number of DSP and memory blocks. The high level synthesis of OpenCL codes can play a fundamental role for FPGAs in HPC, because it allows to implement different designs with lower development effort compared to hand optimized HDL. However, Stratix 10 cards are still hard to fully exploit using the Intel FPGA SDK for OpenCL. The implementation of designs with thousands of concurrent arithmetic operations often suffers from place and route problems that limit the maximum frequency or entirely prevent a successful synthesis. In order to overcome these issues for the implementation of the matrix multiplication, we formulate Cannon's matrix multiplication algorithm with regard to its efficient synthesis within the FPGA logic. We obtain a two-level block algorithm, where the lower level sub-matrices are multiplied using our Cannon's algorithm implementation. Following this design approach with multiple compute units, we are able to get maximum frequencies close to and above 300 MHz with high utilization of DSP and memory blocks. This allows for performance results above 1 TeraFLOPS.}}, author = {{Gorlani, Paolo and Kenter, Tobias and Plessl, Christian}}, booktitle = {{Proceedings of the International Conference on Field-Programmable Technology (FPT)}}, publisher = {{IEEE}}, title = {{{OpenCL Implementation of Cannon's Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs}}}, doi = {{10.1109/ICFPT47387.2019.00020}}, year = {{2019}}, } @inproceedings{15578, author = {{Izu, Cruz and Schulte, Carsten and Aggarwal, Ashish and I. Cutts, Quintin and Duran, Rodrigo and Gutica, Mirela and Heinemann, Birte and Kraemer, Eileen and Lonati, Violetta and Mirolo, Claudio and Weeda, Renske}}, booktitle = {{Proceedings of the 2019 (ACM) Conference on Innovation and Technology in Computer Science Education, Aberdeen, Scotland, UK, July 15-17, 2019}}, pages = {{261--262}}, title = {{{Program Comprehension: Identifying Learning Trajectories for Novice Programmers}}}, doi = {{10.1145/3304221.3325531}}, year = {{2019}}, } @inproceedings{15579, author = {{Kapp, Florian and Schulte, Carsten}}, booktitle = {{Informatik für alle, 18. GI-Fachtagung Informatik und Schule, (INFOS) 2019, 16.-18. September 2019, Dortmund}}, pages = {{247--256}}, title = {{{Einsatz von Jupyter Notebooks am Beispiel eines fiktiven Kriminalfalls}}}, doi = {{10.18420/infos2019-c10}}, year = {{2019}}, } @inproceedings{15581, author = {{Müller, Kathrin and Schulte, Carsten and Magenheim, Johannes}}, booktitle = {{Informatik für alle, 18. GI-Fachtagung Informatik und Schule, (INFOS) 2019, 16.-18. September 2019, Dortmund}}, pages = {{139--148}}, title = {{{Zur Relevanz eines Prozessbereiches Interaktion und Exploration im Kontext informatischer Bildung im Primarbereich}}}, doi = {{10.18420/infos2019-b10}}, year = {{2019}}, } @inproceedings{15583, author = {{Schmidt, Ann-Katrin and Schulte, Carsten}}, booktitle = {{Informatik für alle, 18. GI-Fachtagung Informatik und Schule, (INFOS) 2019, 16.-18. September 2019, Dortmund}}, pages = {{315--324}}, title = {{{Das RetiBNE Café}}}, doi = {{10.18420/infos2019-c17}}, year = {{2019}}, } @inproceedings{15720, author = {{Wilke, Adrian and Magenheim, Johannes}}, booktitle = {{IEEE Global Engineering Education Conference, EDUCON 2019, Dubai, United Arab Emirates, April 8-11, 2019}}, pages = {{892--899}}, title = {{{Critical Incidents for Technology Enhanced Learning in Vocational Education and Training}}}, doi = {{10.1109/EDUCON.2019.8725025}}, year = {{2019}}, } @book{15721, author = {{Köller, Olaf and Magenheim, Johannes and Molitor, Heike and Pfenning, Uwe and Ramseger, J{\ and Steffensky, Mirjam and Wiesmüller, Christian and Winther, Esther and Wollring, Bernd}}, publisher = {{Verlag Barbara Budrich}}, title = {{{Zieldimensionen für Multiplikatorinnen und Multiplikatoren früher MINT-Bildung}}}, year = {{2019}}, } @article{15741, abstract = {{ In many cyber–physical systems, we encounter the problem of remote state estimation of geo- graphically distributed and remote physical processes. This paper studies the scheduling of sensor transmissions to estimate the states of multiple remote, dynamic processes. Information from the different sensors has to be transmitted to a central gateway over a wireless network for monitoring purposes, where typically fewer wireless channels are available than there are processes to be monitored. For effective estimation at the gateway, the sensors need to be scheduled appropriately, i.e., at each time instant one needs to decide which sensors have network access and which ones do not. To address this scheduling problem, we formulate an associated Markov decision process (MDP). This MDP is then solved using a Deep Q-Network, a recent deep reinforcement learning algorithm that is at once scalable and model-free. We compare our scheduling algorithm to popular scheduling algorithms such as round-robin and reduced-waiting-time, among others. Our algorithm is shown to significantly outperform these algorithms for many example scenario}}, author = {{Leong, Alex S. and Ramaswamy, Arunselvan and Quevedo, Daniel E. and Karl, Holger and Shi, Ling}}, issn = {{0005-1098}}, journal = {{Automatica}}, title = {{{Deep reinforcement learning for wireless sensor scheduling in cyber–physical systems}}}, doi = {{10.1016/j.automatica.2019.108759}}, year = {{2019}}, } @misc{15746, author = {{Otte, Oliver}}, title = {{{Outsourced Decryption of Attribute-based Ciphertexts}}}, year = {{2019}}, } @misc{15747, author = {{Wördenweber, Nico Christof}}, title = {{{On the Security of the Rouselakis-Waters Ciphertext-Policy Attribute-Based Encryption Scheme in the Random Oracle Model}}}, year = {{2019}}, } @misc{15819, author = {{Leutnant, Matthias}}, title = {{{Experimentelle Untersuchung des SEM-Algorithmus}}}, year = {{2019}}, } @inproceedings{15838, abstract = {{In the field of software analysis a trade-off between scalability and accuracy always exists. In this respect, Android app analysis is no exception, in particular, analyzing large or many apps can be challenging. Dealing with many small apps is a typical challenge when facing micro-benchmarks such as DROIDBENCH or ICC-BENCH. These particular benchmarks are not only used for the evaluation of novel tools but also in continuous integration pipelines of existing mature tools to maintain and guarantee a certain quality-level. Considering this latter usage it becomes very important to be able to achieve benchmark results as fast as possible. Hence, benchmarks have to be optimized for this purpose. One approach to do so is app merging. We implemented the Android Merge Tool (AMT) following this approach and show that its novel aspects can be used to produce scaled up and accurate benchmarks. For such benchmarks Android app analysis tools do not suffer from the scalability-accuracy trade-off anymore. We show this throughout detailed experiments on DROIDBENCH employing three different analysis tools (AMANDROID, ICCTA, FLOWDROID). Benchmark execution times are largely reduced without losing benchmark accuracy. Moreover, we argue why AMT is an advantageous successor of the state-of-the-art app merging tool (APKCOMBINER) in analysis lift-up scenarios.}}, author = {{Pauck, Felix and Zhang, Shikun}}, booktitle = {{2019 34th IEEE/ACM International Conference on Automated Software Engineering Workshop (ASEW)}}, isbn = {{9781728141367}}, keywords = {{Program Analysis, Android App Analysis, Taint Analysis, App Merging, Benchmark}}, title = {{{Android App Merging for Benchmark Speed-Up and Analysis Lift-Up}}}, doi = {{10.1109/asew.2019.00019}}, year = {{2019}}, } @misc{15883, author = {{Kumar Jeyakumar, Shankar}}, title = {{{Incremental learning with Support Vector Machine on embedded platforms}}}, year = {{2019}}, } @misc{15920, abstract = {{Secure hardware design is the most important aspect to be considered in addition to functional correctness. Achieving hardware security in today’s globalized Integrated Cir- cuit(IC) supply chain is a challenging task. One solution that is widely considered to help achieve secure hardware designs is Information Flow Tracking(IFT). It provides an ap- proach to verify that the systems adhere to security properties either by static verification during design phase or dynamic checking during runtime. Proof-Carrying Hardware(PCH) is an approach to verify a functional design prior to using it in hardware. It is a two-party verification approach, where the target party, the consumer requests new functionalities with pre-defined properties to the producer. In response, the producer designs the IP (Intellectual Property) cores with the requested functionalities that adhere to the consumer-defined properties. The producer provides the IP cores and a proof certificate combined into a proof-carrying bitstream to the consumer to verify it. If the verification is successful, the consumer can use the IP cores in his hardware. In essence, the consumer can only run verified IP cores. Correctly applied, PCH techniques can help consumers to defend against many unintentional modifications and malicious alterations of the modules they receive. There are numerous published examples of how to use PCH to detect any change in the functionality of a circuit, i.e., pairing a PCH approach with functional equivalence checking for combinational or sequential circuits. For non-functional properties, since opening new covert channels to leak secret information from secure circuits is a viable attack vector for hardware trojans, i.e., intentionally added malicious circuitry, IFT technique is employed to make sure that secret/untrusted information never reaches any unclassified/trusted outputs. This master thesis aims to explore the possibility of adapting Information Flow Tracking into a Proof-Carrying Hardware scenario. It aims to create a method that combines Infor- mation Flow Tracking(IFT) with a PCH approach at bitstream level enabling consumers to validate the trustworthiness of a module’s information flow without the computational costs of a complete flow analysis.}}, author = {{Keerthipati, Monica}}, publisher = {{Universität Paderborn}}, title = {{{A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking}}}, year = {{2019}}, } @inproceedings{15921, abstract = {{Ranking plays a central role in a large number of applications driven by RDF knowledge graphs. Over the last years, many popular RDF knowledge graphs have grown so large that rankings for the facts they contain cannot be computed directly using the currently common 64-bit platforms. In this paper, we tackle two problems: Computing ranks on such large knowledge bases efficiently and incrementally. First, we present D-HARE, a distributed approach for computing ranks on very large knowledge graphs. D-HARE assumes the random surfer model and relies on data partitioning to compute matrix multiplications and transpositions on disk for matrices of arbitrary size. Moreover, the data partitioning underlying D-HARE allows the execution of most of its steps in parallel. As very large knowledge graphs are often updated periodically, we tackle the incremental computation of ranks on large knowledge bases as a second problem. We address this problem by presenting I-HARE, an approximation technique for calculating the overall ranking scores of a knowledge without the need to recalculate the ranking from scratch at each new revision. We evaluate our approaches by calculating ranks on the 3 × 10^9 and 2.4 × 10^9 triples from Wikidata resp. LinkedGeoData. Our evaluation demonstrates that D-HARE is the first holistic approach for computing ranks on very large RDF knowledge graphs. In addition, our incremental approach achieves a root mean squared error of less than 10E−7 in the best case. Both D-HARE and I-HARE are open-source and are available at: https://github.com/dice-group/incrementalHARE. }}, author = {{Desouki, Abdelmoneim Amer and Röder, Michael and Ngonga Ngomo, Axel-Cyrille}}, booktitle = {{Proceedings of the 30th ACM Conference on Hypertext and Social Media - HT '19}}, isbn = {{9781450368858}}, keywords = {{Knowledge Graphs, Ranking, RDF}}, pages = {{163--171}}, publisher = {{ACM}}, title = {{{Ranking on Very Large Knowledge Graphs}}}, doi = {{10.1145/3342220.3343660}}, year = {{2019}}, } @inproceedings{14568, author = {{Heindorf, Stefan and Scholten, Yan and Engels, Gregor and Potthast, Martin}}, booktitle = {{INFORMATIK}}, pages = {{289--290}}, title = {{{Debiasing Vandalism Detection Models at Wikidata (Extended Abstract)}}}, doi = {{10.18420/inf2019_48}}, year = {{2019}}, } @article{14817, author = {{Sommer, Christoph and Basagni, Stefano}}, issn = {{1570-8705}}, journal = {{Ad Hoc Networks}}, title = {{{Advances and novel applications of mobile wireless networking}}}, doi = {{10.1016/j.adhoc.2019.101975}}, year = {{2019}}, } @inproceedings{14819, author = {{Heinovski, Julian and Stratmann, Lukas and Buse, Dominik S. and Klingler, Florian and Franke, Mario and Oczko, Marie-Christin H. and Sommer, Christoph and Scharlau, Ingrid and Dressler, Falko}}, booktitle = {{2019 IEEE 20th International Symposium on "A World of Wireless, Mobile and Multimedia Networks" (WoWMoM)}}, isbn = {{9781728102702}}, title = {{{Modeling Cycling Behavior to Improve Bicyclists' Safety at Intersections - A Networking Perspective}}}, doi = {{10.1109/wowmom.2019.8793008}}, year = {{2019}}, }