@inbook{46382, abstract = {{The incorporation of expert knowledge into multiobjective optimization is an important issue which in this paper is reflected in terms of an aspiration set consisting of multiple reference points. The behaviour of the recently introduced evolutionary multiobjective algorithm AS-EMOA is analysed in detail and comparatively studied for bi-objective optimization problems w.r.t. R-NSGA2 and a respective variant. It will be shown that the averaged Hausdorff distance, integrated into AS-EMOA, is an efficient means to accurately approximate the desired aspiration set.}}, author = {{Rudolph, G and Schütze, O and Grimme, C and Trautmann, Heike}}, booktitle = {{EVOLVE — A Bridge between Probability, Set Oriented Numerics, and Evolutionary Computation V}}, editor = {{Tantar, A and Tantar, E and Sun, J and Zhang, W and Ding, Q and Schütze, O and Emmerich, M and Legrand, P and Del, Moral P and Coello, Coello CA}}, isbn = {{978-3-319-07493-1}}, pages = {{261–273}}, publisher = {{Springer International Publishing}}, title = {{{A Multiobjective Evolutionary Algorithm Guided by Averaged Hausdorff Distance to Aspiration Sets}}}, doi = {{10.1007/978-3-319-07494-8_18}}, volume = {{288}}, year = {{2014}}, } @inproceedings{46383, abstract = {{We propose an evolutionary multiobjective algorithm that approximates multiple reference points (the aspiration set) in a single run using the concept of the averaged Hausdorff distance.}}, author = {{Rudolph, Günter and Grimme, Christian and Schütze, Oliver and Trautmann, Heike}}, booktitle = {{Proceedings of the Learning and Intelligent OptimizatioN Conference (LION 8)}}, pages = {{153–156}}, publisher = {{Springer}}, title = {{{An Aspiration Set EMOA Based on Averaged Hausdorff Distances}}}, volume = {{8426}}, year = {{2014}}, } @inproceedings{46384, abstract = {{Multimodal optimization requires maintenance of a good search space coverage and approximation of several optima at the same time. We analyze two constitutive optimization algorithms and show that in many cases, a phase transition occurs at some point, so that either diversity collapses or optimization stagnates. But how to derive suitable stopping criteria for multimodal optimization? Experimental results indicate that an algorithm’s population contains sufficient information to estimate the point in time when several performance indicators reach their optimum. Thus, stopping criteria are formulated based on summary characteristics employing objective values and mutation strength.}}, author = {{Wessing, S and Preuss, M and Trautmann, Heike}}, booktitle = {{Proceedings of the Parallel Problem Solving from Nature — PPSN XIII}}, editor = {{Bartz-Beielstein, T and Branke, J and Filipic, B and Smith, J}}, pages = {{141–150}}, publisher = {{Springer}}, title = {{{Stopping Criteria for Multimodal Optimization}}}, doi = {{10.1007/978-3-319-10762-2_14}}, volume = {{8672}}, year = {{2014}}, } @article{25164, author = {{Becker, Markus and Müller, Wolfgang and Stroop, Joachim and Kiffmeier, Ulrich}}, journal = {{Design, Automation and Test in Europe DATE, University Booth, Dresden}}, title = {{{HeroeS - A Framework for Heterogeneous Software-Intensive System Design with SystemC}}}, year = {{2014}}, } @inproceedings{47162, author = {{Fahl, Sascha and Acar, Yasemin and Perl, Henning and Smith, Matthew}}, booktitle = {{Proceedings of the 9th ACM symposium on Information, computer and communications security}}, publisher = {{ACM}}, title = {{{Why eve and mallory (also) love webmasters}}}, doi = {{10.1145/2590296.2590341}}, year = {{2014}}, } @article{8171, abstract = {{The polynomial hierarchy plays a central role in classical complexity theory. Here, we define a quantum generalization of the polynomial hierarchy, and initiate its study. We show that not only are there natural complete problems for the second level of this quantum hierarchy, but that these problems are in fact hard to approximate. Using the same techniques, we also obtain hardness of approximation for the class QCMA. Our approach is based on the use of dispersers, and is inspired by the classical results of Umans regarding hardness of approximation for the second level of the classical polynomial hierarchy [Umans, FOCS 1999]. The problems for which we prove hardness of approximation for include, among others, a quantum version of the Succinct Set Cover problem, and a variant of the local Hamiltonian problem with hybrid classical-quantum ground states.}}, author = {{Gharibian, Sevag and Kempe, Julia}}, journal = {{Quantum Information & Computation}}, keywords = {{Hardness of approximation, polynomial time hierarchy, succinct set cover, quantum complexity}}, number = {{5-6}}, pages = {{517--540}}, title = {{{Hardness of approximation for quantum problems}}}, volume = {{14}}, year = {{2014}}, } @article{8172, abstract = {{We show how to efficiently simulate continuous-time quantum query algorithms that run in time T in a manner that preserves the query complexity (within a polylogarithmic factor) while also incurring a small overhead cost in the total number of gates between queries. By small overhead, we mean T within a factor that is polylogarithmic in terms of T and a cost measure that reflects the cost of computing the driving Hamiltonian. This permits any continuous-time quantum algorithm based on an efficiently computable driving Hamiltonian to be converted into a gate-efficient algorithm with similar running time.}}, author = {{W. Berry, Dominic and Cleve, Richard and Gharibian, Sevag}}, journal = {{Quantum Information & Computation}}, number = {{1-2}}, pages = {{1--30}}, title = {{{Gate-efficient discrete simulations of continuous-time quantum query algorithms}}}, volume = {{14}}, year = {{2014}}, } @inbook{335, abstract = {{Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung der Ausbildung in den Computerwissenschaften beeinflusst und sogar zur Entstehung von neuen Forschungsrichtungen gef{\"u}hrt. In diesem Beitrag besch{\"a}ftigen wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der Entstehung dieser Grenze, die Hardware und Software erst als eigenst{\"a}ndige Produkte differenziert. Dann widmen wir uns der Frage, welche Funktionen in einem Computersystem besser in Hardware und welche besser in Software realisiert werden sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen Forschungsrichtung, dem sogenannten Hardware/Software Co-design, gef{\"u}hrt hat. Im Hardware/Software Co-design findet eine Verschiebung von Funktionen an der Grenze zwischen Hardware und Software w{\"a}hrend der Entwicklung eines Produktes statt, um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten Produkt hingegen k{\"o}nnen wir dann eine feste Grenze zwischen Hardware und Software beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption, dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware und Software autonom w{\"a}hrend der Betriebszeit vornimmt. Solche Systeme beruhen auf rekonfigurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware eines Computers w{\"a}hrend der Laufzeit ver{\"a}ndert werden kann. Diese Technologie f{\"u}hrt zu einer durchl{\"a}ssigen Grenze zwischen Hardware und Software bzw. l{\"o}st sie die herk{\"o}mmliche Vorstellung einer festen Hardware und einer flexiblen Software damit auf.}}, author = {{Platzner, Marco and Plessl, Christian}}, booktitle = {{Logiken strukturbildender Prozesse: Automatismen}}, editor = {{Künsemöller, Jörn and Eke, Norber Otto and Foit, Lioba and Kaerlein, Timo}}, isbn = {{978-3-7705-5730-1}}, pages = {{123--144}}, publisher = {{Wilhelm Fink}}, title = {{{Verschiebungen an der Grenze zwischen Hardware und Software}}}, year = {{2014}}, } @inproceedings{388, abstract = {{In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties.}}, author = {{Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian}}, booktitle = {{Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)}}, pages = {{144--155}}, publisher = {{Springer International Publishing}}, title = {{{Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer}}}, doi = {{10.1007/978-3-319-05960-0_13}}, volume = {{8405}}, year = {{2014}}, } @article{363, abstract = {{Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices.}}, author = {{Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco and Plessl, Christian}}, journal = {{Microprocessors and Microsystems}}, number = {{8, Part B}}, pages = {{911--919}}, publisher = {{Elsevier}}, title = {{{Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators}}}, doi = {{10.1016/j.micpro.2013.12.001}}, volume = {{38}}, year = {{2014}}, } @inproceedings{377, abstract = {{In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates.}}, author = {{Riebler, Heinrich and Kenter, Tobias and Plessl, Christian and Sorge, Christoph}}, booktitle = {{Proceedings of Field-Programmable Custom Computing Machines (FCCM)}}, keywords = {{coldboot}}, pages = {{222--229}}, publisher = {{IEEE}}, title = {{{Reconstructing AES Key Schedules from Decayed Memory with FPGAs}}}, doi = {{10.1109/FCCM.2014.67}}, year = {{2014}}, } @article{365, abstract = {{Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems.}}, author = {{Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}}, journal = {{ACM Transactions on Reconfigurable Technology and Systems (TRETS)}}, number = {{2}}, publisher = {{ACM}}, title = {{{Self-awareness as a Model for Designing and Operating Heterogeneous Multicores}}}, doi = {{10.1145/2617596}}, volume = {{7}}, year = {{2014}}, } @article{328, abstract = {{The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications}}, author = {{Agne, Andreas and Happe, Markus and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco and Plessl, Christian}}, journal = {{IEEE Micro}}, number = {{1}}, pages = {{60--71}}, publisher = {{IEEE}}, title = {{{ReconOS - An Operating System Approach for Reconfigurable Computing}}}, doi = {{10.1109/MM.2013.110}}, volume = {{34}}, year = {{2014}}, } @inproceedings{1778, author = {{C. Durelli, Gianluca and Pogliani, Marcello and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin Francis and D. Santambrogio, Marco and Bolchini, Cristiana}}, booktitle = {{Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)}}, pages = {{142--149}}, publisher = {{IEEE}}, title = {{{Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach}}}, doi = {{10.1109/ISPA.2014.27}}, year = {{2014}}, } @inproceedings{439, abstract = {{Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes.}}, author = {{Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}}, booktitle = {{Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}}, pages = {{1--8}}, publisher = {{IEEE}}, title = {{{Deferring Accelerator Offloading Decisions to Application Runtime}}}, doi = {{10.1109/ReConFig.2014.7032509}}, year = {{2014}}, } @inproceedings{406, abstract = {{Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design.}}, author = {{Kenter, Tobias and Schmitz, Henning and Plessl, Christian}}, booktitle = {{Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}}, pages = {{1--8}}, publisher = {{IEEE}}, title = {{{Kernel-Centric Acceleration of High Accuracy Stereo-Matching}}}, doi = {{10.1109/ReConFig.2014.7032535}}, year = {{2014}}, } @inproceedings{1780, author = {{C. Durelli, Gianluca and Copolla, Marcello and Djafarian, Karim and Koranaros, George and Miele, Antonio and Paolino, Michele and Pell, Oliver and Plessl, Christian and D. Santambrogio, Marco and Bolchini, Cristiana}}, booktitle = {{Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)}}, publisher = {{Springer}}, title = {{{SAVE: Towards efficient resource management in heterogeneous system architectures}}}, doi = {{10.1007/978-3-319-05960-0_38}}, year = {{2014}}, } @article{1779, author = {{Giefers, Heiner and Plessl, Christian and Förstner, Jens}}, issn = {{0163-5964}}, journal = {{ACM SIGARCH Computer Architecture News}}, keywords = {{funding-maxup, tet_topic_hpc}}, number = {{5}}, pages = {{65--70}}, publisher = {{ACM}}, title = {{{Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers}}}, doi = {{10.1145/2641361.2641372}}, volume = {{41}}, year = {{2014}}, } @article{25117, author = {{Koppelmann, Bastian and Messidat, Bernd and Becker, Markus and Kuznik, Christoph and Müller, Wolfgang and Scheytt, J. Christoph}}, journal = {{Design and Verification Conference (DVCON EUROPE)}}, title = {{{Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}}}, year = {{2014}}, } @article{25162, author = {{Kuznik, Christoph and Müller, Wolfgang}}, journal = {{Design, Automation and Test in Europe DATE, University Booth, Dresden }}, title = {{{Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure}}}, year = {{2014}}, }