@inproceedings{46410, abstract = {{The design and application of termination criteria has become an important aspect in evolutionary multi-objective optimization. Online convergence detection (OCD) determines when further generations are no longer promising based on statistical tests on a set of performance indicators. The behavior of OCD mainly depends on two parameters, the number of preceding generations considered in the statistical tests and the desired variance limit. In this paper, guidelines for selecting appropriate combinations of these parameters are empirically derived based on design-of-experiment methods. Furthermore, a variant of OCD is introduced which directly operates on the hypervolume indicator - the internal measure of the SMS-EMOA. This allows a separated analysis of the variance criterion and reduces the complexity of OCD. Based on the experimental design, a systematic comparison with the classical OCD approach is performed and differences between the appropriate parameterizations of both variants are highlighted.}}, author = {{Wagner, Tobias and Trautmann, Heike}}, booktitle = {{IEEE Congress on Evolutionary Computation}}, issn = {{1941-0026}}, pages = {{1--8}}, title = {{{Online convergence detection for evolutionary multi-objective algorithms revisited}}}, doi = {{10.1109/CEC.2010.5586474}}, year = {{2010}}, } @inproceedings{37007, abstract = {{UML is widely applied for the specification and modeling of software and some studies have demonstrated that it is applicable for HW/SW codesign. However, in this area there is still a big gap from UML modeling to SystemC-based verification and synthesis environments. This paper presents an efficient approach to bridge this gap in the context of Systems-on-a-Chip (SoC) design. We propose a framework for the seamless integration of a customized SysML entry with code generation for HW/SW cosimulation and high-level FPGA synthesis. For this, we extended the SysML UML profile by SystemC and synthesis capabilities. Two case studies demonstrate the applicability of our approach.}}, author = {{Mischkalla, Fabian and He, Da and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE’10}}, keywords = {{Unified modeling language, Field programmable gate arrays, Bridges, Helium, Real time systems, Operating systems, Documentation, Application software, XML, Space exploration}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems}}}, doi = {{10.1109/DATE.2010.5456990}}, year = {{2010}}, } @inproceedings{37009, abstract = {{Today, mobile and embedded real time systems have to cope with the migration and allocation of multiple software tasks running on top of a real time operating system (RTOS) residing on one or several processors. For scaling of each task set and processor configuration, instruction set simulation and worst case timing analysis are typically applied. This paper presents a complementary approach for the verification of RTOS properties based on an abstract RTOS-Model in SystemC. We apply IEEE P1850 PSL for which we present an approach and first experiences for the assertion-based verification of RTOS properties.}}, author = {{Oliveira, Marcio F. S. and Zabel, Henning and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE’10}}, keywords = {{Operating systems, Real time systems, Timing, Hardware, Analytical models, Embedded software, Software systems, Processor scheduling, Software performance, Performance analysis}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{Assertion-Based Verification of RTOS Properties}}}, doi = {{10.1109/DATE.2010.5457130}}, year = {{2010}}, } @inproceedings{37011, abstract = {{Safety-critical automotive systems must fulfill hard real-time constraints for reliability and safety. This paper presents a case study for the application of an AUTOSAR-based language for timing modeling and analysis. We present and apply the Timing Augmented Description Language (TADL) and demonstrate a methodology for the development of a speed-adaptive steer-by-wire system. We examine the impact of TADL and the methodology on the development process and the suitability and interoperability of the applied tools with respect to the AUTOSAR-based tool chain in the context of our case study.}}, author = {{Klobedanz, Kay and Kuznik, Christoph and Thuy, Andre and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE’10, Dresden}}, keywords = {{Timing, Programming, Automotive engineering, Application software, Hardware, Computer architecture, Communication system software, Software architecture, Delay, Software standards}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study}}}, doi = {{10.1109/DATE.2010.5457125}}, year = {{2010}}, } @inproceedings{37037, abstract = {{Today we can identify a big gap between requirement specification and the generation of test environments. This article extends the Classification Tree Method for Embedded Systems (CTM/ES) to fill this gap by new concepts for the precise specification of stimuli for operational ranges of continuous control systems. It introduces novel means for continuous acceptance criteria definition and for functional coverage definition.}}, author = {{Krupp, Alexander and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE’10}}, keywords = {{System testing, Automatic testing, Object oriented modeling, Classification tree analysis, Automotive engineering, Mathematical model, Embedded system, Control systems, Electronic equipment testing, Software testing}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{A Systematic Approach to Combined HW/SW System Test}}}, doi = {{10.1109/DATE.2010.5457186}}, year = {{2010}}, } @inproceedings{37040, abstract = {{Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms.}}, author = {{Becker, Markus and Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli, Graziano and Xie, Tao}}, booktitle = {{Proceedings of DATE’10}}, keywords = {{Timing, Hardware, Operating systems, Process design, Accuracy, Standards development, Context modeling, Real time systems, Communication channels, Microprogramming}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{RTOS-Aware Refinement for TLM2.0-based HW/SW Design}}}, doi = {{10.1109/DATE.2010.5456965}}, year = {{2010}}, } @inproceedings{37046, abstract = {{In this article, we present a flexible simulation environment for embedded real-time software refinement by a mixed level cosimulation. For this, we combine the native speed of an abstract real-time operating system (RTOS) model in SystemC with dynamic binary translation for fast Instruction Set Simulation (ISS) by QEMU. In order to support stepwise RTOS software refinement from system level to the target software, each task can be separately migrated between the native execution and the ISS. By adapting the dynamic binary translation approach to an efficient but yet very accurate synchronization scheme the overhead of QEMU user mode execution is only factor two compared to native SystemC. Furthermore, the simulation speed increases almost linearly according to the utilization of the task set abstracted by the native execution. Hereby, the simulation time can be considerably reduced by cosimulating just a subset of tasks on QEMU.}}, author = {{Becker, Markus and Zabel, Henning and Müller, Wolfgang}}, editor = {{Kleinjohann, L. and Kleinjohann, B.}}, isbn = {{978-3-642-15233-7}}, keywords = {{Application Programming Interface User Mode Kernel Space System Level Design Mixed Level}}, publisher = {{Springer Verlag}}, title = {{{A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement}}}, doi = {{10.1007/978-3-642-15234-4_15}}, year = {{2010}}, } @inproceedings{37044, abstract = {{In this paper we present new concepts to resolve ECU (Electronic Control Unit) failures in FlexRay networks. Our approach extends the FlexRay bus schedule by redundant slots with modifications in the communication and slot assignment. We introduce additional backup nodes to replace faulty nodes. To reduce the required memory resources of the backup nodes, we distribute redundant tasks over different nodes and propose the migration of tasks to the backup node at runtime. We investigate different solutions to migrate the redundant tasks to the backup node by time-triggered and event-triggered transmissions.}}, author = {{Klobedanz, Kay and Defo, Gilles B. and Zabel, Henning and Müller, Wolfgang and Zhi, Yuan}}, editor = {{Kleinjohann, L. and Kleinjohann, B.}}, isbn = {{978-3-642-15233-7}}, keywords = {{Faulty Node Static Segment Slot Assignment Task Migration Communication Controller}}, publisher = {{Springer Verlag}}, title = {{{Task Migration for Fault-Tolerant FlexRay Networks}}}, doi = {{10.1007/978-3-642-15234-4_7}}, year = {{2010}}, } @inproceedings{37042, abstract = {{It's wide application in the area of software engineering, UML is still not fully accepted for other engineering domains like for electronic systems design. The main obstacle is due to a major gap in the design flow between UML-based modeling and verification. To overcome this gap, we introduce a UML profile for synthesizable SystemC and C and present its implementation in the context of the advanced SysML modeling environment of ARTiSAN Studio. We demonstrate how to customize Studio for SystemC/C comodeling so that it can serve as a verification and synthesis front-end.}}, author = {{Mischkalla, Fabian and Müller, Wolfgang and He, Da}}, booktitle = {{Proceedings of the M-BED Workshop}}, title = {{{A UML Profile for SysML-Based Comodeling for Embedded Systems Simulation and Synthesis}}}, year = {{2010}}, } @inproceedings{37043, author = {{Bol, Alexander and Müller, Wolfgang and Krupp, Alexander}}, booktitle = {{Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)}}, title = {{{Eine strukturierte Methode zur Generierung von SystemVerilog-Testumgebungen aus textuellen Anforderungsbeschreibungen}}}, year = {{2010}}, } @inproceedings{37050, abstract = {{The main obstacle for the wide acceptance of UML and SysML in the design of electronic systems is due to a major gap in the design flow between UML-based modeling and SystemC-based verification. To overcome this gap, we present an approach developed in the SATURN project which introduces UML profiles for the co-modeling of SystemC and C with code generation support in the context of the SysML tool suite ARTiSAN Studio®. We finally discuss the evaluation of the approach by two case studies.}}, author = {{Müller, Wolfgang and He, Da and Mischkalla, Fabian and Wegele, Arthur and Larkham, Adrian and Whiston, Paul and Penil, Pablo and Villar, Eugenio and Mitas, Nikolaos and Kritharidis, Dimitros and Azcarate, Florent and Carballeda, Manuel}}, booktitle = {{Proceedings of the IEEE Computer Society Annual Symposium on VLSI}}, keywords = {{Communicate Sequential Process Virtual Platform Smart Camera Synchronous Data Flow Artisan Studio}}, title = {{{The SATURN Approach to SysML-based HW/SW Codesign}}}, doi = {{10.1007/978-94-007-1488-5_9}}, year = {{2010}}, } @inproceedings{37048, abstract = {{We introduce a structured methodology for the generation of executable test environments from textual requirement specifications via UML class diagrams and the application of the classification tree methodology for embedded systems. The first phase is a stepwise transformation from unstructured English text into a textual normal form (TNF), which is automatically translated into UML class diagrams. After annotations of the class diagrams and the definition of test cases by sequence diagrams, both are converted into classification trees. From the classification trees we can finally generate SystemVerilog code. The methodology is introduced and evaluated by the example of an Adaptive Cruise Controller.}}, author = {{Müller, Wolfgang and Bol, Alexander and Krupp, Alexander and Lundkvist, Ola}}, editor = {{Kleinjohann, L. and Kleinjohann, B.}}, isbn = {{978-3-642-15233-7}}, keywords = {{Natural Language UML SystemVerilog Testbenches}}, publisher = {{Springer Verlag}}, title = {{{Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems}}}, doi = {{10.1007/978-3-642-15234-4_9}}, year = {{2010}}, } @inproceedings{37049, author = {{Xie, Tao and Letombe, Florian and Müller, Wolfgang}}, editor = {{Kleinjohann, L. and Kleinjohann, B.}}, publisher = {{Springer Verlag}}, title = {{{Mutation-Analysis Directed Constrained Random Verification}}}, year = {{2010}}, } @inproceedings{37051, author = {{Xie, Tao and Defo, Gilles B. and Müller, Wolfgang}}, location = {{Paris}}, title = {{{An Eclipse-based Framework for the IP-XACT-enabled Assembly of Mixed-Level IPs}}}, year = {{2010}}, } @inproceedings{37057, abstract = {{Many heterogeneous embedded systems, for example industrial automation and automotive applications, require hard-real time constraints to be exhaustively verified - which is a challenging task for the verification engineer. To cope with complexity, verification techniques working on different abstraction levels are best practice. SystemC is a versatile C++ based design and verification language, offering various mechanisms and constructs required for embedded systems modeling. Using the add-on SystemC Verification Library (SCV) elemental constrained-random stimuli techniques may be used for verification. However, SCV has several drawbacks such as lack of functional coverage. In this paper we present a functional coverage library that implements parts of the IEEE 1800-2005 SystemVerilog standard and allows capturing functional coverage throughout the design and verification process with SystemC. Moreover, we will demonstrate the usability of the approach with a case study working on a CAN bus model written in SystemC.}}, author = {{Defo, Gilles B. and Müller, Wolfgang and Kuznik, Christoph}}, booktitle = {{Proceedings of SIES 2010}}, keywords = {{Libraries, Generators, Transfer functions, Monitoring, Computational modeling, Driver circuits, Adaptation model}}, location = {{ Trento, Italy}}, publisher = {{IEEE}}, title = {{{Verification of a CAN Bus Model in SystemC with Functional Coverage}}}, doi = {{10.1109/SIES.2010.5551379}}, year = {{2010}}, } @inproceedings{37056, abstract = {{In this paper we present an approach to increase the fault tolerance in FlexRay networks by introducing backup nodes to replace defect ECUs (Electronic Control Units). In order to reduce the memory requirements of such backup nodes, we distribute redundant tasks over different nodes and propose the distributed coordinated migration of tasks of the defect ECU to the backup node at runtime. This approach enhances our former work in, where we extended the FlexRay bus schedule by redundant slots to consider changes in the communication/slot assignment and investigated and evaluated different solutions to migrate the redundant tasks to the backup node using the static and/or dynamic segment of the communication cycle for transmissions. We present the approach of distributed coordination for migration and communication instead of additional dedicated coordinator nodes to further increase the fault tolerance. With this approach we improve the safety of FlexRay networks by avoiding a possible single point of failure due to a dedicated coordinator node also minimizing the necessary time needed for a reconfiguration after an ECU failure. Furthermore, we reduce the overhead within the communication and the demand for additional hardware components.}}, author = {{Klobedanz, Kay and Defo, Gilles B. and Müller, Wolfgang and Kerstan, Timo}}, booktitle = {{Proceedings of SIES 2010}}, keywords = {{Fault tolerant systems, Protocols, Redundancy, Runtime, Payloads, Schedules}}, title = {{{Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks}}}, doi = {{10.1109/SIES.2010.5551384}}, year = {{2010}}, } @inproceedings{37053, abstract = {{Seamless HW/SW codesign flows support early verification of hardware and Hardware-dependent Software (HdS) like drivers, operating systems, and firmware. For early estimation and verification, the application of SystemC in combination with Instruction Set Simulators and Software Emulators like QEMU is widely accepted. In this article, we present an advanced design flow for HW, (RT)OS and HdS refinement and verification with focus on the transition from abstract RTOS verification to full system RTOS/HdS emulation. In the context of assertion-based verification, we introduce a set of generic real-time properties which can be reused and verified at different abstraction levels and discuss their application. The properties are presented by the means of IEEE standard PSL assertions which are applied for mixed SystemC/HdS models.}}, author = {{Müller, Wolfgang and da S. Oliveira, Marcio F. and Zabel, Henning and Becker, Markus}}, booktitle = {{Proceedings of HLDVT2010}}, keywords = {{Hardware, Microprogramming, Application software, Timing, Protocols, Virtual prototyping, Real time systems, Sampling methods, Operating systems, Emulation}}, location = {{Anaheim, FL, USA}}, publisher = {{IEEE}}, title = {{{Verification of Real-Time Properties for Hardware-Dependant Software}}}, year = {{2010}}, } @inproceedings{37060, author = {{Oliveira, Marcio F. S. and do Nascimento, Francisco Assis M. and Müller, Wolfgang}}, booktitle = {{Proceedings of MoMPES 2010}}, title = {{{Design Space Abstraction and Metamodeling for Embedded Systems Design Space Exploration}}}, year = {{2010}}, } @article{8179, abstract = {{Given the density matrix rho of a bipartite quantum state, the quantum separability problem asks whether rho is entangled or separable. In 2003, Gurvits showed that this problem is NP-hard if rho is located within an inverse exponential (with respect to dimension) distance from the border of the set of separable quantum states. In this paper, we extend this NP-hardness to an inverse polynomial distance from the separable set. The result follows from a simple combination of works by Gurvits, Ioannou, and Liu. We apply our result to show (1) an immediate lower bound on the maximum distance between a bound entangled state and the separable set (assuming P != NP), and (2) NP-hardness for the problem of determining whether a completely positive trace-preserving linear map is entanglement-breaking.}}, author = {{Gharibian, Sevag}}, journal = {{Quantum Information & Computation}}, number = {{3{\&}4}}, pages = {{343--360}}, title = {{{Strong NP-hardness of the quantum separability problem}}}, volume = {{10}}, year = {{2010}}, } @inproceedings{2223, author = {{Lübbers, Enno and Platzner, Marco and Plessl, Christian and Keller, Ariane and Plattner, Bernhard}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-60132-140-6}}, pages = {{225--231}}, publisher = {{CSREA Press}}, title = {{{Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware}}}, year = {{2010}}, }