[{"title":"Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks","conference":{"name":"International Symposium on Industrial Embedded System (SIES)"},"author":[{"full_name":"Klobedanz, Kay","first_name":"Kay","last_name":"Klobedanz"},{"last_name":"Defo","full_name":"Defo, Gilles B.","first_name":"Gilles B."},{"full_name":"Müller, Wolfgang","first_name":"Wolfgang","last_name":"Müller","id":"16243"},{"last_name":"Kerstan","first_name":"Timo","full_name":"Kerstan, Timo"}],"place":"Trento, Italien","abstract":[{"text":"In this paper we present an approach to increase the fault tolerance in FlexRay networks by introducing backup nodes to replace defect ECUs (Electronic Control Units). In order to reduce the memory requirements of such backup nodes, we distribute redundant tasks over different nodes and propose the distributed coordinated migration of tasks of the defect ECU to the backup node at runtime. This approach enhances our former work in, where we extended the FlexRay bus schedule by redundant slots to consider changes in the communication/slot assignment and investigated and evaluated different solutions to migrate the redundant tasks to the backup node using the static and/or dynamic segment of the communication cycle for transmissions. We present the approach of distributed coordination for migration and communication instead of additional dedicated coordinator nodes to further increase the fault tolerance. With this approach we improve the safety of FlexRay networks by avoiding a possible single point of failure due to a dedicated coordinator node also minimizing the necessary time needed for a reconfiguration after an ECU failure. Furthermore, we reduce the overhead within the communication and the demand for additional hardware components.","lang":"eng"}],"doi":"10.1109/SIES.2010.5551384","citation":{"ieee":"K. Klobedanz, G. B. Defo, W. Müller, and T. Kerstan, “Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks,” presented at the International Symposium on Industrial Embedded System (SIES), 2010, doi: <a href=\"https://doi.org/10.1109/SIES.2010.5551384\">10.1109/SIES.2010.5551384</a>.","chicago":"Klobedanz, Kay, Gilles B. Defo, Wolfgang Müller, and Timo Kerstan. “Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks.” In <i>Proceedings of SIES 2010</i>. Trento, Italien, 2010. <a href=\"https://doi.org/10.1109/SIES.2010.5551384\">https://doi.org/10.1109/SIES.2010.5551384</a>.","apa":"Klobedanz, K., Defo, G. B., Müller, W., &#38; Kerstan, T. (2010). Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks. <i>Proceedings of SIES 2010</i>. International Symposium on Industrial Embedded System (SIES). <a href=\"https://doi.org/10.1109/SIES.2010.5551384\">https://doi.org/10.1109/SIES.2010.5551384</a>","ama":"Klobedanz K, Defo GB, Müller W, Kerstan T. Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks. In: <i>Proceedings of SIES 2010</i>. ; 2010. doi:<a href=\"https://doi.org/10.1109/SIES.2010.5551384\">10.1109/SIES.2010.5551384</a>","short":"K. Klobedanz, G.B. Defo, W. Müller, T. Kerstan, in: Proceedings of SIES 2010, Trento, Italien, 2010.","bibtex":"@inproceedings{Klobedanz_Defo_Müller_Kerstan_2010, place={Trento, Italien}, title={Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks}, DOI={<a href=\"https://doi.org/10.1109/SIES.2010.5551384\">10.1109/SIES.2010.5551384</a>}, booktitle={Proceedings of SIES 2010}, author={Klobedanz, Kay and Defo, Gilles B. and Müller, Wolfgang and Kerstan, Timo}, year={2010} }","mla":"Klobedanz, Kay, et al. “Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks.” <i>Proceedings of SIES 2010</i>, 2010, doi:<a href=\"https://doi.org/10.1109/SIES.2010.5551384\">10.1109/SIES.2010.5551384</a>."},"keyword":["Fault tolerant systems","Protocols","Redundancy","Runtime","Payloads","Schedules"],"user_id":"5786","department":[{"_id":"672"}],"date_created":"2023-01-17T11:31:38Z","publication":"Proceedings of SIES 2010","language":[{"iso":"eng"}],"publication_identifier":{"eisbn":["978-1-4244-5841-7"]},"type":"conference","year":"2010","status":"public","_id":"37056","date_updated":"2023-01-17T11:31:47Z"},{"status":"public","publication_identifier":{"eisbn":["978-1-4244-7806-4"]},"year":"2010","type":"conference","language":[{"iso":"eng"}],"publisher":"IEEE","publication":"Proceedings of HLDVT2010","date_created":"2023-01-17T11:28:26Z","date_updated":"2023-01-17T11:28:30Z","_id":"37053","abstract":[{"lang":"eng","text":"Seamless HW/SW codesign flows support early verification of hardware and Hardware-dependent Software (HdS) like drivers, operating systems, and firmware. For early estimation and verification, the application of SystemC in combination with Instruction Set Simulators and Software Emulators like QEMU is widely accepted. In this article, we present an advanced design flow for HW, (RT)OS and HdS refinement and verification with focus on the transition from abstract RTOS verification to full system RTOS/HdS emulation. In the context of assertion-based verification, we introduce a set of generic real-time properties which can be reused and verified at different abstraction levels and discuss their application. The properties are presented by the means of IEEE standard PSL assertions which are applied for mixed SystemC/HdS models."}],"author":[{"last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang"},{"first_name":"Marcio F.","full_name":"da S. Oliveira, Marcio F.","last_name":"da S. Oliveira"},{"last_name":"Zabel","first_name":"Henning","full_name":"Zabel, Henning"},{"first_name":"Markus","full_name":"Becker, Markus","last_name":"Becker"}],"conference":{"name":"IEEE International High Level Design Validation and Test Workshop (HLDVT)","location":"Anaheim, FL, USA"},"title":"Verification of Real-Time Properties for Hardware-Dependant Software","department":[{"_id":"672"}],"user_id":"5786","keyword":["Hardware","Microprogramming","Application software","Timing","Protocols","Virtual prototyping","Real time systems","Sampling methods","Operating systems","Emulation"],"citation":{"ieee":"W. Müller, M. F. da S. Oliveira, H. Zabel, and M. Becker, “Verification of Real-Time Properties for Hardware-Dependant Software,” presented at the IEEE International High Level Design Validation and Test Workshop (HLDVT), Anaheim, FL, USA, 2010.","chicago":"Müller, Wolfgang, Marcio F. da S. Oliveira, Henning Zabel, and Markus Becker. “Verification of Real-Time Properties for Hardware-Dependant Software.” In <i>Proceedings of HLDVT2010</i>. IEEE, 2010.","short":"W. Müller, M.F. da S. Oliveira, H. Zabel, M. Becker, in: Proceedings of HLDVT2010, IEEE, 2010.","apa":"Müller, W., da S. Oliveira, M. F., Zabel, H., &#38; Becker, M. (2010). Verification of Real-Time Properties for Hardware-Dependant Software. <i>Proceedings of HLDVT2010</i>. IEEE International High Level Design Validation and Test Workshop (HLDVT), Anaheim, FL, USA.","ama":"Müller W, da S. Oliveira MF, Zabel H, Becker M. Verification of Real-Time Properties for Hardware-Dependant Software. In: <i>Proceedings of HLDVT2010</i>. IEEE; 2010.","bibtex":"@inproceedings{Müller_da S. Oliveira_Zabel_Becker_2010, title={Verification of Real-Time Properties for Hardware-Dependant Software}, booktitle={Proceedings of HLDVT2010}, publisher={IEEE}, author={Müller, Wolfgang and da S. Oliveira, Marcio F. and Zabel, Henning and Becker, Markus}, year={2010} }","mla":"Müller, Wolfgang, et al. “Verification of Real-Time Properties for Hardware-Dependant Software.” <i>Proceedings of HLDVT2010</i>, IEEE, 2010."}},{"title":"Design Space Abstraction and Metamodeling for Embedded Systems Design Space Exploration","author":[{"first_name":"Marcio F. S.","full_name":"Oliveira, Marcio F. S.","last_name":"Oliveira"},{"first_name":"Francisco Assis M.","full_name":"do Nascimento, Francisco Assis M.","last_name":"do Nascimento"},{"last_name":"Müller","id":"16243","first_name":"Wolfgang","full_name":"Müller, Wolfgang"}],"place":"Antwerp, Belgium","citation":{"bibtex":"@inproceedings{Oliveira_do Nascimento_Müller_2010, place={Antwerp, Belgium}, title={Design Space Abstraction and Metamodeling for Embedded Systems Design Space Exploration}, booktitle={Proceedings of MoMPES 2010}, author={Oliveira, Marcio F. S. and do Nascimento, Francisco Assis M. and Müller, Wolfgang}, year={2010} }","mla":"Oliveira, Marcio F. S., et al. “Design Space Abstraction and Metamodeling for Embedded Systems Design Space Exploration.” <i>Proceedings of MoMPES 2010</i>, 2010.","short":"M.F.S. Oliveira, F.A.M. do Nascimento, W. Müller, in: Proceedings of MoMPES 2010, Antwerp, Belgium, 2010.","apa":"Oliveira, M. F. S., do Nascimento, F. A. M., &#38; Müller, W. (2010). Design Space Abstraction and Metamodeling for Embedded Systems Design Space Exploration. <i>Proceedings of MoMPES 2010</i>.","ama":"Oliveira MFS, do Nascimento FAM, Müller W. Design Space Abstraction and Metamodeling for Embedded Systems Design Space Exploration. In: <i>Proceedings of MoMPES 2010</i>. ; 2010.","ieee":"M. F. S. Oliveira, F. A. M. do Nascimento, and W. Müller, “Design Space Abstraction and Metamodeling for Embedded Systems Design Space Exploration,” 2010.","chicago":"Oliveira, Marcio F. S., Francisco Assis M. do Nascimento, and Wolfgang Müller. “Design Space Abstraction and Metamodeling for Embedded Systems Design Space Exploration.” In <i>Proceedings of MoMPES 2010</i>. Antwerp, Belgium, 2010."},"user_id":"5786","department":[{"_id":"672"}],"date_created":"2023-01-17T11:37:39Z","publication":"Proceedings of MoMPES 2010","language":[{"iso":"eng"}],"year":"2010","type":"conference","status":"public","_id":"37060","date_updated":"2023-01-17T11:37:44Z"},{"date_updated":"2023-02-28T11:04:38Z","_id":"8179","language":[{"iso":"eng"}],"year":"2010","status":"public","date_created":"2019-03-01T12:09:59Z","department":[{"_id":"623"},{"_id":"7"}],"citation":{"short":"S. Gharibian, Quantum Information &#38; Computation 10 (2010) 343–360.","mla":"Gharibian, Sevag. “Strong NP-Hardness of the Quantum Separability Problem.” <i>Quantum Information &#38; Computation</i>, vol. 10, no. 3{\\ &#38; }4, 2010, pp. 343–60.","bibtex":"@article{Gharibian_2010, title={Strong NP-hardness of the quantum separability problem}, volume={10}, number={3{\\ &#38; }4}, journal={Quantum Information &#38; Computation}, author={Gharibian, Sevag}, year={2010}, pages={343–360} }","chicago":"Gharibian, Sevag. “Strong NP-Hardness of the Quantum Separability Problem.” <i>Quantum Information &#38; Computation</i> 10, no. 3{\\ &#38; }4 (2010): 343–60.","ieee":"S. Gharibian, “Strong NP-hardness of the quantum separability problem,” <i>Quantum Information &#38; Computation</i>, vol. 10, no. 3{\\ &#38; }4, pp. 343–360, 2010.","apa":"Gharibian, S. (2010). Strong NP-hardness of the quantum separability problem. <i>Quantum Information &#38; Computation</i>, <i>10</i>(3{\\ &#38; }4), 343–360.","ama":"Gharibian S. Strong NP-hardness of the quantum separability problem. <i>Quantum Information &#38; Computation</i>. 2010;10(3{\\ &#38; }4):343-360."},"publication_status":"published","intvolume":"        10","article_type":"original","author":[{"id":"71541","last_name":"Gharibian","full_name":"Gharibian, Sevag","first_name":"Sevag","orcid":"0000-0002-9992-3379"}],"issue":"3{\\&}4","page":"343-360","volume":10,"type":"journal_article","publication":"Quantum Information & Computation","external_id":{"arxiv":["0810.4507"]},"main_file_link":[{"open_access":"1","url":"https://arxiv.org/abs/0810.4507"}],"user_id":"71541","oa":"1","abstract":[{"text":"Given the density matrix rho of a bipartite quantum state, the quantum separability problem asks whether rho is entangled or separable. In 2003, Gurvits showed that this problem is NP-hard if rho is located within an inverse exponential (with respect to dimension) distance from the border of the set of separable quantum states. In this paper, we extend this NP-hardness to an inverse polynomial distance from the separable set. The result follows from a simple combination of works by Gurvits, Ioannou, and Liu. We apply our result to show (1) an immediate lower bound on the maximum distance between a bound entangled state and the separable set (assuming P != NP), and (2) NP-hardness for the problem of determining whether a completely positive trace-preserving linear map is entanglement-breaking.","lang":"eng"}],"title":"Strong NP-hardness of the quantum separability problem","extern":"1"},{"publisher":"CSREA Press","quality_controlled":"1","publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","date_created":"2018-04-05T16:27:13Z","status":"public","year":"2010","publication_identifier":{"isbn":["1-60132-140-6"]},"type":"conference","language":[{"iso":"eng"}],"_id":"2223","page":"225-231","date_updated":"2023-09-26T13:48:32Z","author":[{"first_name":"Enno","full_name":"Lübbers, Enno","last_name":"Lübbers"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"full_name":"Keller, Ariane","first_name":"Ariane","last_name":"Keller"},{"last_name":"Plattner","full_name":"Plattner, Bernhard","first_name":"Bernhard"}],"title":"Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware","user_id":"15278","citation":{"short":"E. Lübbers, M. Platzner, C. Plessl, A. Keller, B. Plattner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 225–231.","mla":"Lübbers, Enno, et al. “Towards Adaptive Networking for Embedded Devices Based on Reconfigurable Hardware.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2010, pp. 225–31.","bibtex":"@inproceedings{Lübbers_Platzner_Plessl_Keller_Plattner_2010, title={Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Lübbers, Enno and Platzner, Marco and Plessl, Christian and Keller, Ariane and Plattner, Bernhard}, year={2010}, pages={225–231} }","chicago":"Lübbers, Enno, Marco Platzner, Christian Plessl, Ariane Keller, and Bernhard Plattner. “Towards Adaptive Networking for Embedded Devices Based on Reconfigurable Hardware.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 225–31. CSREA Press, 2010.","ieee":"E. Lübbers, M. Platzner, C. Plessl, A. Keller, and B. Plattner, “Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware,” in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2010, pp. 225–231.","ama":"Lübbers E, Platzner M, Plessl C, Keller A, Plattner B. Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware. In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2010:225-231.","apa":"Lübbers, E., Platzner, M., Plessl, C., Keller, A., &#38; Plattner, B. (2010). Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware. <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 225–231."},"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}]},{"author":[{"last_name":"Grad","first_name":"Mariusz","full_name":"Grad, Mariusz"},{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982"}],"title":"Pruning the Design Space for Just-In-Time Processor Customization","doi":"10.1109/ReConFig.2010.19","place":"Los Alamitos, CA, USA","user_id":"15278","citation":{"short":"M. Grad, C. Plessl, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2010, pp. 67–72.","mla":"Grad, Mariusz, and Christian Plessl. “Pruning the Design Space for Just-In-Time Processor Customization.” <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE Computer Society, 2010, pp. 67–72, doi:<a href=\"https://doi.org/10.1109/ReConFig.2010.19\">10.1109/ReConFig.2010.19</a>.","bibtex":"@inproceedings{Grad_Plessl_2010, place={Los Alamitos, CA, USA}, title={Pruning the Design Space for Just-In-Time Processor Customization}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2010.19\">10.1109/ReConFig.2010.19</a>}, booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE Computer Society}, author={Grad, Mariusz and Plessl, Christian}, year={2010}, pages={67–72} }","chicago":"Grad, Mariusz, and Christian Plessl. “Pruning the Design Space for Just-In-Time Processor Customization.” In <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, 67–72. Los Alamitos, CA, USA: IEEE Computer Society, 2010. <a href=\"https://doi.org/10.1109/ReConFig.2010.19\">https://doi.org/10.1109/ReConFig.2010.19</a>.","ieee":"M. Grad and C. Plessl, “Pruning the Design Space for Just-In-Time Processor Customization,” in <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2010, pp. 67–72, doi: <a href=\"https://doi.org/10.1109/ReConFig.2010.19\">10.1109/ReConFig.2010.19</a>.","ama":"Grad M, Plessl C. Pruning the Design Space for Just-In-Time Processor Customization. In: <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE Computer Society; 2010:67-72. doi:<a href=\"https://doi.org/10.1109/ReConFig.2010.19\">10.1109/ReConFig.2010.19</a>","apa":"Grad, M., &#38; Plessl, C. (2010). Pruning the Design Space for Just-In-Time Processor Customization. <i>Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)</i>, 67–72. <a href=\"https://doi.org/10.1109/ReConFig.2010.19\">https://doi.org/10.1109/ReConFig.2010.19</a>"},"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publisher":"IEEE Computer Society","publication":"Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)","quality_controlled":"1","date_created":"2018-04-05T14:48:51Z","status":"public","year":"2010","type":"conference","language":[{"iso":"eng"}],"page":"67-72","_id":"2216","date_updated":"2023-09-26T13:47:11Z"},{"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","citation":{"ieee":"M. Grad and C. Plessl, “An Open Source Circuit Library with Benchmarking Facilities,” in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2010, pp. 144–150.","chicago":"Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with Benchmarking Facilities.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 144–50. CSREA Press, 2010.","apa":"Grad, M., &#38; Plessl, C. (2010). An Open Source Circuit Library with Benchmarking Facilities. <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 144–150.","ama":"Grad M, Plessl C. An Open Source Circuit Library with Benchmarking Facilities. In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2010:144-150.","short":"M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144–150.","bibtex":"@inproceedings{Grad_Plessl_2010, title={An Open Source Circuit Library with Benchmarking Facilities}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Grad, Mariusz and Plessl, Christian}, year={2010}, pages={144–150} }","mla":"Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with Benchmarking Facilities.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2010, pp. 144–50."},"author":[{"full_name":"Grad, Mariusz","first_name":"Mariusz","last_name":"Grad"},{"orcid":"0000-0001-5728-9982","id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","first_name":"Christian"}],"title":"An Open Source Circuit Library with Benchmarking Facilities","date_updated":"2023-09-26T13:48:59Z","page":"144-150","_id":"2224","status":"public","language":[{"iso":"eng"}],"year":"2010","publication_identifier":{"isbn":["1-60132-140-6"]},"type":"conference","publisher":"CSREA Press","date_created":"2018-04-05T16:28:38Z","quality_controlled":"1","publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)"},{"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"citation":{"mla":"Andrews, David, and Christian Plessl. “Configurable Processor Architectures: History and Trends.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2010, p. 165.","bibtex":"@inproceedings{Andrews_Plessl_2010, title={Configurable Processor Architectures: History and Trends}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Andrews, David and Plessl, Christian}, year={2010}, pages={165} }","short":"D. Andrews, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, p. 165.","ama":"Andrews D, Plessl C. Configurable Processor Architectures: History and Trends. In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2010:165.","apa":"Andrews, D., &#38; Plessl, C. (2010). Configurable Processor Architectures: History and Trends. <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 165.","chicago":"Andrews, David, and Christian Plessl. “Configurable Processor Architectures: History and Trends.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 165. CSREA Press, 2010.","ieee":"D. Andrews and C. Plessl, “Configurable Processor Architectures: History and Trends,” in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2010, p. 165."},"user_id":"15278","title":"Configurable Processor Architectures: History and Trends","author":[{"first_name":"David","full_name":"Andrews, David","last_name":"Andrews"},{"first_name":"Christian","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153","orcid":"0000-0001-5728-9982"}],"date_updated":"2023-09-26T13:47:33Z","page":"165","_id":"2220","publication_identifier":{"isbn":["1-60132-140-6"]},"year":"2010","type":"conference","language":[{"iso":"eng"}],"status":"public","publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","quality_controlled":"1","date_created":"2018-04-05T14:57:07Z","publisher":"CSREA Press"},{"date_updated":"2023-09-26T13:48:00Z","_id":"2222","year":"2010","type":"conference_editor","publication_identifier":{"isbn":["1-60132-140-6"]},"language":[{"iso":"eng"}],"status":"public","quality_controlled":"1","date_created":"2018-04-05T15:00:49Z","publisher":"CSREA Press","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"citation":{"short":"T.P. Plaks, D. Andrews, R. DeMara, H. Lam, J. Lee, C. Plessl, G. Stitt, eds., Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010.","mla":"Plaks, Toomas P., et al., editors. <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press, 2010.","bibtex":"@book{Plaks_Andrews_DeMara_Lam_Lee_Plessl_Stitt_2010, title={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, year={2010} }","chicago":"Plaks, Toomas P., David Andrews, Ronald DeMara, Herman Lam, Jooheung Lee, Christian Plessl, and Greg Stitt, eds. <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press, 2010.","ieee":"T. P. Plaks <i>et al.</i>, Eds., <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press, 2010.","apa":"Plaks, T. P., Andrews, D., DeMara, R., Lam, H., Lee, J., Plessl, C., &#38; Stitt, G. (Eds.). (2010). <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press.","ama":"Plaks TP, Andrews D, DeMara R, et al., eds. <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2010."},"user_id":"15278","title":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","editor":[{"full_name":"Plaks, Toomas P.","first_name":"Toomas P.","last_name":"Plaks"},{"last_name":"Andrews","full_name":"Andrews, David","first_name":"David"},{"full_name":"DeMara, Ronald","first_name":"Ronald","last_name":"DeMara"},{"full_name":"Lam, Herman","first_name":"Herman","last_name":"Lam"},{"last_name":"Lee","full_name":"Lee, Jooheung","first_name":"Jooheung"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Stitt","full_name":"Stitt, Greg","first_name":"Greg"}]},{"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"citation":{"short":"T. Beisel, M. Niekamp, C. Plessl, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010, pp. 65–72.","bibtex":"@inproceedings{Beisel_Niekamp_Plessl_2010, title={Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators}, DOI={<a href=\"https://doi.org/10.1109/ASAP.2010.5540798\">10.1109/ASAP.2010.5540798</a>}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Beisel, Tobias and Niekamp, Manuel and Plessl, Christian}, year={2010}, pages={65–72} }","mla":"Beisel, Tobias, et al. “Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators.” <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, IEEE Computer Society, 2010, pp. 65–72, doi:<a href=\"https://doi.org/10.1109/ASAP.2010.5540798\">10.1109/ASAP.2010.5540798</a>.","ieee":"T. Beisel, M. Niekamp, and C. Plessl, “Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators,” in <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, 2010, pp. 65–72, doi: <a href=\"https://doi.org/10.1109/ASAP.2010.5540798\">10.1109/ASAP.2010.5540798</a>.","chicago":"Beisel, Tobias, Manuel Niekamp, and Christian Plessl. “Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators.” In <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, 65–72. IEEE Computer Society, 2010. <a href=\"https://doi.org/10.1109/ASAP.2010.5540798\">https://doi.org/10.1109/ASAP.2010.5540798</a>.","ama":"Beisel T, Niekamp M, Plessl C. Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators. In: <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>. IEEE Computer Society; 2010:65-72. doi:<a href=\"https://doi.org/10.1109/ASAP.2010.5540798\">10.1109/ASAP.2010.5540798</a>","apa":"Beisel, T., Niekamp, M., &#38; Plessl, C. (2010). Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators. <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, 65–72. <a href=\"https://doi.org/10.1109/ASAP.2010.5540798\">https://doi.org/10.1109/ASAP.2010.5540798</a>"},"user_id":"15278","doi":"10.1109/ASAP.2010.5540798","title":"Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators","author":[{"full_name":"Beisel, Tobias","first_name":"Tobias","last_name":"Beisel"},{"first_name":"Manuel","full_name":"Niekamp, Manuel","last_name":"Niekamp"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"date_updated":"2023-09-26T13:49:21Z","_id":"2226","page":"65-72","language":[{"iso":"eng"}],"type":"conference","year":"2010","publication_identifier":{"isbn":["978-1-4244-6965-9"]},"status":"public","date_created":"2018-04-05T16:39:34Z","quality_controlled":"1","publication":"Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)","publisher":"IEEE Computer Society"},{"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","citation":{"short":"A. Keller, B. Plattner, E. Lübbers, M. Platzner, C. Plessl, in: Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp. 372–376.","mla":"Keller, Ariane, et al. “Reconfigurable Nodes for Future Networks.” <i>Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)</i>, IEEE, 2010, pp. 372–76, doi:<a href=\"https://doi.org/10.1109/GLOCOMW.2010.5700341\">10.1109/GLOCOMW.2010.5700341</a>.","bibtex":"@inproceedings{Keller_Plattner_Lübbers_Platzner_Plessl_2010, title={Reconfigurable Nodes for Future Networks}, DOI={<a href=\"https://doi.org/10.1109/GLOCOMW.2010.5700341\">10.1109/GLOCOMW.2010.5700341</a>}, booktitle={Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)}, publisher={IEEE}, author={Keller, Ariane and Plattner, Bernhard and Lübbers, Enno and Platzner, Marco and Plessl, Christian}, year={2010}, pages={372–376} }","chicago":"Keller, Ariane, Bernhard Plattner, Enno Lübbers, Marco Platzner, and Christian Plessl. “Reconfigurable Nodes for Future Networks.” In <i>Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)</i>, 372–76. IEEE, 2010. <a href=\"https://doi.org/10.1109/GLOCOMW.2010.5700341\">https://doi.org/10.1109/GLOCOMW.2010.5700341</a>.","ieee":"A. Keller, B. Plattner, E. Lübbers, M. Platzner, and C. Plessl, “Reconfigurable Nodes for Future Networks,” in <i>Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)</i>, 2010, pp. 372–376, doi: <a href=\"https://doi.org/10.1109/GLOCOMW.2010.5700341\">10.1109/GLOCOMW.2010.5700341</a>.","ama":"Keller A, Plattner B, Lübbers E, Platzner M, Plessl C. Reconfigurable Nodes for Future Networks. In: <i>Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)</i>. IEEE; 2010:372-376. doi:<a href=\"https://doi.org/10.1109/GLOCOMW.2010.5700341\">10.1109/GLOCOMW.2010.5700341</a>","apa":"Keller, A., Plattner, B., Lübbers, E., Platzner, M., &#38; Plessl, C. (2010). Reconfigurable Nodes for Future Networks. <i>Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)</i>, 372–376. <a href=\"https://doi.org/10.1109/GLOCOMW.2010.5700341\">https://doi.org/10.1109/GLOCOMW.2010.5700341</a>"},"doi":"10.1109/GLOCOMW.2010.5700341","author":[{"first_name":"Ariane","full_name":"Keller, Ariane","last_name":"Keller"},{"last_name":"Plattner","first_name":"Bernhard","full_name":"Plattner, Bernhard"},{"full_name":"Lübbers, Enno","first_name":"Enno","last_name":"Lübbers"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982"}],"title":"Reconfigurable Nodes for Future Networks","date_updated":"2023-09-26T13:51:00Z","page":"372-376","_id":"2206","status":"public","language":[{"iso":"eng"}],"year":"2010","type":"conference","publication_identifier":{"isbn":["978-1-4244-8864-3"]},"publisher":"IEEE","date_created":"2018-04-04T09:36:16Z","quality_controlled":"1","publication":"Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)"},{"title":"Rupeas: Ruby Powered Event Analysis DSL","author":[{"full_name":"Woehrle, Matthias","first_name":"Matthias","last_name":"Woehrle"},{"first_name":"Christian","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153","orcid":"0000-0001-5728-9982"},{"first_name":"Lothar","full_name":"Thiele, Lothar","last_name":"Thiele"}],"extern":"1","doi":"10.1109/INSS.2010.5572211","citation":{"short":"M. Woehrle, C. Plessl, L. Thiele, in: Proc. Int. Conf. Networked Sensing Systems (INSS), IEEE, 2010, pp. 245–248.","mla":"Woehrle, Matthias, et al. “Rupeas: Ruby Powered Event Analysis DSL.” <i>Proc. Int. Conf. Networked Sensing Systems (INSS)</i>, IEEE, 2010, pp. 245–48, doi:<a href=\"https://doi.org/10.1109/INSS.2010.5572211\">10.1109/INSS.2010.5572211</a>.","bibtex":"@inproceedings{Woehrle_Plessl_Thiele_2010, title={Rupeas: Ruby Powered Event Analysis DSL}, DOI={<a href=\"https://doi.org/10.1109/INSS.2010.5572211\">10.1109/INSS.2010.5572211</a>}, booktitle={Proc. Int. Conf. Networked Sensing Systems (INSS)}, publisher={IEEE}, author={Woehrle, Matthias and Plessl, Christian and Thiele, Lothar}, year={2010}, pages={245–248} }","chicago":"Woehrle, Matthias, Christian Plessl, and Lothar Thiele. “Rupeas: Ruby Powered Event Analysis DSL.” In <i>Proc. Int. Conf. Networked Sensing Systems (INSS)</i>, 245–48. IEEE, 2010. <a href=\"https://doi.org/10.1109/INSS.2010.5572211\">https://doi.org/10.1109/INSS.2010.5572211</a>.","ieee":"M. Woehrle, C. Plessl, and L. Thiele, “Rupeas: Ruby Powered Event Analysis DSL,” in <i>Proc. Int. Conf. Networked Sensing Systems (INSS)</i>, 2010, pp. 245–248, doi: <a href=\"https://doi.org/10.1109/INSS.2010.5572211\">10.1109/INSS.2010.5572211</a>.","ama":"Woehrle M, Plessl C, Thiele L. Rupeas: Ruby Powered Event Analysis DSL. In: <i>Proc. Int. Conf. Networked Sensing Systems (INSS)</i>. IEEE; 2010:245-248. doi:<a href=\"https://doi.org/10.1109/INSS.2010.5572211\">10.1109/INSS.2010.5572211</a>","apa":"Woehrle, M., Plessl, C., &#38; Thiele, L. (2010). Rupeas: Ruby Powered Event Analysis DSL. <i>Proc. Int. Conf. Networked Sensing Systems (INSS)</i>, 245–248. <a href=\"https://doi.org/10.1109/INSS.2010.5572211\">https://doi.org/10.1109/INSS.2010.5572211</a>"},"user_id":"15278","department":[{"_id":"27"},{"_id":"518"}],"quality_controlled":"1","publication":"Proc. Int. Conf. Networked Sensing Systems (INSS)","date_created":"2018-04-05T16:41:02Z","publisher":"IEEE","year":"2010","type":"conference","publication_identifier":{"isbn":["978-1-4244-7911-5"]},"language":[{"iso":"eng"}],"status":"public","_id":"2227","page":"245-248","date_updated":"2023-09-26T13:49:38Z"},{"author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","id":"3145","last_name":"Kenter"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"orcid":"0000-0001-5728-9982","id":"16153","last_name":"Plessl","first_name":"Christian","full_name":"Plessl, Christian"},{"first_name":"Michael","full_name":"Kauschke, Michael","last_name":"Kauschke"}],"editor":[{"first_name":"Omar","full_name":"Hammami, Omar","last_name":"Hammami"},{"last_name":"Larrabee","first_name":"Sandra","full_name":"Larrabee, Sandra"}],"title":"Performance Estimation for the Exploration of CPU-Accelerator Architectures","user_id":"15278","citation":{"ama":"Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation for the Exploration of CPU-Accelerator Architectures. In: Hammami O, Larrabee S, eds. <i>Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)</i>. ; 2010.","apa":"Kenter, T., Platzner, M., Plessl, C., &#38; Kauschke, M. (2010). Performance Estimation for the Exploration of CPU-Accelerator Architectures. In O. Hammami &#38; S. Larrabee (Eds.), <i>Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)</i>.","chicago":"Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke. “Performance Estimation for the Exploration of CPU-Accelerator Architectures.” In <i>Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)</i>, edited by Omar Hammami and Sandra Larrabee, 2010.","ieee":"T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation for the Exploration of CPU-Accelerator Architectures,” in <i>Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)</i>, 2010.","mla":"Kenter, Tobias, et al. “Performance Estimation for the Exploration of CPU-Accelerator Architectures.” <i>Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)</i>, edited by Omar Hammami and Sandra Larrabee, 2010.","bibtex":"@inproceedings{Kenter_Platzner_Plessl_Kauschke_2010, title={Performance Estimation for the Exploration of CPU-Accelerator Architectures}, booktitle={Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)}, author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}, editor={Hammami, Omar and Larrabee, Sandra}, year={2010} }","short":"T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: O. Hammami, S. Larrabee (Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), 2010."},"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"date_created":"2018-04-05T16:43:04Z","publication":"Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)","quality_controlled":"1","status":"public","language":[{"iso":"eng"}],"year":"2010","type":"conference","_id":"2228","date_updated":"2023-09-26T13:50:04Z"},{"user_id":"117512","abstract":[{"text":"<jats:title>Abstract</jats:title><jats:p>We present a new technique to implement operators that modify the topology of polygonal meshes at intersections and self‐intersections. Depending on the modification strategy, this effectively results in operators for Boolean combinations or for the construction of outer hulls that are suited for mesh repair tasks and accurate mesh‐based front tracking of deformable materials that split and merge. By combining an adaptive octree with nested binary space partitions (BSP), we can guarantee exactness (= correctness) and robustness (= completeness) of the algorithm while still achieving higher performance and less memory consumption than previous approaches. The efficiency and scalability in terms of runtime and memory is obtained by an operation localization scheme. We restrict the essential computations to those cells in the adaptive octree where intersections actually occur. Within those critical cells, we convert the input geometry into a plane‐based BSP‐representation which allows us to perform all computations exactly even with fixed precision arithmetics. We carefully analyze the precision requirements of the involved geometric data and predicates in order to guarantee correctness and show how minimal input mesh quantization can be used to safely rely on computations with standard floating point numbers. We properly evaluate our method with respect to precision, robustness, and efficiency.</jats:p>","lang":"eng"}],"doi":"10.1111/j.1467-8659.2009.01609.x","extern":"1","title":"Exact and Robust (Self‐)Intersections for Polygonal Meshes","issue":"2","volume":29,"page":"397-406","type":"journal_article","publication":"Computer Graphics Forum","department":[{"_id":"969"}],"publication_status":"published","citation":{"mla":"Campen, Marcel, and Leif Kobbelt. “Exact and Robust (Self‐)Intersections for Polygonal Meshes.” <i>Computer Graphics Forum</i>, vol. 29, no. 2, Wiley, 2010, pp. 397–406, doi:<a href=\"https://doi.org/10.1111/j.1467-8659.2009.01609.x\">10.1111/j.1467-8659.2009.01609.x</a>.","bibtex":"@article{Campen_Kobbelt_2010, title={Exact and Robust (Self‐)Intersections for Polygonal Meshes}, volume={29}, DOI={<a href=\"https://doi.org/10.1111/j.1467-8659.2009.01609.x\">10.1111/j.1467-8659.2009.01609.x</a>}, number={2}, journal={Computer Graphics Forum}, publisher={Wiley}, author={Campen, Marcel and Kobbelt, Leif}, year={2010}, pages={397–406} }","short":"M. Campen, L. Kobbelt, Computer Graphics Forum 29 (2010) 397–406.","apa":"Campen, M., &#38; Kobbelt, L. (2010). Exact and Robust (Self‐)Intersections for Polygonal Meshes. <i>Computer Graphics Forum</i>, <i>29</i>(2), 397–406. <a href=\"https://doi.org/10.1111/j.1467-8659.2009.01609.x\">https://doi.org/10.1111/j.1467-8659.2009.01609.x</a>","ama":"Campen M, Kobbelt L. Exact and Robust (Self‐)Intersections for Polygonal Meshes. <i>Computer Graphics Forum</i>. 2010;29(2):397-406. doi:<a href=\"https://doi.org/10.1111/j.1467-8659.2009.01609.x\">10.1111/j.1467-8659.2009.01609.x</a>","chicago":"Campen, Marcel, and Leif Kobbelt. “Exact and Robust (Self‐)Intersections for Polygonal Meshes.” <i>Computer Graphics Forum</i> 29, no. 2 (2010): 397–406. <a href=\"https://doi.org/10.1111/j.1467-8659.2009.01609.x\">https://doi.org/10.1111/j.1467-8659.2009.01609.x</a>.","ieee":"M. Campen and L. Kobbelt, “Exact and Robust (Self‐)Intersections for Polygonal Meshes,” <i>Computer Graphics Forum</i>, vol. 29, no. 2, pp. 397–406, 2010, doi: <a href=\"https://doi.org/10.1111/j.1467-8659.2009.01609.x\">10.1111/j.1467-8659.2009.01609.x</a>."},"intvolume":"        29","author":[{"id":"114904","last_name":"Campen","full_name":"Campen, Marcel","first_name":"Marcel","orcid":"0000-0003-2340-3462"},{"last_name":"Kobbelt","first_name":"Leif","full_name":"Kobbelt, Leif"}],"date_updated":"2025-07-14T12:35:44Z","_id":"60463","status":"public","publication_identifier":{"issn":["0167-7055","1467-8659"]},"year":"2010","language":[{"iso":"eng"}],"publisher":"Wiley","date_created":"2025-06-30T08:24:08Z"},{"user_id":"117512","title":"Polygonal Boundary Evaluation of Minkowski Sums and Swept Volumes","extern":"1","doi":"10.1111/j.1467-8659.2010.01770.x","abstract":[{"text":"<jats:title>Abstract</jats:title><jats:p>We present a novel technique for the efficient boundary evaluation of sweep operations applied to objects in polygonal boundary representation. These sweep operations include Minkowski addition, offsetting, and sweeping along a discrete rigid motion trajectory. Many previous methods focus on the construction of a polygonal superset (containing self‐intersections and spurious internal geometry) of the boundary of the volumes which are swept. Only few are able to determine a clean representation of the actual boundary, most of them in a discrete volumetric setting. We unify such superset constructions into a succinct common formulation and present a technique for the robust extraction of a polygonal mesh representing the outer boundary, i.e. it makes no general position assumptions and always yields a manifold, watertight mesh. It is exact for Minkowski sums and approximates swept volumes polygonally. By using plane‐based geometry in conjunction with hierarchical arrangement computations we avoid the necessity of arbitrary precision arithmetics and extensive special case handling. By restricting operations to regions containing pieces of the boundary, we significantly enhance the performance of the algorithm.</jats:p>","lang":"eng"}],"page":"1613-1622","volume":29,"issue":"5","publication":"Computer Graphics Forum","type":"journal_article","citation":{"ieee":"M. Campen and L. Kobbelt, “Polygonal Boundary Evaluation of Minkowski Sums and Swept Volumes,” <i>Computer Graphics Forum</i>, vol. 29, no. 5, pp. 1613–1622, 2010, doi: <a href=\"https://doi.org/10.1111/j.1467-8659.2010.01770.x\">10.1111/j.1467-8659.2010.01770.x</a>.","chicago":"Campen, Marcel, and Leif Kobbelt. “Polygonal Boundary Evaluation of Minkowski Sums and Swept Volumes.” <i>Computer Graphics Forum</i> 29, no. 5 (2010): 1613–22. <a href=\"https://doi.org/10.1111/j.1467-8659.2010.01770.x\">https://doi.org/10.1111/j.1467-8659.2010.01770.x</a>.","ama":"Campen M, Kobbelt L. Polygonal Boundary Evaluation of Minkowski Sums and Swept Volumes. <i>Computer Graphics Forum</i>. 2010;29(5):1613-1622. doi:<a href=\"https://doi.org/10.1111/j.1467-8659.2010.01770.x\">10.1111/j.1467-8659.2010.01770.x</a>","apa":"Campen, M., &#38; Kobbelt, L. (2010). Polygonal Boundary Evaluation of Minkowski Sums and Swept Volumes. <i>Computer Graphics Forum</i>, <i>29</i>(5), 1613–1622. <a href=\"https://doi.org/10.1111/j.1467-8659.2010.01770.x\">https://doi.org/10.1111/j.1467-8659.2010.01770.x</a>","short":"M. Campen, L. Kobbelt, Computer Graphics Forum 29 (2010) 1613–1622.","bibtex":"@article{Campen_Kobbelt_2010, title={Polygonal Boundary Evaluation of Minkowski Sums and Swept Volumes}, volume={29}, DOI={<a href=\"https://doi.org/10.1111/j.1467-8659.2010.01770.x\">10.1111/j.1467-8659.2010.01770.x</a>}, number={5}, journal={Computer Graphics Forum}, publisher={Wiley}, author={Campen, Marcel and Kobbelt, Leif}, year={2010}, pages={1613–1622} }","mla":"Campen, Marcel, and Leif Kobbelt. “Polygonal Boundary Evaluation of Minkowski Sums and Swept Volumes.” <i>Computer Graphics Forum</i>, vol. 29, no. 5, Wiley, 2010, pp. 1613–22, doi:<a href=\"https://doi.org/10.1111/j.1467-8659.2010.01770.x\">10.1111/j.1467-8659.2010.01770.x</a>."},"publication_status":"published","department":[{"_id":"969"}],"author":[{"orcid":"0000-0003-2340-3462","full_name":"Campen, Marcel","first_name":"Marcel","id":"114904","last_name":"Campen"},{"full_name":"Kobbelt, Leif","first_name":"Leif","last_name":"Kobbelt"}],"intvolume":"        29","_id":"60464","date_updated":"2025-07-14T12:35:40Z","date_created":"2025-06-30T08:34:20Z","publisher":"Wiley","publication_identifier":{"issn":["0167-7055","1467-8659"]},"year":"2010","language":[{"iso":"eng"}],"status":"public"},{"page":"75-87","volume":29,"issue":"1","publication":"Computer Graphics Forum","type":"journal_article","user_id":"117512","title":"Hybrid Booleans","extern":"1","abstract":[{"lang":"eng","text":"<jats:title>Abstract</jats:title><jats:p> <jats:italic>In this paper, we present a novel method to compute Boolean operations on polygonal meshes. Given a Boolean expression over an arbitrary number of input meshes we reliably and efficiently compute an output mesh which faithfully preserves the existing sharp features and precisely reconstructs the new features appearing along the intersections of the input meshes. The term “hybrid” applies to our method in two ways: First, our algorithm operates on a hybrid data structure which stores the original input polygons (surface data) in an adaptively refined octree (volume data). By this we combine the robustness of volumetric techniques with the accuracy of surface‐oriented techniques. Second, we generate a new triangulation only in a close vicinity around the intersections of the input meshes and thus preserve as much of the original mesh structure as possible (hybrid mesh). Since the actual processing of the Boolean operation is confined to a very small region around the intersections of the input meshes, we can achieve very high adaptive refinement resolutions and hence very high precision. We demonstrate our method on a number of challenging examples.</jats:italic> </jats:p>"}],"doi":"10.1111/j.1467-8659.2009.01545.x","_id":"60462","date_updated":"2025-07-14T12:35:48Z","date_created":"2025-06-30T08:22:33Z","publisher":"Wiley","language":[{"iso":"eng"}],"year":"2010","publication_identifier":{"issn":["0167-7055","1467-8659"]},"status":"public","citation":{"ieee":"D. Pavić, M. Campen, and L. Kobbelt, “Hybrid Booleans,” <i>Computer Graphics Forum</i>, vol. 29, no. 1, pp. 75–87, 2010, doi: <a href=\"https://doi.org/10.1111/j.1467-8659.2009.01545.x\">10.1111/j.1467-8659.2009.01545.x</a>.","chicago":"Pavić, Darko, Marcel Campen, and Leif Kobbelt. “Hybrid Booleans.” <i>Computer Graphics Forum</i> 29, no. 1 (2010): 75–87. <a href=\"https://doi.org/10.1111/j.1467-8659.2009.01545.x\">https://doi.org/10.1111/j.1467-8659.2009.01545.x</a>.","apa":"Pavić, D., Campen, M., &#38; Kobbelt, L. (2010). Hybrid Booleans. <i>Computer Graphics Forum</i>, <i>29</i>(1), 75–87. <a href=\"https://doi.org/10.1111/j.1467-8659.2009.01545.x\">https://doi.org/10.1111/j.1467-8659.2009.01545.x</a>","ama":"Pavić D, Campen M, Kobbelt L. Hybrid Booleans. <i>Computer Graphics Forum</i>. 2010;29(1):75-87. doi:<a href=\"https://doi.org/10.1111/j.1467-8659.2009.01545.x\">10.1111/j.1467-8659.2009.01545.x</a>","short":"D. Pavić, M. Campen, L. Kobbelt, Computer Graphics Forum 29 (2010) 75–87.","bibtex":"@article{Pavić_Campen_Kobbelt_2010, title={Hybrid Booleans}, volume={29}, DOI={<a href=\"https://doi.org/10.1111/j.1467-8659.2009.01545.x\">10.1111/j.1467-8659.2009.01545.x</a>}, number={1}, journal={Computer Graphics Forum}, publisher={Wiley}, author={Pavić, Darko and Campen, Marcel and Kobbelt, Leif}, year={2010}, pages={75–87} }","mla":"Pavić, Darko, et al. “Hybrid Booleans.” <i>Computer Graphics Forum</i>, vol. 29, no. 1, Wiley, 2010, pp. 75–87, doi:<a href=\"https://doi.org/10.1111/j.1467-8659.2009.01545.x\">10.1111/j.1467-8659.2009.01545.x</a>."},"publication_status":"published","department":[{"_id":"969"}],"author":[{"last_name":"Pavić","full_name":"Pavić, Darko","first_name":"Darko"},{"orcid":"0000-0003-2340-3462","first_name":"Marcel","full_name":"Campen, Marcel","id":"114904","last_name":"Campen"},{"first_name":"Leif","full_name":"Kobbelt, Leif","last_name":"Kobbelt"}],"intvolume":"        29"},{"series_title":"Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn","citation":{"short":"K. Lürwer-Brüggemeier, Mächtigkeit Und Komplexität von Berechnungen Mit Der Ganzzahligen Division, Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2009.","bibtex":"@book{Lürwer-Brüggemeier_2009, series={Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}, title={Mächtigkeit und Komplexität von Berechnungen mit der ganzzahligen Division}, volume={261}, publisher={Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}, author={Lürwer-Brüggemeier, Katharina}, year={2009}, collection={Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn} }","mla":"Lürwer-Brüggemeier, Katharina. <i>Mächtigkeit Und Komplexität von Berechnungen Mit Der Ganzzahligen Division</i>. Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2009.","ieee":"K. Lürwer-Brüggemeier, <i>Mächtigkeit und Komplexität von Berechnungen mit der ganzzahligen Division</i>, vol. 261. Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2009.","chicago":"Lürwer-Brüggemeier, Katharina. <i>Mächtigkeit Und Komplexität von Berechnungen Mit Der Ganzzahligen Division</i>. Vol. 261. Verlagsschriftenreihe Des Heinz Nixdorf Instituts, Paderborn. Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2009.","ama":"Lürwer-Brüggemeier K. <i>Mächtigkeit Und Komplexität von Berechnungen Mit Der Ganzzahligen Division</i>. Vol 261. Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn; 2009.","apa":"Lürwer-Brüggemeier, K. (2009). <i>Mächtigkeit und Komplexität von Berechnungen mit der ganzzahligen Division</i> (Vol. 261). Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn."},"user_id":"5786","department":[{"_id":"63"},{"_id":"26"}],"title":"Mächtigkeit und Komplexität von Berechnungen mit der ganzzahligen Division","author":[{"full_name":"Lürwer-Brüggemeier, Katharina","first_name":"Katharina","last_name":"Lürwer-Brüggemeier"}],"supervisor":[{"full_name":"Meyer auf der Heide, Friedhelm","first_name":"Friedhelm","last_name":"Meyer auf der Heide","id":"15523"}],"intvolume":"       261","_id":"19605","volume":261,"date_updated":"2022-01-06T06:54:07Z","date_created":"2020-09-21T14:07:23Z","related_material":{"link":[{"url":"http://digital.ub.uni-paderborn.de/ubpb/urn/urn:nbn:de:hbz:466-20090212010","relation":"confirmation"}]},"publisher":"Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn","type":"dissertation","year":"2009","language":[{"iso":"eng"}],"status":"public"},{"status":"public","language":[{"iso":"eng"}],"type":"dissertation","year":"2009","publication_identifier":{"isbn":["978-3-939350-79-8"]},"publisher":"Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn","date_created":"2020-09-22T08:05:15Z","related_material":{"link":[{"relation":"confirmation","url":"http://digital.ub.uni-paderborn.de/ubpb/urn/urn:nbn:de:hbz:466-20090206016"}]},"date_updated":"2022-01-06T06:54:08Z","volume":260,"_id":"19614","intvolume":"       260","supervisor":[{"id":"15523","last_name":"Meyer auf der Heide","full_name":"Meyer auf der Heide, Friedhelm","first_name":"Friedhelm"}],"author":[{"last_name":"Mense","first_name":"Mario","full_name":"Mense, Mario"}],"title":"On Fault-Tolerant Data Placement in Storage Networks","department":[{"_id":"63"},{"_id":"26"}],"user_id":"5786","citation":{"ama":"Mense M. <i>On Fault-Tolerant Data Placement in Storage Networks</i>. Vol 260. Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn; 2009.","apa":"Mense, M. (2009). <i>On Fault-Tolerant Data Placement in Storage Networks</i> (Vol. 260). Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn.","ieee":"M. Mense, <i>On Fault-Tolerant Data Placement in Storage Networks</i>, vol. 260. Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2009.","chicago":"Mense, Mario. <i>On Fault-Tolerant Data Placement in Storage Networks</i>. Vol. 260. Verlagsschriftenreihe Des Heinz Nixdorf Instituts, Paderborn. Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2009.","bibtex":"@book{Mense_2009, series={Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}, title={On Fault-Tolerant Data Placement in Storage Networks}, volume={260}, publisher={Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}, author={Mense, Mario}, year={2009}, collection={Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn} }","mla":"Mense, Mario. <i>On Fault-Tolerant Data Placement in Storage Networks</i>. Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2009.","short":"M. Mense, On Fault-Tolerant Data Placement in Storage Networks, Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2009."},"series_title":"Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn"},{"series_title":"Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn","citation":{"short":"M. Kortenjan, Size Equivalent Cluster Trees - Rendering CAD Models in Industrial Scenes, Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2009.","mla":"Kortenjan, Michael. <i>Size Equivalent Cluster Trees - Rendering CAD Models in Industrial Scenes</i>. Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2009.","bibtex":"@book{Kortenjan_2009, series={Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}, title={Size Equivalent Cluster Trees - Rendering CAD Models in Industrial Scenes}, volume={258}, publisher={Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}, author={Kortenjan, Michael}, year={2009}, collection={Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn} }","chicago":"Kortenjan, Michael. <i>Size Equivalent Cluster Trees - Rendering CAD Models in Industrial Scenes</i>. Vol. 258. Verlagsschriftenreihe Des Heinz Nixdorf Instituts, Paderborn. Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2009.","ieee":"M. Kortenjan, <i>Size Equivalent Cluster Trees - Rendering CAD Models in Industrial Scenes</i>, vol. 258. Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2009.","ama":"Kortenjan M. <i>Size Equivalent Cluster Trees - Rendering CAD Models in Industrial Scenes</i>. Vol 258. Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn; 2009.","apa":"Kortenjan, M. (2009). <i>Size Equivalent Cluster Trees - Rendering CAD Models in Industrial Scenes</i> (Vol. 258). Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn."},"user_id":"5786","department":[{"_id":"63"},{"_id":"26"}],"title":"Size Equivalent Cluster Trees - Rendering CAD Models in Industrial Scenes","author":[{"last_name":"Kortenjan","full_name":"Kortenjan, Michael","first_name":"Michael"}],"supervisor":[{"id":"15523","last_name":"Meyer auf der Heide","full_name":"Meyer auf der Heide, Friedhelm","first_name":"Friedhelm"}],"intvolume":"       258","_id":"19617","volume":258,"date_updated":"2022-01-06T06:54:08Z","date_created":"2020-09-22T08:42:22Z","related_material":{"link":[{"relation":"confirmation","url":"http://digital.ub.uni-paderborn.de/ubpb/urn/urn:nbn:de:hbz:466-20081218010"}]},"publisher":"Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn","publication_identifier":{"isbn":["978-3-939350-77-4"]},"type":"dissertation","year":"2009","language":[{"iso":"eng"}],"status":"public"},{"publisher":"Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn","related_material":{"link":[{"relation":"confirmation","url":"http://digital.ub.uni-paderborn.de/ubpb/urn/urn:nbn:de:hbz:466-20080623016"}]},"date_created":"2020-09-22T08:44:45Z","status":"public","language":[{"iso":"eng"}],"type":"dissertation","publication_identifier":{"isbn":["978-3-939350-76-7"]},"year":"2009","volume":257,"_id":"19618","date_updated":"2022-01-06T06:54:08Z","author":[{"last_name":"Bonorden","full_name":"Bonorden, Olaf","first_name":"Olaf"}],"title":"Versatility of Bulk Synchronous Parallel Computing: From the Heterogeneous Cluster to the System on Chip","intvolume":"       257","supervisor":[{"last_name":"Meyer auf der Heide","id":"15523","first_name":"Friedhelm","full_name":"Meyer auf der Heide, Friedhelm"}],"user_id":"5786","citation":{"bibtex":"@book{Bonorden_2009, series={Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}, title={Versatility of Bulk Synchronous Parallel Computing: From the Heterogeneous Cluster to the System on Chip}, volume={257}, publisher={Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}, author={Bonorden, Olaf}, year={2009}, collection={Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn} }","mla":"Bonorden, Olaf. <i>Versatility of Bulk Synchronous Parallel Computing: From the Heterogeneous Cluster to the System on Chip</i>. Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2009.","short":"O. Bonorden, Versatility of Bulk Synchronous Parallel Computing: From the Heterogeneous Cluster to the System on Chip, Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2009.","apa":"Bonorden, O. (2009). <i>Versatility of Bulk Synchronous Parallel Computing: From the Heterogeneous Cluster to the System on Chip</i> (Vol. 257). Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn.","ama":"Bonorden O. <i>Versatility of Bulk Synchronous Parallel Computing: From the Heterogeneous Cluster to the System on Chip</i>. Vol 257. Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn; 2009.","ieee":"O. Bonorden, <i>Versatility of Bulk Synchronous Parallel Computing: From the Heterogeneous Cluster to the System on Chip</i>, vol. 257. Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2009.","chicago":"Bonorden, Olaf. <i>Versatility of Bulk Synchronous Parallel Computing: From the Heterogeneous Cluster to the System on Chip</i>. Vol. 257. Verlagsschriftenreihe Des Heinz Nixdorf Instituts, Paderborn. Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2009."},"series_title":"Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn","department":[{"_id":"63"},{"_id":"26"}]}]