---
_id: '10627'
author:
- first_name: Arne
  full_name: Bockhorn, Arne
  last_name: Bockhorn
citation:
  ama: Bockhorn A. <i>Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost
    DSP Evaluation Board</i>. Paderborn University; 2014.
  apa: Bockhorn, A. (2014). <i>Echtzeit Klassifikation von sEMG Signalen mit einem
    low-cost DSP Evaluation Board</i>. Paderborn University.
  bibtex: '@book{Bockhorn_2014, title={Echtzeit Klassifikation von sEMG Signalen mit
    einem low-cost DSP Evaluation Board}, publisher={Paderborn University}, author={Bockhorn,
    Arne}, year={2014} }'
  chicago: Bockhorn, Arne. <i>Echtzeit Klassifikation von SEMG Signalen Mit Einem
    Low-Cost DSP Evaluation Board</i>. Paderborn University, 2014.
  ieee: A. Bockhorn, <i>Echtzeit Klassifikation von sEMG Signalen mit einem low-cost
    DSP Evaluation Board</i>. Paderborn University, 2014.
  mla: Bockhorn, Arne. <i>Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost
    DSP Evaluation Board</i>. Paderborn University, 2014.
  short: A. Bockhorn, Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost
    DSP Evaluation Board, Paderborn University, 2014.
date_created: 2019-07-10T09:40:25Z
date_updated: 2022-01-06T06:50:48Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Alexander
  full_name: Boschmann, Alexander
  last_name: Boschmann
title: Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation
  Board
type: bachelorsthesis
user_id: '3118'
year: '2014'
...
---
_id: '10632'
author:
- first_name: Alexander
  full_name: Boschmann, Alexander
  last_name: Boschmann
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Boschmann A, Platzner M. A computer vision-based approach to high density
    EMG pattern recognition using structural similarity. In: <i>Proc. MyoElectric
    Controls Symposium (MEC)</i>. ; 2014.'
  apa: Boschmann, A., &#38; Platzner, M. (2014). A computer vision-based approach
    to high density EMG pattern recognition using structural similarity. In <i>Proc.
    MyoElectric Controls Symposium (MEC)</i>.
  bibtex: '@inproceedings{Boschmann_Platzner_2014, title={A computer vision-based
    approach to high density EMG pattern recognition using structural similarity},
    booktitle={Proc. MyoElectric Controls Symposium (MEC)}, author={Boschmann, Alexander
    and Platzner, Marco}, year={2014} }'
  chicago: Boschmann, Alexander, and Marco Platzner. “A Computer Vision-Based Approach
    to High Density EMG Pattern Recognition Using Structural Similarity.” In <i>Proc.
    MyoElectric Controls Symposium (MEC)</i>, 2014.
  ieee: A. Boschmann and M. Platzner, “A computer vision-based approach to high density
    EMG pattern recognition using structural similarity,” in <i>Proc. MyoElectric
    Controls Symposium (MEC)</i>, 2014.
  mla: Boschmann, Alexander, and Marco Platzner. “A Computer Vision-Based Approach
    to High Density EMG Pattern Recognition Using Structural Similarity.” <i>Proc.
    MyoElectric Controls Symposium (MEC)</i>, 2014.
  short: 'A. Boschmann, M. Platzner, in: Proc. MyoElectric Controls Symposium (MEC),
    2014.'
date_created: 2019-07-10T11:02:58Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publication: Proc. MyoElectric Controls Symposium (MEC)
status: public
title: A computer vision-based approach to high density EMG pattern recognition using
  structural similarity
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10633'
author:
- first_name: Alexander
  full_name: Boschmann, Alexander
  last_name: Boschmann
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Boschmann A, Platzner M. Towards robust HD EMG pattern recognition: Reducing
    electrode displacement effect using structural similarity. In: <i>Proc. IEEE Int.
    Conf. Eng. Med. Biolog. (EMBC)</i>. ; 2014.'
  apa: 'Boschmann, A., &#38; Platzner, M. (2014). Towards robust HD EMG pattern recognition:
    Reducing electrode displacement effect using structural similarity. In <i>Proc.
    IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>.'
  bibtex: '@inproceedings{Boschmann_Platzner_2014, title={Towards robust HD EMG pattern
    recognition: Reducing electrode displacement effect using structural similarity},
    booktitle={Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)}, author={Boschmann,
    Alexander and Platzner, Marco}, year={2014} }'
  chicago: 'Boschmann, Alexander, and Marco Platzner. “Towards Robust HD EMG Pattern
    Recognition: Reducing Electrode Displacement Effect Using Structural Similarity.”
    In <i>Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>, 2014.'
  ieee: 'A. Boschmann and M. Platzner, “Towards robust HD EMG pattern recognition:
    Reducing electrode displacement effect using structural similarity,” in <i>Proc.
    IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>, 2014.'
  mla: 'Boschmann, Alexander, and Marco Platzner. “Towards Robust HD EMG Pattern Recognition:
    Reducing Electrode Displacement Effect Using Structural Similarity.” <i>Proc.
    IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>, 2014.'
  short: 'A. Boschmann, M. Platzner, in: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC),
    2014.'
date_created: 2019-07-10T11:02:59Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publication: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)
status: public
title: 'Towards robust HD EMG pattern recognition: Reducing electrode displacement
  effect using structural similarity'
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10640'
author:
- first_name: Marcel
  full_name: Brand, Marcel
  last_name: Brand
citation:
  ama: Brand M. <i>A Generalized Loop Accelerator Implemented as a Coarse-Grained
    Array</i>. Paderborn University; 2014.
  apa: Brand, M. (2014). <i>A Generalized Loop Accelerator Implemented as a Coarse-Grained
    Array</i>. Paderborn University.
  bibtex: '@book{Brand_2014, title={A Generalized Loop Accelerator Implemented as
    a Coarse-Grained Array}, publisher={Paderborn University}, author={Brand, Marcel},
    year={2014} }'
  chicago: Brand, Marcel. <i>A Generalized Loop Accelerator Implemented as a Coarse-Grained
    Array</i>. Paderborn University, 2014.
  ieee: M. Brand, <i>A Generalized Loop Accelerator Implemented as a Coarse-Grained
    Array</i>. Paderborn University, 2014.
  mla: Brand, Marcel. <i>A Generalized Loop Accelerator Implemented as a Coarse-Grained
    Array</i>. Paderborn University, 2014.
  short: M. Brand, A Generalized Loop Accelerator Implemented as a Coarse-Grained
    Array, Paderborn University, 2014.
date_created: 2019-07-10T11:03:41Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: A Generalized Loop Accelerator Implemented as a Coarse-Grained Array
type: mastersthesis
user_id: '3118'
year: '2014'
...
---
_id: '10645'
author:
- first_name: Marvin
  full_name: Damschen, Marvin
  last_name: Damschen
citation:
  ama: Damschen M. <i>Easy-to-Use-on-the-Fly Binary Program Acceleration on Many-Cores</i>.
    Paderborn University; 2014.
  apa: Damschen, M. (2014). <i>Easy-to-use-on-the-fly binary program acceleration
    on many-cores</i>. Paderborn University.
  bibtex: '@book{Damschen_2014, title={Easy-to-use-on-the-fly binary program acceleration
    on many-cores}, publisher={Paderborn University}, author={Damschen, Marvin}, year={2014}
    }'
  chicago: Damschen, Marvin. <i>Easy-to-Use-on-the-Fly Binary Program Acceleration
    on Many-Cores</i>. Paderborn University, 2014.
  ieee: M. Damschen, <i>Easy-to-use-on-the-fly binary program acceleration on many-cores</i>.
    Paderborn University, 2014.
  mla: Damschen, Marvin. <i>Easy-to-Use-on-the-Fly Binary Program Acceleration on
    Many-Cores</i>. Paderborn University, 2014.
  short: M. Damschen, Easy-to-Use-on-the-Fly Binary Program Acceleration on Many-Cores,
    Paderborn University, 2014.
date_created: 2019-07-10T11:08:47Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Easy-to-use-on-the-fly binary program acceleration on many-cores
type: mastersthesis
user_id: '3118'
year: '2014'
...
---
_id: '10654'
author:
- first_name: Kyrre
  full_name: Glette, Kyrre
  last_name: Glette
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
citation:
  ama: 'Glette K, Kaufmann P. Lookup Table Partial Reconfiguration for an Evolvable
    Hardware Classifier System. In: <i>IEEE Congress on Evolutionary Computation (CEC)</i>.
    ; 2014.'
  apa: Glette, K., &#38; Kaufmann, P. (2014). Lookup Table Partial Reconfiguration
    for an Evolvable Hardware Classifier System. In <i>IEEE Congress on Evolutionary
    Computation (CEC)</i>.
  bibtex: '@inproceedings{Glette_Kaufmann_2014, title={Lookup Table Partial Reconfiguration
    for an Evolvable Hardware Classifier System}, booktitle={IEEE Congress on Evolutionary
    Computation (CEC)}, author={Glette, Kyrre and Kaufmann, Paul}, year={2014} }'
  chicago: Glette, Kyrre, and Paul Kaufmann. “Lookup Table Partial Reconfiguration
    for an Evolvable Hardware Classifier System.” In <i>IEEE Congress on Evolutionary
    Computation (CEC)</i>, 2014.
  ieee: K. Glette and P. Kaufmann, “Lookup Table Partial Reconfiguration for an Evolvable
    Hardware Classifier System,” in <i>IEEE Congress on Evolutionary Computation (CEC)</i>,
    2014.
  mla: Glette, Kyrre, and Paul Kaufmann. “Lookup Table Partial Reconfiguration for
    an Evolvable Hardware Classifier System.” <i>IEEE Congress on Evolutionary Computation
    (CEC)</i>, 2014.
  short: 'K. Glette, P. Kaufmann, in: IEEE Congress on Evolutionary Computation (CEC),
    2014.'
date_created: 2019-07-10T11:13:14Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
publication: IEEE Congress on Evolutionary Computation (CEC)
status: public
title: Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10665'
author:
- first_name: Christoph
  full_name: Hagedorn, Christoph
  last_name: Hagedorn
citation:
  ama: Hagedorn C. <i>Entwicklung Einer Codegrößenoptimierten Softwarebibliothek Für
    8-Bit Mikrocontroller in Netzunabhängigen Notleuchten</i>. Paderborn University;
    2014.
  apa: Hagedorn, C. (2014). <i>Entwicklung einer codegrößenoptimierten Softwarebibliothek
    für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten</i>. Paderborn University.
  bibtex: '@book{Hagedorn_2014, title={Entwicklung einer codegrößenoptimierten Softwarebibliothek
    für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten}, publisher={Paderborn
    University}, author={Hagedorn, Christoph}, year={2014} }'
  chicago: Hagedorn, Christoph. <i>Entwicklung Einer Codegrößenoptimierten Softwarebibliothek
    Für 8-Bit Mikrocontroller in Netzunabhängigen Notleuchten</i>. Paderborn University,
    2014.
  ieee: C. Hagedorn, <i>Entwicklung einer codegrößenoptimierten Softwarebibliothek
    für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten</i>. Paderborn University,
    2014.
  mla: Hagedorn, Christoph. <i>Entwicklung Einer Codegrößenoptimierten Softwarebibliothek
    Für 8-Bit Mikrocontroller in Netzunabhängigen Notleuchten</i>. Paderborn University,
    2014.
  short: C. Hagedorn, Entwicklung Einer Codegrößenoptimierten Softwarebibliothek Für
    8-Bit Mikrocontroller in Netzunabhängigen Notleuchten, Paderborn University, 2014.
date_created: 2019-07-10T11:15:09Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Sebastian
  full_name: Meisner, Sebastian
  last_name: Meisner
title: Entwicklung einer codegrößenoptimierten Softwarebibliothek für 8-Bit Mikrocontroller
  in netzunabhängigen Notleuchten
type: bachelorsthesis
user_id: '3118'
year: '2014'
...
---
_id: '10674'
author:
- first_name: Nam
  full_name: Ho, Nam
  last_name: Ho
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Ho N, Kaufmann P, Platzner M. A hardware/software infrastructure for performance
    monitoring on LEON3 multicore platforms. In: <i>24th Intl. Conf. on Field Programmable
    Logic and Applications (FPL)</i>. ; 2014:1-4. doi:<a href="https://doi.org/10.1109/FPL.2014.6927437">10.1109/FPL.2014.6927437</a>'
  apa: Ho, N., Kaufmann, P., &#38; Platzner, M. (2014). A hardware/software infrastructure
    for performance monitoring on LEON3 multicore platforms. In <i>24th Intl. Conf.
    on Field Programmable Logic and Applications (FPL)</i> (pp. 1–4). <a href="https://doi.org/10.1109/FPL.2014.6927437">https://doi.org/10.1109/FPL.2014.6927437</a>
  bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2014, title={A hardware/software infrastructure
    for performance monitoring on LEON3 multicore platforms}, DOI={<a href="https://doi.org/10.1109/FPL.2014.6927437">10.1109/FPL.2014.6927437</a>},
    booktitle={24th Intl. Conf. on Field Programmable Logic and Applications (FPL)},
    author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={1–4}
    }'
  chicago: Ho, Nam, Paul Kaufmann, and Marco Platzner. “A Hardware/Software Infrastructure
    for Performance Monitoring on LEON3 Multicore Platforms.” In <i>24th Intl. Conf.
    on Field Programmable Logic and Applications (FPL)</i>, 1–4, 2014. <a href="https://doi.org/10.1109/FPL.2014.6927437">https://doi.org/10.1109/FPL.2014.6927437</a>.
  ieee: N. Ho, P. Kaufmann, and M. Platzner, “A hardware/software infrastructure for
    performance monitoring on LEON3 multicore platforms,” in <i>24th Intl. Conf. on
    Field Programmable Logic and Applications (FPL)</i>, 2014, pp. 1–4.
  mla: Ho, Nam, et al. “A Hardware/Software Infrastructure for Performance Monitoring
    on LEON3 Multicore Platforms.” <i>24th Intl. Conf. on Field Programmable Logic
    and Applications (FPL)</i>, 2014, pp. 1–4, doi:<a href="https://doi.org/10.1109/FPL.2014.6927437">10.1109/FPL.2014.6927437</a>.
  short: 'N. Ho, P. Kaufmann, M. Platzner, in: 24th Intl. Conf. on Field Programmable
    Logic and Applications (FPL), 2014, pp. 1–4.'
date_created: 2019-07-10T11:18:01Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/FPL.2014.6927437
keyword:
- Linux
- hardware-software codesign
- multiprocessing systems
- parallel processing
- LEON3 multicore platform
- Linux kernel
- PMU
- hardware counters
- hardware-software infrastructure
- high performance embedded computing
- perf_event
- performance monitoring unit
- Computer architecture
- Hardware
- Monitoring
- Phasor measurement units
- Radiation detectors
- Registers
- Software
language:
- iso: eng
page: 1-4
project:
- _id: '31'
  grant_number: '257906'
  name: Engineering Proprioception in Computing Systems
publication: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL)
status: public
title: A hardware/software infrastructure for performance monitoring on LEON3 multicore
  platforms
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10677'
author:
- first_name: Nam
  full_name: Ho, Nam
  last_name: Ho
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Ho N, Kaufmann P, Platzner M. Towards self-adaptive caches: A run-time reconfigurable
    multi-core infrastructure. In: <i>2014 {IEEE} Intl. Conf. on Evolvable Systems
    (ICES)</i>. ; 2014:31-37. doi:<a href="https://doi.org/10.1109/ICES.2014.7008719">10.1109/ICES.2014.7008719</a>'
  apa: 'Ho, N., Kaufmann, P., &#38; Platzner, M. (2014). Towards self-adaptive caches:
    A run-time reconfigurable multi-core infrastructure. In <i>2014 {IEEE} Intl. Conf.
    on Evolvable Systems (ICES)</i> (pp. 31–37). <a href="https://doi.org/10.1109/ICES.2014.7008719">https://doi.org/10.1109/ICES.2014.7008719</a>'
  bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2014, title={Towards self-adaptive
    caches: A run-time reconfigurable multi-core infrastructure}, DOI={<a href="https://doi.org/10.1109/ICES.2014.7008719">10.1109/ICES.2014.7008719</a>},
    booktitle={2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}, author={Ho, Nam
    and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={31–37} }'
  chicago: 'Ho, Nam, Paul Kaufmann, and Marco Platzner. “Towards Self-Adaptive Caches:
    A Run-Time Reconfigurable Multi-Core Infrastructure.” In <i>2014 {IEEE} Intl.
    Conf. on Evolvable Systems (ICES)</i>, 31–37, 2014. <a href="https://doi.org/10.1109/ICES.2014.7008719">https://doi.org/10.1109/ICES.2014.7008719</a>.'
  ieee: 'N. Ho, P. Kaufmann, and M. Platzner, “Towards self-adaptive caches: A run-time
    reconfigurable multi-core infrastructure,” in <i>2014 {IEEE} Intl. Conf. on Evolvable
    Systems (ICES)</i>, 2014, pp. 31–37.'
  mla: 'Ho, Nam, et al. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core
    Infrastructure.” <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i>, 2014,
    pp. 31–37, doi:<a href="https://doi.org/10.1109/ICES.2014.7008719">10.1109/ICES.2014.7008719</a>.'
  short: 'N. Ho, P. Kaufmann, M. Platzner, in: 2014 {IEEE} Intl. Conf. on Evolvable
    Systems (ICES), 2014, pp. 31–37.'
date_created: 2019-07-10T11:23:00Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/ICES.2014.7008719
keyword:
- Linux
- cache storage
- embedded systems
- granular computing
- multiprocessing systems
- reconfigurable architectures
- Leon3 SPARe processor
- custom logic events
- evolvable-self-adaptable processor cache
- fine granular profiling
- integer unit events
- measurement infrastructure
- microarchitectural events
- multicore embedded system
- perf_event standard Linux performance measurement interface
- processor properties
- run-time reconfigurable memory-to-cache address mapping engine
- run-time reconfigurable multicore infrastructure
- split-level caching
- Field programmable gate arrays
- Frequency locked loops
- Irrigation
- Phasor measurement units
- Registers
- Weaving
language:
- iso: eng
page: 31-37
publication: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)
status: public
title: 'Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure'
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10679'
author:
- first_name: Fabian
  full_name: König, Fabian
  last_name: König
citation:
  ama: König F. <i>EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer
    Virtuellen Prothese</i>. Paderborn University; 2014.
  apa: König, F. (2014). <i>EMG-basierte simultane und proportionale Online-Steuerung
    einer virtuellen Prothese</i>. Paderborn University.
  bibtex: '@book{König_2014, title={EMG-basierte simultane und proportionale Online-Steuerung
    einer virtuellen Prothese}, publisher={Paderborn University}, author={König, Fabian},
    year={2014} }'
  chicago: König, Fabian. <i>EMG-Basierte Simultane Und Proportionale Online-Steuerung
    Einer Virtuellen Prothese</i>. Paderborn University, 2014.
  ieee: F. König, <i>EMG-basierte simultane und proportionale Online-Steuerung einer
    virtuellen Prothese</i>. Paderborn University, 2014.
  mla: König, Fabian. <i>EMG-Basierte Simultane Und Proportionale Online-Steuerung
    Einer Virtuellen Prothese</i>. Paderborn University, 2014.
  short: F. König, EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer
    Virtuellen Prothese, Paderborn University, 2014.
date_created: 2019-07-10T11:23:20Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Alexander
  full_name: Boschmann, Alexander
  last_name: Boschmann
title: EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen
  Prothese
type: bachelorsthesis
user_id: '3118'
year: '2014'
...
---
_id: '10701'
author:
- first_name: Benjamin
  full_name: Koch, Benjamin
  last_name: Koch
citation:
  ama: Koch B. <i>Hardware Acceleration of Mechatronic Controllers on a Zynq Platform
    FPGA</i>. Paderborn University; 2014.
  apa: Koch, B. (2014). <i>Hardware Acceleration of Mechatronic Controllers on a Zynq
    Platform FPGA</i>. Paderborn University.
  bibtex: '@book{Koch_2014, title={Hardware Acceleration of Mechatronic Controllers
    on a Zynq Platform FPGA}, publisher={Paderborn University}, author={Koch, Benjamin},
    year={2014} }'
  chicago: Koch, Benjamin. <i>Hardware Acceleration of Mechatronic Controllers on
    a Zynq Platform FPGA</i>. Paderborn University, 2014.
  ieee: B. Koch, <i>Hardware Acceleration of Mechatronic Controllers on a Zynq Platform
    FPGA</i>. Paderborn University, 2014.
  mla: Koch, Benjamin. <i>Hardware Acceleration of Mechatronic Controllers on a Zynq
    Platform FPGA</i>. Paderborn University, 2014.
  short: B. Koch, Hardware Acceleration of Mechatronic Controllers on a Zynq Platform
    FPGA, Paderborn University, 2014.
date_created: 2019-07-10T11:38:27Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA
type: mastersthesis
user_id: '3118'
year: '2014'
...
---
_id: '10715'
author:
- first_name: Robert
  full_name: Mittendorf, Robert
  last_name: Mittendorf
citation:
  ama: Mittendorf R. <i>Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading
    and FPGAs</i>. Paderborn University; 2014.
  apa: Mittendorf, R. (2014). <i>Advanced AES-key recovery from decayed RAM using
    multi-threading and FPGAs</i>. Paderborn University.
  bibtex: '@book{Mittendorf_2014, title={Advanced AES-key recovery from decayed RAM
    using multi-threading and FPGAs}, publisher={Paderborn University}, author={Mittendorf,
    Robert}, year={2014} }'
  chicago: Mittendorf, Robert. <i>Advanced AES-Key Recovery from Decayed RAM Using
    Multi-Threading and FPGAs</i>. Paderborn University, 2014.
  ieee: R. Mittendorf, <i>Advanced AES-key recovery from decayed RAM using multi-threading
    and FPGAs</i>. Paderborn University, 2014.
  mla: Mittendorf, Robert. <i>Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading
    and FPGAs</i>. Paderborn University, 2014.
  short: R. Mittendorf, Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading
    and FPGAs, Paderborn University, 2014.
date_created: 2019-07-10T11:48:26Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs
type: mastersthesis
user_id: '3118'
year: '2014'
...
---
_id: '10732'
author:
- first_name: Christoph
  full_name: Rüthing, Christoph
  last_name: Rüthing
citation:
  ama: Rüthing C. <i>The Xilinx Zynq Architecture as a Platform for Reconfigurable
    Heterogeneous Multi-Cores</i>. Paderborn University; 2014.
  apa: Rüthing, C. (2014). <i>The Xilinx Zynq Architecture as a Platform for Reconfigurable
    Heterogeneous Multi-Cores</i>. Paderborn University.
  bibtex: '@book{Rüthing_2014, title={The Xilinx Zynq Architecture as a Platform for
    Reconfigurable Heterogeneous Multi-Cores}, publisher={Paderborn University}, author={Rüthing,
    Christoph}, year={2014} }'
  chicago: Rüthing, Christoph. <i>The Xilinx Zynq Architecture as a Platform for Reconfigurable
    Heterogeneous Multi-Cores</i>. Paderborn University, 2014.
  ieee: C. Rüthing, <i>The Xilinx Zynq Architecture as a Platform for Reconfigurable
    Heterogeneous Multi-Cores</i>. Paderborn University, 2014.
  mla: Rüthing, Christoph. <i>The Xilinx Zynq Architecture as a Platform for Reconfigurable
    Heterogeneous Multi-Cores</i>. Paderborn University, 2014.
  short: C. Rüthing, The Xilinx Zynq Architecture as a Platform for Reconfigurable
    Heterogeneous Multi-Cores, Paderborn University, 2014.
date_created: 2019-07-10T11:58:05Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
title: The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous
  Multi-Cores
type: bachelorsthesis
user_id: '3118'
year: '2014'
...
---
_id: '10733'
abstract:
- lang: eng
  text: "Monte-Carlo Tree Search (MCTS) is a class of simulation-based search algorithms.
    It brought about great success in the past few years regarding the evaluation
    of deterministic two-player games such as the Asian board game Go.\r\n\r\nIn this
    thesis, we present a parallelization of the most popular MCTS variant for large
    HPC compute clusters that efficiently shares a single game tree representation
    in a distributed memory environment and scales up to 128 compute nodes and 2048
    cores. It is hereby one of the most powerful MCTS parallelizations to date.\r\n\r\nIn
    order to measure the impact of our parallelization on the search quality and remain
    comparable to the most advanced MCTS implementations to date, we implemented it
    in a state-of-the-art Go engine Gomorra, making it competitive with the strongest
    Go programs in the world.\r\n\r\nWe further present an empirical comparison of
    different Bayesian ranking systems when being used for predicting expert moves
    for the game of Go and introduce a novel technique for automated detection and
    analysis of evaluation uncertainties that show up during MCTS searches."
author:
- first_name: Lars
  full_name: Schäfers, Lars
  last_name: Schäfers
citation:
  ama: 'Schäfers L. <i>Parallel Monte-Carlo Tree Search for HPC Systems and Its Application
    to Computer Go</i>. Berlin: Logos Verlag Berlin GmbH; 2014.'
  apa: 'Schäfers, L. (2014). <i>Parallel Monte-Carlo Tree Search for HPC Systems and
    its Application to Computer Go</i>. Berlin: Logos Verlag Berlin GmbH.'
  bibtex: '@book{Schäfers_2014, place={Berlin}, title={Parallel Monte-Carlo Tree Search
    for HPC Systems and its Application to Computer Go}, publisher={Logos Verlag Berlin
    GmbH}, author={Schäfers, Lars}, year={2014} }'
  chicago: 'Schäfers, Lars. <i>Parallel Monte-Carlo Tree Search for HPC Systems and
    Its Application to Computer Go</i>. Berlin: Logos Verlag Berlin GmbH, 2014.'
  ieee: 'L. Schäfers, <i>Parallel Monte-Carlo Tree Search for HPC Systems and its
    Application to Computer Go</i>. Berlin: Logos Verlag Berlin GmbH, 2014.'
  mla: Schäfers, Lars. <i>Parallel Monte-Carlo Tree Search for HPC Systems and Its
    Application to Computer Go</i>. Logos Verlag Berlin GmbH, 2014.
  short: L. Schäfers, Parallel Monte-Carlo Tree Search for HPC Systems and Its Application
    to Computer Go, Logos Verlag Berlin GmbH, Berlin, 2014.
date_created: 2019-07-10T11:58:06Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
page: '133'
place: Berlin
publication_identifier:
  isbn:
  - 978-3-8325-3748-7
publication_status: published
publisher: Logos Verlag Berlin GmbH
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer
  Go
type: dissertation
user_id: '3118'
year: '2014'
...
---
_id: '10738'
author:
- first_name: Cong
  full_name: Shen, Cong
  last_name: Shen
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Martin
  full_name: Braun, Martin
  last_name: Braun
citation:
  ama: 'Shen C, Kaufmann P, Braun M. Optimizing the Generator Start-up Sequence After
    a Power System Blackout. In: <i>IEEE Power and Energy Society General Meeting
    (IEEE GM)</i>. ; 2014.'
  apa: Shen, C., Kaufmann, P., &#38; Braun, M. (2014). Optimizing the Generator Start-up
    Sequence After a Power System Blackout. In <i>IEEE Power and Energy Society General
    Meeting (IEEE GM)</i>.
  bibtex: '@inproceedings{Shen_Kaufmann_Braun_2014, title={Optimizing the Generator
    Start-up Sequence After a Power System Blackout}, booktitle={IEEE Power and Energy
    Society General Meeting (IEEE GM)}, author={Shen, Cong and Kaufmann, Paul and
    Braun, Martin}, year={2014} }'
  chicago: Shen, Cong, Paul Kaufmann, and Martin Braun. “Optimizing the Generator
    Start-up Sequence After a Power System Blackout.” In <i>IEEE Power and Energy
    Society General Meeting (IEEE GM)</i>, 2014.
  ieee: C. Shen, P. Kaufmann, and M. Braun, “Optimizing the Generator Start-up Sequence
    After a Power System Blackout,” in <i>IEEE Power and Energy Society General Meeting
    (IEEE GM)</i>, 2014.
  mla: Shen, Cong, et al. “Optimizing the Generator Start-up Sequence After a Power
    System Blackout.” <i>IEEE Power and Energy Society General Meeting (IEEE GM)</i>,
    2014.
  short: 'C. Shen, P. Kaufmann, M. Braun, in: IEEE Power and Energy Society General
    Meeting (IEEE GM), 2014.'
date_created: 2019-07-10T11:59:36Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
publication: IEEE Power and Energy Society General Meeting (IEEE GM)
status: public
title: Optimizing the Generator Start-up Sequence After a Power System Blackout
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10739'
author:
- first_name: Cong
  full_name: Shen, Cong
  last_name: Shen
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Martin
  full_name: Braun, Martin
  last_name: Braun
citation:
  ama: 'Shen C, Kaufmann P, Braun M. A New Distribution Network Reconfiguration and
    Restoration Path Selection Algorithm. In: <i>Power Systems Computation Conference
    (PSCC)</i>. IEEE; 2014.'
  apa: Shen, C., Kaufmann, P., &#38; Braun, M. (2014). A New Distribution Network
    Reconfiguration and Restoration Path Selection Algorithm. In <i>Power Systems
    Computation Conference (PSCC)</i>. IEEE.
  bibtex: '@inproceedings{Shen_Kaufmann_Braun_2014, title={A New Distribution Network
    Reconfiguration and Restoration Path Selection Algorithm}, booktitle={Power Systems
    Computation Conference (PSCC)}, publisher={IEEE}, author={Shen, Cong and Kaufmann,
    Paul and Braun, Martin}, year={2014} }'
  chicago: Shen, Cong, Paul Kaufmann, and Martin Braun. “A New Distribution Network
    Reconfiguration and Restoration Path Selection Algorithm.” In <i>Power Systems
    Computation Conference (PSCC)</i>. IEEE, 2014.
  ieee: C. Shen, P. Kaufmann, and M. Braun, “A New Distribution Network Reconfiguration
    and Restoration Path Selection Algorithm,” in <i>Power Systems Computation Conference
    (PSCC)</i>, 2014.
  mla: Shen, Cong, et al. “A New Distribution Network Reconfiguration and Restoration
    Path Selection Algorithm.” <i>Power Systems Computation Conference (PSCC)</i>,
    IEEE, 2014.
  short: 'C. Shen, P. Kaufmann, M. Braun, in: Power Systems Computation Conference
    (PSCC), IEEE, 2014.'
date_created: 2019-07-10T11:59:37Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
publication: Power Systems Computation Conference (PSCC)
publisher: IEEE
status: public
title: A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10744'
author:
- first_name: Sebastian
  full_name: Surmund, Sebastian
  last_name: Surmund
citation:
  ama: Surmund S. <i>Multithreaded Parallelization of Mechatronic Controllers on a
    Zynq Platform FPGA</i>. Paderborn University; 2014.
  apa: Surmund, S. (2014). <i>Multithreaded Parallelization of Mechatronic Controllers
    on a Zynq Platform FPGA</i>. Paderborn University.
  bibtex: '@book{Surmund_2014, title={Multithreaded Parallelization of Mechatronic
    Controllers on a Zynq Platform FPGA}, publisher={Paderborn University}, author={Surmund,
    Sebastian}, year={2014} }'
  chicago: Surmund, Sebastian. <i>Multithreaded Parallelization of Mechatronic Controllers
    on a Zynq Platform FPGA</i>. Paderborn University, 2014.
  ieee: S. Surmund, <i>Multithreaded Parallelization of Mechatronic Controllers on
    a Zynq Platform FPGA</i>. Paderborn University, 2014.
  mla: Surmund, Sebastian. <i>Multithreaded Parallelization of Mechatronic Controllers
    on a Zynq Platform FPGA</i>. Paderborn University, 2014.
  short: S. Surmund, Multithreaded Parallelization of Mechatronic Controllers on a
    Zynq Platform FPGA, Paderborn University, 2014.
date_created: 2019-07-10T12:00:45Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform
  FPGA
type: mastersthesis
user_id: '3118'
year: '2014'
...
---
_id: '10756'
author:
- first_name: Anna
  full_name: I. Esparcia-Alc{\'a}zar, Anna
  last_name: I. Esparcia-Alc{\'a}zar
- first_name: A.E.
  full_name: Eiben, A.E.
  last_name: Eiben
- first_name: Alexandros
  full_name: Agapitos, Alexandros
  last_name: Agapitos
- first_name: Anabela
  full_name: Sim{\~o}es, Anabela
  last_name: Sim{\~o}es
- first_name: Andrea
  full_name: G.B. Tettamanzi, Andrea
  last_name: G.B. Tettamanzi
- first_name: Antonio
  full_name: Della Cioppa, Antonio
  last_name: Della Cioppa
- first_name: Antonio
  full_name: M. Mora, Antonio
  last_name: M. Mora
- first_name: Carlos
  full_name: Cotta, Carlos
  last_name: Cotta
- first_name: Ernesto
  full_name: Tarantino, Ernesto
  last_name: Tarantino
- first_name: Evert
  full_name: Haasdijk, Evert
  last_name: Haasdijk
- first_name: Federico
  full_name: Divina, Federico
  last_name: Divina
- first_name: Francisco
  full_name: Fern{\'a}ndez de Vega, Francisco
  last_name: Fern{\'a}ndez de Vega
- first_name: Giovanni
  full_name: Squillero, Giovanni
  last_name: Squillero
- first_name: Ivanoe
  full_name: De Falco, Ivanoe
  last_name: De Falco
- first_name: J.
  full_name: Ignacio Hidalgo, J.
  last_name: Ignacio Hidalgo
- first_name: Kevin
  full_name: Sim, Kevin
  last_name: Sim
- first_name: Kyrre
  full_name: Glette, Kyrre
  last_name: Glette
- first_name: Mengjie
  full_name: Zhang, Mengjie
  last_name: Zhang
- first_name: Neil
  full_name: Urquhart, Neil
  last_name: Urquhart
- first_name: Paolo
  full_name: Burelli, Paolo
  last_name: Burelli
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Petr
  full_name: Po{\v s}{\'\i}k, Petr
  last_name: Po{\v s}{\'\i}k
- first_name: Robert
  full_name: Schaefer, Robert
  last_name: Schaefer
- first_name: Rolf
  full_name: Drechsler, Rolf
  last_name: Drechsler
- first_name: Sophia
  full_name: Antipolis, Sophia
  last_name: Antipolis
- first_name: Stefano
  full_name: Cagnoni, Stefano
  last_name: Cagnoni
- first_name: Trung
  full_name: Thanh Nguyen, Trung
  last_name: Thanh Nguyen
- first_name: William
  full_name: S. Bush (editors), William
  last_name: S. Bush (editors)
citation:
  ama: 'I. Esparcia-Alc{\’a}zar A, Eiben AE, Agapitos A, et al. <i>Applications of
    Evolutionary Computation - 17th European Conference, EvoApplications</i>. Vol
    8602. Granada, Spain: Springer; 2014.'
  apa: 'I. Esparcia-Alc{\’a}zar, A., Eiben, A. E., Agapitos, A., Sim{\~o}es, A., G.B.
    Tettamanzi, A., Della Cioppa, A., … S. Bush (editors), W. (2014). <i>Applications
    of Evolutionary Computation - 17th European Conference, EvoApplications</i> (Vol.
    8602). Granada, Spain: Springer.'
  bibtex: '@book{I. Esparcia-Alc{\’a}zar_Eiben_Agapitos_Sim{\~o}es_G.B. Tettamanzi_Della
    Cioppa_M. Mora_Cotta_Tarantino_Haasdijk_et al._2014, place={Granada, Spain}, series={Lecture
    Notes in Computer Science}, title={Applications of Evolutionary Computation -
    17th European Conference, EvoApplications}, volume={8602}, publisher={Springer},
    author={I. Esparcia-Alc{\’a}zar, Anna and Eiben, A.E. and Agapitos, Alexandros
    and Sim{\~o}es, Anabela and G.B. Tettamanzi, Andrea and Della Cioppa, Antonio
    and M. Mora, Antonio and Cotta, Carlos and Tarantino, Ernesto and Haasdijk, Evert
    and et al.}, year={2014}, collection={Lecture Notes in Computer Science} }'
  chicago: 'I. Esparcia-Alc{\’a}zar, Anna, A.E. Eiben, Alexandros Agapitos, Anabela
    Sim{\~o}es, Andrea G.B. Tettamanzi, Antonio Della Cioppa, Antonio M. Mora, et
    al. <i>Applications of Evolutionary Computation - 17th European Conference, EvoApplications</i>.
    Vol. 8602. Lecture Notes in Computer Science. Granada, Spain: Springer, 2014.'
  ieee: 'A. I. Esparcia-Alc{\’a}zar <i>et al.</i>, <i>Applications of Evolutionary
    Computation - 17th European Conference, EvoApplications</i>, vol. 8602. Granada,
    Spain: Springer, 2014.'
  mla: I. Esparcia-Alc{\’a}zar, Anna, et al. <i>Applications of Evolutionary Computation
    - 17th European Conference, EvoApplications</i>. Vol. 8602, Springer, 2014.
  short: A. I. Esparcia-Alc{\’a}zar, A.E. Eiben, A. Agapitos, A. Sim{\~o}es, A. G.B.
    Tettamanzi, A. Della Cioppa, A. M. Mora, C. Cotta, E. Tarantino, E. Haasdijk,
    F. Divina, F. Fern{\’a}ndez de Vega, G. Squillero, I. De Falco, J. Ignacio Hidalgo,
    K. Sim, K. Glette, M. Zhang, N. Urquhart, P. Burelli, P. Kaufmann, P. Po{\v s}{\’\i}k,
    R. Schaefer, R. Drechsler, S. Antipolis, S. Cagnoni, T. Thanh Nguyen, W. S. Bush
    (editors), Applications of Evolutionary Computation - 17th European Conference,
    EvoApplications, Springer, Granada, Spain, 2014.
date_created: 2019-07-10T12:06:33Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
intvolume: '      8602'
place: Granada, Spain
publisher: Springer
series_title: Lecture Notes in Computer Science
status: public
title: Applications of Evolutionary Computation - 17th European Conference, EvoApplications
type: book
user_id: '3118'
volume: 8602
year: '2014'
...
---
_id: '10764'
author:
- first_name: Jahanzeb
  full_name: Anwer, Jahanzeb
  last_name: Anwer
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Anwer J, Platzner M. Analytic reliability evaluation for fault-tolerant circuit
    structures on FPGAs. In: <i>IEEE International Symposium on Defect and Fault Tolerance
    in VLSI and Nanotechnology Systems (DFT)</i>. IEEE; 2014:177-184. doi:<a href="https://doi.org/10.1109/DFT.2014.6962108">10.1109/DFT.2014.6962108</a>'
  apa: Anwer, J., &#38; Platzner, M. (2014). Analytic reliability evaluation for fault-tolerant
    circuit structures on FPGAs. In <i>IEEE International Symposium on Defect and
    Fault Tolerance in VLSI and Nanotechnology Systems (DFT)</i> (pp. 177–184). IEEE.
    <a href="https://doi.org/10.1109/DFT.2014.6962108">https://doi.org/10.1109/DFT.2014.6962108</a>
  bibtex: '@inproceedings{Anwer_Platzner_2014, title={Analytic reliability evaluation
    for fault-tolerant circuit structures on FPGAs}, DOI={<a href="https://doi.org/10.1109/DFT.2014.6962108">10.1109/DFT.2014.6962108</a>},
    booktitle={IEEE International Symposium on Defect and Fault Tolerance in VLSI
    and Nanotechnology Systems (DFT)}, publisher={IEEE}, author={Anwer, Jahanzeb and
    Platzner, Marco}, year={2014}, pages={177–184} }'
  chicago: Anwer, Jahanzeb, and Marco Platzner. “Analytic Reliability Evaluation for
    Fault-Tolerant Circuit Structures on FPGAs.” In <i>IEEE International Symposium
    on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)</i>, 177–84.
    IEEE, 2014. <a href="https://doi.org/10.1109/DFT.2014.6962108">https://doi.org/10.1109/DFT.2014.6962108</a>.
  ieee: J. Anwer and M. Platzner, “Analytic reliability evaluation for fault-tolerant
    circuit structures on FPGAs,” in <i>IEEE International Symposium on Defect and
    Fault Tolerance in VLSI and Nanotechnology Systems (DFT)</i>, 2014, pp. 177–184.
  mla: Anwer, Jahanzeb, and Marco Platzner. “Analytic Reliability Evaluation for Fault-Tolerant
    Circuit Structures on FPGAs.” <i>IEEE International Symposium on Defect and Fault
    Tolerance in VLSI and Nanotechnology Systems (DFT)</i>, IEEE, 2014, pp. 177–84,
    doi:<a href="https://doi.org/10.1109/DFT.2014.6962108">10.1109/DFT.2014.6962108</a>.
  short: 'J. Anwer, M. Platzner, in: IEEE International Symposium on Defect and Fault
    Tolerance in VLSI and Nanotechnology Systems (DFT), IEEE, 2014, pp. 177–184.'
date_created: 2019-07-10T12:07:05Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/DFT.2014.6962108
language:
- iso: eng
page: 177-184
publication: IEEE International Symposium on Defect and Fault Tolerance in VLSI and
  Nanotechnology Systems (DFT)
publisher: IEEE
status: public
title: Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs
type: conference
user_id: '398'
year: '2014'
...
---
_id: '10773'
author:
- first_name: Hassan
  full_name: Ghasemzadeh Mohammadi, Hassan
  id: '61186'
  last_name: Ghasemzadeh Mohammadi
- first_name: Pierre-Emmanuel
  full_name: Gaillardon, Pierre-Emmanuel
  last_name: Gaillardon
- first_name: Majid
  full_name: Yazdani, Majid
  last_name: Yazdani
- first_name: Giovanni
  full_name: De Micheli, Giovanni
  last_name: De Micheli
citation:
  ama: 'Ghasemzadeh Mohammadi H, Gaillardon P-E, Yazdani M, De Micheli G. Fast process
    variation analysis in nano-scaled technologies using column-wise sparse parameter
    selection. In: <i>2014 IEEE/ACM International Symposium on Nanoscale Architectures
    (NANOARCH)</i>. IEEE; 2014:163-168. doi:<a href="https://doi.org/10.1109/NANOARCH.2014.6880479">10.1109/NANOARCH.2014.6880479</a>'
  apa: Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., Yazdani, M., &#38; De Micheli,
    G. (2014). Fast process variation analysis in nano-scaled technologies using column-wise
    sparse parameter selection. In <i>2014 IEEE/ACM International Symposium on Nanoscale
    Architectures (NANOARCH)</i> (pp. 163–168). IEEE. <a href="https://doi.org/10.1109/NANOARCH.2014.6880479">https://doi.org/10.1109/NANOARCH.2014.6880479</a>
  bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Gaillardon_Yazdani_De Micheli_2014,
    title={Fast process variation analysis in nano-scaled technologies using column-wise
    sparse parameter selection}, DOI={<a href="https://doi.org/10.1109/NANOARCH.2014.6880479">10.1109/NANOARCH.2014.6880479</a>},
    booktitle={2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)},
    publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel
    and Yazdani, Majid and De Micheli, Giovanni}, year={2014}, pages={163–168} }'
  chicago: Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, Majid Yazdani,
    and Giovanni De Micheli. “Fast Process Variation Analysis in Nano-Scaled Technologies
    Using Column-Wise Sparse Parameter Selection.” In <i>2014 IEEE/ACM International
    Symposium on Nanoscale Architectures (NANOARCH)</i>, 163–68. IEEE, 2014. <a href="https://doi.org/10.1109/NANOARCH.2014.6880479">https://doi.org/10.1109/NANOARCH.2014.6880479</a>.
  ieee: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, and G. De Micheli,
    “Fast process variation analysis in nano-scaled technologies using column-wise
    sparse parameter selection,” in <i>2014 IEEE/ACM International Symposium on Nanoscale
    Architectures (NANOARCH)</i>, 2014, pp. 163–168.
  mla: Ghasemzadeh Mohammadi, Hassan, et al. “Fast Process Variation Analysis in Nano-Scaled
    Technologies Using Column-Wise Sparse Parameter Selection.” <i>2014 IEEE/ACM International
    Symposium on Nanoscale Architectures (NANOARCH)</i>, IEEE, 2014, pp. 163–68, doi:<a
    href="https://doi.org/10.1109/NANOARCH.2014.6880479">10.1109/NANOARCH.2014.6880479</a>.
  short: 'H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, G. De Micheli, in:
    2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), IEEE,
    2014, pp. 163–168.'
date_created: 2019-07-10T12:10:16Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/NANOARCH.2014.6880479
extern: '1'
language:
- iso: eng
page: 163-168
publication: 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
publisher: IEEE
status: public
title: Fast process variation analysis in nano-scaled technologies using column-wise
  sparse parameter selection
type: conference
user_id: '3118'
year: '2014'
...