---
_id: '37056'
abstract:
- lang: eng
text: In this paper we present an approach to increase the fault tolerance in FlexRay
networks by introducing backup nodes to replace defect ECUs (Electronic Control
Units). In order to reduce the memory requirements of such backup nodes, we distribute
redundant tasks over different nodes and propose the distributed coordinated migration
of tasks of the defect ECU to the backup node at runtime. This approach enhances
our former work in, where we extended the FlexRay bus schedule by redundant slots
to consider changes in the communication/slot assignment and investigated and
evaluated different solutions to migrate the redundant tasks to the backup node
using the static and/or dynamic segment of the communication cycle for transmissions.
We present the approach of distributed coordination for migration and communication
instead of additional dedicated coordinator nodes to further increase the fault
tolerance. With this approach we improve the safety of FlexRay networks by avoiding
a possible single point of failure due to a dedicated coordinator node also minimizing
the necessary time needed for a reconfiguration after an ECU failure. Furthermore,
we reduce the overhead within the communication and the demand for additional
hardware components.
author:
- first_name: Kay
full_name: Klobedanz, Kay
last_name: Klobedanz
- first_name: Gilles B.
full_name: Defo, Gilles B.
last_name: Defo
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Timo
full_name: Kerstan, Timo
last_name: Kerstan
citation:
ama: 'Klobedanz K, Defo GB, Müller W, Kerstan T. Distributed Coordination of Task
Migration for Fault-Tolerant FlexRay Networks. In: Proceedings of SIES 2010.
; 2010. doi:10.1109/SIES.2010.5551384'
apa: Klobedanz, K., Defo, G. B., Müller, W., & Kerstan, T. (2010). Distributed
Coordination of Task Migration for Fault-Tolerant FlexRay Networks. Proceedings
of SIES 2010. International Symposium on Industrial Embedded System (SIES).
https://doi.org/10.1109/SIES.2010.5551384
bibtex: '@inproceedings{Klobedanz_Defo_Müller_Kerstan_2010, place={Trento, Italien},
title={Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks},
DOI={10.1109/SIES.2010.5551384},
booktitle={Proceedings of SIES 2010}, author={Klobedanz, Kay and Defo, Gilles
B. and Müller, Wolfgang and Kerstan, Timo}, year={2010} }'
chicago: Klobedanz, Kay, Gilles B. Defo, Wolfgang Müller, and Timo Kerstan. “Distributed
Coordination of Task Migration for Fault-Tolerant FlexRay Networks.” In Proceedings
of SIES 2010. Trento, Italien, 2010. https://doi.org/10.1109/SIES.2010.5551384.
ieee: 'K. Klobedanz, G. B. Defo, W. Müller, and T. Kerstan, “Distributed Coordination
of Task Migration for Fault-Tolerant FlexRay Networks,” presented at the International
Symposium on Industrial Embedded System (SIES), 2010, doi: 10.1109/SIES.2010.5551384.'
mla: Klobedanz, Kay, et al. “Distributed Coordination of Task Migration for Fault-Tolerant
FlexRay Networks.” Proceedings of SIES 2010, 2010, doi:10.1109/SIES.2010.5551384.
short: 'K. Klobedanz, G.B. Defo, W. Müller, T. Kerstan, in: Proceedings of SIES
2010, Trento, Italien, 2010.'
conference:
name: International Symposium on Industrial Embedded System (SIES)
date_created: 2023-01-17T11:31:38Z
date_updated: 2023-01-17T11:31:47Z
department:
- _id: '672'
doi: 10.1109/SIES.2010.5551384
keyword:
- Fault tolerant systems
- Protocols
- Redundancy
- Runtime
- Payloads
- Schedules
language:
- iso: eng
place: Trento, Italien
publication: Proceedings of SIES 2010
publication_identifier:
eisbn:
- 978-1-4244-5841-7
status: public
title: Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37053'
abstract:
- lang: eng
text: Seamless HW/SW codesign flows support early verification of hardware and Hardware-dependent
Software (HdS) like drivers, operating systems, and firmware. For early estimation
and verification, the application of SystemC in combination with Instruction Set
Simulators and Software Emulators like QEMU is widely accepted. In this article,
we present an advanced design flow for HW, (RT)OS and HdS refinement and verification
with focus on the transition from abstract RTOS verification to full system RTOS/HdS
emulation. In the context of assertion-based verification, we introduce a set
of generic real-time properties which can be reused and verified at different
abstraction levels and discuss their application. The properties are presented
by the means of IEEE standard PSL assertions which are applied for mixed SystemC/HdS
models.
author:
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Marcio F.
full_name: da S. Oliveira, Marcio F.
last_name: da S. Oliveira
- first_name: Henning
full_name: Zabel, Henning
last_name: Zabel
- first_name: Markus
full_name: Becker, Markus
last_name: Becker
citation:
ama: 'Müller W, da S. Oliveira MF, Zabel H, Becker M. Verification of Real-Time
Properties for Hardware-Dependant Software. In: Proceedings of HLDVT2010.
IEEE; 2010.'
apa: Müller, W., da S. Oliveira, M. F., Zabel, H., & Becker, M. (2010). Verification
of Real-Time Properties for Hardware-Dependant Software. Proceedings of HLDVT2010.
IEEE International High Level Design Validation and Test Workshop (HLDVT), Anaheim,
FL, USA.
bibtex: '@inproceedings{Müller_da S. Oliveira_Zabel_Becker_2010, title={Verification
of Real-Time Properties for Hardware-Dependant Software}, booktitle={Proceedings
of HLDVT2010}, publisher={IEEE}, author={Müller, Wolfgang and da S. Oliveira,
Marcio F. and Zabel, Henning and Becker, Markus}, year={2010} }'
chicago: Müller, Wolfgang, Marcio F. da S. Oliveira, Henning Zabel, and Markus Becker.
“Verification of Real-Time Properties for Hardware-Dependant Software.” In Proceedings
of HLDVT2010. IEEE, 2010.
ieee: W. Müller, M. F. da S. Oliveira, H. Zabel, and M. Becker, “Verification of
Real-Time Properties for Hardware-Dependant Software,” presented at the IEEE International
High Level Design Validation and Test Workshop (HLDVT), Anaheim, FL, USA, 2010.
mla: Müller, Wolfgang, et al. “Verification of Real-Time Properties for Hardware-Dependant
Software.” Proceedings of HLDVT2010, IEEE, 2010.
short: 'W. Müller, M.F. da S. Oliveira, H. Zabel, M. Becker, in: Proceedings of
HLDVT2010, IEEE, 2010.'
conference:
location: Anaheim, FL, USA
name: IEEE International High Level Design Validation and Test Workshop (HLDVT)
date_created: 2023-01-17T11:28:26Z
date_updated: 2023-01-17T11:28:30Z
department:
- _id: '672'
keyword:
- Hardware
- Microprogramming
- Application software
- Timing
- Protocols
- Virtual prototyping
- Real time systems
- Sampling methods
- Operating systems
- Emulation
language:
- iso: eng
publication: Proceedings of HLDVT2010
publication_identifier:
eisbn:
- 978-1-4244-7806-4
publisher: IEEE
status: public
title: Verification of Real-Time Properties for Hardware-Dependant Software
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '37060'
author:
- first_name: Marcio F. S.
full_name: Oliveira, Marcio F. S.
last_name: Oliveira
- first_name: Francisco Assis M.
full_name: do Nascimento, Francisco Assis M.
last_name: do Nascimento
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Oliveira MFS, do Nascimento FAM, Müller W. Design Space Abstraction and Metamodeling
for Embedded Systems Design Space Exploration. In: Proceedings of MoMPES 2010.
; 2010.'
apa: Oliveira, M. F. S., do Nascimento, F. A. M., & Müller, W. (2010). Design
Space Abstraction and Metamodeling for Embedded Systems Design Space Exploration.
Proceedings of MoMPES 2010.
bibtex: '@inproceedings{Oliveira_do Nascimento_Müller_2010, place={Antwerp, Belgium},
title={Design Space Abstraction and Metamodeling for Embedded Systems Design Space
Exploration}, booktitle={Proceedings of MoMPES 2010}, author={Oliveira, Marcio
F. S. and do Nascimento, Francisco Assis M. and Müller, Wolfgang}, year={2010}
}'
chicago: Oliveira, Marcio F. S., Francisco Assis M. do Nascimento, and Wolfgang
Müller. “Design Space Abstraction and Metamodeling for Embedded Systems Design
Space Exploration.” In Proceedings of MoMPES 2010. Antwerp, Belgium, 2010.
ieee: M. F. S. Oliveira, F. A. M. do Nascimento, and W. Müller, “Design Space Abstraction
and Metamodeling for Embedded Systems Design Space Exploration,” 2010.
mla: Oliveira, Marcio F. S., et al. “Design Space Abstraction and Metamodeling for
Embedded Systems Design Space Exploration.” Proceedings of MoMPES 2010,
2010.
short: 'M.F.S. Oliveira, F.A.M. do Nascimento, W. Müller, in: Proceedings of MoMPES
2010, Antwerp, Belgium, 2010.'
date_created: 2023-01-17T11:37:39Z
date_updated: 2023-01-17T11:37:44Z
department:
- _id: '672'
language:
- iso: eng
place: Antwerp, Belgium
publication: Proceedings of MoMPES 2010
status: public
title: Design Space Abstraction and Metamodeling for Embedded Systems Design Space
Exploration
type: conference
user_id: '5786'
year: '2010'
...
---
_id: '8179'
abstract:
- lang: eng
text: Given the density matrix rho of a bipartite quantum state, the quantum separability
problem asks whether rho is entangled or separable. In 2003, Gurvits showed that
this problem is NP-hard if rho is located within an inverse exponential (with
respect to dimension) distance from the border of the set of separable quantum
states. In this paper, we extend this NP-hardness to an inverse polynomial distance
from the separable set. The result follows from a simple combination of works
by Gurvits, Ioannou, and Liu. We apply our result to show (1) an immediate lower
bound on the maximum distance between a bound entangled state and the separable
set (assuming P != NP), and (2) NP-hardness for the problem of determining whether
a completely positive trace-preserving linear map is entanglement-breaking.
article_type: original
author:
- first_name: Sevag
full_name: Gharibian, Sevag
id: '71541'
last_name: Gharibian
orcid: 0000-0002-9992-3379
citation:
ama: Gharibian S. Strong NP-hardness of the quantum separability problem. Quantum
Information & Computation. 2010;10(3{\ & }4):343-360.
apa: Gharibian, S. (2010). Strong NP-hardness of the quantum separability problem.
Quantum Information & Computation, 10(3{\ & }4), 343–360.
bibtex: '@article{Gharibian_2010, title={Strong NP-hardness of the quantum separability
problem}, volume={10}, number={3{\ & }4}, journal={Quantum Information &
Computation}, author={Gharibian, Sevag}, year={2010}, pages={343–360} }'
chicago: 'Gharibian, Sevag. “Strong NP-Hardness of the Quantum Separability Problem.”
Quantum Information & Computation 10, no. 3{\ & }4 (2010): 343–60.'
ieee: S. Gharibian, “Strong NP-hardness of the quantum separability problem,” Quantum
Information & Computation, vol. 10, no. 3{\ & }4, pp. 343–360, 2010.
mla: Gharibian, Sevag. “Strong NP-Hardness of the Quantum Separability Problem.”
Quantum Information & Computation, vol. 10, no. 3{\ & }4, 2010,
pp. 343–60.
short: S. Gharibian, Quantum Information & Computation 10 (2010) 343–360.
date_created: 2019-03-01T12:09:59Z
date_updated: 2023-02-28T11:04:38Z
department:
- _id: '623'
- _id: '7'
extern: '1'
external_id:
arxiv:
- '0810.4507'
intvolume: ' 10'
issue: 3{\&}4
language:
- iso: eng
main_file_link:
- open_access: '1'
url: https://arxiv.org/abs/0810.4507
oa: '1'
page: 343-360
publication: Quantum Information & Computation
publication_status: published
status: public
title: Strong NP-hardness of the quantum separability problem
type: journal_article
user_id: '71541'
volume: 10
year: '2010'
...
---
_id: '2223'
author:
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Ariane
full_name: Keller, Ariane
last_name: Keller
- first_name: Bernhard
full_name: Plattner, Bernhard
last_name: Plattner
citation:
ama: 'Lübbers E, Platzner M, Plessl C, Keller A, Plattner B. Towards Adaptive Networking
for Embedded Devices based on Reconfigurable Hardware. In: Proc. Int. Conf.
on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press;
2010:225-231.'
apa: Lübbers, E., Platzner, M., Plessl, C., Keller, A., & Plattner, B. (2010).
Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware.
Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
225–231.
bibtex: '@inproceedings{Lübbers_Platzner_Plessl_Keller_Plattner_2010, title={Towards
Adaptive Networking for Embedded Devices based on Reconfigurable Hardware}, booktitle={Proc.
Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA
Press}, author={Lübbers, Enno and Platzner, Marco and Plessl, Christian and Keller,
Ariane and Plattner, Bernhard}, year={2010}, pages={225–231} }'
chicago: Lübbers, Enno, Marco Platzner, Christian Plessl, Ariane Keller, and Bernhard
Plattner. “Towards Adaptive Networking for Embedded Devices Based on Reconfigurable
Hardware.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and
Algorithms (ERSA), 225–31. CSREA Press, 2010.
ieee: E. Lübbers, M. Platzner, C. Plessl, A. Keller, and B. Plattner, “Towards Adaptive
Networking for Embedded Devices based on Reconfigurable Hardware,” in Proc.
Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
2010, pp. 225–231.
mla: Lübbers, Enno, et al. “Towards Adaptive Networking for Embedded Devices Based
on Reconfigurable Hardware.” Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 225–31.
short: 'E. Lübbers, M. Platzner, C. Plessl, A. Keller, B. Plattner, in: Proc. Int.
Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press,
2010, pp. 225–231.'
date_created: 2018-04-05T16:27:13Z
date_updated: 2023-09-26T13:48:32Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
language:
- iso: eng
page: 225-231
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA)
publication_identifier:
isbn:
- 1-60132-140-6
publisher: CSREA Press
quality_controlled: '1'
status: public
title: Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2216'
author:
- first_name: Mariusz
full_name: Grad, Mariusz
last_name: Grad
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Grad M, Plessl C. Pruning the Design Space for Just-In-Time Processor Customization.
In: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig).
IEEE Computer Society; 2010:67-72. doi:10.1109/ReConFig.2010.19'
apa: Grad, M., & Plessl, C. (2010). Pruning the Design Space for Just-In-Time
Processor Customization. Proc. Int. Conf. on ReConFigurable Computing and FPGAs
(ReConFig), 67–72. https://doi.org/10.1109/ReConFig.2010.19
bibtex: '@inproceedings{Grad_Plessl_2010, place={Los Alamitos, CA, USA}, title={Pruning
the Design Space for Just-In-Time Processor Customization}, DOI={10.1109/ReConFig.2010.19},
booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)},
publisher={IEEE Computer Society}, author={Grad, Mariusz and Plessl, Christian},
year={2010}, pages={67–72} }'
chicago: 'Grad, Mariusz, and Christian Plessl. “Pruning the Design Space for Just-In-Time
Processor Customization.” In Proc. Int. Conf. on ReConFigurable Computing and
FPGAs (ReConFig), 67–72. Los Alamitos, CA, USA: IEEE Computer Society, 2010.
https://doi.org/10.1109/ReConFig.2010.19.'
ieee: 'M. Grad and C. Plessl, “Pruning the Design Space for Just-In-Time Processor
Customization,” in Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig),
2010, pp. 67–72, doi: 10.1109/ReConFig.2010.19.'
mla: Grad, Mariusz, and Christian Plessl. “Pruning the Design Space for Just-In-Time
Processor Customization.” Proc. Int. Conf. on ReConFigurable Computing and
FPGAs (ReConFig), IEEE Computer Society, 2010, pp. 67–72, doi:10.1109/ReConFig.2010.19.
short: 'M. Grad, C. Plessl, in: Proc. Int. Conf. on ReConFigurable Computing and
FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2010, pp. 67–72.'
date_created: 2018-04-05T14:48:51Z
date_updated: 2023-09-26T13:47:11Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2010.19
language:
- iso: eng
page: 67-72
place: Los Alamitos, CA, USA
publication: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: Pruning the Design Space for Just-In-Time Processor Customization
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2224'
author:
- first_name: Mariusz
full_name: Grad, Mariusz
last_name: Grad
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Grad M, Plessl C. An Open Source Circuit Library with Benchmarking Facilities.
In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA). CSREA Press; 2010:144-150.'
apa: Grad, M., & Plessl, C. (2010). An Open Source Circuit Library with Benchmarking
Facilities. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA), 144–150.
bibtex: '@inproceedings{Grad_Plessl_2010, title={An Open Source Circuit Library
with Benchmarking Facilities}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Grad, Mariusz
and Plessl, Christian}, year={2010}, pages={144–150} }'
chicago: Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with
Benchmarking Facilities.” In Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), 144–50. CSREA Press, 2010.
ieee: M. Grad and C. Plessl, “An Open Source Circuit Library with Benchmarking Facilities,”
in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA), 2010, pp. 144–150.
mla: Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with Benchmarking
Facilities.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and
Algorithms (ERSA), CSREA Press, 2010, pp. 144–50.
short: 'M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144–150.'
date_created: 2018-04-05T16:28:38Z
date_updated: 2023-09-26T13:48:59Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
language:
- iso: eng
page: 144-150
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA)
publication_identifier:
isbn:
- 1-60132-140-6
publisher: CSREA Press
quality_controlled: '1'
status: public
title: An Open Source Circuit Library with Benchmarking Facilities
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2220'
author:
- first_name: David
full_name: Andrews, David
last_name: Andrews
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Andrews D, Plessl C. Configurable Processor Architectures: History and Trends.
In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA). CSREA Press; 2010:165.'
apa: 'Andrews, D., & Plessl, C. (2010). Configurable Processor Architectures:
History and Trends. Proc. Int. Conf. on Engineering of Reconfigurable Systems
and Algorithms (ERSA), 165.'
bibtex: '@inproceedings{Andrews_Plessl_2010, title={Configurable Processor Architectures:
History and Trends}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Andrews, David
and Plessl, Christian}, year={2010}, pages={165} }'
chicago: 'Andrews, David, and Christian Plessl. “Configurable Processor Architectures:
History and Trends.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems
and Algorithms (ERSA), 165. CSREA Press, 2010.'
ieee: 'D. Andrews and C. Plessl, “Configurable Processor Architectures: History
and Trends,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and
Algorithms (ERSA), 2010, p. 165.'
mla: 'Andrews, David, and Christian Plessl. “Configurable Processor Architectures:
History and Trends.” Proc. Int. Conf. on Engineering of Reconfigurable Systems
and Algorithms (ERSA), CSREA Press, 2010, p. 165.'
short: 'D. Andrews, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), CSREA Press, 2010, p. 165.'
date_created: 2018-04-05T14:57:07Z
date_updated: 2023-09-26T13:47:33Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
language:
- iso: eng
page: '165'
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA)
publication_identifier:
isbn:
- 1-60132-140-6
publisher: CSREA Press
quality_controlled: '1'
status: public
title: 'Configurable Processor Architectures: History and Trends'
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2222'
citation:
ama: Plaks TP, Andrews D, DeMara R, et al., eds. Proc. Int. Conf. on Engineering
of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010.
apa: Plaks, T. P., Andrews, D., DeMara, R., Lam, H., Lee, J., Plessl, C., &
Stitt, G. (Eds.). (2010). Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA). CSREA Press.
bibtex: '@book{Plaks_Andrews_DeMara_Lam_Lee_Plessl_Stitt_2010, title={Proc. Int.
Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA
Press}, year={2010} }'
chicago: Plaks, Toomas P., David Andrews, Ronald DeMara, Herman Lam, Jooheung Lee,
Christian Plessl, and Greg Stitt, eds. Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA). CSREA Press, 2010.
ieee: T. P. Plaks et al., Eds., Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA). CSREA Press, 2010.
mla: Plaks, Toomas P., et al., editors. Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA). CSREA Press, 2010.
short: T.P. Plaks, D. Andrews, R. DeMara, H. Lam, J. Lee, C. Plessl, G. Stitt, eds.,
Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
CSREA Press, 2010.
date_created: 2018-04-05T15:00:49Z
date_updated: 2023-09-26T13:48:00Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
editor:
- first_name: Toomas P.
full_name: Plaks, Toomas P.
last_name: Plaks
- first_name: David
full_name: Andrews, David
last_name: Andrews
- first_name: Ronald
full_name: DeMara, Ronald
last_name: DeMara
- first_name: Herman
full_name: Lam, Herman
last_name: Lam
- first_name: Jooheung
full_name: Lee, Jooheung
last_name: Lee
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Greg
full_name: Stitt, Greg
last_name: Stitt
language:
- iso: eng
publication_identifier:
isbn:
- 1-60132-140-6
publisher: CSREA Press
quality_controlled: '1'
status: public
title: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)
type: conference_editor
user_id: '15278'
year: '2010'
...
---
_id: '2226'
author:
- first_name: Tobias
full_name: Beisel, Tobias
last_name: Beisel
- first_name: Manuel
full_name: Niekamp, Manuel
last_name: Niekamp
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Beisel T, Niekamp M, Plessl C. Using Shared Library Interposing for Transparent
Acceleration in Systems with Heterogeneous Hardware Accelerators. In: Proc.
Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP).
IEEE Computer Society; 2010:65-72. doi:10.1109/ASAP.2010.5540798'
apa: Beisel, T., Niekamp, M., & Plessl, C. (2010). Using Shared Library Interposing
for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators.
Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors
(ASAP), 65–72. https://doi.org/10.1109/ASAP.2010.5540798
bibtex: '@inproceedings{Beisel_Niekamp_Plessl_2010, title={Using Shared Library
Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware
Accelerators}, DOI={10.1109/ASAP.2010.5540798},
booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and
Processors (ASAP)}, publisher={IEEE Computer Society}, author={Beisel, Tobias
and Niekamp, Manuel and Plessl, Christian}, year={2010}, pages={65–72} }'
chicago: Beisel, Tobias, Manuel Niekamp, and Christian Plessl. “Using Shared Library
Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware
Accelerators.” In Proc. Int. Conf. on Application-Specific Systems, Architectures,
and Processors (ASAP), 65–72. IEEE Computer Society, 2010. https://doi.org/10.1109/ASAP.2010.5540798.
ieee: 'T. Beisel, M. Niekamp, and C. Plessl, “Using Shared Library Interposing for
Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators,”
in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors
(ASAP), 2010, pp. 65–72, doi: 10.1109/ASAP.2010.5540798.'
mla: Beisel, Tobias, et al. “Using Shared Library Interposing for Transparent Acceleration
in Systems with Heterogeneous Hardware Accelerators.” Proc. Int. Conf. on Application-Specific
Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010,
pp. 65–72, doi:10.1109/ASAP.2010.5540798.
short: 'T. Beisel, M. Niekamp, C. Plessl, in: Proc. Int. Conf. on Application-Specific
Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010, pp.
65–72.'
date_created: 2018-04-05T16:39:34Z
date_updated: 2023-09-26T13:49:21Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ASAP.2010.5540798
language:
- iso: eng
page: 65-72
publication: Proc. Int. Conf. on Application-Specific Systems, Architectures, and
Processors (ASAP)
publication_identifier:
isbn:
- 978-1-4244-6965-9
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: Using Shared Library Interposing for Transparent Acceleration in Systems with
Heterogeneous Hardware Accelerators
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2206'
author:
- first_name: Ariane
full_name: Keller, Ariane
last_name: Keller
- first_name: Bernhard
full_name: Plattner, Bernhard
last_name: Plattner
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Keller A, Plattner B, Lübbers E, Platzner M, Plessl C. Reconfigurable Nodes
for Future Networks. In: Proc. IEEE Globecom Workshop on Network of the Future
(FutureNet). IEEE; 2010:372-376. doi:10.1109/GLOCOMW.2010.5700341'
apa: Keller, A., Plattner, B., Lübbers, E., Platzner, M., & Plessl, C. (2010).
Reconfigurable Nodes for Future Networks. Proc. IEEE Globecom Workshop on Network
of the Future (FutureNet), 372–376. https://doi.org/10.1109/GLOCOMW.2010.5700341
bibtex: '@inproceedings{Keller_Plattner_Lübbers_Platzner_Plessl_2010, title={Reconfigurable
Nodes for Future Networks}, DOI={10.1109/GLOCOMW.2010.5700341},
booktitle={Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)},
publisher={IEEE}, author={Keller, Ariane and Plattner, Bernhard and Lübbers, Enno
and Platzner, Marco and Plessl, Christian}, year={2010}, pages={372–376} }'
chicago: Keller, Ariane, Bernhard Plattner, Enno Lübbers, Marco Platzner, and Christian
Plessl. “Reconfigurable Nodes for Future Networks.” In Proc. IEEE Globecom
Workshop on Network of the Future (FutureNet), 372–76. IEEE, 2010. https://doi.org/10.1109/GLOCOMW.2010.5700341.
ieee: 'A. Keller, B. Plattner, E. Lübbers, M. Platzner, and C. Plessl, “Reconfigurable
Nodes for Future Networks,” in Proc. IEEE Globecom Workshop on Network of the
Future (FutureNet), 2010, pp. 372–376, doi: 10.1109/GLOCOMW.2010.5700341.'
mla: Keller, Ariane, et al. “Reconfigurable Nodes for Future Networks.” Proc.
IEEE Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp.
372–76, doi:10.1109/GLOCOMW.2010.5700341.
short: 'A. Keller, B. Plattner, E. Lübbers, M. Platzner, C. Plessl, in: Proc. IEEE
Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp. 372–376.'
date_created: 2018-04-04T09:36:16Z
date_updated: 2023-09-26T13:51:00Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/GLOCOMW.2010.5700341
language:
- iso: eng
page: 372-376
publication: Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)
publication_identifier:
isbn:
- 978-1-4244-8864-3
publisher: IEEE
quality_controlled: '1'
status: public
title: Reconfigurable Nodes for Future Networks
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2227'
author:
- first_name: Matthias
full_name: Woehrle, Matthias
last_name: Woehrle
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Lothar
full_name: Thiele, Lothar
last_name: Thiele
citation:
ama: 'Woehrle M, Plessl C, Thiele L. Rupeas: Ruby Powered Event Analysis DSL. In:
Proc. Int. Conf. Networked Sensing Systems (INSS). IEEE; 2010:245-248.
doi:10.1109/INSS.2010.5572211'
apa: 'Woehrle, M., Plessl, C., & Thiele, L. (2010). Rupeas: Ruby Powered Event
Analysis DSL. Proc. Int. Conf. Networked Sensing Systems (INSS), 245–248.
https://doi.org/10.1109/INSS.2010.5572211'
bibtex: '@inproceedings{Woehrle_Plessl_Thiele_2010, title={Rupeas: Ruby Powered
Event Analysis DSL}, DOI={10.1109/INSS.2010.5572211},
booktitle={Proc. Int. Conf. Networked Sensing Systems (INSS)}, publisher={IEEE},
author={Woehrle, Matthias and Plessl, Christian and Thiele, Lothar}, year={2010},
pages={245–248} }'
chicago: 'Woehrle, Matthias, Christian Plessl, and Lothar Thiele. “Rupeas: Ruby
Powered Event Analysis DSL.” In Proc. Int. Conf. Networked Sensing Systems
(INSS), 245–48. IEEE, 2010. https://doi.org/10.1109/INSS.2010.5572211.'
ieee: 'M. Woehrle, C. Plessl, and L. Thiele, “Rupeas: Ruby Powered Event Analysis
DSL,” in Proc. Int. Conf. Networked Sensing Systems (INSS), 2010, pp. 245–248,
doi: 10.1109/INSS.2010.5572211.'
mla: 'Woehrle, Matthias, et al. “Rupeas: Ruby Powered Event Analysis DSL.” Proc.
Int. Conf. Networked Sensing Systems (INSS), IEEE, 2010, pp. 245–48, doi:10.1109/INSS.2010.5572211.'
short: 'M. Woehrle, C. Plessl, L. Thiele, in: Proc. Int. Conf. Networked Sensing
Systems (INSS), IEEE, 2010, pp. 245–248.'
date_created: 2018-04-05T16:41:02Z
date_updated: 2023-09-26T13:49:38Z
department:
- _id: '27'
- _id: '518'
doi: 10.1109/INSS.2010.5572211
extern: '1'
language:
- iso: eng
page: 245-248
publication: Proc. Int. Conf. Networked Sensing Systems (INSS)
publication_identifier:
isbn:
- 978-1-4244-7911-5
publisher: IEEE
quality_controlled: '1'
status: public
title: 'Rupeas: Ruby Powered Event Analysis DSL'
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '2228'
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Michael
full_name: Kauschke, Michael
last_name: Kauschke
citation:
ama: 'Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation for the
Exploration of CPU-Accelerator Architectures. In: Hammami O, Larrabee S, eds.
Proc. Workshop on Architectural Research Prototyping (WARP), International
Symposium on Computer Architecture (ISCA). ; 2010.'
apa: Kenter, T., Platzner, M., Plessl, C., & Kauschke, M. (2010). Performance
Estimation for the Exploration of CPU-Accelerator Architectures. In O. Hammami
& S. Larrabee (Eds.), Proc. Workshop on Architectural Research Prototyping
(WARP), International Symposium on Computer Architecture (ISCA).
bibtex: '@inproceedings{Kenter_Platzner_Plessl_Kauschke_2010, title={Performance
Estimation for the Exploration of CPU-Accelerator Architectures}, booktitle={Proc.
Workshop on Architectural Research Prototyping (WARP), International Symposium
on Computer Architecture (ISCA)}, author={Kenter, Tobias and Platzner, Marco and
Plessl, Christian and Kauschke, Michael}, editor={Hammami, Omar and Larrabee,
Sandra}, year={2010} }'
chicago: Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke.
“Performance Estimation for the Exploration of CPU-Accelerator Architectures.”
In Proc. Workshop on Architectural Research Prototyping (WARP), International
Symposium on Computer Architecture (ISCA), edited by Omar Hammami and Sandra
Larrabee, 2010.
ieee: T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation
for the Exploration of CPU-Accelerator Architectures,” in Proc. Workshop on
Architectural Research Prototyping (WARP), International Symposium on Computer
Architecture (ISCA), 2010.
mla: Kenter, Tobias, et al. “Performance Estimation for the Exploration of CPU-Accelerator
Architectures.” Proc. Workshop on Architectural Research Prototyping (WARP),
International Symposium on Computer Architecture (ISCA), edited by Omar Hammami
and Sandra Larrabee, 2010.
short: 'T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: O. Hammami, S. Larrabee
(Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International
Symposium on Computer Architecture (ISCA), 2010.'
date_created: 2018-04-05T16:43:04Z
date_updated: 2023-09-26T13:50:04Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
editor:
- first_name: Omar
full_name: Hammami, Omar
last_name: Hammami
- first_name: Sandra
full_name: Larrabee, Sandra
last_name: Larrabee
language:
- iso: eng
publication: Proc. Workshop on Architectural Research Prototyping (WARP), International
Symposium on Computer Architecture (ISCA)
quality_controlled: '1'
status: public
title: Performance Estimation for the Exploration of CPU-Accelerator Architectures
type: conference
user_id: '15278'
year: '2010'
...
---
_id: '60463'
abstract:
- lang: eng
text: AbstractWe present a new technique to implement
operators that modify the topology of polygonal meshes at intersections and self‐intersections.
Depending on the modification strategy, this effectively results in operators
for Boolean combinations or for the construction of outer hulls that are suited
for mesh repair tasks and accurate mesh‐based front tracking of deformable materials
that split and merge. By combining an adaptive octree with nested binary space
partitions (BSP), we can guarantee exactness (= correctness) and robustness (=
completeness) of the algorithm while still achieving higher performance and less
memory consumption than previous approaches. The efficiency and scalability in
terms of runtime and memory is obtained by an operation localization scheme. We
restrict the essential computations to those cells in the adaptive octree where
intersections actually occur. Within those critical cells, we convert the input
geometry into a plane‐based BSP‐representation which allows us to perform all
computations exactly even with fixed precision arithmetics. We carefully analyze
the precision requirements of the involved geometric data and predicates in order
to guarantee correctness and show how minimal input mesh quantization can be used
to safely rely on computations with standard floating point numbers. We properly
evaluate our method with respect to precision, robustness, and efficiency.
author:
- first_name: Marcel
full_name: Campen, Marcel
id: '114904'
last_name: Campen
orcid: 0000-0003-2340-3462
- first_name: Leif
full_name: Kobbelt, Leif
last_name: Kobbelt
citation:
ama: Campen M, Kobbelt L. Exact and Robust (Self‐)Intersections for Polygonal Meshes.
Computer Graphics Forum. 2010;29(2):397-406. doi:10.1111/j.1467-8659.2009.01609.x
apa: Campen, M., & Kobbelt, L. (2010). Exact and Robust (Self‐)Intersections
for Polygonal Meshes. Computer Graphics Forum, 29(2), 397–406. https://doi.org/10.1111/j.1467-8659.2009.01609.x
bibtex: '@article{Campen_Kobbelt_2010, title={Exact and Robust (Self‐)Intersections
for Polygonal Meshes}, volume={29}, DOI={10.1111/j.1467-8659.2009.01609.x},
number={2}, journal={Computer Graphics Forum}, publisher={Wiley}, author={Campen,
Marcel and Kobbelt, Leif}, year={2010}, pages={397–406} }'
chicago: 'Campen, Marcel, and Leif Kobbelt. “Exact and Robust (Self‐)Intersections
for Polygonal Meshes.” Computer Graphics Forum 29, no. 2 (2010): 397–406.
https://doi.org/10.1111/j.1467-8659.2009.01609.x.'
ieee: 'M. Campen and L. Kobbelt, “Exact and Robust (Self‐)Intersections for Polygonal
Meshes,” Computer Graphics Forum, vol. 29, no. 2, pp. 397–406, 2010, doi:
10.1111/j.1467-8659.2009.01609.x.'
mla: Campen, Marcel, and Leif Kobbelt. “Exact and Robust (Self‐)Intersections for
Polygonal Meshes.” Computer Graphics Forum, vol. 29, no. 2, Wiley, 2010,
pp. 397–406, doi:10.1111/j.1467-8659.2009.01609.x.
short: M. Campen, L. Kobbelt, Computer Graphics Forum 29 (2010) 397–406.
date_created: 2025-06-30T08:24:08Z
date_updated: 2025-07-14T12:35:44Z
department:
- _id: '969'
doi: 10.1111/j.1467-8659.2009.01609.x
extern: '1'
intvolume: ' 29'
issue: '2'
language:
- iso: eng
page: 397-406
publication: Computer Graphics Forum
publication_identifier:
issn:
- 0167-7055
- 1467-8659
publication_status: published
publisher: Wiley
status: public
title: Exact and Robust (Self‐)Intersections for Polygonal Meshes
type: journal_article
user_id: '117512'
volume: 29
year: '2010'
...
---
_id: '60464'
abstract:
- lang: eng
text: AbstractWe present a novel technique for
the efficient boundary evaluation of sweep operations applied to objects in polygonal
boundary representation. These sweep operations include Minkowski addition, offsetting,
and sweeping along a discrete rigid motion trajectory. Many previous methods focus
on the construction of a polygonal superset (containing self‐intersections and
spurious internal geometry) of the boundary of the volumes which are swept. Only
few are able to determine a clean representation of the actual boundary, most
of them in a discrete volumetric setting. We unify such superset constructions
into a succinct common formulation and present a technique for the robust extraction
of a polygonal mesh representing the outer boundary, i.e. it makes no general
position assumptions and always yields a manifold, watertight mesh. It is exact
for Minkowski sums and approximates swept volumes polygonally. By using plane‐based
geometry in conjunction with hierarchical arrangement computations we avoid the
necessity of arbitrary precision arithmetics and extensive special case handling.
By restricting operations to regions containing pieces of the boundary, we significantly
enhance the performance of the algorithm.
author:
- first_name: Marcel
full_name: Campen, Marcel
id: '114904'
last_name: Campen
orcid: 0000-0003-2340-3462
- first_name: Leif
full_name: Kobbelt, Leif
last_name: Kobbelt
citation:
ama: Campen M, Kobbelt L. Polygonal Boundary Evaluation of Minkowski Sums and Swept
Volumes. Computer Graphics Forum. 2010;29(5):1613-1622. doi:10.1111/j.1467-8659.2010.01770.x
apa: Campen, M., & Kobbelt, L. (2010). Polygonal Boundary Evaluation of Minkowski
Sums and Swept Volumes. Computer Graphics Forum, 29(5), 1613–1622.
https://doi.org/10.1111/j.1467-8659.2010.01770.x
bibtex: '@article{Campen_Kobbelt_2010, title={Polygonal Boundary Evaluation of Minkowski
Sums and Swept Volumes}, volume={29}, DOI={10.1111/j.1467-8659.2010.01770.x},
number={5}, journal={Computer Graphics Forum}, publisher={Wiley}, author={Campen,
Marcel and Kobbelt, Leif}, year={2010}, pages={1613–1622} }'
chicago: 'Campen, Marcel, and Leif Kobbelt. “Polygonal Boundary Evaluation of Minkowski
Sums and Swept Volumes.” Computer Graphics Forum 29, no. 5 (2010): 1613–22.
https://doi.org/10.1111/j.1467-8659.2010.01770.x.'
ieee: 'M. Campen and L. Kobbelt, “Polygonal Boundary Evaluation of Minkowski Sums
and Swept Volumes,” Computer Graphics Forum, vol. 29, no. 5, pp. 1613–1622,
2010, doi: 10.1111/j.1467-8659.2010.01770.x.'
mla: Campen, Marcel, and Leif Kobbelt. “Polygonal Boundary Evaluation of Minkowski
Sums and Swept Volumes.” Computer Graphics Forum, vol. 29, no. 5, Wiley,
2010, pp. 1613–22, doi:10.1111/j.1467-8659.2010.01770.x.
short: M. Campen, L. Kobbelt, Computer Graphics Forum 29 (2010) 1613–1622.
date_created: 2025-06-30T08:34:20Z
date_updated: 2025-07-14T12:35:40Z
department:
- _id: '969'
doi: 10.1111/j.1467-8659.2010.01770.x
extern: '1'
intvolume: ' 29'
issue: '5'
language:
- iso: eng
page: 1613-1622
publication: Computer Graphics Forum
publication_identifier:
issn:
- 0167-7055
- 1467-8659
publication_status: published
publisher: Wiley
status: public
title: Polygonal Boundary Evaluation of Minkowski Sums and Swept Volumes
type: journal_article
user_id: '117512'
volume: 29
year: '2010'
...
---
_id: '60462'
abstract:
- lang: eng
text: 'Abstract In this paper, we
present a novel method to compute Boolean operations on polygonal meshes. Given
a Boolean expression over an arbitrary number of input meshes we reliably and
efficiently compute an output mesh which faithfully preserves the existing sharp
features and precisely reconstructs the new features appearing along the intersections
of the input meshes. The term “hybrid” applies to our method in two ways: First,
our algorithm operates on a hybrid data structure which stores the original input
polygons (surface data) in an adaptively refined octree (volume data). By this
we combine the robustness of volumetric techniques with the accuracy of surface‐oriented
techniques. Second, we generate a new triangulation only in a close vicinity around
the intersections of the input meshes and thus preserve as much of the original
mesh structure as possible (hybrid mesh). Since the actual processing of the Boolean
operation is confined to a very small region around the intersections of the input
meshes, we can achieve very high adaptive refinement resolutions and hence very
high precision. We demonstrate our method on a number of challenging examples.
'
author:
- first_name: Darko
full_name: Pavić, Darko
last_name: Pavić
- first_name: Marcel
full_name: Campen, Marcel
id: '114904'
last_name: Campen
orcid: 0000-0003-2340-3462
- first_name: Leif
full_name: Kobbelt, Leif
last_name: Kobbelt
citation:
ama: Pavić D, Campen M, Kobbelt L. Hybrid Booleans. Computer Graphics Forum.
2010;29(1):75-87. doi:10.1111/j.1467-8659.2009.01545.x
apa: Pavić, D., Campen, M., & Kobbelt, L. (2010). Hybrid Booleans. Computer
Graphics Forum, 29(1), 75–87. https://doi.org/10.1111/j.1467-8659.2009.01545.x
bibtex: '@article{Pavić_Campen_Kobbelt_2010, title={Hybrid Booleans}, volume={29},
DOI={10.1111/j.1467-8659.2009.01545.x},
number={1}, journal={Computer Graphics Forum}, publisher={Wiley}, author={Pavić,
Darko and Campen, Marcel and Kobbelt, Leif}, year={2010}, pages={75–87} }'
chicago: 'Pavić, Darko, Marcel Campen, and Leif Kobbelt. “Hybrid Booleans.” Computer
Graphics Forum 29, no. 1 (2010): 75–87. https://doi.org/10.1111/j.1467-8659.2009.01545.x.'
ieee: 'D. Pavić, M. Campen, and L. Kobbelt, “Hybrid Booleans,” Computer Graphics
Forum, vol. 29, no. 1, pp. 75–87, 2010, doi: 10.1111/j.1467-8659.2009.01545.x.'
mla: Pavić, Darko, et al. “Hybrid Booleans.” Computer Graphics Forum, vol.
29, no. 1, Wiley, 2010, pp. 75–87, doi:10.1111/j.1467-8659.2009.01545.x.
short: D. Pavić, M. Campen, L. Kobbelt, Computer Graphics Forum 29 (2010) 75–87.
date_created: 2025-06-30T08:22:33Z
date_updated: 2025-07-14T12:35:48Z
department:
- _id: '969'
doi: 10.1111/j.1467-8659.2009.01545.x
extern: '1'
intvolume: ' 29'
issue: '1'
language:
- iso: eng
page: 75-87
publication: Computer Graphics Forum
publication_identifier:
issn:
- 0167-7055
- 1467-8659
publication_status: published
publisher: Wiley
status: public
title: Hybrid Booleans
type: journal_article
user_id: '117512'
volume: 29
year: '2010'
...
---
_id: '19605'
author:
- first_name: Katharina
full_name: Lürwer-Brüggemeier, Katharina
last_name: Lürwer-Brüggemeier
citation:
ama: Lürwer-Brüggemeier K. Mächtigkeit Und Komplexität von Berechnungen Mit Der
Ganzzahligen Division. Vol 261. Verlagsschriftenreihe des Heinz Nixdorf Instituts,
Paderborn; 2009.
apa: Lürwer-Brüggemeier, K. (2009). Mächtigkeit und Komplexität von Berechnungen
mit der ganzzahligen Division (Vol. 261). Verlagsschriftenreihe des Heinz
Nixdorf Instituts, Paderborn.
bibtex: '@book{Lürwer-Brüggemeier_2009, series={Verlagsschriftenreihe des Heinz
Nixdorf Instituts, Paderborn}, title={Mächtigkeit und Komplexität von Berechnungen
mit der ganzzahligen Division}, volume={261}, publisher={Verlagsschriftenreihe
des Heinz Nixdorf Instituts, Paderborn}, author={Lürwer-Brüggemeier, Katharina},
year={2009}, collection={Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}
}'
chicago: Lürwer-Brüggemeier, Katharina. Mächtigkeit Und Komplexität von Berechnungen
Mit Der Ganzzahligen Division. Vol. 261. Verlagsschriftenreihe Des Heinz Nixdorf
Instituts, Paderborn. Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn,
2009.
ieee: K. Lürwer-Brüggemeier, Mächtigkeit und Komplexität von Berechnungen mit
der ganzzahligen Division, vol. 261. Verlagsschriftenreihe des Heinz Nixdorf
Instituts, Paderborn, 2009.
mla: Lürwer-Brüggemeier, Katharina. Mächtigkeit Und Komplexität von Berechnungen
Mit Der Ganzzahligen Division. Verlagsschriftenreihe des Heinz Nixdorf Instituts,
Paderborn, 2009.
short: K. Lürwer-Brüggemeier, Mächtigkeit Und Komplexität von Berechnungen Mit Der
Ganzzahligen Division, Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn,
2009.
date_created: 2020-09-21T14:07:23Z
date_updated: 2022-01-06T06:54:07Z
department:
- _id: '63'
- _id: '26'
intvolume: ' 261'
language:
- iso: eng
publisher: Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn
related_material:
link:
- relation: confirmation
url: http://digital.ub.uni-paderborn.de/ubpb/urn/urn:nbn:de:hbz:466-20090212010
series_title: Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn
status: public
supervisor:
- first_name: Friedhelm
full_name: Meyer auf der Heide, Friedhelm
id: '15523'
last_name: Meyer auf der Heide
title: Mächtigkeit und Komplexität von Berechnungen mit der ganzzahligen Division
type: dissertation
user_id: '5786'
volume: 261
year: '2009'
...
---
_id: '19614'
author:
- first_name: Mario
full_name: Mense, Mario
last_name: Mense
citation:
ama: Mense M. On Fault-Tolerant Data Placement in Storage Networks. Vol 260.
Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn; 2009.
apa: Mense, M. (2009). On Fault-Tolerant Data Placement in Storage Networks
(Vol. 260). Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn.
bibtex: '@book{Mense_2009, series={Verlagsschriftenreihe des Heinz Nixdorf Instituts,
Paderborn}, title={On Fault-Tolerant Data Placement in Storage Networks}, volume={260},
publisher={Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}, author={Mense,
Mario}, year={2009}, collection={Verlagsschriftenreihe des Heinz Nixdorf Instituts,
Paderborn} }'
chicago: Mense, Mario. On Fault-Tolerant Data Placement in Storage Networks.
Vol. 260. Verlagsschriftenreihe Des Heinz Nixdorf Instituts, Paderborn. Verlagsschriftenreihe
des Heinz Nixdorf Instituts, Paderborn, 2009.
ieee: M. Mense, On Fault-Tolerant Data Placement in Storage Networks, vol.
260. Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2009.
mla: Mense, Mario. On Fault-Tolerant Data Placement in Storage Networks.
Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2009.
short: M. Mense, On Fault-Tolerant Data Placement in Storage Networks, Verlagsschriftenreihe
des Heinz Nixdorf Instituts, Paderborn, 2009.
date_created: 2020-09-22T08:05:15Z
date_updated: 2022-01-06T06:54:08Z
department:
- _id: '63'
- _id: '26'
intvolume: ' 260'
language:
- iso: eng
publication_identifier:
isbn:
- 978-3-939350-79-8
publisher: Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn
related_material:
link:
- relation: confirmation
url: http://digital.ub.uni-paderborn.de/ubpb/urn/urn:nbn:de:hbz:466-20090206016
series_title: Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn
status: public
supervisor:
- first_name: Friedhelm
full_name: Meyer auf der Heide, Friedhelm
id: '15523'
last_name: Meyer auf der Heide
title: On Fault-Tolerant Data Placement in Storage Networks
type: dissertation
user_id: '5786'
volume: 260
year: '2009'
...
---
_id: '19617'
author:
- first_name: Michael
full_name: Kortenjan, Michael
last_name: Kortenjan
citation:
ama: Kortenjan M. Size Equivalent Cluster Trees - Rendering CAD Models in Industrial
Scenes. Vol 258. Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn;
2009.
apa: Kortenjan, M. (2009). Size Equivalent Cluster Trees - Rendering CAD Models
in Industrial Scenes (Vol. 258). Verlagsschriftenreihe des Heinz Nixdorf Instituts,
Paderborn.
bibtex: '@book{Kortenjan_2009, series={Verlagsschriftenreihe des Heinz Nixdorf Instituts,
Paderborn}, title={Size Equivalent Cluster Trees - Rendering CAD Models in Industrial
Scenes}, volume={258}, publisher={Verlagsschriftenreihe des Heinz Nixdorf Instituts,
Paderborn}, author={Kortenjan, Michael}, year={2009}, collection={Verlagsschriftenreihe
des Heinz Nixdorf Instituts, Paderborn} }'
chicago: Kortenjan, Michael. Size Equivalent Cluster Trees - Rendering CAD Models
in Industrial Scenes. Vol. 258. Verlagsschriftenreihe Des Heinz Nixdorf Instituts,
Paderborn. Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2009.
ieee: M. Kortenjan, Size Equivalent Cluster Trees - Rendering CAD Models in Industrial
Scenes, vol. 258. Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn,
2009.
mla: Kortenjan, Michael. Size Equivalent Cluster Trees - Rendering CAD Models
in Industrial Scenes. Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn,
2009.
short: M. Kortenjan, Size Equivalent Cluster Trees - Rendering CAD Models in Industrial
Scenes, Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2009.
date_created: 2020-09-22T08:42:22Z
date_updated: 2022-01-06T06:54:08Z
department:
- _id: '63'
- _id: '26'
intvolume: ' 258'
language:
- iso: eng
publication_identifier:
isbn:
- 978-3-939350-77-4
publisher: Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn
related_material:
link:
- relation: confirmation
url: http://digital.ub.uni-paderborn.de/ubpb/urn/urn:nbn:de:hbz:466-20081218010
series_title: Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn
status: public
supervisor:
- first_name: Friedhelm
full_name: Meyer auf der Heide, Friedhelm
id: '15523'
last_name: Meyer auf der Heide
title: Size Equivalent Cluster Trees - Rendering CAD Models in Industrial Scenes
type: dissertation
user_id: '5786'
volume: 258
year: '2009'
...
---
_id: '19618'
author:
- first_name: Olaf
full_name: Bonorden, Olaf
last_name: Bonorden
citation:
ama: 'Bonorden O. Versatility of Bulk Synchronous Parallel Computing: From the
Heterogeneous Cluster to the System on Chip. Vol 257. Verlagsschriftenreihe
des Heinz Nixdorf Instituts, Paderborn; 2009.'
apa: 'Bonorden, O. (2009). Versatility of Bulk Synchronous Parallel Computing:
From the Heterogeneous Cluster to the System on Chip (Vol. 257). Verlagsschriftenreihe
des Heinz Nixdorf Instituts, Paderborn.'
bibtex: '@book{Bonorden_2009, series={Verlagsschriftenreihe des Heinz Nixdorf Instituts,
Paderborn}, title={Versatility of Bulk Synchronous Parallel Computing: From the
Heterogeneous Cluster to the System on Chip}, volume={257}, publisher={Verlagsschriftenreihe
des Heinz Nixdorf Instituts, Paderborn}, author={Bonorden, Olaf}, year={2009},
collection={Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn} }'
chicago: 'Bonorden, Olaf. Versatility of Bulk Synchronous Parallel Computing:
From the Heterogeneous Cluster to the System on Chip. Vol. 257. Verlagsschriftenreihe
Des Heinz Nixdorf Instituts, Paderborn. Verlagsschriftenreihe des Heinz Nixdorf
Instituts, Paderborn, 2009.'
ieee: 'O. Bonorden, Versatility of Bulk Synchronous Parallel Computing: From
the Heterogeneous Cluster to the System on Chip, vol. 257. Verlagsschriftenreihe
des Heinz Nixdorf Instituts, Paderborn, 2009.'
mla: 'Bonorden, Olaf. Versatility of Bulk Synchronous Parallel Computing: From
the Heterogeneous Cluster to the System on Chip. Verlagsschriftenreihe des
Heinz Nixdorf Instituts, Paderborn, 2009.'
short: 'O. Bonorden, Versatility of Bulk Synchronous Parallel Computing: From the
Heterogeneous Cluster to the System on Chip, Verlagsschriftenreihe des Heinz Nixdorf
Instituts, Paderborn, 2009.'
date_created: 2020-09-22T08:44:45Z
date_updated: 2022-01-06T06:54:08Z
department:
- _id: '63'
- _id: '26'
intvolume: ' 257'
language:
- iso: eng
publication_identifier:
isbn:
- 978-3-939350-76-7
publisher: Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn
related_material:
link:
- relation: confirmation
url: http://digital.ub.uni-paderborn.de/ubpb/urn/urn:nbn:de:hbz:466-20080623016
series_title: Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn
status: public
supervisor:
- first_name: Friedhelm
full_name: Meyer auf der Heide, Friedhelm
id: '15523'
last_name: Meyer auf der Heide
title: 'Versatility of Bulk Synchronous Parallel Computing: From the Heterogeneous
Cluster to the System on Chip'
type: dissertation
user_id: '5786'
volume: 257
year: '2009'
...