@inproceedings{64112,
  author       = {{Jalil, Farjana and Awais, Muhammad and Ahmed, Qazi Arbab and Mohammadi, Hassan Ghasemzadeh and Jungeblut, Thorsten and Platzner, Marco}},
  booktitle    = {{2025 55th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)}},
  publisher    = {{IEEE}},
  title        = {{{Deep&Wide: Achieving Area Efficiency in Scalable Approximate Accelerators}}},
  doi          = {{10.1109/dsn-w65791.2025.00048}},
  year         = {{2025}},
}

@inproceedings{64113,
  author       = {{Hadipour, Amir Hossein and Jafari, Atousa and Awais, Muhammad and Platzner, Marco}},
  booktitle    = {{2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)}},
  publisher    = {{IEEE}},
  title        = {{{A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation}}},
  doi          = {{10.1109/ddecs63720.2025.11006769}},
  year         = {{2025}},
}

@unpublished{61152,
  abstract     = {{While neural network quantization effectively reduces the cost of matrix multiplications, aggressive quantization can expose non-matrix-multiply operations as significant performance and resource bottlenecks on embedded systems. Addressing such bottlenecks requires a comprehensive approach to tailoring the precision across operations in the inference computation. To this end, we introduce scaled-integer range analysis (SIRA), a static analysis technique employing interval arithmetic to determine the range, scale, and bias for tensors in quantized neural networks. We show how this information can be exploited to reduce the resource footprint of FPGA dataflow neural network accelerators via tailored bitwidth adaptation for accumulators and downstream operations, aggregation of scales and biases, and conversion of consecutive elementwise operations to thresholding operations. We integrate SIRA-driven optimizations into the open-source FINN framework, then evaluate their effectiveness across a range of quantized neural network workloads and compare implementation alternatives for non-matrix-multiply operations. We demonstrate an average reduction of 17% for LUTs, 66% for DSPs, and 22% for accumulator bitwidths with SIRA optimizations, providing detailed benchmark analysis and analytical models to guide the implementation style for non-matrix layers. Finally, we open-source SIRA to facilitate community exploration of its benefits across various applications and hardware platforms.}},
  author       = {{Umuroglu, Yaman and Berganski, Christoph and Jentzsch, Felix and Danilowicz, Michal and Kryjak, Tomasz and Bezaitis, Charalampos and Sjalander, Magnus and Colbert, Ian and Preusser, Thomas and Petri-Koenig, Jakoba and Blott, Michaela}},
  title        = {{{SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators}}},
  year         = {{2025}},
}

@article{62020,
  author       = {{Awais, Muhammad and Mohammadi, Hassan Ghasemzadeh and Platzner, Marco}},
  issn         = {{1063-8210}},
  journal      = {{IEEE Transactions on Very Large Scale Integration (VLSI) Systems}},
  number       = {{9}},
  pages        = {{2395--2405}},
  publisher    = {{Institute of Electrical and Electronics Engineers (IEEE)}},
  title        = {{{Design Space Exploration for Approximate Circuits via Checkpointing and DNN-Based Estimators}}},
  doi          = {{10.1109/tvlsi.2025.3559377}},
  volume       = {{33}},
  year         = {{2025}},
}

@inproceedings{62019,
  author       = {{Hadipour, Amir Hossein and Jafari, Atousa and Awais, Muhammad and Platzner, Marco}},
  booktitle    = {{2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)}},
  publisher    = {{IEEE}},
  title        = {{{A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation}}},
  doi          = {{10.1109/ddecs63720.2025.11006769}},
  year         = {{2025}},
}

@misc{62268,
  author       = {{Bengaluru Amarnath, Prajwal}},
  publisher    = {{Paderborn University}},
  title        = {{{Design and Integration of Intra-Process Communication for ROS 2 into ReconROS}}},
  year         = {{2025}},
}

@article{52686,
  author       = {{Ahmed, Qazi Arbab and Wiersema, Tobias and Platzner, Marco}},
  issn         = {{2509-3428}},
  journal      = {{Journal of Hardware and Systems Security}},
  keywords     = {{General Engineering, Energy Engineering and Power Technology}},
  publisher    = {{Springer Science and Business Media LLC}},
  title        = {{{Post-configuration Activation of Hardware Trojans in FPGAs}}},
  doi          = {{10.1007/s41635-024-00147-5}},
  year         = {{2024}},
}

@misc{54245,
  author       = {{Henke, Luca-Sebastian}},
  title        = {{{Exploring Custom FPGA Accelerators for DNN-based RF Fingerprinting}}},
  year         = {{2024}},
}

@inproceedings{54468,
  author       = {{Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}},
  booktitle    = {{To apear in IEEE ISVLSI 2024}},
  location     = {{Knoxville, Tennessee, USA}},
  title        = {{{DeepApprox: Rapid Deep Learning based Design Space Exploration of Approximate Circuits via Check-pointing}}},
  year         = {{2024}},
}

@inproceedings{56481,
  author       = {{Berganski, Christoph and Jentzsch, Felix and Platzner, Marco and Kuhmichel, Max and Giefers, Heiner}},
  location     = {{Sydney}},
  title        = {{{FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers}}},
  year         = {{2024}},
}

@misc{58132,
  author       = {{Hartinger, Maximilian}},
  publisher    = {{Paderborn University}},
  title        = {{{Controlling I/O Devices from Hardware-Mapped ReconROS Nodes}}},
  year         = {{2024}},
}

@phdthesis{47837,
  author       = {{Hansmeier, Tim}},
  title        = {{{XCS for Self-awareness in Autonomous Computing Systems}}},
  year         = {{2023}},
}

@inproceedings{53794,
  author       = {{Lienen, Christian and Brede, Mathis and Karger, Daniel and Koch, Kevin and Logan, Dalisha and Mazur, Janet and Nowosad, Alexander Philipp and Schnelle, Alexander and Waizy, Mohness and Platzner, Marco}},
  booktitle    = {{2023 Seventh IEEE International Conference on Robotic Computing (IRC)}},
  publisher    = {{IEEE}},
  title        = {{{AutonomROS: A ReconROS-based Autonomous Driving Unit}}},
  doi          = {{10.1109/irc59093.2023.00056}},
  year         = {{2023}},
}

@inproceedings{45913,
  author       = {{Clausing, Lennart and Guetattfi, Zakarya and Kaufmann, Paul and Lienen, Christian and Platzner, Marco}},
  booktitle    = {{Proceedings of the 19th International Symposium on Applied Reconfigurable Computing (ARC)}},
  title        = {{{On Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconOS64}}},
  doi          = {{https://doi.org/10.1007/978-3-031-42921-7_17}},
  year         = {{2023}},
}

@inproceedings{46229,
  author       = {{Lienen, Christian and Nowosad, Alexander Philipp and Platzner, Marco}},
  booktitle    = {{Proceedings of the 2023 9th International Conference on Robotics and Artificial Intelligence (ICRAI)}},
  title        = {{{Mapping and Optimizing Communication in ROS 2-based Applications on Configurable System-on-Chip Platforms}}},
  doi          = {{https://doi.org/10.1145/3637843.3637846}},
  year         = {{2023}},
}

@inproceedings{43048,
  author       = {{Lienen, Christian and Middeke, Sorel Horst and Platzner, Marco}},
  booktitle    = {{ Proceedings of the 2023 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS)}},
  title        = {{{fpgaDDS: An Intra-FPGA Data Distribution Service for ROS 2 Robotics Applications}}},
  doi          = {{10.1109/IROS55552.2023.10341921}},
  year         = {{2023}},
}

@inbook{45888,
  author       = {{Wehrheim, Heike and Platzner, Marco and Bodden, Eric and Schubert, Philipp  and Pauck, Felix and Jakobs, Marie-Christine}},
  booktitle    = {{On-The-Fly Computing -- Individualized IT-services in dynamic markets}},
  editor       = {{Haake, Claus-Jochen and Meyer auf der Heide, Friedhelm and Platzner, Marco and Wachsmuth, Henning and Wehrheim, Heike}},
  pages        = {{125--144}},
  publisher    = {{Heinz Nixdorf Institut, Universität Paderborn}},
  title        = {{{Verifying Software and Reconfigurable Hardware Services}}},
  doi          = {{10.5281/zenodo.8068583}},
  volume       = {{412}},
  year         = {{2023}},
}

@inbook{45893,
  author       = {{Hansmeier, Tim and Kenter, Tobias and Meyer, Marius and Riebler, Heinrich and Platzner, Marco and Plessl, Christian}},
  booktitle    = {{On-The-Fly Computing -- Individualized IT-services in dynamic markets}},
  editor       = {{Haake, Claus-Jochen and Meyer auf der Heide, Friedhelm and Platzner, Marco and Wachsmuth, Henning and Wehrheim, Heike}},
  pages        = {{165--182}},
  publisher    = {{Heinz Nixdorf Institut, Universität Paderborn}},
  title        = {{{Compute Centers I: Heterogeneous Execution Environments}}},
  doi          = {{10.5281/zenodo.8068642}},
  volume       = {{412}},
  year         = {{2023}},
}

@inbook{45899,
  author       = {{Boschmann, Alexander and Clausing, Lennart and Jentzsch, Felix and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}},
  booktitle    = {{On-The-Fly Computing -- Individualized IT-services in dynamic markets}},
  editor       = {{Haake, Claus-Jochen and Meyer auf der Heide, Friedhelm and Platzner, Marco and Wachsmuth, Henning and Wehrheim, Heike}},
  pages        = {{225--236}},
  publisher    = {{Heinz Nixdorf Institut, Universität Paderborn}},
  title        = {{{Flexible Industrial Analytics on Reconfigurable Systems-On-Chip}}},
  doi          = {{10.5281/zenodo.8068713}},
  volume       = {{412}},
  year         = {{2023}},
}

@misc{54127,
  author       = {{Anantha Rao, Deepak Bhardwaj}},
  publisher    = {{Paderborn University}},
  title        = {{{Efficient Neural Network Inference for Velocity Estimation in Athletic Relay Races on a Microcontroller}}},
  year         = {{2023}},
}