@inproceedings{10735, author = {{Schumacher, Tobias and Lübbers, Enno and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO)}}, pages = {{749--756}}, publisher = {{IOS Press}}, title = {{{Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster}}}, volume = {{15}}, year = {{2007}}, } @inproceedings{13627, author = {{Giefers, Heiner and Platzner, Marco}}, booktitle = {{Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL)}}, isbn = {{9781424410590}}, publisher = {{IEEE}}, title = {{{A Many-Core Implementation Based on the Reconfigurable Mesh Model}}}, doi = {{10.1109/fpl.2007.4380623}}, year = {{2007}}, } @inproceedings{13628, author = {{Lübbers, Enno and Platzner, Marco}}, booktitle = {{Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL)}}, isbn = {{9781424410590}}, publisher = {{IEEE}}, title = {{{ReconOS: An RTOS Supporting Hard-and Software Threads}}}, doi = {{10.1109/fpl.2007.4380686}}, year = {{2007}}, } @inproceedings{2401, abstract = {{ This paper presents a novel method for optimal temporal partitioning of sequential circuits for time-multiplexed reconfigurable architectures. The method bases on slowdown and retiming and maximizes the circuit's performance during execution while restricting the size of the partitions to respect the resource constraints of the reconfigurable architecture. We provide a mixed integer linear program (MILP) formulation of the problem, which can be solved exactly. In contrast to related work, our approach optimizes performance directly, takes structural modifications of the circuit into account, and is extensible. We present the application of the new method to temporal partitioning for a coarse-grained reconfigurable architecture. }}, author = {{Plessl, Christian and Platzner, Marco and Thiele, Lothar}}, booktitle = {{Proc. Int. Conf. on Field Programmable Technology (ICFPT)}}, keywords = {{temporal partitioning, retiming, ILP}}, pages = {{345--348}}, publisher = {{IEEE Computer Society}}, title = {{{Optimal Temporal Partitioning based on Slowdown and Retiming}}}, doi = {{10.1109/FPT.2006.270344}}, year = {{2006}}, } @inproceedings{10688, author = {{Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD)}}, title = {{{Multi-objective Intrinsic Hardware Evolution}}}, year = {{2006}}, } @misc{10716, author = {{Mühlenbernd, Roland}}, publisher = {{Paderborn University}}, title = {{{FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks}}}, year = {{2006}}, } @inproceedings{13624, author = {{Danne, Klaus and Mühlenbernd, Roland and Platzner, Marco}}, booktitle = {{Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL)}}, publisher = {{IEEE}}, title = {{{Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions}}}, year = {{2006}}, } @inproceedings{13625, author = {{Danne, Klaus and Platzner, Marco}}, booktitle = {{In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)}}, title = {{{An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices}}}, year = {{2006}}, } @inproceedings{13626, author = {{Danne, Klaus and Platzner, Marco}}, booktitle = {{Proceedings of the 13th Reconfigurable Architectures Workshop (RAW)}}, publisher = {{IEEE CS Press}}, title = {{{Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware}}}, year = {{2006}}, } @inproceedings{2411, abstract = {{ This paper motivates the use of hardware virtualization on coarse-grained reconfigurable architectures. We introduce Zippy, a coarse-grained multi-context hybrid CPU with architectural support for efficient hardware virtualization. The architectural details and the corresponding tool flow are outlined. As a case study, we compare the non-virtualized and the virtualized execution of an ADPCM decoder. }}, author = {{Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}}, keywords = {{Zippy}}, pages = {{213--218}}, publisher = {{IEEE Computer Society}}, title = {{{Zippy – A coarse-grained reconfigurable array with support for hardware virtualization}}}, doi = {{10.1109/ASAP.2005.69}}, year = {{2005}}, }