@inproceedings{2424, abstract = {{ Recent generations of high-density and high-speed FPGAs provide a sufficient capacity for implementing complete configurable systems on a chip (CSoCs). Hybrid CPUs that combine standard CPU cores with reconfigurable coprocessors are an important subclass of CSoCs. With partially reconfigurable FPGAs, coprocessors can be loaded on demand while the CPU remains running. However, the lack of high-level design tools for partial reconfiguration makes practical implementations a challenging task. In this paper, we introduce a design flow to implement hybrid processors on Xilinx Virtex. The design flow is based on two techniques, virtual sockets and feed-through components, and can efficiently generate partial configurations from industry-quality cores. We discuss the design flow and present a fully operational audio streaming prototype to demonstrate its feasibility. }}, author = {{Dyer, Matthias and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}}, keywords = {{partial reconfiguration}}, pages = {{292--301}}, publisher = {{Springer}}, title = {{{Partially Reconfigurable Cores for Xilinx Virtex}}}, doi = {{10.1007/3-540-46117-5}}, volume = {{2438}}, year = {{2002}}, } @inproceedings{2425, abstract = {{ We present instance-specific custom computing machines for the set covering problem. Four accelerator architectures are developed that implement branch \& bound in 3-valued logic and many of the deduction techniques found in software solvers. We use set covering benchmarks from two-level logic minimization and Steiner triple systems to derive and discuss experimental results. The resulting raw speedups are in the order of four magnitudes on average. Finally, we propose a hybrid solver architecture that combines the raw speed of instance-specific reconfigurable hardware with flexible bounding schemes implemented in software. }}, author = {{Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}}, pages = {{163--172}}, publisher = {{IEEE Computer Society}}, title = {{{Custom Computing Machines for the Set Covering Problem}}}, doi = {{10.1109/FPGA.2002.1106671}}, year = {{2002}}, } @article{10651, author = {{Eisenring, Michael and Platzner, Marco}}, journal = {{The Journal of Supercomputing}}, number = {{2}}, pages = {{145--159}}, publisher = {{Kluwer Academic Publishers}}, title = {{{A Framework for Run-time Reconfigurable Systems}}}, doi = {{10.1023/a:1013627403946}}, volume = {{21}}, year = {{2002}}, } @inproceedings{13611, author = {{Walder, Herbert and Platzner, Marco}}, booktitle = {{Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, pages = {{24--30}}, publisher = {{CSREA Press}}, title = {{{Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform}}}, year = {{2002}}, } @inproceedings{2428, abstract = {{ In this paper we present instance-specific accelerators for minimum-cost covering problems. We first define the covering problem and discuss a branch&bound algorithm to solve it. Then we describe an instance-specific hardware architecture that implements branch&bound in 3-valued logic and uses reduction techniques usually found in software solvers. Results for small unate covering problems reveal significant raw speedups. }}, author = {{Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, keywords = {{minimum covering, accelerator, funding-sundance}}, pages = {{85--91}}, publisher = {{CSREA Press}}, title = {{{Instance-Specific Accelerators for Minimum Covering}}}, year = {{2001}}, } @inproceedings{2432, abstract = {{In this paper, we present the analysis of applications from the domain of handheld and wearable computing. This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurable processors. We discuss the selection of representative benchmarks for handhelds and wearables and group the applications into multimedia, communications, and cryptography programs. We simulate the applications on a cycle-accurate processor simulator and gather statistical data such as instruction mix, cache hit rates and memory requirements for an embedded processor model. A breakdown of the executed cycles into different functions identifies the most compute-intensive code sections - the kernels. Then, we analyze the applications and discuss parameters that strongly influence the design of dynamically reconfigurable processors. Finally, we outline the construction of a parameterizable simulation model for a reconfigurable unit that is attached to a processor core.}}, author = {{Enzler, Rolf and Platzner, Marco and Plessl, Christian and Thiele, Lothar and Tröster, Gerhard}}, booktitle = {{Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III}}, keywords = {{benchmark}}, pages = {{135--146}}, title = {{{Reconfigurable Processors for Handhelds and Wearables: Application Analysis}}}, doi = {{10.1117/12.434376}}, volume = {{4525}}, year = {{2001}}, } @article{10713, author = {{Mencer, Oskar and Platzner, Marco and Morf, Martin and J. Flynn, Michael}}, journal = {{{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems}}, number = {{1}}, pages = {{205--210}}, title = {{{Object-oriented domain specific compilers for programming FPGAs}}}, doi = {{10.1109/92.920835}}, volume = {{9}}, year = {{2001}}, } @misc{13463, author = {{Enzler, Rolf and Platzner, Marco}}, publisher = {{TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1)}}, title = {{{Dynamically Reconfigurable Processors}}}, year = {{2001}}, } @article{6507, author = {{Platzner, Marco}}, issn = {{0018-9162}}, journal = {{Computer}}, number = {{4}}, pages = {{58--60}}, publisher = {{Institute of Electrical and Electronics Engineers (IEEE)}}, title = {{{Reconfigurable accelerators for combinatorial problems}}}, doi = {{10.1109/2.839322}}, volume = {{33}}, year = {{2000}}, } @article{10606, author = {{Eisenring, Michael and Platzner, Marco}}, journal = {{IEE Proceedings -- Computers & Digital Techniques}}, pages = {{159--165}}, publisher = {{IET}}, title = {{{Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems}}}, doi = {{10.1049/ip-cdt:20000496}}, volume = {{147}}, year = {{2000}}, }