@article{52686, author = {{Ahmed, Qazi Arbab and Wiersema, Tobias and Platzner, Marco}}, issn = {{2509-3428}}, journal = {{Journal of Hardware and Systems Security}}, keywords = {{General Engineering, Energy Engineering and Power Technology}}, publisher = {{Springer Science and Business Media LLC}}, title = {{{Post-configuration Activation of Hardware Trojans in FPGAs}}}, doi = {{10.1007/s41635-024-00147-5}}, year = {{2024}}, } @unpublished{43048, author = {{Lienen, Christian and Middeke, Sorel Horst and Platzner, Marco}}, title = {{{fpgaDDS: An Intra-FPGA Data Distribution Service for ROS 2 Robotics Applications}}}, year = {{2023}}, } @inproceedings{44194, author = {{Ahmed, Qazi Arbab and Awais, Muhammad and Platzner, Marco}}, booktitle = {{The 24th International Symposium on Quality Electronic Design (ISQED'23), San Francisco, Califorina USA}}, location = {{San Fransico CA 94023-0607, USA}}, title = {{{MAAS: Hiding Trojans in Approximate Circuits}}}, year = {{2023}}, } @misc{45762, author = {{Simon-Mertens, Florian}}, title = {{{Effizienzanalyse leichtgewichtiger Neuronaler Netze für FPGA-basierte Modulationsklassifikation}}}, year = {{2023}}, } @misc{45917, author = {{Raeisi Nafchi, Masood}}, publisher = {{Paderborn University}}, title = {{{Reconfigurable Random Forest Implementation on FPGA}}}, year = {{2023}}, } @misc{45916, author = {{Yadalam Murali Kumar, Nihal}}, publisher = {{Paderborn University}}, title = {{{Data Analytics for Predictive Maintenance of Time Series Data}}}, year = {{2023}}, } @misc{46075, author = {{Raeisi Nafchi, Masood}}, title = {{{Reconfigurable Random Forest Implementation on FPGA}}}, year = {{2023}}, } @unpublished{46229, author = {{Lienen, Christian and Nowosad, Alexander Philipp and Platzner, Marco}}, title = {{{Mapping and Optimizing Communication in ROS 2-based Applications on Configurable System-on-Chip Platforms}}}, year = {{2023}}, } @inproceedings{45913, author = {{Clausing, Lennart and Guetattfi, Zakarya and Kaufmann, Paul and Lienen, Christian and Platzner, Marco}}, booktitle = {{Proceedings of the 19th International Symposium on Applied Reconfigurable Computing (ARC)}}, title = {{{On Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconOS64}}}, year = {{2023}}, } @phdthesis{47837, author = {{Hansmeier, Tim}}, title = {{{XCS for Self-awareness in Autonomous Computing Systems}}}, year = {{2023}}, } @misc{52480, author = {{Klassen, Alexander}}, title = {{{Fast Partial Reconfiguration for ReconOS64 on Xilinx MPSoC Devices}}}, year = {{2023}}, } @inproceedings{29945, author = {{Witschen, Linus Matthias and Wiersema, Tobias and Reuter, Lucas David and Platzner, Marco}}, booktitle = {{2022 59th ACM/IEEE Design Automation Conference (DAC)}}, location = {{San Francisco, USA}}, title = {{{Search Space Characterization for Approximate Logic Synthesis }}}, year = {{2022}}, } @inproceedings{29865, author = {{Witschen, Linus Matthias and Wiersema, Tobias and Artmann, Matthias and Platzner, Marco}}, booktitle = {{Design, Automation and Test in Europe (DATE)}}, location = {{Online}}, title = {{{MUSCAT: MUS-based Circuit Approximation Technique}}}, year = {{2022}}, } @inproceedings{30971, author = {{Hansmeier, Tim and Platzner, Marco}}, booktitle = {{Applications of Evolutionary Computation, EvoApplications 2022, Proceedings}}, isbn = {{9783031024610}}, issn = {{0302-9743}}, location = {{Madrid}}, pages = {{386--401}}, publisher = {{Springer International Publishing}}, title = {{{Integrating Safety Guarantees into the Learning Classifier System XCS}}}, doi = {{10.1007/978-3-031-02462-7_25}}, volume = {{13224}}, year = {{2022}}, } @inproceedings{32855, author = {{Clausing, Lennart and Platzner, Marco}}, booktitle = {{2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}}, location = {{ Lyon, France}}, pages = {{120--127}}, publisher = {{IEEE}}, title = {{{ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support}}}, doi = {{10.1109/ipdpsw55747.2022.00029}}, year = {{2022}}, } @inproceedings{33253, author = {{Hansmeier, Tim and Brede, Mathis and Platzner, Marco}}, booktitle = {{GECCO '22: Proceedings of the Genetic and Evolutionary Computation Conference Companion}}, location = {{Boston, MA, USA}}, pages = {{2071--2079}}, publisher = {{Association for Computing Machinery (ACM)}}, title = {{{XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion}}}, doi = {{10.1145/3520304.3533977}}, year = {{2022}}, } @phdthesis{29769, abstract = {{Wettstreit zwischen der Entwicklung neuer Hardwaretrojaner und entsprechender Gegenmaßnahmen beschreiten Widersacher immer raffiniertere Wege um Schaltungsentwürfe zu infizieren und dabei selbst fortgeschrittene Test- und Verifikationsmethoden zu überlisten. Abgesehen von den konventionellen Methoden um einen Trojaner in eine Schaltung für ein Field-programmable Gate Array (FPGA) einzuschleusen, können auch die Entwurfswerkzeuge heimlich kompromittiert werden um einen Angreifer dabei zu unterstützen einen erfolgreichen Angriff durchzuführen, der zum Beispiel Fehlfunktionen oder ungewollte Informationsabflüsse bewirken kann. Diese Dissertation beschäftigt sich hauptsächlich mit den beiden Blickwinkeln auf Hardwaretrojaner in rekonfigurierbaren Systemen, einerseits der Perspektive des Verteidigers mit einer Methode zur Erkennung von Trojanern auf der Bitstromebene, und andererseits derjenigen des Angreifers mit einer neuartigen Angriffsmethode für FPGA Trojaner. Für die Verteidigung gegen den Trojaner ``Heimtückische LUT'' stellen wir die allererste erfolgreiche Gegenmaßnahme vor, die durch Verifikation mittels Proof-carrying Hardware (PCH) auf der Bitstromebene direkt vor der Konfiguration der Hardware angewendet werden kann, und präsentieren ein vollständiges Schema für den Entwurf und die Verifikation von Schaltungen für iCE40 FPGAs. Für die Gegenseite führen wir einen neuen Angriff ein, welcher bösartiges Routing im eingefügten Trojaner ausnutzt um selbst im fertigen Bitstrom in einem inaktiven Zustand zu verbleiben: Hierdurch kann dieser neuartige Angriff zur Zeit weder von herkömmlichen Test- und Verifikationsmethoden, noch von unserer vorher vorgestellten Verifikation auf der Bitstromebene entdeckt werden.}}, author = {{Ahmed, Qazi Arbab}}, keywords = {{FPGA Security, Hardware Trojans, Bitstream-level Trojans, Bitstream Verification}}, publisher = {{ Paderborn University, Paderborn, Germany}}, title = {{{Hardware Trojans in Reconfigurable Computing}}}, doi = {{10.17619/UNIPB/1-1271}}, year = {{2022}}, } @unpublished{29541, author = {{Lienen, Christian and Platzner, Marco}}, title = {{{ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications}}}, year = {{2022}}, } @inproceedings{34007, author = {{Lienen, Christian and Platzner, Marco}}, location = {{Neaples, Italy}}, title = {{{Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS}}}, year = {{2022}}, } @inproceedings{34005, author = {{Lienen, Christian and Platzner, Marco}}, booktitle = {{2022 25th Euromicro Conference on Digital System Design (DSD)}}, location = {{Maspalomas, Gran Canaria, Spain}}, title = {{{Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications}}}, doi = {{10.1109/DSD57027.2022.00088}}, year = {{2022}}, } @phdthesis{34041, author = {{Witschen, Linus Matthias}}, title = {{{Frameworks and Methodologies for Search-based Approximate Logic Synthesis}}}, doi = {{10.17619/UNIPB/1-1649}}, year = {{2022}}, } @inproceedings{32342, author = {{Ahmed, Qazi Arbab and Platzner, Marco}}, location = {{Pafos, Cyprus}}, publisher = {{IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022)}}, title = {{{On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs}}}, year = {{2022}}, } @misc{42839, author = {{Mehlich, Florian}}, publisher = {{Paderborn University}}, title = {{{An Evaluation of XCS on the OpenAI Gym}}}, year = {{2022}}, } @article{33990, abstract = {{Deep neural networks (DNNs) are penetrating into a broad spectrum of applications and replacing manual algorithmic implementations, including the radio frequency communications domain with classical signal processing algorithms. However, the high throughput (gigasamples per second) and low latency requirements of this application domain pose a significant hurdle for adopting computationally demanding DNNs. In this article, we explore highly specialized DNN inference accelerator approaches on field-programmable gate arrays (FPGAs) for RadioML modulation classification. Using an automated end-to-end flow for the generation of the FPGA solution, we can easily explore a spectrum of solutions that optimize for different design targets, including accuracy, power efficiency, resources, throughput, and latency. By leveraging reduced precision arithmetic and customized streaming dataflow, we demonstrate a solution that meets the application requirements and outperforms alternative FPGA efforts by 3.5x in terms of throughput. Against modern embedded graphics processing units (GPUs), we measure >10x higher throughput and >100x lower latency under comparable accuracy and power envelopes.}}, author = {{Jentzsch, Felix and Umuroglu, Yaman and Pappalardo, Alessandro and Blott, Michaela and Platzner, Marco}}, journal = {{IEEE Micro}}, number = {{6}}, pages = {{125--133}}, publisher = {{IEEE}}, title = {{{RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures}}}, doi = {{10.1109/MM.2022.3202091}}, volume = {{42}}, year = {{2022}}, } @misc{45715, author = {{Tcheussi Ngayap, Vanessa Ingrid}}, title = {{{FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators}}}, year = {{2022}}, } @misc{45914, author = {{Manjunatha, Suraj}}, publisher = {{Paderborn University }}, title = {{{Dealing With Pre-Processing And Feature Extraction Of Time-Series Data In Predictive Maintenance}}}, year = {{2022}}, } @misc{45915, author = {{Kaur , Parvinder}}, title = {{{Analysis of Time-Series Classification in Conditional Monitoring Systems}}}, year = {{2022}}, } @phdthesis{26746, abstract = {{Previous research in proof-carrying hardware has established the feasibility and utility of the approach, and provided a concrete solution for employing it for the certification of functional equivalence checking against a specification, but fell short in connecting it to state-of-the-art formal verification insights, methods and tools. Due to the immense complexity of modern circuits, and verification challenges such as the state explosion problem for sequential circuits, this restriction of readily-available verification solutions severely limited the applicability of the approach in wider contexts. This thesis closes the gap between the PCH approach and current advances in formal hardware verification, provides methods and tools to express and certify a wide range of circuit properties, both functional and non-functional, and presents for the first time prototypes in which circuits that are implemented on actual reconfigurable hardware are verified with PCH methods. Using these results, designers can now apply PCH to establish trust in more complex circuits, by using more diverse properties which they can express using modern, efficient property specification techniques.}}, author = {{Wiersema, Tobias}}, keywords = {{Proof-Carrying Hardware, Formal Verification, Sequential Circuits, Non-Functional Properties, Functional Properties}}, pages = {{293}}, publisher = {{Paderborn University}}, title = {{{Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware}}}, year = {{2021}}, } @article{29150, abstract = {{Robotics applications process large amounts of data in real time and require compute platforms that provide high performance and energy efficiency. FPGAs are well suited for many of these applications, but there is a reluctance in the robotics community to use hardware acceleration due to increased design complexity and a lack of consistent programming models across the software/hardware boundary. In this article, we present ReconROS, a framework that integrates the widely used robot operating system (ROS) with ReconOS, which features multithreaded programming of hardware and software threads for reconfigurable computers. This unique combination gives ROS 2 developers the flexibility to transparently accelerate parts of their robotics applications in hardware. We elaborate on the architecture and the design flow for ReconROS and report on a set of experiments that underline the feasibility and flexibility of our approach.}}, author = {{Lienen, Christian and Platzner, Marco}}, issn = {{1936-7406}}, journal = {{ACM Transactions on Reconfigurable Technology and Systems}}, pages = {{1--20}}, title = {{{Design of Distributed Reconfigurable Robotics Systems with ReconROS}}}, doi = {{10.1145/3494571}}, year = {{2021}}, } @misc{29151, abstract = {{Automation becomes a vital part in the High-Performance computing system in situational dynamics to take the decisions on the fly. Heterogeneous compute nodes consist of computing resources such as CPU, GPU and FPGA and are the important components of the high-performance computing system that can adapt the automation to achieve the given goal. While implanting automation in the computing resources, management of the resources is one of the essential aspects that need to be taken care of. Tasks are continuously executed on the resources using its unique characteristics. Effective scheduling is essential to make the best use of the characteristics provided by each resource. Scheduling enables the execution of each task by allocating resources so that they take advantage of all the characteristics of the compute resources. Various scheduling heuristics can be used to create effective scheduling, which might require the execution time to schedule the task efficiently. Providing actual execution time is not possible in many cases; hence we can provide the estimations for the actual execution time . The purpose of this master's thesis is to design a predictive model or system that estimates the execution time required to execute tasks using historical execution time data on the heterogeneous compute nodes. In this thesis, regression techniques(SGD Regressor, Passive-Aggressive Regressor, MLP Regressor, and XCSF Regressor) are compared in terms of their prediction accuracy in order to determine which technique produces reliable predictions for the execution time. These estimations must be generated in an online learning environment in which data points arrive in any sequence, one by one, and the regression model must learn from them. After evaluating the regression algorithms, it is seen that the XCSF regressor provides the highest overall prediction accuracy for the supplied data sets. The regression technique's parameters also play a significant role in achieving an acceptable prediction accuracy. As a remark, when using online learning in regression analysis, the accuracy depends upon both the order of sequential data points that are coming to train the model and the parameter configuration for each regression technique.}}, author = {{Kashikar, Chinmay}}, publisher = {{Paderborn University}}, title = {{{A Comparison of Machine Learning Techniques for the On-line Characterization of Tasks Executed on Heterogeneous Compute Nodes}}}, year = {{2021}}, } @inproceedings{21610, author = {{Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}}, booktitle = {{Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021}}, location = {{Virtual}}, pages = {{27--32}}, publisher = {{ACM}}, title = {{{LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis}}}, doi = {{https://doi.org/10.1145/3453688.3461506}}, year = {{2021}}, } @misc{22216, author = {{Rehnen, Jakob Werner}}, title = {{{Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib}}}, year = {{2021}}, } @inproceedings{22309, abstract = {{Approximate computing (AC) has acquired significant maturity in recent years as a promising approach to obtain energy and area-efficient hardware. Automated approximate accelerator synthesis involves a great deal of complexity on the size of design space which exponentially grows with the number of possible approximations. Design space exploration of approximate accelerator synthesis is usually targeted via heuristic-based search methods. The majority of existing frameworks prune a large part of the design space using a greedy-based approach to keep the problem tractable. Therefore, they result in inferior solutions since many potential solutions are neglected in the pruning process without the possibility of backtracking of removed approximate instances. In this paper, we address the aforementioned issue by adopting Monte Carlo Tree Search (MCTS), as an efficient stochastic learning-based search algorithm, in the context of automated synthesis of approximate accelerators. This enables the synthesis frameworks to deeply subsamples the design space of approximate accelerator synthesis toward most promising approximate instances based on the required performance goals, i.e., power consumption, area, or/and delay. We investigated the challenges of providing an efficient open-source framework that benefits analytical and search-based approximation techniques simultaneously to both speed up the synthesis runtime and improve the quality of obtained results. Besides, we studied the utilization of machine learning algorithms to improve the performance of several critical steps, i.e., accelerator quality testing, in the synthesis framework. The proposed framework can help the community to rapidly generate efficient approximate accelerators in a reasonable runtime.}}, author = {{Awais, Muhammad and Platzner, Marco}}, booktitle = {{Proceedings of IEEE Computer Society Annual Symposium on VLSI}}, keywords = {{Approximate computing, Design space exploration, Accelerator synthesis}}, location = {{Tampa, Florida USA (Virtual)}}, pages = {{384--389}}, publisher = {{IEEE}}, title = {{{MCTS-Based Synthesis Towards Efficient Approximate Accelerators}}}, year = {{2021}}, } @misc{22483, abstract = {{This bachelor thesis presents a C/C++ implementation of the XCS algorithm for an embedded system and profiling results concerning the execution time of the functions. These are then analyzed in relation to the input characteristics of the examined learning environments and compared with related work. Three main conclusions can be drawn from the measured results. First, the maximum size of the population of the classifiers influences the runtime of the genetic algorithm; second, the size of the input space has a direct effect on the execution time of the matching function; and last, a larger action space results in a longer runtime generating the prediction for the possible actions. The dependencies identified here can serve to optimize the computational efficiency and make XCS more suitable for embedded systems.}}, author = {{Brede, Mathis}}, publisher = {{Paderborn University}}, title = {{{Implementation and Profiling of XCS in the Context of Embedded Systems}}}, year = {{2021}}, } @inproceedings{21953, author = {{Witschen, Linus Matthias and Wiersema, Tobias and Raeisi Nafchi, Masood and Bockhorn, Arne and Platzner, Marco}}, booktitle = {{Proceedings of International Symposium on Applied Reconfigurable Computing (ARC'21)}}, editor = {{Hannig, Frank and Derrien, Steven and Diniz, Pedro and Chillet, Daniel}}, location = {{Virtual conference}}, publisher = {{Springer Lecture Notes in Computer Science}}, title = {{{Timing Optimization for Virtual FPGA Configurations}}}, doi = {{10.1007/978-3-030-79025-7_4}}, year = {{2021}}, } @article{30906, abstract = {{Abstract Background Hand amputation can have a truly debilitating impact on the life of the affected person. A multifunctional myoelectric prosthesis controlled using pattern classification can be used to restore some of the lost motor abilities. However, learning to control an advanced prosthesis can be a challenging task, but virtual and augmented reality (AR) provide means to create an engaging and motivating training. Methods In this study, we present a novel training framework that integrates virtual elements within a real scene (AR) while allowing the view from the first-person perspective. The framework was evaluated in 13 able-bodied subjects and a limb-deficient person divided into intervention (IG) and control (CG) groups. The IG received training by performing simulated clothespin task and both groups conducted a pre- and posttest with a real prosthesis. When training with the AR, the subjects received visual feedback on the generated grasping force. The main outcome measure was the number of pins that were successfully transferred within 20 min (task duration), while the number of dropped and broken pins were also registered. The participants were asked to score the difficulty of the real task (posttest), fun-factor and motivation, as well as the utility of the feedback. Results The performance (median/interquartile range) consistently increased during the training sessions (4/3 to 22/4). While the results were similar for the two groups in the pretest, the performance improved in the posttest only in IG. In addition, the subjects in IG transferred significantly more pins (28/10.5 versus 14.5/11), and dropped (1/2.5 versus 3.5/2) and broke (5/3.8 versus 14.5/9) significantly fewer pins in the posttest compared to CG. The participants in IG assigned (mean ± std) significantly lower scores to the difficulty compared to CG (5.2 ± 1.9 versus 7.1 ± 0.9), and they highly rated the fun factor (8.7 ± 1.3) and usefulness of feedback (8.5 ± 1.7). Conclusion The results demonstrated that the proposed AR system allows for the transfer of skills from the simulated to the real task while providing a positive user experience. The present study demonstrates the effectiveness and flexibility of the proposed AR framework. Importantly, the developed system is open source and available for download and further development. }}, author = {{Boschmann, Alexander and Neuhaus, Dorothee and Vogt, Sarah and Kaltschmidt, Christian and Platzner, Marco and Dosen, Strahinja}}, issn = {{1743-0003}}, journal = {{Journal of NeuroEngineering and Rehabilitation}}, keywords = {{Health Informatics, Rehabilitation}}, number = {{1}}, publisher = {{Springer Science and Business Media LLC}}, title = {{{Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis}}}, doi = {{10.1186/s12984-021-00822-6}}, volume = {{18}}, year = {{2021}}, } @article{30907, author = {{Rodriguez, Alfonso and Otero, Andres and Platzner, Marco and De la Torre, Eduardo}}, issn = {{0018-9340}}, journal = {{IEEE Transactions on Computers}}, keywords = {{Computational Theory and Mathematics, Hardware and Architecture, Theoretical Computer Science, Software}}, pages = {{1--1}}, publisher = {{Institute of Electrical and Electronics Engineers (IEEE)}}, title = {{{Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs}}}, doi = {{10.1109/tc.2021.3107196}}, year = {{2021}}, } @inproceedings{29137, author = {{Hansmeier, Tim}}, booktitle = {{HEART '21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies}}, location = {{Online}}, publisher = {{Association for Computing Machinery (ACM)}}, title = {{{Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS}}}, doi = {{10.1145/3468044.3468055}}, year = {{2021}}, } @misc{29540, abstract = {{Autonomous mobile robots are becoming increasingly more capable and widespread. Reliable Obstacle avoidance is an integral part of autonomous navigation. This involves real time interpretation and processing of a complex environment. Strict time and energy constraints of a mobile autonomous system make efficient computation extremely desirable. The benefits of employing Hardware/Software co-designed applications are obvious and significant. Hardware accelerators are used for efficient processing of the algorithms by exploiting parallelism. FPGAs are a class of hardware accelerators, which can contain hundreds of small execution units, and can be used for Hardware/Software co-designed application. However, there is a reluctance when it comes to adoption of these devices in well established application domains, such as Robotics, due to a steep learning curve needed for FPGA application design. ReconROS has successfully bridged the gap between robotic and FPGA application development, by providing an intuitive, common development platform for robotic application development for FPGA. It does so by integrating Robotics Operating System(ROS) which is an industry and academia standard for robotics application development, with ReconOS, an operating system for re-configurable hardware. In this thesis an obstacle avoidance system is designed and implemented for an autonomous vehicle using ReconROS. The objectives of the thesis is to demonstrate and explore ReconROS integration within the ROS ecosystem and explore the design process within ReconROS framework, and to demonstrate the effectiveness of Hardware Acceleration in Robotics, by analysing the resulting architectures for Latency and Power Consumption.}}, author = {{Sheikh, Muhammad Aamir}}, publisher = {{Paderborn University}}, title = {{{Design and Implementation of a ReconROS-based Obstacle Avoidance System}}}, year = {{2021}}, } @unpublished{22764, abstract = {{Robotics applications process large amounts of data in real-time and require compute platforms that provide high performance and energy-efficiency. FPGAs are well-suited for many of these applications, but there is a reluctance in the robotics community to use hardware acceleration due to increased design complexity and a lack of consistent programming models across the software/hardware boundary. In this paper we present ReconROS, a framework that integrates the widely-used robot operating system (ROS) with ReconOS, which features multithreaded programming of hardware and software threads for reconfigurable computers. This unique combination gives ROS2 developers the flexibility to transparently accelerate parts of their robotics applications in hardware. We elaborate on the architecture and the design flow for ReconROS and report on a set of experiments that underline the feasibility and flexibility of our approach.}}, author = {{Lienen, Christian and Platzner, Marco}}, booktitle = {{arXiv:2107.07208}}, pages = {{19}}, title = {{{Design of Distributed Reconfigurable Robotics Systems with ReconROS}}}, year = {{2021}}, } @inproceedings{21813, author = {{Hansmeier, Tim and Platzner, Marco}}, booktitle = {{GECCO '21: Proceedings of the Genetic and Evolutionary Computation Conference Companion}}, isbn = {{978-1-4503-8351-6}}, location = {{Lille, France}}, pages = {{1639–1647}}, publisher = {{Association for Computing Machinery (ACM)}}, title = {{{An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS}}}, doi = {{10.1145/3449726.3463159}}, year = {{2021}}, } @article{27841, abstract = {{Verification of software and processor hardware usually proceeds separately, software analysis relying on the correctness of processors executing machine instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption. In this paper we present a novel formal approach for hardware/software co-verification targeting processors with custom instruction set extensions. We detail two different approaches for checking whether the hardware fulfills the requirements expected by the software analysis. The approaches are designed to explore a trade-off between generality of the verification and computational effort. Then, we describe the integration of software and hardware analyses for both techniques and describe a fully automated tool chain implementing the approaches. Finally, we demonstrate and compare the two approaches on example source code with custom instructions, using state-of-the-art software analysis and hardware verification techniques.}}, author = {{Jakobs, Marie-Christine and Pauck, Felix and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}}, journal = {{IEEE Access}}, keywords = {{Software Analysis, Abstract Interpretation, Custom Instruction, Hardware Verification}}, publisher = {{IEEE}}, title = {{{Software/Hardware Co-Verification for Custom Instruction Set Processors}}}, doi = {{10.1109/ACCESS.2021.3131213}}, year = {{2021}}, } @inproceedings{29138, author = {{Ahmed, Qazi Arbab}}, booktitle = {{2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)}}, title = {{{Hardware Trojans in Reconfigurable Computing}}}, doi = {{10.1109/vlsi-soc53125.2021.9606974}}, year = {{2021}}, } @inproceedings{20681, abstract = {{The battle of developing hardware Trojans and corresponding countermeasures has taken adversaries towards ingenious ways of compromising hardware designs by circumventing even advanced testing and verification methods. Besides conventional methods of inserting Trojans into a design by a malicious entity, the design flow for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised to assist the attacker to perform a successful malfunctioning or information leakage attack. The advanced stealthy malicious look-up-table (LUT) attack activates a Trojan only when generating the FPGA bitstream and can thus not be detected by register transfer and gate level testing and verification. However, also this attack was recently revealed by a bitstream-level proof-carrying hardware (PCH) approach. In this paper, we present a novel attack that leverages malicious routing of the inserted Trojan circuit to acquire a dormant state even in the generated and transmitted bitstream. The Trojan's payload is connected to primary inputs/outputs of the FPGA via a programmable interconnect point (PIP). The Trojan is detached from inputs/outputs during place-and-route and re-connected only when the FPGA is being programmed, thus activating the Trojan circuit without any need for a trigger logic. Since the Trojan is injected in a post-synthesis step and remains unconnected in the bitstream, the presented attack can currently neither be prevented by conventional testing and verification methods nor by recent bitstream-level verification techniques.}}, author = {{Ahmed, Qazi Arbab and Wiersema, Tobias and Platzner, Marco}}, booktitle = {{2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)}}, location = {{Alpexpo | Grenoble, France}}, publisher = {{2021 Design, Automation and Test in Europe Conference (DATE)}}, title = {{{Malicious Routing: Circumventing Bitstream-level Verification for FPGAs}}}, doi = {{10.23919/DATE51398.2021.9474026}}, year = {{2021}}, } @inproceedings{30909, author = {{Clausing, Lennart}}, booktitle = {{Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies}}, publisher = {{ACM}}, title = {{{ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip}}}, doi = {{10.1145/3468044.3468056}}, year = {{2021}}, } @inproceedings{30908, author = {{Ghasemzadeh Mohammadi, Hassan and Jentzsch, Felix and Kuschel, Maurice and Arshad, Rahil and Rautmare, Sneha and Manjunatha, Suraj and Platzner, Marco and Boschmann, Alexander and Schollbach, Dirk }}, booktitle = {{ Machine Learning and Principles and Practice of Knowledge Discovery in Databases}}, publisher = {{Springer}}, title = {{{FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics}}}, doi = {{https://doi.org/10.1007/978-3-030-93736-2_27}}, year = {{2021}}, } @inproceedings{3583, author = {{ Guetttatfi, Zakarya and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)}}, title = {{{Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices}}}, year = {{2020}}, } @misc{21324, author = {{Chandrakar, Khushboo}}, title = {{{Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis}}}, year = {{2020}}, } @misc{21432, abstract = {{Robots are becoming increasingly autonomous and more capable. Because of a limited portable energy budget by e.g. batteries, and more demanding algorithms, an efficient computation is of interest. Field Programmable Gate Arrays (FPGAs) for example can provide fast and efficient processing and the Robot Operating System (ROS) is a popular middleware used for robotic applications. The novel ReconROS combines version 2 of the Robot Operating System with ReconOS, a framework for integrating reconfigurable hardware. It provides a unified interface between software and hardware. ReconROS is evaluated in this thesis by implementing a Sobel filter as the video processing application, running on a Zynq-7000 series System on Chip. Timing measurements were taken of execution and transfer times and were compared to theoretical values. Designing the hardware implementation is done by C code using High Level Synthesis and with the interface and functionality provided by ReconROS. An important aspect is the publish/subscribe mechanism of ROS. The Operating System interface functions for publishing and subscribing are reasonably fast at below 10 ms for a 1 MB color VGA image. The main memory interface performs well at higher data sizes, crossing 100 MB/s at 20 kB and increasing to a maximum of around 150 MB/s. Furthermore, the hardware implementation introduces consistency to the execution times and performs twice as fast as the software implementation.}}, author = {{Henke, Luca-Sebastian}}, title = {{{Evaluation of a ReconOS-ROS Combination based on a Video Processing Application}}}, year = {{2020}}, } @inproceedings{21584, author = {{Gatica, Carlos Paiz and Platzner, Marco}}, booktitle = {{Machine Learning for Cyber Physical Systems (ML4CPS 2017)}}, isbn = {{9783662590836}}, issn = {{2522-8579}}, title = {{{Adaptable Realization of Industrial Analytics Functions on Edge-Devices using Reconfigurable Architectures}}}, doi = {{10.1007/978-3-662-59084-3_9}}, year = {{2020}}, } @article{17358, abstract = {{Approximate circuits trade-off computational accuracy against improvements in hardware area, delay, or energy consumption. IP core vendors who wish to create such circuits need to convince consumers of the resulting approximation quality. As a solution we propose proof-carrying approximate circuits: The vendor creates an approximate IP core together with a certificate that proves the approximation quality. The proof certificate is bundled with the approximate IP core and sent off to the consumer. The consumer can formally verify the approximation quality of the IP core at a fraction of the typical computational cost for formal verification. In this paper, we first make the case for proof-carrying approximate circuits and then demonstrate the feasibility of the approach by a set of synthesis experiments using an exemplary approximation framework.}}, author = {{Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}}, issn = {{1557-9999}}, journal = {{IEEE Transactions On Very Large Scale Integration Systems}}, keywords = {{Approximate circuit synthesis, approximate computing, error metrics, formal verification, proof-carrying hardware}}, number = {{9}}, pages = {{2084 -- 2088}}, publisher = {{IEEE}}, title = {{{Proof-carrying Approximate Circuits}}}, doi = {{10.1109/TVLSI.2020.3008061}}, volume = {{28}}, year = {{2020}}, } @article{17369, author = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}}, journal = {{International Journal of Hybrid intelligent Systems}}, publisher = {{IOS Press}}, title = {{{Evolution of Application-Specific Cache Mappings}}}, year = {{2020}}, } @unpublished{20748, abstract = {{On the circuit level, the design paradigm Approximate Computing seeks to trade off computational accuracy against a target metric, e.g., energy consumption. This trade-off is possible for many applications due to their inherent resiliency against inaccuracies. In the past, several automated approximation frameworks have been presented, which either utilize designated approximation techniques or libraries to replace approximable circuit parts with inaccurate versions. The frameworks invoke a search algorithm to iteratively explore the search space of performance degraded circuits, and validate their quality individually. In this paper, we propose to reverse this procedure. Rather than exploring the search space, we delineate the approximate parts of the search space which are guaranteed to lead to valid approximate circuits. Our methodology is supported by formal verification and independent of approximation techniques. Eventually, the user is provided with quality bounds of the individual approximable circuit parts. Consequently, our approach guarantees that any approximate circuit which implements these parts within the determined quality constraints satisfies the global quality constraints, superseding a subsequent quality verification. In our experimental results, we present the runtimes of our approach.}}, author = {{Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}}, booktitle = {{Fifth Workshop on Approximate Computing (AxC 2020)}}, pages = {{2}}, title = {{{Search Space Characterization for AxC Synthesis}}}, year = {{2020}}, } @inproceedings{20750, author = {{Lienen, Christian and Platzner, Marco and Rinner, Bernhard}}, booktitle = {{Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT)}}, title = {{{ReconROS: Flexible Hardware Acceleration for ROS2 Applications}}}, year = {{2020}}, } @misc{20820, author = {{Thiele, Simon}}, title = {{{Implementing Machine Learning Functions as PYNQ FPGA Overlays}}}, year = {{2020}}, } @misc{20821, author = {{Jaganath, Vivek}}, title = {{{Extension and Evaluation of Python-based High-Level Synthesis Tool Flows}}}, year = {{2020}}, } @inproceedings{17063, author = {{Hansmeier, Tim and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{GECCO '20: Proceedings of the Genetic and Evolutionary Computation Conference Companion}}, isbn = {{978-1-4503-7127-8}}, location = {{Cancún, Mexico}}, pages = {{1756--1764}}, publisher = {{Association for Computing Machinery (ACM)}}, title = {{{An Adaption Mechanism for the Error Threshold of XCSF}}}, doi = {{10.1145/3377929.3398106}}, year = {{2020}}, } @article{17092, abstract = {{Radiation tolerance in FPGAs is an important field of research particularly for reliable computation in electronics used in aerospace and satellite missions. The motivation behind this research is the degradation of reliability in FPGA hardware due to single-event effects caused by radiation particles. Redundancy is a commonly used technique to enhance the fault-tolerance capability of radiation-sensitive applications. However, redundancy comes with an overhead in terms of excessive area consumption, latency, and power dissipation. Moreover, the redundant circuit implementations vary in structure and resource usage with the redundancy insertion algorithms as well as number of used redundant stages. The radiation environment varies during the operation time span of the mission depending on the orbit and space weather conditions. Therefore, the overheads due to redundancy should also be optimized at run-time with respect to the current radiation level. In this paper, we propose a technique called Dynamic Reliability Management (DRM) that utilizes the radiation data, interprets it, selects a suitable redundancy level, and performs the run-time reconfiguration, thus varying the reliability levels of the target computation modules. DRM is composed of two parts. The design-time tool flow of DRM generates a library of various redundant implementations of the circuit with different magnitudes of performance factors. The run-time tool flow, while utilizing the radiation/error-rate data, selects a required redundancy level and reconfigures the computation module with the corresponding redundant implementation. Both parts of DRM have been verified by experimentation on various benchmarks. The most significant finding we have from this experimentation is that the performance can be scaled multiple times by using partial reconfiguration feature of DRM, e.g., 7.7 and 3.7 times better performance results obtained for our data sorter and matrix multiplier case studies compared with static reliability management techniques. Therefore, DRM allows for maintaining a suitable trade-off between computation reliability and performance overhead during run-time of an application.}}, author = {{Anwer, Jahanzeb and Meisner, Sebastian and Platzner, Marco}}, issn = {{1687-7195}}, journal = {{International Journal of Reconfigurable Computing}}, pages = {{1--19}}, title = {{{Dynamic Reliability Management for FPGA-Based Systems}}}, doi = {{10.1155/2020/2808710}}, year = {{2020}}, } @article{15836, author = {{Bellman, K. and Dutt, N. and Esterle, L. and Herkersdorf, A. and Jantsch, A. and Landauer, C. and R. Lewis, P. and Platzner, Marco and TaheriNejad, N. and Tammemäe, K.}}, journal = {{ACM Transactions on Cyber-Physical Systems}}, pages = {{1--24}}, title = {{{Self-aware Cyber-Physical Systems}}}, volume = {{Accepted for Publication}}, year = {{2020}}, } @inproceedings{16213, abstract = {{Automated synthesis of approximate circuits via functional approximations is of prominent importance to provide efficiency in energy, runtime, and chip area required to execute an application. Approximate circuits are usually obtained either through analytical approximation methods leveraging approximate transformations such as bit-width scaling or via iterative search-based optimization methods when a library of approximate components, e.g., approximate adders and multipliers, is available. For the latter, exploring the extremely large design space is challenging in terms of both computations and quality of results. While the combination of both methods can create more room for further approximations, the \textit{Design Space Exploration}~(DSE) becomes a crucial issue. In this paper, we present such a hybrid synthesis methodology that applies a low-cost analytical method followed by parallel stochastic search-based optimization. We address the DSE challenge through efficient pruning of the design space and skipping unnecessary expensive testing and/or verification steps. The experimental results reveal up to 10.57x area savings in comparison with both purely analytical or search-based approaches. }}, author = {{Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}}, booktitle = {{Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020}}, location = {{Beijing, China}}, pages = {{421--426}}, publisher = {{ACM}}, title = {{{A Hybrid Synthesis Methodology for Approximate Circuits}}}, doi = {{10.1145/3386263.3406952}}, year = {{2020}}, } @inproceedings{16363, author = {{Hansmeier, Tim and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{GECCO '20: Proceedings of the Genetic and Evolutionary Computation Conference Companion}}, isbn = {{978-1-4503-7127-8}}, location = {{Cancún, Mexico}}, pages = {{125--126}}, publisher = {{Association for Computing Machinery (ACM)}}, title = {{{Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold}}}, doi = {{10.1145/3377929.3389968}}, year = {{2020}}, } @inproceedings{20838, author = {{Lösch, Achim and Platzner, Marco}}, booktitle = {{2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}}, isbn = {{9781728174457}}, title = {{{MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes}}}, doi = {{10.1109/ipdpsw50202.2020.00012}}, year = {{2020}}, } @misc{21433, abstract = {{Modern machine learning (ML) techniques continue to move into the embedded system space because traditional centralized compute resources do not suit certain application domains, for example in mobile or real-time environments. Google’s TensorFlow Lite (TFLite) framework supports this shift from cloud to edge computing and makes ML inference accessible on resource-constrained devices. While it offers the possibility to partially delegate computation to hardware accelerators, there is no such “delegate” available to utilize the promising characteristics of reconfigurable hardware. This thesis incorporates modern platform FPGAs into TFLite by implementing a modular delegate framework, which allows accelerators within the programmable logic to take over the execution of neural network layers. To facilitate the necessary hardware/software codesign, the FPGA delegate is based on the operating system for reconfigurable computing (ReconOS), whose partial reconfiguration support enables the instantiation of model-tailored accelerator architectures. In the hardware back-end, a streaming-based prototype accelerator for the MobileNet model family showcases the working order of the platform, but falls short of the desired performance. Thus, it indicates the need for further exploration of alternative accelerator designs, which the delegate could automatically synthesize to meet a model’s demands.}}, author = {{Jentzsch, Felix P.}}, title = {{{Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture}}}, year = {{2020}}, } @article{3585, abstract = {{Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments.}}, author = {{Witschen, Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais, Muhammad and Platzner, Marco}}, issn = {{0026-2714}}, journal = {{Microelectronics Reliability}}, keywords = {{Approximate Computing, Framework, Pareto Front, Accuracy}}, pages = {{277--290}}, publisher = {{Elsevier}}, title = {{{CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation}}}, doi = {{10.1016/j.microrel.2019.04.003}}, volume = {{99}}, year = {{2019}}, } @unpublished{16853, abstract = {{State-of-the-art frameworks for generating approximate circuits usually rely on information gained through circuit synthesis and/or verification to explore the search space and to find an optimal solution. Throughout the process, a large number of circuits may be subject to processing, leading to considerable runtimes. In this work, we propose a search which takes error bounds and pre-computed impact factors into account to reduce the number of invoked synthesis and verification processes. In our experimental results, we achieved speed-ups of up to 76x while area savings remain comparable to the reference search method, simulated annealing.}}, author = {{Witschen, Linus Matthias and Ghasemzadeh Mohammadi, Hassan and Artmann, Matthias and Platzner, Marco}}, booktitle = {{Fourth Workshop on Approximate Computing (AxC 2019)}}, keywords = {{Approximate computing, parameter selection, search space exploration, verification, circuit synthesis}}, pages = {{2}}, title = {{{Jump Search: A Fast Technique for the Synthesis of Approximate Circuits}}}, year = {{2019}}, } @inproceedings{10577, abstract = {{State-of-the-art frameworks for generating approximate circuits automatically explore the search space in an iterative process - often greedily. Synthesis and verification processes are invoked in each iteration to evaluate the found solutions and to guide the search algorithm. As a result, a large number of approximate circuits is subjected to analysis - leading to long runtimes - but only a few approximate circuits might form an acceptable solution. In this paper, we present our Jump Search (JS) method which seeks to reduce the runtime of an approximation process by reducing the number of expensive synthesis and verification steps. To reduce the runtime, JS computes impact factors for each approximation candidate in the circuit to create a selection of approximate circuits without invoking synthesis or verification processes. We denote the selection as path from which JS determines the final solution. In our experimental results, JS achieved speed-ups of up to 57x while area savings remain comparable to the reference search method, Simulated Annealing.}}, author = {{Witschen, Linus Matthias and Ghasemzadeh Mohammadi, Hassan and Artmann, Matthias and Platzner, Marco}}, booktitle = {{Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI '19}}, isbn = {{9781450362528}}, keywords = {{Approximate computing, design automation, parameter selection, circuit synthesis}}, location = {{Tysons Corner, VA, USA}}, publisher = {{ACM}}, title = {{{Jump Search: A Fast Technique for the Synthesis of Approximate Circuits}}}, doi = {{10.1145/3299874.3317998}}, year = {{2019}}, } @article{11950, abstract = {{Advances in electromyographic (EMG) sensor technology and machine learning algorithms have led to an increased research effort into high density EMG-based pattern recognition methods for prosthesis control. With the goal set on an autonomous multi-movement prosthesis capable of performing training and classification of an amputee’s EMG signals, the focus of this paper lies in the acceleration of the embedded signal processing chain. We present two Xilinx Zynq-based architectures for accelerating two inherently different high density EMG-based control algorithms. The first hardware accelerated design achieves speed-ups of up to 4.8 over the software-only solution, allowing for a processing delay lower than the sample period of 1 ms. The second system achieved a speed-up of 5.5 over the software-only version and operates at a still satisfactory low processing delay of up to 15 ms while providing a higher reliability and robustness against electrode shift and noisy channels.}}, author = {{Boschmann, Alexander and Agne, Andreas and Thombansen, Georg and Witschen, Linus Matthias and Kraus, Florian and Platzner, Marco}}, issn = {{0743-7315}}, journal = {{Journal of Parallel and Distributed Computing}}, keywords = {{High density electromyography, FPGA acceleration, Medical signal processing, Pattern recognition, Prosthetics}}, pages = {{77--89}}, publisher = {{Elsevier}}, title = {{{Zynq-based acceleration of robust high density myoelectric signal processing}}}, doi = {{10.1016/j.jpdc.2018.07.004}}, volume = {{123}}, year = {{2019}}, } @article{12967, abstract = {{Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory.}}, author = {{Hansmeier, Tim and Platzner, Marco and Pantho, Md Jubaer Hossain and Andrews, David}}, issn = {{1939-8018}}, journal = {{Journal of Signal Processing Systems}}, number = {{11}}, pages = {{1259 -- 1272}}, title = {{{An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology}}}, doi = {{10.1007/s11265-018-1435-y}}, volume = {{91}}, year = {{2019}}, } @inproceedings{15422, author = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{World Congress on Nature and Biologically Inspired Computing (NaBIC)}}, publisher = {{Springer}}, title = {{{Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor}}}, year = {{2019}}, } @misc{15883, author = {{Kumar Jeyakumar, Shankar}}, title = {{{Incremental learning with Support Vector Machine on embedded platforms}}}, year = {{2019}}, } @misc{15920, abstract = {{Secure hardware design is the most important aspect to be considered in addition to functional correctness. Achieving hardware security in today’s globalized Integrated Cir- cuit(IC) supply chain is a challenging task. One solution that is widely considered to help achieve secure hardware designs is Information Flow Tracking(IFT). It provides an ap- proach to verify that the systems adhere to security properties either by static verification during design phase or dynamic checking during runtime. Proof-Carrying Hardware(PCH) is an approach to verify a functional design prior to using it in hardware. It is a two-party verification approach, where the target party, the consumer requests new functionalities with pre-defined properties to the producer. In response, the producer designs the IP (Intellectual Property) cores with the requested functionalities that adhere to the consumer-defined properties. The producer provides the IP cores and a proof certificate combined into a proof-carrying bitstream to the consumer to verify it. If the verification is successful, the consumer can use the IP cores in his hardware. In essence, the consumer can only run verified IP cores. Correctly applied, PCH techniques can help consumers to defend against many unintentional modifications and malicious alterations of the modules they receive. There are numerous published examples of how to use PCH to detect any change in the functionality of a circuit, i.e., pairing a PCH approach with functional equivalence checking for combinational or sequential circuits. For non-functional properties, since opening new covert channels to leak secret information from secure circuits is a viable attack vector for hardware trojans, i.e., intentionally added malicious circuitry, IFT technique is employed to make sure that secret/untrusted information never reaches any unclassified/trusted outputs. This master thesis aims to explore the possibility of adapting Information Flow Tracking into a Proof-Carrying Hardware scenario. It aims to create a method that combines Infor- mation Flow Tracking(IFT) with a PCH approach at bitstream level enabling consumers to validate the trustworthiness of a module’s information flow without the computational costs of a complete flow analysis.}}, author = {{Keerthipati, Monica}}, publisher = {{Universität Paderborn}}, title = {{{A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking}}}, year = {{2019}}, } @misc{14831, author = {{Sabu, Nithin S.}}, publisher = {{Paderborn University}}, title = {{{FPGA Acceleration of String Search Techniques in Huge Data Sets}}}, year = {{2019}}, } @misc{15946, author = {{Mehta, Jinay}}, title = {{{Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recon􏰃gurable System-on-Chip}}}, year = {{2019}}, } @misc{14546, author = {{Hansmeier, Tim}}, publisher = {{Universität Paderborn}}, title = {{{Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers}}}, year = {{2019}}, } @inproceedings{31067, author = {{Guettatfi, Zakarya and Platzner, Marco and Kermia, Omar and Khouas, Abdelhakim}}, booktitle = {{2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}}, publisher = {{IEEE}}, title = {{{An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware}}}, doi = {{10.1109/ipdpsw.2019.00027}}, year = {{2019}}, } @inproceedings{9913, abstract = {{Reconfigurable hardware has received considerable attention as a platform that enables dynamic hardware updates and thus is able to adapt new configurations at runtime. However, due to their dynamic nature, e.g., field-programmable gate arrays (FPGA) are subject to a constant possibility of attacks, since each new configuration might be compromised. Trojans for reconfigurable hardware that evade state-of-the-art detection techniques and even formal verification, are thus a large threat to these devices. One such stealthy hardware Trojan, that is inserted and activated in two stages by compromised electronic design automation (EDA) tools, has recently been presented and shown to evade all forms of classical pre-configuration detection techniques. This paper presents a successful pre-configuration countermeasure against this ``Malicious Look-up-table (LUT)''-hardware Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH). We show that the method is able to alert innocent module creators to infected EDA tools, and to prohibit malicious ones to sell infected modules to unsuspecting customers.}}, author = {{Ahmed, Qazi Arbab and Wiersema, Tobias and Platzner, Marco}}, booktitle = {{Applied Reconfigurable Computing}}, editor = {{Hochberger, Christian and Nelson, Brent and Koch, Andreas and Woods, Roger and Diniz, Pedro}}, isbn = {{978-3-030-17227-5}}, location = {{Darmstadt, Germany}}, pages = {{127--136}}, publisher = {{Springer International Publishing}}, title = {{{Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan}}}, doi = {{10.1007/978-3-030-17227-5_10}}, volume = {{11444}}, year = {{2019}}, } @misc{15874, author = {{Lienen, Christian}}, publisher = {{Universität Paderborn}}, title = {{{Implementing a Real-time System on a Platform FPGA operated with ReconOS}}}, year = {{2019}}, } @article{12871, author = {{Platzner, Marco and Plessl, Christian}}, issn = {{0170-6012}}, journal = {{Informatik Spektrum}}, title = {{{FPGAs im Rechenzentrum}}}, doi = {{10.1007/s00287-019-01187-w}}, year = {{2019}}, } @misc{52478, author = {{Mehta, Jinay D}}, title = {{{Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable System-on-Chip}}}, year = {{2019}}, } @inproceedings{3362, abstract = {{Profiling applications on a heterogeneous compute node is challenging since the way to retrieve data from the resources and interpret them varies between resource types and manufacturers. This holds especially true for measuring the energy consumption. In this paper we present Ampehre, a novel open source measurement framework that allows developers to gather comparable measurements from heterogeneous compute nodes, e.g., nodes comprising CPU, GPU, and FPGA. We explain the architecture of Ampehre and detail the measurement process on the example of energy measurements on CPU and GPU. To characterize the probing effect, we quantitatively analyze the trade-off between the accuracy of measurements and the CPU load imposed by Ampehre. Based on this analysis, we are able to specify reasonable combinations of sampling periods for the different resource types of a compute node.}}, author = {{Lösch, Achim and Wiens, Alex and Platzner, Marco}}, booktitle = {{Proceedings of the International Conference on Architecture of Computing Systems (ARCS)}}, isbn = {{9783319776095}}, issn = {{0302-9743}}, pages = {{73--84}}, publisher = {{Springer International Publishing}}, title = {{{Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes}}}, doi = {{10.1007/978-3-319-77610-1_6}}, volume = {{10793}}, year = {{2018}}, } @misc{3365, author = {{Schnuer, Jan-Philip}}, publisher = {{Universität Paderborn}}, title = {{{Static Scheduling Algorithms for Heterogeneous Compute Nodes}}}, year = {{2018}}, } @misc{3366, author = {{Croce, Marcel}}, publisher = {{Universität Paderborn}}, title = {{{Evaluation of OpenCL-based Compilation for FPGAs}}}, year = {{2018}}, } @inproceedings{3373, abstract = {{Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory.}}, author = {{Hansmeier, Tim and Platzner, Marco and Andrews, David}}, booktitle = {{ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications}}, isbn = {{9783319788890}}, issn = {{0302-9743}}, location = {{Santorini, Greece}}, pages = {{153--165}}, publisher = {{Springer International Publishing}}, title = {{{An FPGA/HMC-Based Accelerator for Resolution Proof Checking}}}, doi = {{10.1007/978-3-319-78890-6_13}}, volume = {{10824}}, year = {{2018}}, } @unpublished{3586, abstract = {{Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments.}}, author = {{Witschen, Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais, Muhammad and Platzner, Marco}}, booktitle = {{Third Workshop on Approximate Computing (AxC 2018)}}, keywords = {{Approximate Computing, Framework, Pareto Front, Accuracy}}, pages = {{6}}, title = {{{CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation}}}, year = {{2018}}, } @phdthesis{3720, abstract = {{Traditional cache design uses a consolidated block of memory address bits to index a cache set, equivalent to the use of modulo functions. While this module-based mapping scheme is widely used in contemporary cache structures due to the simplicity of its hardware design and its good performance for sequences of consecutive addresses, its use may not be satisfactory for a variety of application domains having different characteristics.This thesis presents a new type of cache mapping scheme, motivated by programmable capabilities combined with Nature-inspired optimization of reconfigurable hardware. This research has focussed on an FPGA-based evolvable cache structure of the first level cache in a multi-core processor architecture, able to dynamically change cache indexing. To solve the challenge of reconfigurable cache mappings, a programmable Boolean circuit based on a combination of Look-up Table (LUT) memory elements is proposed. Focusing on optimization aspects at the system level, a Performance Measurement Infrastructure is introduced that is able to monitor the underlying microarchitectural metrics, and an adaptive evaluation strategy is presented that leverages on Evolutionary Algorithms, that is not only capable of evolving application-specific address-to-cache-index mappings for level one split caches but also of reducing optimization times. Putting this all together and prototyping in an FPGA for a LEON3/Linux-based multi-core processor, the creation of a system architecture reduces cache misses and improves performance over the use of conventional caches.}}, author = {{Ho, Nam}}, pages = {{139}}, publisher = {{Universität Paderborn}}, title = {{{FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization}}}, doi = {{10.17619/UNIPB/1-376}}, year = {{2018}}, } @unpublished{1165, author = {{Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}}, booktitle = {{4th Workshop On Approximate Computing (WAPCO 2018)}}, title = {{{Making the Case for Proof-carrying Approximate Circuits}}}, year = {{2018}}, } @inproceedings{5547, author = {{Lösch, Achim and Platzner, Marco}}, booktitle = {{2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)}}, isbn = {{9781538674796}}, location = {{Milan, Italy}}, publisher = {{IEEE}}, title = {{{A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes}}}, doi = {{10.1109/asap.2018.8445098}}, year = {{2018}}, } @inproceedings{10598, abstract = {{Approximate computing has become a very popular design strategy that exploits error resilient computations to achieve higher performance and energy efficiency. Automated synthesis of approximate circuits is performed via functional approximation, in which various parts of the target circuit are extensively examined with a library of approximate components/transformations to trade off the functional accuracy and computational budget (i.e., power). However, as the number of possible approximate transformations increases, traditional search techniques suffer from a combinatorial explosion due to the large branching factor. In this work, we present a comprehensive framework for automated synthesis of approximate circuits from either structural or behavioral descriptions. We adapt the Monte Carlo Tree Search (MCTS), as a stochastic search technique, to deal with the large design space exploration, which enables a broader range of potential possible approximations through lightweight random simulations. The proposed framework is able to recognize the design Pareto set even with low computational budgets. Experimental results highlight the capabilities of the proposed synthesis framework by resulting in up to 61.69% energy saving while maintaining the predefined quality constraints.}}, author = {{Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}}, booktitle = {{26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)}}, keywords = {{Approximate computing, High-level synthesis, Accuracy, Monte-Carlo tree search, Circuit simulation}}, pages = {{219--224}}, title = {{{An MCTS-based Framework for Synthesis of Approximate Circuits}}}, doi = {{10.1109/VLSI-SoC.2018.8645026}}, year = {{2018}}, } @misc{10782, author = {{Clausing, Lennart}}, publisher = {{Ruhr-University Bochum}}, title = {{{Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data}}}, year = {{2018}}, } @misc{1097, author = {{Jentzsch, Felix Paul}}, keywords = {{Approximate Computing, Proof-Carrying Hardware, Formal Verification}}, publisher = {{Universität Paderborn}}, title = {{{Enforcing IP Core Connection Properties with Verifiable Security Monitors}}}, year = {{2018}}, } @article{12965, author = {{Ghribi, Ines and Abdallah, Riadh Ben and Khalgui, Mohamed and Li, Zhiwu and Alnowibet, Khalid and Platzner, Marco}}, issn = {{2169-3536}}, journal = {{IEEE Access}}, pages = {{14078--14092}}, title = {{{R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints}}}, doi = {{10.1109/access.2018.2799852}}, year = {{2018}}, } @misc{3580, author = {{Hansmeier, Tim}}, publisher = {{Universität Paderborn}}, title = {{{An FPGA Accelerator for Checking Resolution Proofs}}}, year = {{2017}}, } @misc{1157, author = {{Witschen, Linus Matthias}}, publisher = {{Universität Paderborn}}, title = {{{A Framework for the Synthesis of Approximate Circuits}}}, year = {{2017}}, } @misc{74, author = {{Knorr, Christoph}}, publisher = {{Universität Paderborn}}, title = {{{OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten}}}, year = {{2017}}, } @article{9919, abstract = {{This is a study of a combined load restoration and generator start-up procedure. The procedure is structured into three stages according to the power system status and the goal of load restoration. Moreover, for each load restoration stage, the proposed algorithm determines a load restoration sequence by considering renewable energy such as solar and wind park to achieve objective functions. The validity and performance of the proposed algorithm is demonstrated through simulations using IEEE-39 network.}}, author = {{Shen, Cong and Kaufmann, Paul and Braun, Martin}}, journal = {{Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)}}, keywords = {{Load restorationRestoration stageRenewable energyVoltage/frequency fluctuations}}, pages = {{287--299}}, title = {{{Three-Stage Power System Restoration Methodology Considering Renewable Energies}}}, doi = {{10.1016/j.ijepes.2017.07.007}}, volume = {{94}}, year = {{2017}}, } @inproceedings{65, abstract = {{Heterogeneous compute nodes in form of CPUs with attached GPU and FPGA accelerators have strongly gained interested in the last years. Applications differ in their execution characteristics and can therefore benefit from such heterogeneous resources in terms of performance or energy consumption. While performance optimization has been the only goal for a long time, nowadays research is more and more focusing on techniques to minimize energy consumption due to rising electricity costs.This paper presents reMinMin, a novel static list scheduling approach for optimizing the total energy consumption for a set of tasks executed on a heterogeneous compute node. reMinMin bases on a new energy model that differentiates between static and dynamic energy components and covers effects of accelerator tasks on the host CPU. The required energy values are retrieved by measurements on the real computing system. In order to evaluate reMinMin, we compare it with two reference implementations on three task sets with different degrees of heterogeneity. In our experiments, MinMin is consistently better than a scheduler optimizing for dynamic energy only, which requires up to 19.43% more energy, and very close to optimal schedules.}}, author = {{Lösch, Achim and Platzner, Marco}}, booktitle = {{Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)}}, title = {{{reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements}}}, doi = {{10.1109/ASAP.2017.7995272}}, year = {{2017}}, } @article{68, abstract = {{Proof-carrying hardware (PCH) is a principle for achieving safety for dynamically reconfigurable hardware systems. The producer of a hardware module spends huge effort when creating a proof for a safety policy. The proof is then transferred as a certificate together with the configuration bitstream to the consumer of the hardware module, who can quickly verify the given proof. Previous work utilized SAT solvers and resolution traces to set up a PCH technology and corresponding tool flows. In this article, we present a novel technology for PCH based on inductive invariants. For sequential circuits, our approach is fundamentally stronger than the previous SAT-based one since we avoid the limitations of bounded unrolling. We contrast our technology to existing ones and show that it fits into previously proposed tool flows. We conduct experiments with four categories of benchmark circuits and report consumer and producer runtime and peak memory consumption, as well as the size of the certificates and the distribution of the workload between producer and consumer. Experiments clearly show that our new induction-based technology is superior for sequential circuits, whereas the previous SAT-based technology is the better choice for combinational circuits.}}, author = {{Isenberg, Tobias and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}}, journal = {{ACM Transactions on Design Automation of Electronic Systems}}, number = {{4}}, pages = {{61:1----61:23}}, publisher = {{ACM}}, title = {{{Proof-Carrying Hardware via Inductive Invariants}}}, doi = {{10.1145/3054743}}, year = {{2017}}, } @article{10600, author = {{H.W. Leong, Philip and Amano, Hideharu and Anderson, Jason and Bertels, Koen and M.P. Cardoso, Jo\~{a}o and Diessel, Oliver and Gogniat, Guy and Hutton, Mike and Lee, JunKyu and Luk, Wayne and Lysaght, Patrick and Platzner, Marco and K. Prasanna, Viktor and Rissa, Tero and Silvano, Cristina and So, Hayden and Wang, Yu}}, journal = {{ACM Transactions on Reconfigurable Technology and Systems}}, title = {{{The First 25 Years of the FPL Conference – Significant Papers}}}, doi = {{10.1145/2996468}}, year = {{2017}}, } @article{10601, author = {{F. DeMara, Ronald and Platzner, Marco and Ottavi, Marco}}, journal = {{IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing}}, title = {{{Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial)}}}, doi = {{10.1109/TETC.2016.2641599}}, year = {{2017}}, } @article{10611, author = {{Anwer, Jahanzeb and Platzner, Marco}}, journal = {{Microprocessors and Microsystems}}, pages = {{160--172}}, publisher = {{Elsevier}}, title = {{{Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus}}}, doi = {{10.1016/j.micpro.2017.06.002}}, year = {{2017}}, }