@misc{10665, author = {{Hagedorn, Christoph}}, publisher = {{Paderborn University}}, title = {{{Entwicklung einer codegrößenoptimierten Softwarebibliothek für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten}}}, year = {{2014}}, } @inproceedings{10674, author = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{24th Intl. Conf. on Field Programmable Logic and Applications (FPL)}}, keywords = {{Linux, hardware-software codesign, multiprocessing systems, parallel processing, LEON3 multicore platform, Linux kernel, PMU, hardware counters, hardware-software infrastructure, high performance embedded computing, perf_event, performance monitoring unit, Computer architecture, Hardware, Monitoring, Phasor measurement units, Radiation detectors, Registers, Software}}, pages = {{1--4}}, title = {{{A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms}}}, doi = {{10.1109/FPL.2014.6927437}}, year = {{2014}}, } @inproceedings{10677, author = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}}, keywords = {{Linux, cache storage, embedded systems, granular computing, multiprocessing systems, reconfigurable architectures, Leon3 SPARe processor, custom logic events, evolvable-self-adaptable processor cache, fine granular profiling, integer unit events, measurement infrastructure, microarchitectural events, multicore embedded system, perf_event standard Linux performance measurement interface, processor properties, run-time reconfigurable memory-to-cache address mapping engine, run-time reconfigurable multicore infrastructure, split-level caching, Field programmable gate arrays, Frequency locked loops, Irrigation, Phasor measurement units, Registers, Weaving}}, pages = {{31--37}}, title = {{{Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure}}}, doi = {{10.1109/ICES.2014.7008719}}, year = {{2014}}, } @misc{10679, author = {{König, Fabian}}, publisher = {{Paderborn University}}, title = {{{EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese}}}, year = {{2014}}, } @misc{10701, author = {{Koch, Benjamin}}, publisher = {{Paderborn University}}, title = {{{Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA}}}, year = {{2014}}, } @misc{10715, author = {{Mittendorf, Robert}}, publisher = {{Paderborn University}}, title = {{{Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs}}}, year = {{2014}}, } @misc{10732, author = {{Rüthing, Christoph}}, publisher = {{Paderborn University}}, title = {{{The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores}}}, year = {{2014}}, } @phdthesis{10733, abstract = {{Monte-Carlo Tree Search (MCTS) is a class of simulation-based search algorithms. It brought about great success in the past few years regarding the evaluation of deterministic two-player games such as the Asian board game Go. In this thesis, we present a parallelization of the most popular MCTS variant for large HPC compute clusters that efficiently shares a single game tree representation in a distributed memory environment and scales up to 128 compute nodes and 2048 cores. It is hereby one of the most powerful MCTS parallelizations to date. In order to measure the impact of our parallelization on the search quality and remain comparable to the most advanced MCTS implementations to date, we implemented it in a state-of-the-art Go engine Gomorra, making it competitive with the strongest Go programs in the world. We further present an empirical comparison of different Bayesian ranking systems when being used for predicting expert moves for the game of Go and introduce a novel technique for automated detection and analysis of evaluation uncertainties that show up during MCTS searches.}}, author = {{Schäfers, Lars}}, isbn = {{978-3-8325-3748-7}}, pages = {{133}}, publisher = {{Logos Verlag Berlin GmbH}}, title = {{{Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go}}}, year = {{2014}}, } @inproceedings{10738, author = {{Shen, Cong and Kaufmann, Paul and Braun, Martin}}, booktitle = {{IEEE Power and Energy Society General Meeting (IEEE GM)}}, title = {{{Optimizing the Generator Start-up Sequence After a Power System Blackout}}}, year = {{2014}}, } @inproceedings{10739, author = {{Shen, Cong and Kaufmann, Paul and Braun, Martin}}, booktitle = {{Power Systems Computation Conference (PSCC)}}, publisher = {{IEEE}}, title = {{{A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm}}}, year = {{2014}}, } @misc{10744, author = {{Surmund, Sebastian}}, publisher = {{Paderborn University}}, title = {{{Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA}}}, year = {{2014}}, } @book{10756, author = {{I. Esparcia-Alc{\'a}zar, Anna and Eiben, A.E. and Agapitos, Alexandros and Sim{\~o}es, Anabela and G.B. Tettamanzi, Andrea and Della Cioppa, Antonio and M. Mora, Antonio and Cotta, Carlos and Tarantino, Ernesto and Haasdijk, Evert and Divina, Federico and Fern{\'a}ndez de Vega, Francisco and Squillero, Giovanni and De Falco, Ivanoe and Ignacio Hidalgo, J. and Sim, Kevin and Glette, Kyrre and Zhang, Mengjie and Urquhart, Neil and Burelli, Paolo and Kaufmann, Paul and Po{\v s}{\'\i}k, Petr and Schaefer, Robert and Drechsler, Rolf and Antipolis, Sophia and Cagnoni, Stefano and Thanh Nguyen, Trung and S. Bush (editors), William}}, publisher = {{Springer}}, title = {{{Applications of Evolutionary Computation - 17th European Conference, EvoApplications}}}, volume = {{8602}}, year = {{2014}}, } @inproceedings{10764, author = {{Anwer, Jahanzeb and Platzner, Marco}}, booktitle = {{IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)}}, pages = {{177--184}}, publisher = {{IEEE}}, title = {{{Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs}}}, doi = {{10.1109/DFT.2014.6962108}}, year = {{2014}}, } @inproceedings{10773, author = {{Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and Yazdani, Majid and De Micheli, Giovanni}}, booktitle = {{2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)}}, pages = {{163--168}}, publisher = {{IEEE}}, title = {{{Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection}}}, doi = {{10.1109/NANOARCH.2014.6880479}}, year = {{2014}}, } @inproceedings{13154, author = {{Graf, Tobias and Platzner, Marco}}, booktitle = {{2014 IEEE Conference on Computational Intelligence and Games}}, pages = {{1--8}}, title = {{{Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go}}}, doi = {{10.1109/CIG.2014.6932863}}, year = {{2014}}, } @inbook{335, abstract = {{Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung der Ausbildung in den Computerwissenschaften beeinflusst und sogar zur Entstehung von neuen Forschungsrichtungen gef{\"u}hrt. In diesem Beitrag besch{\"a}ftigen wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der Entstehung dieser Grenze, die Hardware und Software erst als eigenst{\"a}ndige Produkte differenziert. Dann widmen wir uns der Frage, welche Funktionen in einem Computersystem besser in Hardware und welche besser in Software realisiert werden sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen Forschungsrichtung, dem sogenannten Hardware/Software Co-design, gef{\"u}hrt hat. Im Hardware/Software Co-design findet eine Verschiebung von Funktionen an der Grenze zwischen Hardware und Software w{\"a}hrend der Entwicklung eines Produktes statt, um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten Produkt hingegen k{\"o}nnen wir dann eine feste Grenze zwischen Hardware und Software beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption, dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware und Software autonom w{\"a}hrend der Betriebszeit vornimmt. Solche Systeme beruhen auf rekonfigurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware eines Computers w{\"a}hrend der Laufzeit ver{\"a}ndert werden kann. Diese Technologie f{\"u}hrt zu einer durchl{\"a}ssigen Grenze zwischen Hardware und Software bzw. l{\"o}st sie die herk{\"o}mmliche Vorstellung einer festen Hardware und einer flexiblen Software damit auf.}}, author = {{Platzner, Marco and Plessl, Christian}}, booktitle = {{Logiken strukturbildender Prozesse: Automatismen}}, editor = {{Künsemöller, Jörn and Eke, Norber Otto and Foit, Lioba and Kaerlein, Timo}}, isbn = {{978-3-7705-5730-1}}, pages = {{123--144}}, publisher = {{Wilhelm Fink}}, title = {{{Verschiebungen an der Grenze zwischen Hardware und Software}}}, year = {{2014}}, } @inproceedings{388, abstract = {{In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties.}}, author = {{Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian}}, booktitle = {{Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)}}, pages = {{144--155}}, publisher = {{Springer International Publishing}}, title = {{{Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer}}}, doi = {{10.1007/978-3-319-05960-0_13}}, volume = {{8405}}, year = {{2014}}, } @article{363, abstract = {{Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices.}}, author = {{Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco and Plessl, Christian}}, journal = {{Microprocessors and Microsystems}}, number = {{8, Part B}}, pages = {{911--919}}, publisher = {{Elsevier}}, title = {{{Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators}}}, doi = {{10.1016/j.micpro.2013.12.001}}, volume = {{38}}, year = {{2014}}, } @inproceedings{377, abstract = {{In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates.}}, author = {{Riebler, Heinrich and Kenter, Tobias and Plessl, Christian and Sorge, Christoph}}, booktitle = {{Proceedings of Field-Programmable Custom Computing Machines (FCCM)}}, keywords = {{coldboot}}, pages = {{222--229}}, publisher = {{IEEE}}, title = {{{Reconstructing AES Key Schedules from Decayed Memory with FPGAs}}}, doi = {{10.1109/FCCM.2014.67}}, year = {{2014}}, } @article{365, abstract = {{Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems.}}, author = {{Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}}, journal = {{ACM Transactions on Reconfigurable Technology and Systems (TRETS)}}, number = {{2}}, publisher = {{ACM}}, title = {{{Self-awareness as a Model for Designing and Operating Heterogeneous Multicores}}}, doi = {{10.1145/2617596}}, volume = {{7}}, year = {{2014}}, } @article{328, abstract = {{The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications}}, author = {{Agne, Andreas and Happe, Markus and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco and Plessl, Christian}}, journal = {{IEEE Micro}}, number = {{1}}, pages = {{60--71}}, publisher = {{IEEE}}, title = {{{ReconOS - An Operating System Approach for Reconfigurable Computing}}}, doi = {{10.1109/MM.2013.110}}, volume = {{34}}, year = {{2014}}, } @inproceedings{1778, author = {{C. Durelli, Gianluca and Pogliani, Marcello and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin Francis and D. Santambrogio, Marco and Bolchini, Cristiana}}, booktitle = {{Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)}}, pages = {{142--149}}, publisher = {{IEEE}}, title = {{{Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach}}}, doi = {{10.1109/ISPA.2014.27}}, year = {{2014}}, } @inproceedings{439, abstract = {{Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes.}}, author = {{Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}}, booktitle = {{Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}}, pages = {{1--8}}, publisher = {{IEEE}}, title = {{{Deferring Accelerator Offloading Decisions to Application Runtime}}}, doi = {{10.1109/ReConFig.2014.7032509}}, year = {{2014}}, } @inproceedings{406, abstract = {{Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design.}}, author = {{Kenter, Tobias and Schmitz, Henning and Plessl, Christian}}, booktitle = {{Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}}, pages = {{1--8}}, publisher = {{IEEE}}, title = {{{Kernel-Centric Acceleration of High Accuracy Stereo-Matching}}}, doi = {{10.1109/ReConFig.2014.7032535}}, year = {{2014}}, } @inproceedings{1780, author = {{C. Durelli, Gianluca and Copolla, Marcello and Djafarian, Karim and Koranaros, George and Miele, Antonio and Paolino, Michele and Pell, Oliver and Plessl, Christian and D. Santambrogio, Marco and Bolchini, Cristiana}}, booktitle = {{Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)}}, publisher = {{Springer}}, title = {{{SAVE: Towards efficient resource management in heterogeneous system architectures}}}, doi = {{10.1007/978-3-319-05960-0_38}}, year = {{2014}}, } @article{1779, author = {{Giefers, Heiner and Plessl, Christian and Förstner, Jens}}, issn = {{0163-5964}}, journal = {{ACM SIGARCH Computer Architecture News}}, keywords = {{funding-maxup, tet_topic_hpc}}, number = {{5}}, pages = {{65--70}}, publisher = {{ACM}}, title = {{{Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers}}}, doi = {{10.1145/2641361.2641372}}, volume = {{41}}, year = {{2014}}, } @phdthesis{11619, abstract = {{Reconfigurable circuit devices have opened up a fundamentally new way of creating adaptable systems. Combined with artificial evolution, reconfigurable circuits allow an elegant adaptation approach to compensating for changes in the distribution of input data, computational resource errors, and variations in resource requirements. Referred to as ``Evolvable Hardware'' (EHW), this paradigm has yielded astonishing results for traditional engineering challenges and has discovered intriguing design principles, which have not yet been seen in conventional engineering. In this thesis, we present new and fundamental work on Evolvable Hardware motivated by the insight that Evolvable Hardware needs to compensate for events with different change rates. To solve the challenge of different adaptation speeds, we propose a unified adaptation approach based on multi-objective evolution, evolving and propagating candidate solutions that are diverse in objectives that may experience radical changes. Focusing on algorithmic aspects, we enable Cartesian Genetic Programming (CGP) model, which we are using to encode Boolean circuits, for multi-objective optimization by introducing a meaningful recombination operator. We improve the scalability of CGP by objectives scaling, periodization of local- and global-search algorithms, and the automatic acquisition and reuse of subfunctions using age- and cone-based techniques. We validate our methods on the applications of adaptation of hardware classifiers to resource changes, recognition of muscular signals for prosthesis control and optimization of processor caches.}}, author = {{Kaufmann, Paul}}, isbn = {{978-3-8325-3530-8}}, pages = {{249}}, publisher = {{Logos Verlag Berlin GmbH}}, title = {{{Adapting Hardware Systems by Means of Multi-Objective Evolution}}}, year = {{2013}}, } @inproceedings{1786, author = {{Kasap, Server and Redif, Soydan}}, booktitle = {{Proc. IEEE Signal Processing and Communications Conf. (SUI)}}, publisher = {{IEEE}}, title = {{{FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm}}}, doi = {{10.1109/SIU.2013.6531530}}, year = {{2013}}, } @article{1792, author = {{Kasap, Server and Redif, Soydan}}, journal = {{IEEE Trans. on Very Large Scale Integration (VLSI) Systems}}, number = {{3}}, pages = {{522--536}}, publisher = {{IEEE}}, title = {{{Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices}}}, doi = {{10.1109/TVLSI.2013.2248069}}, volume = {{22}}, year = {{2013}}, } @phdthesis{501, abstract = {{Handling run-time dynamics on embedded system-on-chip architectures has become more challenging over the years. On the one hand, the impact of workload and physical dynamics on the system behavior has dramatically increased. On the other hand, embedded architectures have become more complex as they have evolved from single-processor systems over multi-processor systems to hybrid multi-core platforms.Static design-time techniques no longer provide suitable solutions to deal with the run-time dynamics of today's embedded systems. Therefore, system designers have to apply run-time solutions, which have hardly been investigated for hybrid multi-core platforms.In this thesis, we present fundamental work in the new area of run-time management on hybrid multi-core platforms. We propose a novel architecture, a self-adaptive hybrid multi-core system, that combines heterogeneous processors, reconfigurable hardware cores, and monitoring cores on a single chip. Using self-adaptation on thread-level, our hybrid multi-core systems can effectively perform performance and thermal management autonomously at run-time. }}, author = {{Happe, Markus}}, isbn = {{978-3-8325-3425-7}}, pages = {{220}}, publisher = {{Logos Verlag Berlin GmbH}}, title = {{{Performance and thermal management on self-adaptive hybrid multi-cores}}}, year = {{2013}}, } @article{10604, author = {{Happe, Markus and Lübbers, Enno and Platzner, Marco}}, journal = {{International Journal of Real-time Image Processing}}, number = {{1}}, pages = {{95 -- 110}}, publisher = {{Springer}}, title = {{{A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking}}}, doi = {{doi:10.1007/s11554-011-0212-y}}, volume = {{8}}, year = {{2013}}, } @inproceedings{10620, author = {{Anwer, Jahanzeb and Meisner, Sebastian and Platzner, Marco}}, booktitle = {{Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on}}, keywords = {{fault tolerant computing, field programmable gate arrays, logic design, reliability, BYU-LANL tool, DRM tool flow, FPGA based hardware designs, avionic application, device technologies, dynamic reliability management, fault-tolerant operation, hardware designs, reconfiguring reliability levels, space applications, Field programmable gate arrays, Hardware, Redundancy, Reliability engineering, Runtime, Tunneling magnetoresistance}}, pages = {{1--6}}, title = {{{Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime}}}, doi = {{10.1109/ReConFig.2013.6732280}}, year = {{2013}}, } @misc{10626, author = {{Bick, Christian}}, publisher = {{Paderborn University}}, title = {{{Beschleunigung von Tiefenberechnung aus Stereobildern durch FPGA-basierte Datenflussrechner}}}, year = {{2013}}, } @inproceedings{10634, author = {{Boschmann, Alexander and Nofen, Barbara and Platzner, Marco}}, booktitle = {{Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)}}, title = {{{Improving transient state myoelectric signal recognition in hand movement classification using gyroscopes}}}, year = {{2013}}, } @inproceedings{10635, author = {{Boschmann, Alexander and Platzner, Marco}}, booktitle = {{Proc. IEEE ISSNIP Biosignals and Biorobotics Conference (BRC)}}, title = {{{Reducing the limb position effect in pattern recognition based myoelectric control using a high density electrode array}}}, year = {{2013}}, } @inproceedings{10655, author = {{Glette, Kyrre and Kaufmann, Paul and Assad, Christopher and Wolf, Michael}}, booktitle = {{IEEE Intl. Conf. on Evolvable Systems (ICES)}}, pages = {{1--1}}, publisher = {{Springer}}, title = {{{Investigating Evolvable Hardware Classification for the BioSleeve Electromyographic Interface}}}, volume = {{1}}, year = {{2013}}, } @book{10681, author = {{Kaufmann, Paul}}, publisher = {{Logos Verlag}}, title = {{{Adapting Hardware Systems by Means of Multi-Objective Evolution}}}, year = {{2013}}, } @article{10684, author = {{Kaufmann, Paul and Glette, Kyrre and Gruber, Tiemo and Platzner, Marco and Torresen, Jim and Sick, Bernhard}}, journal = {{IEEE Transactions on Evolutionary Computation}}, number = {{1}}, pages = {{46--63}}, title = {{{Classification of Electromyographic Signals: Comparing Evolvable Hardware to Conventional Classifiers}}}, doi = {{10.1109/TEVC.2012.2185845}}, volume = {{17}}, year = {{2013}}, } @misc{10700, author = {{Knoop, Michael}}, publisher = {{IWES Kassel}}, title = {{{Behavior Models for Electric Vehicles}}}, year = {{2013}}, } @misc{10720, author = {{Nofen, Barbara}}, publisher = {{Paderborn University}}, title = {{{Verbesserung der Erkennungsrate eines Systems zur Klassifikation von EMG-Signalen durch den Einsatz eines hybriden Lagesensors}}}, year = {{2013}}, } @misc{10727, author = {{Pudelko, Daniel}}, publisher = {{Paderborn University}}, title = {{{Überquerung der Styx - Betriebsparametervariation und Fehlerverhalten eines Platform FPGAs}}}, year = {{2013}}, } @misc{10730, author = {{Riebler, Heinrich}}, publisher = {{Paderborn University}}, title = {{{Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs}}}, year = {{2013}}, } @misc{10741, author = {{Sprenger, Alexander}}, publisher = {{Paderborn University}}, title = {{{MiBenchHybrid : Erweiterung eines Benchmarks um Hardwarebeschleunigung}}}, year = {{2013}}, } @misc{10743, author = {{Steppeler, Philipp}}, publisher = {{Paderborn University}}, title = {{{Beschleunigung von Einzelbild-Erkennungsverfahren auf Datenfluss basierenden HPC Systemen}}}, year = {{2013}}, } @inproceedings{10745, author = {{Toebermann, Christian and Geibel, Daniel and Hau, Manuel and Brandl, Ron and Kaufmann, Paul and Ma, Chenjie and Braun, Martin and Degner, Tobias}}, booktitle = {{Real-Time Conference}}, publisher = {{OPAL RT Paris}}, title = {{{Real-Time Simulation of Distribution Grids with high Penetration of Regenerative and Distributed Generation}}}, year = {{2013}}, } @inproceedings{10774, author = {{Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and Yazdani, Majid and De Micheli, Giovanni}}, booktitle = {{2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)}}, pages = {{83--88}}, publisher = {{IEEE}}, title = {{{A fast TCAD-based methodology for Variation analysis of emerging nano-devices}}}, doi = {{10.1109/DFT.2013.6653587}}, year = {{2013}}, } @inproceedings{10775, author = {{Gaillardon, Pierre-Emmanuel and Ghasemzadeh Mohammadi, Hassan and De Micheli, Giovanni}}, booktitle = {{2013 14th Latin American Test Workshop-LATW}}, pages = {{1--6}}, publisher = {{IEEE}}, title = {{{Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study}}}, doi = {{10.1109/LATW.2013.6562673}}, year = {{2013}}, } @inproceedings{13645, author = {{Graf, Tobias and Schäfers, Lars and Platzner, Marco}}, booktitle = {{Proceedings of the International Conference on Computers and Games (CG)}}, publisher = {{Springer}}, title = {{{On Semeai Detection in Monte-Carlo Go.}}}, year = {{2013}}, } @inproceedings{528, abstract = {{Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES.}}, author = {{Riebler, Heinrich and Kenter, Tobias and Sorge, Christoph and Plessl, Christian}}, booktitle = {{Proceedings of the International Conference on Field-Programmable Technology (FPT)}}, keywords = {{coldboot}}, pages = {{386--389}}, publisher = {{IEEE}}, title = {{{FPGA-accelerated Key Search for Cold-Boot Attacks against AES}}}, doi = {{10.1109/FPT.2013.6718394}}, year = {{2013}}, } @inproceedings{505, abstract = {{In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas.}}, author = {{Happe, Markus and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide, Friedhelm}}, booktitle = {{Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)}}, publisher = {{IEEE}}, title = {{{On-The-Fly Computing: A Novel Paradigm for Individualized IT Services}}}, doi = {{10.1109/ISORC.2013.6913232}}, year = {{2013}}, } @inproceedings{1787, author = {{Suess, Tim and Schoenrock, Andrew and Meisner, Sebastian and Plessl, Christian}}, booktitle = {{Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)}}, isbn = {{978-0-7695-4979-8}}, pages = {{64--73}}, publisher = {{IEEE Computer Society}}, title = {{{Parallel Macro Pipelining on the Intel SCC Many-Core Computer}}}, doi = {{10.1109/IPDPSW.2013.136}}, year = {{2013}}, } @inproceedings{2097, author = {{Kasap, Server and Redif, Soydan}}, booktitle = {{Proc. Int. Conf. on Field Programmable Technology (ICFPT)}}, pages = {{135--140}}, publisher = {{IEEE Computer Society}}, title = {{{FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm}}}, doi = {{10.1109/FPT.2012.6412125}}, year = {{2012}}, } @inproceedings{2100, author = {{Kasap, Server and Redif, Soydan}}, booktitle = {{Int. Architecture and Engineering Symp. (ARCHENG)}}, title = {{{FPGA implementation of a second-order convolutive blind signal separation algorithm}}}, year = {{2012}}, } @inproceedings{2103, author = {{Wistuba, Martin and Schaefers, Lars and Platzner, Marco}}, booktitle = {{Proc. IEEE Conf. on Computational Intelligence and Games (CIG)}}, pages = {{91--99}}, publisher = {{IEEE}}, title = {{{Comparison of Bayesian Move Prediction Systems for Computer Go}}}, doi = {{10.1109/CIG.2012.6374143}}, year = {{2012}}, } @article{2172, author = {{Thielemans, Kris and Tsoumpas, Charalampos and Mustafovic, Sanida and Beisel, Tobias and Aguiar, Pablo and Dikaios, Nikolaos and W Jacobson, Matthew}}, journal = {{Physics in Medicine and Biology}}, number = {{4}}, pages = {{867--883}}, publisher = {{IOP Publishing}}, title = {{{STIR: Software for Tomographic Image Reconstruction Release 2}}}, doi = {{10.1088/0031-9155/57/4/867}}, volume = {{57}}, year = {{2012}}, } @article{2173, author = {{Redif, Soydan and Kasap, Server}}, journal = {{Int. Journal of Electronics}}, number = {{12}}, pages = {{1646--1651}}, publisher = {{Taylor & Francis}}, title = {{{Parallel algorithm for computation of second-order sequential best rotations}}}, doi = {{10.1080/00207217.2012.751343}}, volume = {{100}}, year = {{2012}}, } @article{2174, author = {{Kasap, Server and Benkrid, Khaled}}, journal = {{Journal of Computers}}, number = {{6}}, pages = {{1312--1328}}, publisher = {{Academy Publishers}}, title = {{{Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer}}}, volume = {{7}}, year = {{2012}}, } @phdthesis{586, abstract = {{FPGAs, systems on chip and embedded systems are nowadays irreplaceable. They combine the computational power of application specific hardware with software-like flexibility. At runtime, they can adjust their functionality by downloading new hardware modules and integrating their functionality. Due to their growing capabilities, the demands made to reconfigurable hardware grow. Their deployment in increasingly security critical scenarios requires new ways of enforcing security since a failure in security has severe consequences. Aside from financial losses, a loss of human life and risks to national security are possible. With this work I present the novel and groundbreaking concept of proof-carrying hardware. It is a method for the verification of properties of hardware modules to guarantee security for a target platform at runtime. The producer of a hardware module delivers based on the consumer's safety policy a safety proof in combination with the reconfiguration bitstream. The extensive computation of a proof is a contrast to the comparatively undemanding checking of the proof. I present a prototype based on open-source tools and an abstract FPGA architecture and bitstream format. The proof of the usability of proof-carrying hardware provides the evaluation of the prototype with the exemplary application of securing combinational and bounded sequential equivalence of reference monitor modules for memory safety.}}, author = {{Drzevitzky, Stephanie}}, pages = {{114}}, publisher = {{Universität Paderborn}}, title = {{{Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security}}}, year = {{2012}}, } @misc{587, author = {{Plessl, Christian and Platzner, Marco and Agne, Andreas and Happe, Markus and Lübbers, Enno}}, publisher = {{Awareness Magazine}}, title = {{{Programming models for reconfigurable heterogeneous multi-cores}}}, year = {{2012}}, } @inproceedings{10636, author = {{Boschmann, Alexander and Platzner, Marco}}, booktitle = {{Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)}}, title = {{{Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array}}}, year = {{2012}}, } @misc{10650, author = {{Dridger, Denis}}, publisher = {{Paderborn University}}, title = {{{Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer}}}, year = {{2012}}, } @phdthesis{10652, abstract = {{The paradigm shift towards many-core parallelism is accompanied by two fundamental questions: how should the many processors on a single die communicate to each other and what are suitable programming models for these novel architectures? In this thesis, the author tackles both questions by reviewing the reconfigurable mesh model of massively parallel computation for many-cores. The book presents the design, implementation and evaluation of a many-core architecture that is based on the execution principles and communication infrastructure of the reconfigurable mesh. This work fundamentally rests on FPGA implementations and shows that reconfigurable mesh processors with hundreds of autonomous cores are feasible. Several case studies demonstrate the effectiveness of programming and illustrate why the reconfigurable mesh is a promising model for many-cores.}}, author = {{Giefers, Heiner}}, isbn = {{978-3-8325-3165-2}}, pages = {{159}}, publisher = {{Logos Verlag Berlin GmbH}}, title = {{{Design and Programming of Reconfigurable Mesh based Many-Cores}}}, year = {{2012}}, } @misc{10658, author = {{Graf, Tobias}}, publisher = {{Paderborn University}}, title = {{{Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go}}}, year = {{2012}}, } @misc{10667, author = {{Hangmann, Hendrik}}, publisher = {{Paderborn University}}, title = {{{Generating Adjustable Temperature Gradients on modern FPGAs}}}, year = {{2012}}, } @article{10685, author = {{Kaufmann, Paul and Glette, Kyrre and Platzner, Marco and Torresen, Jim}}, journal = {{International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS)}}, number = {{4}}, pages = {{17--31}}, publisher = {{IGI Global}}, title = {{{Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture}}}, doi = {{10.4018/jaras.2012100102}}, volume = {{3}}, year = {{2012}}, } @misc{10723, author = {{Platzner, Marco and Boschmann, Alexander and Kaufmann, Paul}}, pages = {{6--11}}, title = {{{Wieder natürlich gehen und greifen}}}, year = {{2012}}, } @misc{10734, author = {{Schmitz, Henning}}, publisher = {{Paderborn University}}, title = {{{Stereo Matching on a HC-1 Hybrid Core Computer}}}, year = {{2012}}, } @misc{10747, author = {{Topmöller, Christoph}}, publisher = {{Paderborn University}}, title = {{{Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System}}}, year = {{2012}}, } @misc{10754, author = {{Wistuba, Martin}}, publisher = {{Paderborn University}}, title = {{{Analysis of Pattern Based Model Design and Learning in Computer-Go}}}, year = {{2012}}, } @misc{13462, author = {{Lewis, Peter and Platzner, Marco and Yao, Xin}}, publisher = {{Awareness Magazine}}, title = {{{An outlook for self-awareness in computing systems}}}, year = {{2012}}, } @inproceedings{2106, abstract = {{Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator. In this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort can actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like programming environment exists. As case study we use an application from computational nanophotonics. Our results show that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view.}}, author = {{Meyer, Björn and Schumacher, Jörn and Plessl, Christian and Förstner, Jens}}, booktitle = {{Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}}, keywords = {{funding-upb-forschungspreis, funding-maxup, tet_topic_hpc}}, pages = {{189--196}}, publisher = {{IEEE}}, title = {{{Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?}}}, doi = {{10.1109/FPL.2012.6339370}}, year = {{2012}}, } @article{2108, author = {{Schumacher, Tobias and Plessl, Christian and Platzner, Marco}}, issn = {{0141-9331}}, journal = {{Microprocessors and Microsystems}}, keywords = {{funding-altera}}, number = {{2}}, pages = {{110--126}}, title = {{{IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators}}}, doi = {{10.1016/j.micpro.2011.04.002}}, volume = {{36}}, year = {{2012}}, } @inproceedings{615, abstract = {{Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices.}}, author = {{Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}}, booktitle = {{Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}}, pages = {{1--8}}, publisher = {{IEEE}}, title = {{{Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}}}, doi = {{10.1109/ReConFig.2012.6416745}}, year = {{2012}}, } @inproceedings{591, abstract = {{One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort.}}, author = {{Kenter, Tobias and Plessl, Christian and Schmitz, Henning}}, booktitle = {{Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}}, pages = {{1--8}}, publisher = {{IEEE}}, title = {{{Pragma based parallelization - Trading hardware efficiency for ease of use?}}}, doi = {{10.1109/ReConFig.2012.6416773}}, year = {{2012}}, } @inproceedings{609, abstract = {{Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method.}}, author = {{Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}}, pages = {{8--9}}, title = {{{Hardware/Software Platform for Self-aware Compute Nodes}}}, year = {{2012}}, } @inproceedings{567, abstract = {{Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided.}}, author = {{Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}}, booktitle = {{Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}}, pages = {{559--565}}, publisher = {{IEEE}}, title = {{{Turning control flow graphs into function calls: Code generation for heterogeneous architectures}}}, doi = {{10.1109/HPCSim.2012.6266973}}, year = {{2012}}, } @inproceedings{612, abstract = {{While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA.}}, author = {{Rüthing, Christoph and Happe, Markus and Agne, Andreas and Plessl, Christian}}, booktitle = {{Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}}, pages = {{559--562}}, publisher = {{IEEE}}, title = {{{Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs}}}, doi = {{10.1109/FPL.2012.6339370}}, year = {{2012}}, } @inproceedings{2180, author = {{Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}}, booktitle = {{Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)}}, keywords = {{funding-enhance}}, title = {{{Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux}}}, year = {{2012}}, } @article{2177, author = {{Grad, Mariusz and Plessl, Christian}}, journal = {{Int. Journal of Reconfigurable Computing (IJRC)}}, publisher = {{Hindawi Publishing Corp.}}, title = {{{On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors}}}, doi = {{10.1155/2012/418315}}, year = {{2012}}, } @inproceedings{2191, author = {{Kenter, Tobias and Plessl, Christian and Platzner, Marco and Kauschke, Michael}}, booktitle = {{Intel European Research and Innovation Conference}}, keywords = {{funding-intel}}, title = {{{Estimation and Partitioning for CPU-Accelerator Architectures}}}, year = {{2011}}, } @inbook{2202, author = {{Plessl, Christian and Platzner, Marco}}, booktitle = {{Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility}}, editor = {{Khalgui, Mohamed and Hanisch, Hans-Michael}}, isbn = {{978-1-60960-086-0}}, publisher = {{IGI Global}}, title = {{{Hardware Virtualization on Dynamically Reconfigurable Embedded Processors}}}, doi = {{10.4018/978-1-60960-086-0}}, year = {{2011}}, } @inproceedings{2204, author = {{Graf, Tobias and Lorenz, Ulf and Platzner, Marco and Schaefers, Lars}}, booktitle = {{Proc. European Conf. on Parallel Processing (Euro-Par)}}, publisher = {{Springer}}, title = {{{Parallel Monte-Carlo Tree Search for HPC Systems}}}, doi = {{10.1007/978-3-642-23397-5_36}}, volume = {{6853}}, year = {{2011}}, } @inproceedings{666, abstract = {{Reconfigurable systems on chip are increasingly deployed in security and safety critical contexts. When downloading and configuring new hardware functions, we want to make sure that modules adhere to certain security specifications and do not, for example, contain hardware Trojans. As a possible approach to achieving hardware security we propose and demonstrate the concept of proof-carrying hardware, a concept inspired by previous work on proof-carrying code techniques in the software domain. In this paper, we discuss the hardware trust and threat models behind proof-carrying hardware and then present our experimental setup. We detail the employed open-source tool chain for the runtime verification of combinational equivalence and our bitstream format for an abstract FPGA architecture that allows us to experimentally validate the feasibility of our approach.}}, author = {{Drzevitzky, Stephanie and Platzner, Marco}}, booktitle = {{Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}}, pages = {{58--65}}, title = {{{Achieving Hardware Security for Reconfigurable Systems on Chip by a Proof-Carrying Code Approach}}}, doi = {{10.1109/ReCoSoC.2011.5981499}}, year = {{2011}}, } @inproceedings{10637, author = {{Boschmann, Alexander and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Proc. IEEE Int. Conf. Bioinformatics and Biomedical Technology (ICBBT)}}, title = {{{Accurate gait phase detection using surface electromyographic signals and support vector machines}}}, year = {{2011}}, } @inproceedings{10638, author = {{Boschmann, Alexander and Platzner, Marco and Robrecht, Michael and Hahn, Martin and Winkler, Michael}}, booktitle = {{Proc. MyoElectric Controls Symposium (MEC)}}, title = {{{Development of a pattern recognition-based myoelectric transhumeral prosthesis with multifunctional simultaneous control using a model-driven ppproach for mechatronic systems}}}, year = {{2011}}, } @misc{10678, author = {{Ikonomakis, Nikolaos}}, publisher = {{Paderborn University}}, title = {{{PinSim: Schnelle Simulation mit Pintools}}}, year = {{2011}}, } @misc{10680, author = {{Kassner, Hendrik}}, publisher = {{Paderborn University}}, title = {{{MPI-CUDA Codegenerierung für Nanophoton Simulationen auf Clustern}}}, year = {{2011}}, } @inbook{10687, author = {{Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Organic Computing---A Paradigm Shift for Complex Systems}}, editor = {{Müller-Schloer, Christian and Schmeck, Hartmut and Ungerer, Theo}}, pages = {{193--206}}, publisher = {{Springer Basel}}, title = {{{Multi-objective Intrinsic Evolution of Embedded Systems}}}, volume = {{1}}, year = {{2011}}, } @misc{10736, author = {{Schwabe, Arne}}, publisher = {{Paderborn University}}, title = {{{Analysis of Algorithmic Approaches for Temporal Partitioning}}}, year = {{2011}}, } @inbook{10737, author = {{Sekanina, Lukas and Walker, James Alfred and Kaufmann, Paul and Plessl, Christian and Platzner, Marco}}, booktitle = {{Cartesian Genetic Programming}}, pages = {{125--179}}, publisher = {{Springer Berlin Heidelberg}}, title = {{{Evolution of Electronic Circuits}}}, year = {{2011}}, } @inbook{10748, author = {{Walker, James Alfred and Miller, Julian F. and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Cartesian Genetic Programming}}, pages = {{35--99}}, publisher = {{Springer Berlin Heidelberg}}, title = {{{Problem Decomposition in Cartesian Genetic Programming}}}, year = {{2011}}, } @misc{10750, author = {{Welp, Daniel}}, publisher = {{Paderborn University}}, title = {{{User Space Scheduling for Heterogeneous Systems}}}, year = {{2011}}, } @inproceedings{13643, author = {{Agne, Andreas and Platzner, Marco and Lübbers, Enno}}, booktitle = {{Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}}, isbn = {{9781457714849}}, pages = {{185--188}}, publisher = {{IEEE}}, title = {{{Memory Virtualization for Multithreaded Reconfigurable Hardware}}}, doi = {{10.1109/fpl.2011.42}}, year = {{2011}}, } @inproceedings{13644, author = {{Henkel, Jörg and Hedrich, Lars and Herkersdorf, Andreas and Kapitza, Rüdiger and Lohmann, Daniel and Marwedel, Peter and Platzner, Marco and Rosenstiel, Wolfgang and Schlichtmann, Ulf and Spinczyk, Olaf and Tahoori, Mehdi and Bauer, Lars and Teich, Jürgen and Wehn, Norbert and Wunderlich, Hans-Joachim and Becker, Joachim and Bringmann, Oliver and Brinkschulte, Uwe and Chakraborty, Samarjit and Engel, Michael and Ernst, Rolf and Härtig, Hermann}}, booktitle = {{Proceedings of the seventh IEEE/ACM/IFIP International Conference on Hardware/software Codesign and system synthesis - CODES+ISSS '11}}, isbn = {{9781450307154}}, title = {{{Design and architectures for dependable embedded systems}}}, doi = {{10.1145/2039370.2039384}}, year = {{2011}}, } @inproceedings{2194, author = {{Meyer, Björn and Plessl, Christian and Förstner, Jens}}, booktitle = {{Symp. on Application Accelerators in High Performance Computing (SAAHPC)}}, keywords = {{tet_topic_hpc}}, pages = {{60--63}}, publisher = {{IEEE Computer Society}}, title = {{{Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend}}}, doi = {{10.1109/SAAHPC.2011.12}}, year = {{2011}}, } @inproceedings{2193, author = {{Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}}, booktitle = {{Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}}, pages = {{223--226}}, publisher = {{IEEE Computer Society}}, title = {{{Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler}}}, doi = {{10.1109/ASAP.2011.6043273}}, year = {{2011}}, } @inproceedings{656, abstract = {{In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time.}}, author = {{Happe, Markus and Agne, Andreas and Plessl, Christian}}, booktitle = {{Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)}}, pages = {{55--60}}, publisher = {{IEEE}}, title = {{{Measuring and Predicting Temperature Distributions on FPGAs at Run-Time}}}, doi = {{10.1109/ReConFig.2011.59}}, year = {{2011}}, } @inproceedings{2200, author = {{Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}}, booktitle = {{Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}}, isbn = {{978-1-4503-0554-9}}, keywords = {{design space exploration, LLVM, partitioning, performance, estimation, funding-intel}}, pages = {{177--180}}, publisher = {{ACM}}, title = {{{Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures}}}, doi = {{10.1145/1950413.1950448}}, year = {{2011}}, } @article{2201, author = {{Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}}, journal = {{Int. Journal of Recon- figurable Computing (IJRC)}}, keywords = {{funding-altera}}, publisher = {{Hindawi Publishing Corp.}}, title = {{{FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study}}}, doi = {{10.1155/2011/760954}}, year = {{2011}}, } @inproceedings{2198, author = {{Grad, Mariusz and Plessl, Christian}}, booktitle = {{Proc. Reconfigurable Architectures Workshop (RAW)}}, pages = {{278--285}}, publisher = {{IEEE Computer Society}}, title = {{{Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture}}}, doi = {{10.1109/IPDPS.2011.153}}, year = {{2011}}, }