@inproceedings{13642, author = {{Giefers, Heiner and Platzner, Marco}}, booktitle = {{Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, publisher = {{CSREA Press}}, title = {{{A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics}}}, year = {{2010}}, } @inproceedings{2223, author = {{Lübbers, Enno and Platzner, Marco and Plessl, Christian and Keller, Ariane and Plattner, Bernhard}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-60132-140-6}}, pages = {{225--231}}, publisher = {{CSREA Press}}, title = {{{Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware}}}, year = {{2010}}, } @inproceedings{2216, author = {{Grad, Mariusz and Plessl, Christian}}, booktitle = {{Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}}, pages = {{67--72}}, publisher = {{IEEE Computer Society}}, title = {{{Pruning the Design Space for Just-In-Time Processor Customization}}}, doi = {{10.1109/ReConFig.2010.19}}, year = {{2010}}, } @inproceedings{2224, author = {{Grad, Mariusz and Plessl, Christian}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-60132-140-6}}, pages = {{144--150}}, publisher = {{CSREA Press}}, title = {{{An Open Source Circuit Library with Benchmarking Facilities}}}, year = {{2010}}, } @inproceedings{2220, author = {{Andrews, David and Plessl, Christian}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-60132-140-6}}, pages = {{165}}, publisher = {{CSREA Press}}, title = {{{Configurable Processor Architectures: History and Trends}}}, year = {{2010}}, } @proceedings{2222, editor = {{Plaks, Toomas P. and Andrews, David and DeMara, Ronald and Lam, Herman and Lee, Jooheung and Plessl, Christian and Stitt, Greg}}, isbn = {{1-60132-140-6}}, publisher = {{CSREA Press}}, title = {{{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}}, year = {{2010}}, } @inproceedings{2226, author = {{Beisel, Tobias and Niekamp, Manuel and Plessl, Christian}}, booktitle = {{Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}}, isbn = {{978-1-4244-6965-9}}, pages = {{65--72}}, publisher = {{IEEE Computer Society}}, title = {{{Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators}}}, doi = {{10.1109/ASAP.2010.5540798}}, year = {{2010}}, } @inproceedings{2206, author = {{Keller, Ariane and Plattner, Bernhard and Lübbers, Enno and Platzner, Marco and Plessl, Christian}}, booktitle = {{Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)}}, isbn = {{978-1-4244-8864-3}}, pages = {{372--376}}, publisher = {{IEEE}}, title = {{{Reconfigurable Nodes for Future Networks}}}, doi = {{10.1109/GLOCOMW.2010.5700341}}, year = {{2010}}, } @inproceedings{2228, author = {{Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}}, booktitle = {{Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)}}, editor = {{Hammami, Omar and Larrabee, Sandra}}, title = {{{Performance Estimation for the Exploration of CPU-Accelerator Architectures}}}, year = {{2010}}, } @inproceedings{10639, author = {{Boschmann, Alexander and Kaufmann, Paul and Platzner, Marco and Winkler, Michael}}, booktitle = {{Proc. Technically Assisted Rehabilitation (TAR)}}, title = {{{Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets}}}, year = {{2009}}, } @misc{10702, author = {{Kostin, Alexander}}, publisher = {{Paderborn University}}, title = {{{Evolvable Robot Controller}}}, year = {{2009}}, } @article{10703, author = {{Lübbers, Enno and Platzner, Marco}}, issn = {{1539-9087}}, journal = {{ACM Transactions on Embedded Computing Systems}}, keywords = {{Reconfigurable computing, multithreading, operating systems}}, number = {{1}}, pages = {{8:1--8:33}}, title = {{{ReconOS: Multithreaded Programming for Reconfigurable Computers}}}, doi = {{10.1145/1596532.1596540}}, volume = {{9}}, year = {{2009}}, } @misc{10746, author = {{Tofall, Martin}}, publisher = {{Paderborn University}}, title = {{{Compiler for a Custom Instruction Set CPU}}}, year = {{2009}}, } @misc{10749, author = {{Warkentin, Alexander}}, publisher = {{Paderborn University}}, title = {{{Coarse-grained CGP Model using Xilinx Virtex5 DSP48E Functional Units}}}, year = {{2009}}, } @misc{10753, author = {{Wildenhain, Benedikt}}, publisher = {{Paderborn University}}, title = {{{Implementierung von Kryptographie-Hardwarebeschleunigern für das HW/SW-Betriebssystem ReconOS}}}, year = {{2009}}, } @inproceedings{10777, author = {{Ghasemzadeh Mohammadi, Hassan and Miremadi, Seyed Ghassem and Ejlali, Alireza}}, booktitle = {{Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium on}}, pages = {{252--255}}, publisher = {{IEEE}}, title = {{{Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors}}}, doi = {{10.1109/PRDC.2009.69}}, year = {{2009}}, } @inproceedings{13632, author = {{Happe, Markus and Lübbers, Enno and Platzner, Marco}}, booktitle = {{Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC)}}, publisher = {{Springer}}, title = {{{A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms}}}, year = {{2009}}, } @inproceedings{13634, author = {{Giefers, Heiner and Platzner, Marco}}, booktitle = {{Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS)}}, title = {{{Towards Models for Many-Cores: The Case for the Reconfigurable Mesh}}}, year = {{2009}}, } @inproceedings{13635, author = {{Giefers, Heiner and Platzner, Marco}}, booktitle = {{Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium}}, publisher = {{IEEE}}, title = {{{ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores}}}, year = {{2009}}, } @inproceedings{13636, author = {{Lübbers, Enno and Platzner, Marco}}, booktitle = {{Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) }}, publisher = {{IEEE}}, title = {{{Cooperative Multithreading in Dynamically Reconfigurable Systems}}}, year = {{2009}}, } @inproceedings{13637, author = {{Giefers, Heiner and Platzner, Marco}}, booktitle = {{Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) }}, publisher = {{IEEE}}, title = {{{Program-driven Fine-grained Power Management for the Reconfigurable Mesh}}}, year = {{2009}}, } @inproceedings{13638, author = {{Happe, Markus and Lübbers, Enno and Platzner, Marco}}, booktitle = {{Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT)}}, isbn = {{9781424443758}}, publisher = {{IEEE}}, title = {{{An adaptive Sequential Monte Carlo framework with runtime HW/SW repartitioning}}}, doi = {{10.1109/fpt.2009.5377645}}, year = {{2009}}, } @inproceedings{13639, author = {{Drzevitzky, Stephanie and Kastens, Uwe and Platzner, Marco}}, booktitle = {{Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}}, publisher = {{IEEE}}, title = {{{Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules}}}, year = {{2009}}, } @inproceedings{2350, abstract = {{Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. }}, author = {{Schumacher, Tobias and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}}, isbn = {{978-1-4244-4450-2}}, keywords = {{IMORC, interconnect, performance}}, pages = {{275--278}}, publisher = {{IEEE Computer Society}}, title = {{{IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing}}}, doi = {{10.1109/FCCM.2009.25}}, year = {{2009}}, } @inproceedings{2262, abstract = {{In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. }}, author = {{Kaufmann, Paul and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}}, keywords = {{EvoCache, evolvable hardware, computer architecture}}, pages = {{11--18}}, publisher = {{IEEE Computer Society}}, title = {{{EvoCaches: Application-specific Adaptation of Cache Mapping}}}, year = {{2009}}, } @inproceedings{2238, author = {{Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}}, isbn = {{978-0-7695-3917-1}}, keywords = {{IMORC, graphics}}, pages = {{119--124}}, publisher = {{IEEE Computer Society}}, title = {{{Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000}}}, doi = {{10.1109/ReConFig.2009.32}}, year = {{2009}}, } @inproceedings{2261, author = {{Schumacher, Tobias and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}}, isbn = {{978-1-4244-3892-1}}, issn = {{1946-1488}}, keywords = {{IMORC, NOC, KNN, accelerator}}, pages = {{338--344}}, publisher = {{IEEE}}, title = {{{An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}}}, year = {{2009}}, } @inproceedings{2263, abstract = {{In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Unit (APU) as well as the partial reconfiguration capabilities to provide dynamically reconfigurable custom instructions. We also present a hardware tool flow that automatically translates software functions into custom instructions and a software tool flow that creates binaries using these instructions. While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit. }}, author = {{Grad, Mariusz and Plessl, Christian}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-60132-101-5}}, pages = {{319--322}}, publisher = {{CSREA Press}}, title = {{{Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX}}}, year = {{2009}}, } @inproceedings{2358, author = {{Beisel, Tobias and Lietsch, Stefan and Thielemans, Kris}}, booktitle = {{IEEE Nuclear Science Symposium Conference Record (NSS)}}, pages = {{4161--4168}}, publisher = {{IEEE}}, title = {{{A method for OSEM PET reconstruction on parallel architectures using STIR}}}, doi = {{10.1109/NSSMIC.2008.4774198}}, year = {{2008}}, } @inproceedings{2365, author = {{Platzner, Marco and Döhre, Sven and Happe, Markus and Kenter, Tobias and Lorenz, Ulf and Schumacher, Tobias and Send, Andre and Warkentin, Alexander}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-60132-064-7}}, pages = {{245--251}}, publisher = {{CSREA Press}}, title = {{{The GOmputer: Accelerating GO with FPGAs}}}, year = {{2008}}, } @misc{10628, author = {{Boschmann, Alexander}}, publisher = {{Paderborn University}}, title = {{{Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen}}}, year = {{2008}}, } @misc{10641, author = {{Breitlauch, Daniel}}, publisher = {{Paderborn University}}, title = {{{Selbstoptimierender Cache-Kontroller}}}, year = {{2008}}, } @misc{10644, author = {{Ceylan, Toni and Yalcin, Coni}}, publisher = {{Paderborn University}}, title = {{{Verteilte Simulation von mobilen Robotern mit EyeSim}}}, year = {{2008}}, } @inproceedings{10653, author = {{Glette, Kyrre and Gruber, Thiemo and Kaufmann, Paul and Torresen, Jim and Sick, Bernhard and Platzner, Marco}}, booktitle = {{IEEE Adaptive Hardware and Systems (AHS)}}, pages = {{32--39}}, publisher = {{IEEE}}, title = {{{Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control}}}, year = {{2008}}, } @inproceedings{10656, author = {{Glette, Kyrre and Torresen, Jim and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{IEEE Intl. Conf. on Evolvable Systems (ICES)}}, pages = {{22--33}}, publisher = {{Springer}}, title = {{{A Comparison of Evolvable Hardware Architectures for Classification Tasks}}}, volume = {{5216}}, year = {{2008}}, } @misc{10669, author = {{Happe, Markus}}, publisher = {{Paderborn University}}, title = {{{Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern}}}, year = {{2008}}, } @unpublished{10690, author = {{Torresen, Jim and Glette, Kyrre and Platzner, Marco and Kaufmann, Paul}}, title = {{{Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS)}}}, year = {{2008}}, } @inproceedings{10691, author = {{Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Genetic and Evolutionary Computation (GECCO)}}, pages = {{1219 -- 1226}}, publisher = {{ACM Press}}, title = {{{Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming}}}, year = {{2008}}, } @misc{10696, author = {{Knieper, Tobias}}, publisher = {{Paderborn University}}, title = {{{Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf}}}, year = {{2008}}, } @inproceedings{10698, author = {{Knieper, Tobias and Defo, Bertrand and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Biologically Inspired Collaborative Computing (BICC)}}, pages = {{2313--222}}, publisher = {{Springer}}, title = {{{On Robust Evolution of Digital Hardware}}}, volume = {{268}}, year = {{2008}}, } @misc{10718, author = {{Niklas, Jörg}}, publisher = {{Paderborn University}}, title = {{{Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme}}}, year = {{2008}}, } @misc{10721, author = {{Östermann, Marco}}, publisher = {{Paderborn University}}, title = {{{Raytracing on a Custom Instruction Set CPU}}}, year = {{2008}}, } @misc{10751, author = {{Westerheide, Nico}}, publisher = {{Paderborn University}}, title = {{{Design and Evaluation of MicroBlaze Multi-core Architectures}}}, year = {{2008}}, } @inproceedings{10778, author = {{Ghasemzadeh Mohammadi, Hassan and Tabkhi, Hamed and Miremadi, Seyed Ghassem and Ejlali, Alireza}}, booktitle = {{2008 International Conference on Microelectronics}}, pages = {{444--447}}, publisher = {{IEEE}}, title = {{{A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic}}}, doi = {{10.1109/ICM.2008.5393497}}, year = {{2008}}, } @inproceedings{13629, author = {{Giefers, Heiner and Platzner, Marco}}, booktitle = {{Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS)}}, publisher = {{IEEE}}, title = {{{Realizing Reconfigurable Mesh Algorithms on Softcore Arrays}}}, year = {{2008}}, } @inproceedings{13630, author = {{Lübbers, Enno and Platzner, Marco}}, booktitle = {{Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, publisher = {{CSREA Press}}, title = {{{Communication and Synchronization in Multithreaded Reconfigurable Computing Systems}}}, year = {{2008}}, } @inproceedings{13631, author = {{Lübbers, Enno and Platzner, Marco}}, booktitle = {{Proceedings of the 18th International Conference on Field Programmable Logic and Applications (FPL)}}, isbn = {{9781424419609}}, publisher = {{IEEE}}, title = {{{A portable abstraction layer for hardware threads}}}, doi = {{10.1109/fpl.2008.4629901}}, year = {{2008}}, } @inproceedings{2364, author = {{Schumacher, Tobias and Meiche, Robert and Kaufmann, Paul and Lübbers, Enno and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-60132-064-7}}, pages = {{245--251}}, publisher = {{CSREA Press}}, title = {{{A Hardware Accelerator for k-th Nearest Neighbor Thinning}}}, year = {{2008}}, } @inproceedings{2372, author = {{Schumacher, Tobias and Plessl, Christian and Platzner, Marco}}, booktitle = {{Many-core and Reconfigurable Supercomputing Conference (MRSC)}}, keywords = {{IMORC, IP core, interconnect}}, title = {{{IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers}}}, year = {{2008}}, } @inproceedings{6508, abstract = {{In this paper, we present a framework that supports experimenting with evolutionary hardware design. We describe the framework's modules for composing evolutionary optimizers and for setting up, controlling, and analyzing experiments. Two case studies demonstrate the usefulness of the framework: evolution of hash functions and evolution based on pre-engineered circuits.}}, author = {{Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)}}, isbn = {{076952866X}}, keywords = {{integrated circuit design, hardware evolution, evolutionary hardware design, evolutionary optimizers, hash functions, preengineered circuits, Hardware, Circuits, Design optimization, Visualization, Genetic programming, Genetic mutations, Clustering algorithms, Biological cells, Field programmable gate arrays, Routing}}, location = {{Edinburgh, UK}}, pages = {{447--454}}, publisher = {{IEEE}}, title = {{{MOVES: A Modular Framework for Hardware Evolution}}}, doi = {{10.1109/ahs.2007.73}}, year = {{2007}}, } @misc{10623, author = {{Beisel, Tobias}}, publisher = {{Paderborn University}}, title = {{{Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen}}}, year = {{2007}}, } @article{10625, author = {{Bergmann, Neil and Platzner, Marco and Teich, Jürgen}}, journal = {{{EURASIP} Journal on Embedded Systems}}, pages = {{1--2}}, publisher = {{Springer Science+Business Media}}, title = {{{Dynamically Reconfigurable Architectures (editorial)}}}, doi = {{10.1155/2007/28405}}, volume = {{2007}}, year = {{2007}}, } @misc{10643, author = {{Ceylan, Toni and Yalcin, Coni}}, publisher = {{Paderborn University}}, title = {{{Distributed Simulation of mobile Robots using EyeSim}}}, year = {{2007}}, } @article{10646, author = {{Danne, Klaus and Mühlenbernd, Roland and Platzner, Marco}}, issn = {{1751-8601}}, journal = {{IET Computers Digital Techniques}}, keywords = {{reconfigurable architectures, resource allocation, device reconfiguration time, dynamic hardware reconfiguration, dynamically reconfigurable hardware, light-weight runtime system, merge server distribute load, periodic real-time tasks, runtime system overheads, schedulability analysis, scheduling technique, server-based execution, synthesis tool flow}}, number = {{4}}, pages = {{295--302}}, title = {{{Server-based execution of periodic tasks on dynamically reconfigurable hardware}}}, doi = {{10.1049/iet-cdt:20060186}}, volume = {{1}}, year = {{2007}}, } @misc{10647, author = {{Defo, Bertrand}}, publisher = {{Paderborn University}}, title = {{{A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization}}}, year = {{2007}}, } @misc{10648, author = {{Döhre, Sven}}, publisher = {{Paderborn University}}, title = {{{Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme}}}, year = {{2007}}, } @inproceedings{10689, author = {{Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Architecture of Computing Systems (ARCS)}}, pages = {{199--208}}, publisher = {{Springer}}, title = {{{Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution}}}, volume = {{4415}}, year = {{2007}}, } @misc{10709, author = {{Meiche, Robert}}, publisher = {{Paderborn University}}, title = {{{VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen}}}, year = {{2007}}, } @misc{10728, author = {{Reisch, Waldemar}}, publisher = {{Paderborn University}}, title = {{{Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS}}}, year = {{2007}}, } @misc{10729, author = {{Rethmeier, Eike}}, publisher = {{Paderborn University}}, title = {{{Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem}}}, year = {{2007}}, } @inproceedings{10735, author = {{Schumacher, Tobias and Lübbers, Enno and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO)}}, pages = {{749--756}}, publisher = {{IOS Press}}, title = {{{Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster}}}, volume = {{15}}, year = {{2007}}, } @inproceedings{13627, author = {{Giefers, Heiner and Platzner, Marco}}, booktitle = {{Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL)}}, isbn = {{9781424410590}}, publisher = {{IEEE}}, title = {{{A Many-Core Implementation Based on the Reconfigurable Mesh Model}}}, doi = {{10.1109/fpl.2007.4380623}}, year = {{2007}}, } @inproceedings{13628, author = {{Lübbers, Enno and Platzner, Marco}}, booktitle = {{Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL)}}, isbn = {{9781424410590}}, publisher = {{IEEE}}, title = {{{ReconOS: An RTOS Supporting Hard-and Software Threads}}}, doi = {{10.1109/fpl.2007.4380686}}, year = {{2007}}, } @inproceedings{2401, abstract = {{ This paper presents a novel method for optimal temporal partitioning of sequential circuits for time-multiplexed reconfigurable architectures. The method bases on slowdown and retiming and maximizes the circuit's performance during execution while restricting the size of the partitions to respect the resource constraints of the reconfigurable architecture. We provide a mixed integer linear program (MILP) formulation of the problem, which can be solved exactly. In contrast to related work, our approach optimizes performance directly, takes structural modifications of the circuit into account, and is extensible. We present the application of the new method to temporal partitioning for a coarse-grained reconfigurable architecture. }}, author = {{Plessl, Christian and Platzner, Marco and Thiele, Lothar}}, booktitle = {{Proc. Int. Conf. on Field Programmable Technology (ICFPT)}}, keywords = {{temporal partitioning, retiming, ILP}}, pages = {{345--348}}, publisher = {{IEEE Computer Society}}, title = {{{Optimal Temporal Partitioning based on Slowdown and Retiming}}}, doi = {{10.1109/FPT.2006.270344}}, year = {{2006}}, } @inproceedings{10688, author = {{Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD)}}, title = {{{Multi-objective Intrinsic Hardware Evolution}}}, year = {{2006}}, } @misc{10716, author = {{Mühlenbernd, Roland}}, publisher = {{Paderborn University}}, title = {{{FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks}}}, year = {{2006}}, } @inproceedings{13624, author = {{Danne, Klaus and Mühlenbernd, Roland and Platzner, Marco}}, booktitle = {{Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL)}}, publisher = {{IEEE}}, title = {{{Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions}}}, year = {{2006}}, } @inproceedings{13625, author = {{Danne, Klaus and Platzner, Marco}}, booktitle = {{In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)}}, title = {{{An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices}}}, year = {{2006}}, } @inproceedings{13626, author = {{Danne, Klaus and Platzner, Marco}}, booktitle = {{Proceedings of the 13th Reconfigurable Architectures Workshop (RAW)}}, publisher = {{IEEE CS Press}}, title = {{{Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware}}}, year = {{2006}}, } @inproceedings{2411, abstract = {{ This paper motivates the use of hardware virtualization on coarse-grained reconfigurable architectures. We introduce Zippy, a coarse-grained multi-context hybrid CPU with architectural support for efficient hardware virtualization. The architectural details and the corresponding tool flow are outlined. As a case study, we compare the non-virtualized and the virtualized execution of an ADPCM decoder. }}, author = {{Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}}, keywords = {{Zippy}}, pages = {{213--218}}, publisher = {{IEEE Computer Society}}, title = {{{Zippy – A coarse-grained reconfigurable array with support for hardware virtualization}}}, doi = {{10.1109/ASAP.2005.69}}, year = {{2005}}, } @article{2412, abstract = {{ Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving impact of these design decisions on the overall system performance is a challenging task. In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors.}}, author = {{Enzler, Rolf and Plessl, Christian and Platzner, Marco}}, journal = {{Microprocessors and Microsystems}}, keywords = {{FPGA, reconfigurable computing, co-simulation, Zippy}}, number = {{2-3}}, pages = {{63--73}}, publisher = {{Elsevier}}, title = {{{System-level performance evaluation of reconfigurable processors}}}, doi = {{10.1016/j.micpro.2004.06.004}}, volume = {{29}}, year = {{2005}}, } @inproceedings{13621, author = {{Danne, Klaus and Platzner, Marco}}, booktitle = {{Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES)}}, isbn = {{3902463031}}, title = {{{Periodic real-time scheduling for FPGA computers}}}, doi = {{10.1109/wises.2005.1438720}}, year = {{2005}}, } @inproceedings{13622, author = {{Danne, Klaus and Platzner, Marco}}, booktitle = {{Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS)}}, title = {{{Memory-demanding Periodic Real-time Applications on FPGA Computers}}}, year = {{2005}}, } @inproceedings{13623, author = {{Danne, Klaus and Platzner, Marco}}, booktitle = {{Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL)}}, isbn = {{0780393627}}, publisher = {{IEEE CS Press}}, title = {{{A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware}}}, doi = {{10.1109/fpl.2005.1515787}}, year = {{2005}}, } @inproceedings{2415, abstract = {{In this paper we introduce to virtualization of hardware on reconfigurable devices. We identify three main approaches denoted with temporal partitioning, virtualized execution, and virtual machine. For each virtualization approach, we discuss the application models, the required execution architectures, the design tools and the run-time systems. Then, we survey a selection of important projects in the field. }}, author = {{Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, keywords = {{hardware virtualization}}, pages = {{63--69}}, publisher = {{CSREA Press}}, title = {{{Virtualization of Hardware – Introduction and Survey}}}, year = {{2004}}, } @article{10742, author = {{Steiger, Christoph and Walder, Herbert and Platzner, Marco}}, journal = {{{IEEE} Transactions on Computers}}, number = {{11}}, pages = {{1393--1407}}, title = {{{Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks}}}, doi = {{10.1109/tc.2004.99}}, volume = {{53}}, year = {{2004}}, } @inproceedings{13618, author = {{Walder, Herbert and Platzner, Marco}}, booktitle = {{Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL)}}, isbn = {{9783540229896}}, issn = {{0302-9743}}, pages = {{831--835}}, publisher = {{Springer}}, title = {{{A Runtime Environment for Reconfigurable Hardware Operating Systems}}}, doi = {{10.1007/978-3-540-30117-2_84}}, year = {{2004}}, } @inproceedings{13619, author = {{Walder, Hebert and Nobs, Samuel and Platzner, Marco}}, booktitle = {{Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, publisher = {{CSREA Press}}, title = {{{XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems}}}, year = {{2004}}, } @inproceedings{13620, author = {{Dyer, Matthias and Platzner, Marco and Thiele, Lothar}}, booktitle = {{Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)}}, isbn = {{0769522300}}, publisher = {{IEEE CS Press}}, title = {{{Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine}}}, doi = {{10.1109/fccm.2004.31}}, year = {{2004}}, } @inproceedings{2418, abstract = {{ This paper presents TKDM, a PC-based high-performance reconfigurable computing environment. The TKDM hardware consists of an FPGA module that uses the DIMM (dual inline memory module) bus for high-bandwidth and low-latency communication with the host CPU. The system's firmware is integrated with the Linux host operating system and offers functions for data communication and FPGA reconfiguration. The intended use of TKDM is that of a dynamically reconfigurable co-processor for data streaming applications. The system's firmware can be customized for specific application domains to facilitate simple and easy-to-use programming interfaces. }}, author = {{Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Field Programmable Technology (ICFPT)}}, keywords = {{coprocessor, DIMM, memory bus, FPGA, high performance computing}}, pages = {{252--259}}, publisher = {{IEEE Computer Society}}, title = {{{TKDM – A Reconfigurable Co-processor in a PC's Memory Slot}}}, doi = {{10.1109/FPT.2003.1275755}}, year = {{2003}}, } @article{2419, abstract = {{Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM.}}, author = {{Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan and Platzner, Marco and Thiele, Lothar and Tröster, Gerhard}}, journal = {{Personal and Ubiquitous Computing}}, number = {{5}}, pages = {{299--308}}, publisher = {{Springer}}, title = {{{The Case for Reconfigurable Hardware in Wearable Computing}}}, doi = {{10.1007/s00779-003-0243-x}}, volume = {{7}}, year = {{2003}}, } @article{2420, abstract = {{ This paper presents the acceleration of minimum-cost covering problems by instance-specific hardware. First, we formulate the minimum-cost covering problem and discuss a branch \& bound algorithm to solve it. Then we describe instance-specific hardware architectures that implement branch \& bound in 3-valued logic and use reduction techniques similar to those found in software solvers. We further present prototypical accelerator implementations and a corresponding design tool flow. Our experiments reveal significant raw speedups up to five orders of magnitude for a set of smaller unate covering problems. Provided that hardware compilation times can be reduced, we conclude that instance-specific acceleration of hard minimum-cost covering problems will lead to substantial overall speedups. }}, author = {{Plessl, Christian and Platzner, Marco}}, issn = {{0920-8542}}, journal = {{Journal of Supercomputing}}, keywords = {{reconfigurable computing, instance-specific acceleration, minimum covering}}, number = {{2}}, pages = {{109--129}}, publisher = {{Kluwer Academic Publishers}}, title = {{{Instance-Specific Accelerators for Minimum Covering}}}, doi = {{10.1023/a:1024443416592}}, volume = {{26}}, year = {{2003}}, } @inproceedings{2421, abstract = {{In contrast to processors, current reconfigurable devices totally lack programming models that would allow for device independent compilation and forward compatibility. The key to overcome this limitation is hardware virtualization. In this paper, we resort to a macro-pipelined execution model to achieve hardware virtualization for data streaming applications. As a hardware implementation we present a hybrid multi-context architecture that attaches a coarse-grained reconfigurable array to a host CPU. A co-simulation framework enables cycle-accurate simulation of the complete architecture. As a case study we map an FIR filter to our virtualized hardware model and evaluate different designs. We discuss the impact of the number of contexts and the feature of context state on the speedup and the CPU load.}}, author = {{Enzler, Rolf and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}}, keywords = {{Zippy, multi-context, FPGA}}, pages = {{151--160}}, publisher = {{Springer}}, title = {{{Virtualizing Hardware with Multi-Context Reconfigurable Arrays}}}, doi = {{10.1007/b12007}}, volume = {{2778}}, year = {{2003}}, } @inproceedings{2422, abstract = {{Reconfigurable computing architectures aim to dynamically adapt their hardware to the application at hand. As research shows, the time it takes to reconfigure the hardware forms an overhead that can significantly impair the benefits of hardware customization. Multi-context devices are one promising approach to overcome the limitations posed by long reconfiguration times. In contrast to more traditional reconfigurable architectures, multi-context devices hold several configurations on-chip. On demand, the device can quickly switch to another context. In this paper we present a co-simulation environment to investigate design trade-offs for hybrid multi-context architectures. Our architectural model comprises a reconfigurable unit closely coupled to a CPU core. As a case study, we discuss the implementation of a FIR filter partitioned into several contexts. We outline the mapping process and present simulation results for single- and multi-context reconfigurable units coupled with both embedded and high-end CPUs.}}, author = {{Enzler, Rolf and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-932415-05-X}}, keywords = {{Zippy, co-simulation}}, pages = {{174--180}}, publisher = {{CSREA Press}}, title = {{{Co-simulation of a Hybrid Multi-Context Architecture}}}, year = {{2003}}, } @inproceedings{13612, author = {{Walder, Herbert and Platzner, Marco}}, booktitle = {{Proceedings Design, Automation and Test in Europe Conference (DATE)}}, isbn = {{0769518702}}, pages = {{290--295}}, publisher = {{IEEE CS Press}}, title = {{{Online scheduling for block-partitioned reconfigurable devices}}}, doi = {{10.1109/date.2003.1253622}}, year = {{2003}}, } @inproceedings{13613, author = {{Walder, Herbert and Steiger, Christoph and Platzner, Marco}}, booktitle = {{Proceedings International Parallel and Distributed Processing Symposium}}, isbn = {{0769519261}}, publisher = {{IEEE CS Press}}, title = {{{Fast online task placement on FPGAs: free space partitioning and 2D-hashing}}}, doi = {{10.1109/ipdps.2003.1213329}}, year = {{2003}}, } @inproceedings{13614, author = {{Walder, Herbert and Platzner, Marco}}, booktitle = {{Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, pages = {{284--287}}, publisher = {{CSREA Press}}, title = {{{Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations}}}, year = {{2003}}, } @inproceedings{13615, author = {{Steiger, Christoph and Walder, Herbert and Platzner, Marco}}, booktitle = {{Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL)}}, isbn = {{9783540408222}}, issn = {{0302-9743}}, pages = {{575--584}}, publisher = {{Springer}}, title = {{{Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices}}}, doi = {{10.1007/978-3-540-45234-8_56}}, year = {{2003}}, } @inproceedings{13617, author = {{Steiger, Christoph and Walder, Herbert and Platzner, Marco and Thiele, Lothar}}, booktitle = {{Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS)}}, isbn = {{0769520448}}, pages = {{252--235}}, publisher = {{IEEE CS Press}}, title = {{{Online scheduling and placement of real-time tasks to partially reconfigurable devices}}}, doi = {{10.1109/real.2003.1253269}}, year = {{2003}}, } @inproceedings{2423, abstract = {{Wearable computers are embedded into the mobile environment of the human body. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with low energy consumption required to maximize battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss two experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we develop and evaluate task placement techniques used in the operating system layer of WURM.}}, author = {{Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan and Platzner, Marco and Thiele, Lothar}}, booktitle = {{Proc. Int. Symp. on Wearable Computers (ISWC)}}, isbn = {{0-7695-1816-8}}, keywords = {{wearable computing}}, pages = {{215--222}}, publisher = {{IEEE Computer Society}}, title = {{{Reconfigurable Hardware in Wearable Computing Nodes}}}, doi = {{10.1109/ISWC.2002.1167250}}, year = {{2002}}, } @inproceedings{2424, abstract = {{ Recent generations of high-density and high-speed FPGAs provide a sufficient capacity for implementing complete configurable systems on a chip (CSoCs). Hybrid CPUs that combine standard CPU cores with reconfigurable coprocessors are an important subclass of CSoCs. With partially reconfigurable FPGAs, coprocessors can be loaded on demand while the CPU remains running. However, the lack of high-level design tools for partial reconfiguration makes practical implementations a challenging task. In this paper, we introduce a design flow to implement hybrid processors on Xilinx Virtex. The design flow is based on two techniques, virtual sockets and feed-through components, and can efficiently generate partial configurations from industry-quality cores. We discuss the design flow and present a fully operational audio streaming prototype to demonstrate its feasibility. }}, author = {{Dyer, Matthias and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}}, keywords = {{partial reconfiguration}}, pages = {{292--301}}, publisher = {{Springer}}, title = {{{Partially Reconfigurable Cores for Xilinx Virtex}}}, doi = {{10.1007/3-540-46117-5}}, volume = {{2438}}, year = {{2002}}, } @inproceedings{2425, abstract = {{ We present instance-specific custom computing machines for the set covering problem. Four accelerator architectures are developed that implement branch \& bound in 3-valued logic and many of the deduction techniques found in software solvers. We use set covering benchmarks from two-level logic minimization and Steiner triple systems to derive and discuss experimental results. The resulting raw speedups are in the order of four magnitudes on average. Finally, we propose a hybrid solver architecture that combines the raw speed of instance-specific reconfigurable hardware with flexible bounding schemes implemented in software. }}, author = {{Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}}, pages = {{163--172}}, publisher = {{IEEE Computer Society}}, title = {{{Custom Computing Machines for the Set Covering Problem}}}, doi = {{10.1109/FPGA.2002.1106671}}, year = {{2002}}, } @article{10651, author = {{Eisenring, Michael and Platzner, Marco}}, journal = {{The Journal of Supercomputing}}, number = {{2}}, pages = {{145--159}}, publisher = {{Kluwer Academic Publishers}}, title = {{{A Framework for Run-time Reconfigurable Systems}}}, doi = {{10.1023/a:1013627403946}}, volume = {{21}}, year = {{2002}}, } @inproceedings{13611, author = {{Walder, Herbert and Platzner, Marco}}, booktitle = {{Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, pages = {{24--30}}, publisher = {{CSREA Press}}, title = {{{Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform}}}, year = {{2002}}, } @inproceedings{2428, abstract = {{ In this paper we present instance-specific accelerators for minimum-cost covering problems. We first define the covering problem and discuss a branch&bound algorithm to solve it. Then we describe an instance-specific hardware architecture that implements branch&bound in 3-valued logic and uses reduction techniques usually found in software solvers. Results for small unate covering problems reveal significant raw speedups. }}, author = {{Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, keywords = {{minimum covering, accelerator, funding-sundance}}, pages = {{85--91}}, publisher = {{CSREA Press}}, title = {{{Instance-Specific Accelerators for Minimum Covering}}}, year = {{2001}}, } @inproceedings{2432, abstract = {{In this paper, we present the analysis of applications from the domain of handheld and wearable computing. This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurable processors. We discuss the selection of representative benchmarks for handhelds and wearables and group the applications into multimedia, communications, and cryptography programs. We simulate the applications on a cycle-accurate processor simulator and gather statistical data such as instruction mix, cache hit rates and memory requirements for an embedded processor model. A breakdown of the executed cycles into different functions identifies the most compute-intensive code sections - the kernels. Then, we analyze the applications and discuss parameters that strongly influence the design of dynamically reconfigurable processors. Finally, we outline the construction of a parameterizable simulation model for a reconfigurable unit that is attached to a processor core.}}, author = {{Enzler, Rolf and Platzner, Marco and Plessl, Christian and Thiele, Lothar and Tröster, Gerhard}}, booktitle = {{Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III}}, keywords = {{benchmark}}, pages = {{135--146}}, title = {{{Reconfigurable Processors for Handhelds and Wearables: Application Analysis}}}, doi = {{10.1117/12.434376}}, volume = {{4525}}, year = {{2001}}, } @article{10713, author = {{Mencer, Oskar and Platzner, Marco and Morf, Martin and J. Flynn, Michael}}, journal = {{{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems}}, number = {{1}}, pages = {{205--210}}, title = {{{Object-oriented domain specific compilers for programming FPGAs}}}, doi = {{10.1109/92.920835}}, volume = {{9}}, year = {{2001}}, } @misc{13463, author = {{Enzler, Rolf and Platzner, Marco}}, publisher = {{TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1)}}, title = {{{Dynamically Reconfigurable Processors}}}, year = {{2001}}, } @article{6507, author = {{Platzner, Marco}}, issn = {{0018-9162}}, journal = {{Computer}}, number = {{4}}, pages = {{58--60}}, publisher = {{Institute of Electrical and Electronics Engineers (IEEE)}}, title = {{{Reconfigurable accelerators for combinatorial problems}}}, doi = {{10.1109/2.839322}}, volume = {{33}}, year = {{2000}}, } @article{10606, author = {{Eisenring, Michael and Platzner, Marco}}, journal = {{IEE Proceedings -- Computers & Digital Techniques}}, pages = {{159--165}}, publisher = {{IET}}, title = {{{Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems}}}, doi = {{10.1049/ip-cdt:20000496}}, volume = {{147}}, year = {{2000}}, }