@misc{3365, author = {{Schnuer, Jan-Philip}}, publisher = {{Universität Paderborn}}, title = {{{Static Scheduling Algorithms for Heterogeneous Compute Nodes}}}, year = {{2018}}, } @misc{3366, author = {{Croce, Marcel}}, publisher = {{Universität Paderborn}}, title = {{{Evaluation of OpenCL-based Compilation for FPGAs}}}, year = {{2018}}, } @inproceedings{3373, abstract = {{Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory.}}, author = {{Hansmeier, Tim and Platzner, Marco and Andrews, David}}, booktitle = {{ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications}}, isbn = {{9783319788890}}, issn = {{0302-9743}}, location = {{Santorini, Greece}}, pages = {{153--165}}, publisher = {{Springer International Publishing}}, title = {{{An FPGA/HMC-Based Accelerator for Resolution Proof Checking}}}, doi = {{10.1007/978-3-319-78890-6_13}}, volume = {{10824}}, year = {{2018}}, } @unpublished{3586, abstract = {{Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments.}}, author = {{Witschen, Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais, Muhammad and Platzner, Marco}}, booktitle = {{Third Workshop on Approximate Computing (AxC 2018)}}, keywords = {{Approximate Computing, Framework, Pareto Front, Accuracy}}, pages = {{6}}, title = {{{CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation}}}, year = {{2018}}, } @phdthesis{3720, abstract = {{Traditional cache design uses a consolidated block of memory address bits to index a cache set, equivalent to the use of modulo functions. While this module-based mapping scheme is widely used in contemporary cache structures due to the simplicity of its hardware design and its good performance for sequences of consecutive addresses, its use may not be satisfactory for a variety of application domains having different characteristics.This thesis presents a new type of cache mapping scheme, motivated by programmable capabilities combined with Nature-inspired optimization of reconfigurable hardware. This research has focussed on an FPGA-based evolvable cache structure of the first level cache in a multi-core processor architecture, able to dynamically change cache indexing. To solve the challenge of reconfigurable cache mappings, a programmable Boolean circuit based on a combination of Look-up Table (LUT) memory elements is proposed. Focusing on optimization aspects at the system level, a Performance Measurement Infrastructure is introduced that is able to monitor the underlying microarchitectural metrics, and an adaptive evaluation strategy is presented that leverages on Evolutionary Algorithms, that is not only capable of evolving application-specific address-to-cache-index mappings for level one split caches but also of reducing optimization times. Putting this all together and prototyping in an FPGA for a LEON3/Linux-based multi-core processor, the creation of a system architecture reduces cache misses and improves performance over the use of conventional caches.}}, author = {{Ho, Nam}}, pages = {{139}}, publisher = {{Universität Paderborn}}, title = {{{FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization}}}, doi = {{10.17619/UNIPB/1-376}}, year = {{2018}}, } @unpublished{1165, author = {{Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}}, booktitle = {{4th Workshop On Approximate Computing (WAPCO 2018)}}, title = {{{Making the Case for Proof-carrying Approximate Circuits}}}, year = {{2018}}, } @inproceedings{5547, author = {{Lösch, Achim and Platzner, Marco}}, booktitle = {{2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)}}, isbn = {{9781538674796}}, location = {{Milan, Italy}}, publisher = {{IEEE}}, title = {{{A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes}}}, doi = {{10.1109/asap.2018.8445098}}, year = {{2018}}, } @inproceedings{10598, abstract = {{Approximate computing has become a very popular design strategy that exploits error resilient computations to achieve higher performance and energy efficiency. Automated synthesis of approximate circuits is performed via functional approximation, in which various parts of the target circuit are extensively examined with a library of approximate components/transformations to trade off the functional accuracy and computational budget (i.e., power). However, as the number of possible approximate transformations increases, traditional search techniques suffer from a combinatorial explosion due to the large branching factor. In this work, we present a comprehensive framework for automated synthesis of approximate circuits from either structural or behavioral descriptions. We adapt the Monte Carlo Tree Search (MCTS), as a stochastic search technique, to deal with the large design space exploration, which enables a broader range of potential possible approximations through lightweight random simulations. The proposed framework is able to recognize the design Pareto set even with low computational budgets. Experimental results highlight the capabilities of the proposed synthesis framework by resulting in up to 61.69% energy saving while maintaining the predefined quality constraints.}}, author = {{Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}}, booktitle = {{26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)}}, keywords = {{Approximate computing, High-level synthesis, Accuracy, Monte-Carlo tree search, Circuit simulation}}, pages = {{219--224}}, title = {{{An MCTS-based Framework for Synthesis of Approximate Circuits}}}, doi = {{10.1109/VLSI-SoC.2018.8645026}}, year = {{2018}}, } @misc{10782, author = {{Clausing, Lennart}}, publisher = {{Ruhr-University Bochum}}, title = {{{Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data}}}, year = {{2018}}, } @misc{1097, author = {{Jentzsch, Felix Paul}}, keywords = {{Approximate Computing, Proof-Carrying Hardware, Formal Verification}}, publisher = {{Universität Paderborn}}, title = {{{Enforcing IP Core Connection Properties with Verifiable Security Monitors}}}, year = {{2018}}, } @article{12965, author = {{Ghribi, Ines and Abdallah, Riadh Ben and Khalgui, Mohamed and Li, Zhiwu and Alnowibet, Khalid and Platzner, Marco}}, issn = {{2169-3536}}, journal = {{IEEE Access}}, pages = {{14078--14092}}, title = {{{R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints}}}, doi = {{10.1109/access.2018.2799852}}, year = {{2018}}, } @misc{3580, author = {{Hansmeier, Tim}}, publisher = {{Universität Paderborn}}, title = {{{An FPGA Accelerator for Checking Resolution Proofs}}}, year = {{2017}}, } @misc{1157, author = {{Witschen, Linus Matthias}}, publisher = {{Universität Paderborn}}, title = {{{A Framework for the Synthesis of Approximate Circuits}}}, year = {{2017}}, } @misc{74, author = {{Knorr, Christoph}}, publisher = {{Universität Paderborn}}, title = {{{OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten}}}, year = {{2017}}, } @article{9919, abstract = {{This is a study of a combined load restoration and generator start-up procedure. The procedure is structured into three stages according to the power system status and the goal of load restoration. Moreover, for each load restoration stage, the proposed algorithm determines a load restoration sequence by considering renewable energy such as solar and wind park to achieve objective functions. The validity and performance of the proposed algorithm is demonstrated through simulations using IEEE-39 network.}}, author = {{Shen, Cong and Kaufmann, Paul and Braun, Martin}}, journal = {{Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)}}, keywords = {{Load restorationRestoration stageRenewable energyVoltage/frequency fluctuations}}, pages = {{287--299}}, title = {{{Three-Stage Power System Restoration Methodology Considering Renewable Energies}}}, doi = {{10.1016/j.ijepes.2017.07.007}}, volume = {{94}}, year = {{2017}}, } @inproceedings{65, abstract = {{Heterogeneous compute nodes in form of CPUs with attached GPU and FPGA accelerators have strongly gained interested in the last years. Applications differ in their execution characteristics and can therefore benefit from such heterogeneous resources in terms of performance or energy consumption. While performance optimization has been the only goal for a long time, nowadays research is more and more focusing on techniques to minimize energy consumption due to rising electricity costs.This paper presents reMinMin, a novel static list scheduling approach for optimizing the total energy consumption for a set of tasks executed on a heterogeneous compute node. reMinMin bases on a new energy model that differentiates between static and dynamic energy components and covers effects of accelerator tasks on the host CPU. The required energy values are retrieved by measurements on the real computing system. In order to evaluate reMinMin, we compare it with two reference implementations on three task sets with different degrees of heterogeneity. In our experiments, MinMin is consistently better than a scheduler optimizing for dynamic energy only, which requires up to 19.43% more energy, and very close to optimal schedules.}}, author = {{Lösch, Achim and Platzner, Marco}}, booktitle = {{Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)}}, title = {{{reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements}}}, doi = {{10.1109/ASAP.2017.7995272}}, year = {{2017}}, } @article{68, abstract = {{Proof-carrying hardware (PCH) is a principle for achieving safety for dynamically reconfigurable hardware systems. The producer of a hardware module spends huge effort when creating a proof for a safety policy. The proof is then transferred as a certificate together with the configuration bitstream to the consumer of the hardware module, who can quickly verify the given proof. Previous work utilized SAT solvers and resolution traces to set up a PCH technology and corresponding tool flows. In this article, we present a novel technology for PCH based on inductive invariants. For sequential circuits, our approach is fundamentally stronger than the previous SAT-based one since we avoid the limitations of bounded unrolling. We contrast our technology to existing ones and show that it fits into previously proposed tool flows. We conduct experiments with four categories of benchmark circuits and report consumer and producer runtime and peak memory consumption, as well as the size of the certificates and the distribution of the workload between producer and consumer. Experiments clearly show that our new induction-based technology is superior for sequential circuits, whereas the previous SAT-based technology is the better choice for combinational circuits.}}, author = {{Isenberg, Tobias and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}}, journal = {{ACM Transactions on Design Automation of Electronic Systems}}, number = {{4}}, pages = {{61:1----61:23}}, publisher = {{ACM}}, title = {{{Proof-Carrying Hardware via Inductive Invariants}}}, doi = {{10.1145/3054743}}, year = {{2017}}, } @article{10600, author = {{H.W. Leong, Philip and Amano, Hideharu and Anderson, Jason and Bertels, Koen and M.P. Cardoso, Jo\~{a}o and Diessel, Oliver and Gogniat, Guy and Hutton, Mike and Lee, JunKyu and Luk, Wayne and Lysaght, Patrick and Platzner, Marco and K. Prasanna, Viktor and Rissa, Tero and Silvano, Cristina and So, Hayden and Wang, Yu}}, journal = {{ACM Transactions on Reconfigurable Technology and Systems}}, title = {{{The First 25 Years of the FPL Conference – Significant Papers}}}, doi = {{10.1145/2996468}}, year = {{2017}}, } @article{10601, author = {{F. DeMara, Ronald and Platzner, Marco and Ottavi, Marco}}, journal = {{IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing}}, title = {{{Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial)}}}, doi = {{10.1109/TETC.2016.2641599}}, year = {{2017}}, } @article{10611, author = {{Anwer, Jahanzeb and Platzner, Marco}}, journal = {{Microprocessors and Microsystems}}, pages = {{160--172}}, publisher = {{Elsevier}}, title = {{{Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus}}}, doi = {{10.1016/j.micpro.2017.06.002}}, year = {{2017}}, } @misc{10613, author = {{Kaltschmidt, Christian}}, publisher = {{Paderborn University}}, title = {{{An AR-based Training and Assessment System for Myoelectrical Prosthetic Control}}}, year = {{2017}}, } @inproceedings{10630, author = {{Boschmann, Alexander and Thombansen, Georg and Witschen, Linus Matthias and Wiens, Alex and Platzner, Marco}}, booktitle = {{Design, Automation and Test in Europe (DATE)}}, title = {{{A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller}}}, doi = {{10.23919/DATE.2017.7927137}}, year = {{2017}}, } @misc{10666, author = {{Riaz, Umair}}, publisher = {{Paderborn University}}, title = {{{Acceleration of Industrial Analytics Functions on a Platform FPGA}}}, year = {{2017}}, } @inproceedings{10672, author = {{Ho, Nam and Ashraf, Ishraq Ibne and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Proc. Design, Automation and Test in Europe Conf. (DATE)}}, title = {{{Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor}}}, doi = {{10.23919/DATE.2017.7927096}}, year = {{2017}}, } @inproceedings{10676, author = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{2017 International Conference on Field Programmable Technology (ICFPT)}}, keywords = {{Linux, cache storage, microprocessor chips, multiprocessing systems, LEON3-Linux based multicore processor, MiBench suite, block sizes, cache adaptation, evolvable caches, memory-to-cache-index mapping function, processor caches, reconfigurable cache mapping optimization, reconfigurable hardware technology, replacement strategies, standard Linux OS, time a complete hardware implementation, Hardware, Indexes, Linux, Measurement, Multicore processing, Optimization, Training}}, pages = {{215--218}}, title = {{{Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor}}}, doi = {{10.1109/FPT.2017.8280144}}, year = {{2017}}, } @article{10692, author = {{Shen, Cong and Kaufmann, Paul and Braun, Martin}}, journal = {{Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)}}, title = {{{Three-Stage Power System Restoration Methodology Considering Renewable Energies}}}, year = {{2017}}, } @misc{10708, author = {{Dietrich, Andreas}}, publisher = {{Paderborn University}}, title = {{{Reconfigurable Cryptographic Services}}}, year = {{2017}}, } @article{10740, author = {{Shen, Cong and Kaufmann, Paul and Braun, Martin}}, journal = {{The Journal of Engineering}}, pages = {{19pp}}, title = {{{Fast Network Restoration by Partitioning of Parallel Black Start Zones}}}, doi = {{10.1049/joe.2017.0032}}, year = {{2017}}, } @book{10759, author = {{Squillero, Giovanni and Burelli, Paolo and M. Mora, Antonio and Agapitos, Alexandros and S. Bush, William and Cagnoni, Stefano and Cotta, Carlos and De Falco, Ivanoe and Della Cioppa, Antonio and Divina, Federico and Eiben, A.E. and I. Esparcia-Alc{\'a}zar, Anna and Fern{\'a}ndez de Vega, Francisco and Glette, Kyrre and Haasdijk, Evert and Ignacio Hidalgo, J. and Kampouridis, Michael and Kaufmann, Paul and Mavrovouniotis, Michalis and Thanh Nguyen, Trung and Schaefer, Robert and Sim, Kevin and Tarantino, Ernesto and Urquhart, Neil and Zhang (editors), Mengjie}}, publisher = {{Springer}}, title = {{{Applications of Evolutionary Computation - 20th European Conference, EvoApplications}}}, year = {{2017}}, } @inproceedings{10760, author = {{Kaufmann, Paul and Kalkreuth, Roman}}, booktitle = {{KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI}}, publisher = {{Springer International Publishing}}, title = {{{Parametrizing Cartesian Genetic Programming: An Empirical Study}}}, doi = {{10.1007/978-3-319-67190-1_26}}, year = {{2017}}, } @inproceedings{10761, author = {{Kaufmann, Paul and Ho, Nam and Platzner, Marco}}, booktitle = {{Adaptive Hardware and Systems (AHS)}}, publisher = {{IEEE}}, title = {{{Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches}}}, doi = {{10.1109/AHS.2017.8046380}}, year = {{2017}}, } @inproceedings{10762, author = {{Kaufmann, Paul and Kalkreuth, Roman}}, booktitle = {{Genetic and Evolutionary Computation (GECCO), Compendium}}, publisher = {{ACM}}, title = {{{An Empirical Study on the Parametrization of Cartesian Genetic Programming}}}, doi = {{10.1145/3067695.3075980}}, year = {{2017}}, } @inproceedings{10780, author = {{Guettatfi, Zakarya and Hübner, Philipp and Platzner, Marco and Rinner, Bernhard}}, booktitle = {{12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}}, keywords = {{embedded systems, image sensors, power aware computing, wireless sensor networks, Zynq-based VSN node prototype, computational self-awareness, design approach, platform levels, power consumption, visual sensor networks, visual sensor nodes, Cameras, Hardware, Middleware, Multicore processing, Operating systems, Runtime, Reconfigurable platforms, distributed embedded systems, performance-resource trade-off, self-awareness, visual sensor nodes}}, pages = {{1--8}}, title = {{{Computational self-awareness as design approach for visual sensor nodes}}}, doi = {{10.1109/ReCoSoC.2017.8016147}}, year = {{2017}}, } @inproceedings{14893, author = {{Ghribi, Ines and Abdallah, Riadh Ben and Khalgui, Mohamed and Platzner, Marco}}, booktitle = {{Communications in Computer and Information Science}}, isbn = {{9783319625683}}, issn = {{1865-0929}}, publisher = {{Springer }}, title = {{{I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems}}}, doi = {{10.1007/978-3-319-62569-0_8}}, year = {{2017}}, } @article{222, abstract = {{Virtual field programmable gate arrays (FPGA) are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA, along with an analysis of the area and delay overheads involved.}}, author = {{Wiersema, Tobias and Bockhorn, Arne and Platzner, Marco}}, journal = {{Computers & Electrical Engineering}}, pages = {{112----122}}, publisher = {{Elsevier}}, title = {{{An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip}}}, doi = {{10.1016/j.compeleceng.2016.04.005}}, year = {{2016}}, } @inproceedings{5812, author = {{Boschmann, Alexander and Agne, Andreas and Witschen, Linus and Thombansen, Georg and Kraus, Florian and Platzner, Marco}}, booktitle = {{2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)}}, isbn = {{9781467394062}}, publisher = {{IEEE}}, title = {{{FPGA-based acceleration of high density myoelectric signal processing}}}, doi = {{10.1109/reconfig.2015.7393312}}, year = {{2016}}, } @misc{10612, author = {{Cedric Mertens, Jan}}, publisher = {{Paderborn University}}, title = {{{Sprint Diagnostic with RTK-GPS \& IMU Sensor Fusion}}}, year = {{2016}}, } @misc{10616, author = {{Nassery, Abdul Sami}}, publisher = {{Paderborn University}}, title = {{{Implementation of Bilinear Pairings on Reconfigurable Hardware}}}, year = {{2016}}, } @misc{10617, author = {{Amin, Omair}}, publisher = {{Paderborn University}}, title = {{{Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method}}}, year = {{2016}}, } @inproceedings{10622, author = {{Anwer, Jahanzeb and Platzner, Marco}}, booktitle = {{Euromicro Conference on Digital System Design (DSD)}}, title = {{{Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs}}}, doi = {{10.1109/DSD.2016.35}}, year = {{2016}}, } @inproceedings{10631, author = {{Boschmann, Alexander and Dosen, Strahinja and Werner, Andreas and Raies, Ali and Farina, Dario}}, booktitle = {{Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI)}}, title = {{{A novel immersive augmented reality system for prosthesis training and assessment}}}, year = {{2016}}, } @article{10661, author = {{Graf, Tobias and Platzner, Marco}}, journal = {{Journal Theoretical Computer Science}}, pages = {{53--62}}, publisher = {{Elsevier}}, title = {{{Adaptive playouts for online learning of policies during Monte Carlo Tree Search}}}, doi = {{10.1016/j.tcs.2016.06.029}}, volume = {{644}}, year = {{2016}}, } @misc{10695, author = {{Horstmann, Jens}}, publisher = {{Paderborn University}}, title = {{{Beschleunigte Simulation elektrischer Stromnetze mit GPUs}}}, year = {{2016}}, } @article{10705, author = {{Ma, Chenjie and Kaufmann, Paul and Töbermann, J.-Christian and Braun, Martin}}, journal = {{Renewable Energy}}, number = {{(part 2)}}, pages = {{946--953}}, publisher = {{Elsevier}}, title = {{{Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control}}}, doi = {{10.1016/j.renene.2015.07.083}}, volume = {{87}}, year = {{2016}}, } @misc{10706, author = {{Makeswaran, Vignesh}}, publisher = {{Paderborn University}}, title = {{{Operating System Support for Reconfigurable Cache}}}, year = {{2016}}, } @misc{10707, author = {{Ibne Ashraf, Ishraq}}, publisher = {{Paderborn University}}, title = {{{Private/Shared Data Classification and Implementation for a Multi-Softcore Platform}}}, year = {{2016}}, } @inproceedings{10712, author = {{Meisner, Sebastian and Platzner, Marco}}, booktitle = {{Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on}}, pages = {{1--8}}, title = {{{Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level}}}, doi = {{10.1109/ReConFig.2016.7857193}}, year = {{2016}}, } @misc{10755, author = {{Schmidt, Marco}}, publisher = {{Paderborn University}}, title = {{{Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung}}}, year = {{2016}}, } @book{10758, author = {{Squillero, Giovanni and Burelli, Paolo and M. Mora, Antonio and Agapitos, Alexandros and S. Bush, William and Cagnoni, Stefano and Cotta, Carlos and De Falco, Ivanoe and Della Cioppa, Antonio and Divina, Federico and Eiben, A.E. and I. Esparcia-Alc{\'a}zar, Anna and Fern{\'a}ndez de Vega, Francisco and Glette, Kyrre and Haasdijk, Evert and Ignacio Hidalgo, J. and Kampouridis, Michael and Kaufmann, Paul and Mavrovouniotis, Michalis and Thanh Nguyen, Trung and Schaefer, Robert and Sim, Kevin and Tarantino, Ernesto and Urquhart, Neil and Zhang (editors), Mengjie}}, publisher = {{Springer}}, title = {{{Applications of Evolutionary Computation - 19th European Conference, EvoApplications}}}, volume = {{9597}}, year = {{2016}}, } @inproceedings{10766, author = {{Ghribi, Ines and Ben Abdallah, Riadh and Khalgui, Mohamed and Platzner, Marco}}, booktitle = {{Proceedings of the 30th European Simulation and Modelling Conference (ESM)}}, title = {{{RCo-Design: New Visual Environment for Reconfigurable Embedded Systems}}}, year = {{2016}}, } @inproceedings{10768, author = {{Ghribi, Ines and Ben Abdallah, Riadh and Khalgui, Mohamed and Platzner, Marco}}, booktitle = {{Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA)}}, pages = {{185--195}}, title = {{{New Co-design Methodology for Real-time Embedded Systems}}}, year = {{2016}}, } @article{10769, author = {{Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}}, journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}}, number = {{99}}, pages = {{1--1}}, publisher = {{IEEE}}, title = {{{Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation}}}, doi = {{10.1109/TCAD.2016.2547908}}, volume = {{PP}}, year = {{2016}}, } @misc{10781, author = {{Hermansen, Sven}}, publisher = {{Paderborn University}}, title = {{{Custom Memory Controller for ReconOS}}}, year = {{2016}}, } @book{12972, abstract = {{Taking inspiration from self-awareness in humans, this book introduces the new notion of computational self-awareness as a fundamental concept for designing and operating computing systems. The basic ability of such self-aware computing systems is to collect information about their state and progress, learning and maintaining models containing knowledge that enables them to reason about their behaviour. Self-aware computing systems will have the ability to utilise this knowledge to effectively and autonomously adapt and explain their behaviour, in changing conditions. This book addresses these fundamental concepts from an engineering perspective, aiming at developing primitives for building systems and applications. It will be of value to researchers, professionals and graduate students in computer science and engineering.}}, editor = {{Lewis, Peter R. and Platzner, Marco and Rinner, Bernhard and Tørresen, Jim and Yao, Xin}}, isbn = {{9783319396743}}, issn = {{1619-7127}}, publisher = {{Springer}}, title = {{{Self-aware Computing Systems: An Engineering Approach}}}, doi = {{10.1007/978-3-319-39675-0}}, year = {{2016}}, } @inproceedings{15873, author = {{Boschmann, Alexander and Agne, Andreas and Witschen, Linus Matthias and Thombansen, Georg and Kraus, Florian and Platzner, Marco}}, booktitle = {{2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)}}, isbn = {{9781467394062}}, keywords = {{Electromyography, Feature extraction, Delays, Hardware Pattern recognition, Prosthetics, High definition video}}, location = {{Mexiko City, Mexiko}}, publisher = {{IEEE}}, title = {{{FPGA-based acceleration of high density myoelectric signal processing}}}, doi = {{10.1109/reconfig.2015.7393312}}, year = {{2016}}, } @inproceedings{13151, author = {{Graf, Tobias and Platzner, Marco}}, booktitle = {{Computer and Games}}, title = {{{Using Deep Convolutional Neural Networks in Monte Carlo Tree Search}}}, year = {{2016}}, } @inproceedings{13152, author = {{Graf, Tobias and Platzner, Marco}}, booktitle = {{IEEE Computational Intelligence and Games}}, title = {{{Monte-Carlo Simulation Balancing Revisited}}}, year = {{2016}}, } @inproceedings{132, abstract = {{Runtime reconfiguration can be used to replace hardware modules in the field and even to continuously improve them during operation. Runtime reconfiguration poses new challenges for validation, since the required properties of newly arriving modules may be difficult to check fast enough to sustain the intended system dynamics. In this paper we present a method for just-in-time verification of the worst-case completion time of a reconfigurable hardware module. We assume so-called run-to-completion modules that exhibit start and done signals indicating the start and end of execution, respectively. We present a formal verification approach that exploits the concept of proof-carrying hardware. The approach tasks the creator of a hardware module with constructing a proof of the worst-case completion time, which can then easily be checked by the user of the module, just prior to reconfiguration. After explaining the verification approach and a corresponding tool flow, we present results from two case studies, a short term synthesis filter and a multihead weigher. The resultsclearly show that cost of verifying the completion time of the module is paid by the creator instead of the user of the module.}}, author = {{Wiersema, Tobias and Platzner, Marco}}, booktitle = {{Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016)}}, pages = {{1----8}}, title = {{{Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware}}}, doi = {{10.1109/ReCoSoC.2016.7533910}}, year = {{2016}}, } @inbook{29, abstract = {{In this chapter, we present an introduction to the ReconOS operating system for reconfigurable computing. ReconOS offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. By supporting standard POSIX operating system functions for both software and hardware threads, ReconOS particularly caters to developers with a software background, because developers can use well-known mechanisms such as semaphores, mutexes, condition variables, and message queues for developing hybrid applications with threads running on the CPU and FPGA concurrently. Through the semantic integration of hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications between different reconfigurable computing systems.}}, author = {{Agne, Andreas and Platzner, Marco and Plessl, Christian and Happe, Markus and Lübbers, Enno}}, booktitle = {{FPGAs for Software Programmers}}, editor = {{Koch, Dirk and Hannig, Frank and Ziener, Daniel}}, isbn = {{978-3-319-26406-6}}, pages = {{227--244}}, publisher = {{Springer International Publishing}}, title = {{{ReconOS}}}, doi = {{10.1007/978-3-319-26408-0_13}}, year = {{2016}}, } @inbook{156, abstract = {{Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level.}}, author = {{Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}}, booktitle = {{Self-aware Computing Systems}}, pages = {{145--165}}, publisher = {{Springer International Publishing}}, title = {{{Self-aware Compute Nodes}}}, doi = {{10.1007/978-3-319-39675-0_8}}, year = {{2016}}, } @inproceedings{168, abstract = {{The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative.}}, author = {{Lösch, Achim and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)}}, pages = {{912--917}}, publisher = {{EDA Consortium / IEEE}}, title = {{{Performance-centric scheduling with task migration for a heterogeneous compute node in the data center}}}, year = {{2016}}, } @inproceedings{269, abstract = {{Proof-carrying hardware is an approach that has recently been proposed for the efficient verification of reconfigurable modules. We present an application of proof-carrying hardware to guarantee the correct functionality of dynamically reconfigured image processing modules. Our prototype comprises a reconfigurable-system-on-chip with an embedded virtual FPGA fabric. This setup allows us to leverage open source FPGA synthesis and backend tools to produce FPGA configuration bitstreams with an open format and, thus, to demonstrate and experimentally evaluate proof-carrying hardware at the bitstream level.}}, author = {{Wiersema, Tobias and Wu, Sen and Platzner, Marco}}, booktitle = {{Proceedings of the International Symposium in Reconfigurable Computing (ARC)}}, pages = {{365----372}}, title = {{{On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach}}}, doi = {{10.1007/978-3-319-16214-0_32}}, year = {{2015}}, } @misc{3364, author = {{Knorr, Christoph}}, publisher = {{Universität Paderborn}}, title = {{{Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten}}}, year = {{2015}}, } @article{1772, author = {{Torresen, Jim and Plessl, Christian and Yao, Xin}}, journal = {{IEEE Computer}}, keywords = {{self-awareness, self-expression}}, number = {{7}}, pages = {{18--20}}, publisher = {{IEEE Computer Society}}, title = {{{Self-Aware and Self-Expressive Systems – Guest Editor's Introduction}}}, doi = {{10.1109/MC.2015.205}}, volume = {{48}}, year = {{2015}}, } @misc{10615, author = {{Ahmed, Abdullah Fathi}}, publisher = {{Paderborn University}}, title = {{{Self-Optimizing Organic Cache}}}, year = {{2015}}, } @phdthesis{10624, abstract = {{The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types. Enabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes. This thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies.}}, author = {{Beisel, Tobias}}, isbn = {{978-3-8325-4155-2}}, pages = {{183}}, publisher = {{Logos Verlag Berlin GmbH}}, title = {{{Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing}}}, year = {{2015}}, } @misc{10668, author = {{Hangmann, Hendrik}}, publisher = {{Paderborn University}}, title = {{{Evolution of Heat Flow Prediction Models for FPGA Devices}}}, year = {{2015}}, } @misc{10671, author = {{Haupt, Christian}}, publisher = {{Paderborn University}}, title = {{{Computer Vision basierte Klassifikation von HD EMG Signalen}}}, year = {{2015}}, } @inproceedings{10673, author = {{Ho, Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}}, keywords = {{cache storage, field programmable gate arrays, multiprocessing systems, parallel architectures, reconfigurable architectures, FPGA, dynamic reconfiguration, evolvable cache mapping, many-core architecture, memory-to-cache address mapping function, microarchitectural optimization, multicore architecture, nature-inspired optimization, parallelization degrees, processor, reconfigurable cache mapping, reconfigurable computing, Field programmable gate arrays, Software, Tuning}}, pages = {{1--7}}, title = {{{Microarchitectural optimization by means of reconfigurable and evolvable cache mappings}}}, doi = {{10.1109/AHS.2015.7231178}}, year = {{2015}}, } @inproceedings{10693, author = {{Kaufmann, Paul and Shen, Cong}}, booktitle = {{Genetic and Evolutionary Computation (GECCO)}}, pages = {{409--416}}, publisher = {{ACM}}, title = {{{Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing}}}, year = {{2015}}, } @inproceedings{10711, author = {{Meisner, Sebastian and Platzner, Marco}}, booktitle = {{Field Programmable Technology (FPT), 2015 International Conference on}}, pages = {{212--215}}, title = {{{Comparison of thread signatures for error detection in hybrid multi-cores}}}, doi = {{10.1109/FPT.2015.7393153}}, year = {{2015}}, } @misc{10714, author = {{Meißner, Roland}}, publisher = {{Universität Paderborn}}, title = {{{Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs}}}, year = {{2015}}, } @misc{10726, author = {{Posewsky, Thorbjörn}}, publisher = {{Paderborn University}}, title = {{{Acceleration of Artificial Neural Networks on a Zynq Platform}}}, year = {{2015}}, } @book{10757, author = {{M. Mora, Antonio and Squillero, Giovanni and Agapitos, Alexandros and Burelli, Paolo and S. Bush, William and Cagnoni, Stefano and Cotta, Carlos and De Falco, Ivanoe and Della Cioppa, Antonio and Divina, Federico and Eiben, A.E. and I. Esparcia-Alc{\'a}zar, Anna and Fern{\'a}ndez de Vega, Francisco and Glette, Kyrre and Haasdijk, Evert and Ignacio Hidalgo, J. and Kampouridis, Michael and Kaufmann, Paul and Mavrovouniotis, Michalis and Thanh Nguyen, Trung and Schaefer, Robert and Sim, Kevin and Tarantino, Ernesto and Urquhart, Neil and Zhang (editors), Mengjie}}, publisher = {{Springer}}, title = {{{Applications of Evolutionary Computation - 18th European Conference, EvoApplications}}}, volume = {{9028}}, year = {{2015}}, } @inproceedings{10765, author = {{H.W. Leong, Philip and Amano, Hideharu and Anderson, Jason and Bertels, Koen and M.P. Cardoso, Jo\~ao and Diessel, Oliver and Gogniat, Guy and Hutton, Mike and Lee, JunKyu and Luk, Wayne and Lysaght, Patrick and Platzner, Marco and K. Prasanna, Viktor and Rissa, Tero and Silvano, Cristina and So, Hayden and Wang, Yu}}, booktitle = {{Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL)}}, pages = {{1--3}}, publisher = {{Imperial College}}, title = {{{Significant papers from the first 25 years of the FPL conference}}}, doi = {{10.1109/FPL.2015.7293747}}, year = {{2015}}, } @inproceedings{10767, author = {{Ghribi, Ines and Ben Abdallah, Riadh and Khalgui, Mohamed and Platzner, Marco}}, booktitle = {{Proceedings of the 29th European Simulation and Modelling Conference (ESM)}}, title = {{{New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software}}}, year = {{2015}}, } @article{10770, author = {{Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}}, journal = {{IEEE Transactions on Nanotechnology}}, number = {{6}}, pages = {{1117--1126}}, publisher = {{IEEE}}, title = {{{From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires}}}, doi = {{10.1109/TNANO.2015.2482359}}, volume = {{14}}, year = {{2015}}, } @inproceedings{10771, author = {{Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and Zhang, Jian and De Micheli, Giovanni and Sanchez, Eduardo and Reorda, Matteo Sonza}}, booktitle = {{2015 IEEE Computer Society Annual Symposium on VLSI}}, pages = {{491--496}}, publisher = {{IEEE}}, title = {{{On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors}}}, doi = {{10.1109/ISVLSI.2015.13}}, year = {{2015}}, } @inproceedings{10772, author = {{Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}}, booktitle = {{Proceedings of the 2015 Design, Automation & Test in Europe Conference \& Exhibition}}, pages = {{453--458}}, publisher = {{EDA Consortium}}, title = {{{Fault modeling in controllable polarity silicon nanowire circuits}}}, doi = {{10.7873/DATE.2015.0428}}, year = {{2015}}, } @inproceedings{10779, author = {{Guettatfi, Zakarya and Kermia, Omar and Khouas, Abdelhakim}}, booktitle = {{25th International Conference on Field Programmable Logic and Applications (FPL)}}, issn = {{1946-147X}}, keywords = {{embedded systems, field programmable gate arrays, operating systems (computers), scheduling, μC/OS-II, FPGAs, OS foundation, SafeRTOS, Xenomai, chip utilization ration, complex time constraints, embedded systems, hard real-time hardware task allocation, hard real-time hardware task scheduling, hardware-software real-time operating systems, partially reconfigurable field-programmable gate arrays, resource constraints, safety-critical RTOS, Field programmable gate arrays, Hardware, Job shop scheduling, Real-time systems, Shape, Software}}, publisher = {{Imperial College}}, title = {{{Over effective hard real-time hardware tasks scheduling and allocation}}}, doi = {{10.1109/FPL.2015.7293994}}, year = {{2015}}, } @inproceedings{13153, author = {{Graf, Tobias and Platzner, Marco}}, booktitle = {{Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers}}, pages = {{1--11}}, publisher = {{Springer International Publishing}}, title = {{{Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning}}}, doi = {{10.1007/978-3-319-27992-3_1}}, year = {{2015}}, } @article{296, abstract = {{FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x.}}, author = {{Kenter, Tobias and Schmitz, Henning and Plessl, Christian}}, journal = {{International Journal of Reconfigurable Computing (IJRC)}}, publisher = {{Hindawi}}, title = {{{Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study}}}, doi = {{10.1155/2015/859425}}, volume = {{2015}}, year = {{2015}}, } @inproceedings{303, abstract = {{This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement.}}, author = {{Damschen, Marvin and Plessl, Christian}}, booktitle = {{Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}}, title = {{{Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores}}}, year = {{2015}}, } @inproceedings{1773, author = {{Schumacher, Jörn and T. Anderson, J. and Borga, A. and Boterenbrood, H. and Chen, H. and Chen, K. and Drake, G. and Francis, D. and Gorini, B. and Lanni, F. and Lehmann-Miotto, Giovanna and Levinson, L. and Narevicius, J. and Plessl, Christian and Roich, A. and Ryu, S. and P. Schreuder, F. and Vandelli, Wainer and Vermeulen, J. and Zhang, J.}}, booktitle = {{Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)}}, publisher = {{ACM}}, title = {{{Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm}}}, doi = {{10.1145/2675743.2771824}}, year = {{2015}}, } @article{1768, author = {{Plessl, Christian and Platzner, Marco and Schreier, Peter J.}}, journal = {{Informatik Spektrum}}, keywords = {{approximate computing, survey}}, number = {{5}}, pages = {{396--399}}, publisher = {{Springer}}, title = {{{Aktuelles Schlagwort: Approximate Computing}}}, doi = {{10.1007/s00287-015-0911-z}}, year = {{2015}}, } @inproceedings{238, abstract = {{In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator.}}, author = {{Damschen, Marvin and Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}}, booktitle = {{Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)}}, pages = {{1078--1083}}, publisher = {{EDA Consortium / IEEE}}, title = {{{Transparent offloading of computational hotspots from binary code to Xeon Phi}}}, doi = {{10.7873/DATE.2015.1124}}, year = {{2015}}, } @inproceedings{347, abstract = {{Dynamic thread duplication is a known redundancy technique for multi-cores. The approach duplicates a thread under observation for some time period and compares the signatures of the two threads to detect errors. Hybrid multi-cores, typically implemented on platform FPGAs, enable the unique option of running the thread under observation and its copy in different modalities, i.e., software and hardware. We denote our dynamic redundancy technique on hybrid multi-cores as thread shadowing. In this paper we present the concept of thread shadowing and an implementation on a multi-threaded hybrid multi-core architecture. We report on experiments with a block-processing application and demonstrate the overheads, detection latencies and coverage for a range of thread shadowing modes. The results show that trans-modal thread shadowing, although bearing long detection latencies, offers attractive coverage at a low overhead.}}, author = {{Meisner, Sebastian and Platzner, Marco}}, booktitle = {{Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC)}}, editor = {{Goehringer, Diana and Santambrogio, MarcoDomenico and Cardoso, JoãoM.P. and Bertels, Koen}}, pages = {{283--290}}, publisher = {{Springer}}, title = {{{Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection}}}, doi = {{10.1007/978-3-319-05960-0_30}}, year = {{2014}}, } @inproceedings{1782, author = {{Graf, Tobias and Schaefers, Lars and Platzner, Marco}}, booktitle = {{Proc. Conf. on Computers and Games (CG)}}, number = {{8427}}, pages = {{14--25}}, publisher = {{Springer}}, title = {{{On Semeai Detection in Monte-Carlo Go}}}, doi = {{10.1007/978-3-319-09165-5_2}}, year = {{2014}}, } @inproceedings{399, abstract = {{Ensuring memory access security is a challenge for reconfigurable systems with multiple cores. Previous work introduced access monitors attached to the memory subsystem to ensure that the cores adhere to pre-defined protocols when accessing memory. In this paper, we combine access monitors with a formal runtime verification technique known as proof-carrying hardware to guarantee memory security. We extend previous work on proof-carrying hardware by covering sequential circuits and demonstrate our approach with a prototype leveraging ReconOS/Zynq with an embedded ZUMA virtual FPGA overlay. Experiments show the feasibility of the approach and the capabilities of the prototype, which constitutes the first realization of proof-carrying hardware on real FPGAs. The area overheads for the virtual FPGA are measured as 2x-10x, depending on the resource type. The delay overhead is substantial with almost 100x, but this is an extremely pessimistic estimate that will be lowered once accurate timing analysis for FPGA overlays become available. Finally, reconfiguration time for the virtual FPGA is about one order of magnitude lower than for the native Zynq fabric.}}, author = {{Wiersema, Tobias and Drzevitzky, Stephanie and Platzner, Marco}}, booktitle = {{Proceedings of the International Conference on Field-Programmable Technology (FPT)}}, pages = {{167--174}}, title = {{{Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring}}}, doi = {{10.1109/FPT.2014.7082771}}, year = {{2014}}, } @inproceedings{408, abstract = {{Verification of hardware and software usually proceeds separately, software analysis relying on the correctness of processors executing instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption.In this paper we present an approach for integrating software analyses with hardware verification, specifically targeting custom instruction set extensions. We propose three different techniques for deriving the properties to be proven for the hardware implementation of a custom instruction in order to support software analyses. The techniques are designed to explore the trade-off between generality and efficiency and span from proving functional equivalence over checking the rules of a particular analysis domain to verifying actual pre and post conditions resulting from program analysis. We demonstrate and compare the three techniques on example programs with custom instructions, using stateof-the-art software and hardware verification techniques.}}, author = {{Jakobs, Marie-Christine and Platzner, Marco and Wiersema, Tobias and Wehrheim, Heike}}, booktitle = {{Proceedings of the 11th International Conference on Integrated Formal Methods (iFM)}}, editor = {{Albert, Elvira and Sekerinski, Emil}}, pages = {{307--322}}, title = {{{Integrating Software and Hardware Verification}}}, doi = {{10.1007/978-3-319-10181-1_19}}, year = {{2014}}, } @inproceedings{433, abstract = {{Virtual FPGAs are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA.}}, author = {{Wiersema, Tobias and Bockhorn, Arne and Platzner, Marco}}, booktitle = {{Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}}, pages = {{1--6 }}, title = {{{Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA}}}, doi = {{10.1109/ReConFig.2014.7032514}}, year = {{2014}}, } @article{10602, author = {{Schaefers, Lars and Platzner, Marco}}, journal = {{IEEE Transactions on Computational Intelligence and AI in Games}}, number = {{3}}, pages = {{361--374}}, title = {{{A Novel Technique and its Application to Computer Go}}}, doi = {{10.1109/TCIAIG.2014.2346997}}, volume = {{6}}, year = {{2014}}, } @article{10603, author = {{Giefers, Heiner and Platzner, Marco}}, journal = {{IEEE Transactions on Computers}}, number = {{12}}, pages = {{2919 -- 2932}}, title = {{{An FPGA-based Reconfigurable Mesh Many-Core}}}, doi = {{10.1109/TC.2013.174}}, volume = {{63}}, year = {{2014}}, } @inproceedings{10621, author = {{Anwer, Jahanzeb and Platzner, Marco and Meisner, Sebastian}}, booktitle = {{Reconfigurable Architectures Workshop (RAW)}}, title = {{{FPGA Redundancy Configurations: An Automated Design Space Exploration}}}, doi = {{10.1109/IPDPSW.2014.37}}, year = {{2014}}, } @misc{10627, author = {{Bockhorn, Arne}}, publisher = {{Paderborn University}}, title = {{{Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation Board}}}, year = {{2014}}, } @inproceedings{10632, author = {{Boschmann, Alexander and Platzner, Marco}}, booktitle = {{Proc. MyoElectric Controls Symposium (MEC)}}, title = {{{A computer vision-based approach to high density EMG pattern recognition using structural similarity}}}, year = {{2014}}, } @inproceedings{10633, author = {{Boschmann, Alexander and Platzner, Marco}}, booktitle = {{Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)}}, title = {{{Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity}}}, year = {{2014}}, } @misc{10640, author = {{Brand, Marcel}}, publisher = {{Paderborn University}}, title = {{{A Generalized Loop Accelerator Implemented as a Coarse-Grained Array}}}, year = {{2014}}, } @misc{10645, author = {{Damschen, Marvin}}, publisher = {{Paderborn University}}, title = {{{Easy-to-use-on-the-fly binary program acceleration on many-cores}}}, year = {{2014}}, } @inproceedings{10654, author = {{Glette, Kyrre and Kaufmann, Paul}}, booktitle = {{IEEE Congress on Evolutionary Computation (CEC)}}, title = {{{Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System}}}, year = {{2014}}, }