@misc{52480, author = {{Klassen, Alexander}}, title = {{{Fast Partial Reconfiguration for ReconOS64 on Xilinx MPSoC Devices}}}, year = {{2023}}, } @inproceedings{29945, author = {{Witschen, Linus Matthias and Wiersema, Tobias and Reuter, Lucas David and Platzner, Marco}}, booktitle = {{2022 59th ACM/IEEE Design Automation Conference (DAC)}}, location = {{San Francisco, USA}}, title = {{{Search Space Characterization for Approximate Logic Synthesis }}}, year = {{2022}}, } @inproceedings{29865, author = {{Witschen, Linus Matthias and Wiersema, Tobias and Artmann, Matthias and Platzner, Marco}}, booktitle = {{Design, Automation and Test in Europe (DATE)}}, location = {{Online}}, title = {{{MUSCAT: MUS-based Circuit Approximation Technique}}}, year = {{2022}}, } @inproceedings{30971, author = {{Hansmeier, Tim and Platzner, Marco}}, booktitle = {{Applications of Evolutionary Computation, EvoApplications 2022, Proceedings}}, isbn = {{9783031024610}}, issn = {{0302-9743}}, location = {{Madrid}}, pages = {{386--401}}, publisher = {{Springer International Publishing}}, title = {{{Integrating Safety Guarantees into the Learning Classifier System XCS}}}, doi = {{10.1007/978-3-031-02462-7_25}}, volume = {{13224}}, year = {{2022}}, } @inproceedings{32855, author = {{Clausing, Lennart and Platzner, Marco}}, booktitle = {{2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}}, location = {{ Lyon, France}}, pages = {{120--127}}, publisher = {{IEEE}}, title = {{{ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support}}}, doi = {{10.1109/ipdpsw55747.2022.00029}}, year = {{2022}}, } @inproceedings{33253, author = {{Hansmeier, Tim and Brede, Mathis and Platzner, Marco}}, booktitle = {{GECCO '22: Proceedings of the Genetic and Evolutionary Computation Conference Companion}}, location = {{Boston, MA, USA}}, pages = {{2071--2079}}, publisher = {{Association for Computing Machinery (ACM)}}, title = {{{XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion}}}, doi = {{10.1145/3520304.3533977}}, year = {{2022}}, } @phdthesis{29769, abstract = {{Wettstreit zwischen der Entwicklung neuer Hardwaretrojaner und entsprechender Gegenmaßnahmen beschreiten Widersacher immer raffiniertere Wege um Schaltungsentwürfe zu infizieren und dabei selbst fortgeschrittene Test- und Verifikationsmethoden zu überlisten. Abgesehen von den konventionellen Methoden um einen Trojaner in eine Schaltung für ein Field-programmable Gate Array (FPGA) einzuschleusen, können auch die Entwurfswerkzeuge heimlich kompromittiert werden um einen Angreifer dabei zu unterstützen einen erfolgreichen Angriff durchzuführen, der zum Beispiel Fehlfunktionen oder ungewollte Informationsabflüsse bewirken kann. Diese Dissertation beschäftigt sich hauptsächlich mit den beiden Blickwinkeln auf Hardwaretrojaner in rekonfigurierbaren Systemen, einerseits der Perspektive des Verteidigers mit einer Methode zur Erkennung von Trojanern auf der Bitstromebene, und andererseits derjenigen des Angreifers mit einer neuartigen Angriffsmethode für FPGA Trojaner. Für die Verteidigung gegen den Trojaner ``Heimtückische LUT'' stellen wir die allererste erfolgreiche Gegenmaßnahme vor, die durch Verifikation mittels Proof-carrying Hardware (PCH) auf der Bitstromebene direkt vor der Konfiguration der Hardware angewendet werden kann, und präsentieren ein vollständiges Schema für den Entwurf und die Verifikation von Schaltungen für iCE40 FPGAs. Für die Gegenseite führen wir einen neuen Angriff ein, welcher bösartiges Routing im eingefügten Trojaner ausnutzt um selbst im fertigen Bitstrom in einem inaktiven Zustand zu verbleiben: Hierdurch kann dieser neuartige Angriff zur Zeit weder von herkömmlichen Test- und Verifikationsmethoden, noch von unserer vorher vorgestellten Verifikation auf der Bitstromebene entdeckt werden.}}, author = {{Ahmed, Qazi Arbab}}, keywords = {{FPGA Security, Hardware Trojans, Bitstream-level Trojans, Bitstream Verification}}, publisher = {{ Paderborn University, Paderborn, Germany}}, title = {{{Hardware Trojans in Reconfigurable Computing}}}, doi = {{10.17619/UNIPB/1-1271}}, year = {{2022}}, } @unpublished{29541, author = {{Lienen, Christian and Platzner, Marco}}, title = {{{ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications}}}, year = {{2022}}, } @inproceedings{34007, author = {{Lienen, Christian and Platzner, Marco}}, location = {{Neaples, Italy}}, title = {{{Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS}}}, year = {{2022}}, } @inproceedings{34005, author = {{Lienen, Christian and Platzner, Marco}}, booktitle = {{2022 25th Euromicro Conference on Digital System Design (DSD)}}, location = {{Maspalomas, Gran Canaria, Spain}}, title = {{{Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications}}}, doi = {{10.1109/DSD57027.2022.00088}}, year = {{2022}}, } @phdthesis{34041, author = {{Witschen, Linus Matthias}}, title = {{{Frameworks and Methodologies for Search-based Approximate Logic Synthesis}}}, doi = {{10.17619/UNIPB/1-1649}}, year = {{2022}}, } @inproceedings{32342, author = {{Ahmed, Qazi Arbab and Platzner, Marco}}, location = {{Pafos, Cyprus}}, publisher = {{IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022)}}, title = {{{On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs}}}, year = {{2022}}, } @misc{42839, author = {{Mehlich, Florian}}, publisher = {{Paderborn University}}, title = {{{An Evaluation of XCS on the OpenAI Gym}}}, year = {{2022}}, } @article{33990, abstract = {{Deep neural networks (DNNs) are penetrating into a broad spectrum of applications and replacing manual algorithmic implementations, including the radio frequency communications domain with classical signal processing algorithms. However, the high throughput (gigasamples per second) and low latency requirements of this application domain pose a significant hurdle for adopting computationally demanding DNNs. In this article, we explore highly specialized DNN inference accelerator approaches on field-programmable gate arrays (FPGAs) for RadioML modulation classification. Using an automated end-to-end flow for the generation of the FPGA solution, we can easily explore a spectrum of solutions that optimize for different design targets, including accuracy, power efficiency, resources, throughput, and latency. By leveraging reduced precision arithmetic and customized streaming dataflow, we demonstrate a solution that meets the application requirements and outperforms alternative FPGA efforts by 3.5x in terms of throughput. Against modern embedded graphics processing units (GPUs), we measure >10x higher throughput and >100x lower latency under comparable accuracy and power envelopes.}}, author = {{Jentzsch, Felix and Umuroglu, Yaman and Pappalardo, Alessandro and Blott, Michaela and Platzner, Marco}}, journal = {{IEEE Micro}}, number = {{6}}, pages = {{125--133}}, publisher = {{IEEE}}, title = {{{RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures}}}, doi = {{10.1109/MM.2022.3202091}}, volume = {{42}}, year = {{2022}}, } @misc{45715, author = {{Tcheussi Ngayap, Vanessa Ingrid}}, title = {{{FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators}}}, year = {{2022}}, } @misc{45914, author = {{Manjunatha, Suraj}}, publisher = {{Paderborn University }}, title = {{{Dealing With Pre-Processing And Feature Extraction Of Time-Series Data In Predictive Maintenance}}}, year = {{2022}}, } @misc{45915, author = {{Kaur , Parvinder}}, title = {{{Analysis of Time-Series Classification in Conditional Monitoring Systems}}}, year = {{2022}}, } @phdthesis{26746, abstract = {{Previous research in proof-carrying hardware has established the feasibility and utility of the approach, and provided a concrete solution for employing it for the certification of functional equivalence checking against a specification, but fell short in connecting it to state-of-the-art formal verification insights, methods and tools. Due to the immense complexity of modern circuits, and verification challenges such as the state explosion problem for sequential circuits, this restriction of readily-available verification solutions severely limited the applicability of the approach in wider contexts. This thesis closes the gap between the PCH approach and current advances in formal hardware verification, provides methods and tools to express and certify a wide range of circuit properties, both functional and non-functional, and presents for the first time prototypes in which circuits that are implemented on actual reconfigurable hardware are verified with PCH methods. Using these results, designers can now apply PCH to establish trust in more complex circuits, by using more diverse properties which they can express using modern, efficient property specification techniques.}}, author = {{Wiersema, Tobias}}, keywords = {{Proof-Carrying Hardware, Formal Verification, Sequential Circuits, Non-Functional Properties, Functional Properties}}, pages = {{293}}, publisher = {{Paderborn University}}, title = {{{Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware}}}, year = {{2021}}, } @article{29150, abstract = {{Robotics applications process large amounts of data in real time and require compute platforms that provide high performance and energy efficiency. FPGAs are well suited for many of these applications, but there is a reluctance in the robotics community to use hardware acceleration due to increased design complexity and a lack of consistent programming models across the software/hardware boundary. In this article, we present ReconROS, a framework that integrates the widely used robot operating system (ROS) with ReconOS, which features multithreaded programming of hardware and software threads for reconfigurable computers. This unique combination gives ROS 2 developers the flexibility to transparently accelerate parts of their robotics applications in hardware. We elaborate on the architecture and the design flow for ReconROS and report on a set of experiments that underline the feasibility and flexibility of our approach.}}, author = {{Lienen, Christian and Platzner, Marco}}, issn = {{1936-7406}}, journal = {{ACM Transactions on Reconfigurable Technology and Systems}}, pages = {{1--20}}, title = {{{Design of Distributed Reconfigurable Robotics Systems with ReconROS}}}, doi = {{10.1145/3494571}}, year = {{2021}}, } @misc{29151, abstract = {{Automation becomes a vital part in the High-Performance computing system in situational dynamics to take the decisions on the fly. Heterogeneous compute nodes consist of computing resources such as CPU, GPU and FPGA and are the important components of the high-performance computing system that can adapt the automation to achieve the given goal. While implanting automation in the computing resources, management of the resources is one of the essential aspects that need to be taken care of. Tasks are continuously executed on the resources using its unique characteristics. Effective scheduling is essential to make the best use of the characteristics provided by each resource. Scheduling enables the execution of each task by allocating resources so that they take advantage of all the characteristics of the compute resources. Various scheduling heuristics can be used to create effective scheduling, which might require the execution time to schedule the task efficiently. Providing actual execution time is not possible in many cases; hence we can provide the estimations for the actual execution time . The purpose of this master's thesis is to design a predictive model or system that estimates the execution time required to execute tasks using historical execution time data on the heterogeneous compute nodes. In this thesis, regression techniques(SGD Regressor, Passive-Aggressive Regressor, MLP Regressor, and XCSF Regressor) are compared in terms of their prediction accuracy in order to determine which technique produces reliable predictions for the execution time. These estimations must be generated in an online learning environment in which data points arrive in any sequence, one by one, and the regression model must learn from them. After evaluating the regression algorithms, it is seen that the XCSF regressor provides the highest overall prediction accuracy for the supplied data sets. The regression technique's parameters also play a significant role in achieving an acceptable prediction accuracy. As a remark, when using online learning in regression analysis, the accuracy depends upon both the order of sequential data points that are coming to train the model and the parameter configuration for each regression technique.}}, author = {{Kashikar, Chinmay}}, publisher = {{Paderborn University}}, title = {{{A Comparison of Machine Learning Techniques for the On-line Characterization of Tasks Executed on Heterogeneous Compute Nodes}}}, year = {{2021}}, }