@misc{10613, author = {{Kaltschmidt, Christian}}, publisher = {{Paderborn University}}, title = {{{An AR-based Training and Assessment System for Myoelectrical Prosthetic Control}}}, year = {{2017}}, } @inproceedings{10630, author = {{Boschmann, Alexander and Thombansen, Georg and Witschen, Linus Matthias and Wiens, Alex and Platzner, Marco}}, booktitle = {{Design, Automation and Test in Europe (DATE)}}, title = {{{A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller}}}, doi = {{10.23919/DATE.2017.7927137}}, year = {{2017}}, } @misc{10666, author = {{Riaz, Umair}}, publisher = {{Paderborn University}}, title = {{{Acceleration of Industrial Analytics Functions on a Platform FPGA}}}, year = {{2017}}, } @inproceedings{10672, author = {{Ho, Nam and Ashraf, Ishraq Ibne and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Proc. Design, Automation and Test in Europe Conf. (DATE)}}, title = {{{Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor}}}, doi = {{10.23919/DATE.2017.7927096}}, year = {{2017}}, } @inproceedings{10676, author = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{2017 International Conference on Field Programmable Technology (ICFPT)}}, keywords = {{Linux, cache storage, microprocessor chips, multiprocessing systems, LEON3-Linux based multicore processor, MiBench suite, block sizes, cache adaptation, evolvable caches, memory-to-cache-index mapping function, processor caches, reconfigurable cache mapping optimization, reconfigurable hardware technology, replacement strategies, standard Linux OS, time a complete hardware implementation, Hardware, Indexes, Linux, Measurement, Multicore processing, Optimization, Training}}, pages = {{215--218}}, title = {{{Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor}}}, doi = {{10.1109/FPT.2017.8280144}}, year = {{2017}}, } @article{10692, author = {{Shen, Cong and Kaufmann, Paul and Braun, Martin}}, journal = {{Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)}}, title = {{{Three-Stage Power System Restoration Methodology Considering Renewable Energies}}}, year = {{2017}}, } @misc{10708, author = {{Dietrich, Andreas}}, publisher = {{Paderborn University}}, title = {{{Reconfigurable Cryptographic Services}}}, year = {{2017}}, } @article{10740, author = {{Shen, Cong and Kaufmann, Paul and Braun, Martin}}, journal = {{The Journal of Engineering}}, pages = {{19pp}}, title = {{{Fast Network Restoration by Partitioning of Parallel Black Start Zones}}}, doi = {{10.1049/joe.2017.0032}}, year = {{2017}}, } @book{10759, author = {{Squillero, Giovanni and Burelli, Paolo and M. Mora, Antonio and Agapitos, Alexandros and S. Bush, William and Cagnoni, Stefano and Cotta, Carlos and De Falco, Ivanoe and Della Cioppa, Antonio and Divina, Federico and Eiben, A.E. and I. Esparcia-Alc{\'a}zar, Anna and Fern{\'a}ndez de Vega, Francisco and Glette, Kyrre and Haasdijk, Evert and Ignacio Hidalgo, J. and Kampouridis, Michael and Kaufmann, Paul and Mavrovouniotis, Michalis and Thanh Nguyen, Trung and Schaefer, Robert and Sim, Kevin and Tarantino, Ernesto and Urquhart, Neil and Zhang (editors), Mengjie}}, publisher = {{Springer}}, title = {{{Applications of Evolutionary Computation - 20th European Conference, EvoApplications}}}, year = {{2017}}, } @inproceedings{10760, author = {{Kaufmann, Paul and Kalkreuth, Roman}}, booktitle = {{KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI}}, publisher = {{Springer International Publishing}}, title = {{{Parametrizing Cartesian Genetic Programming: An Empirical Study}}}, doi = {{10.1007/978-3-319-67190-1_26}}, year = {{2017}}, } @inproceedings{10761, author = {{Kaufmann, Paul and Ho, Nam and Platzner, Marco}}, booktitle = {{Adaptive Hardware and Systems (AHS)}}, publisher = {{IEEE}}, title = {{{Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches}}}, doi = {{10.1109/AHS.2017.8046380}}, year = {{2017}}, } @inproceedings{10762, author = {{Kaufmann, Paul and Kalkreuth, Roman}}, booktitle = {{Genetic and Evolutionary Computation (GECCO), Compendium}}, publisher = {{ACM}}, title = {{{An Empirical Study on the Parametrization of Cartesian Genetic Programming}}}, doi = {{10.1145/3067695.3075980}}, year = {{2017}}, } @inproceedings{10780, author = {{Guettatfi, Zakarya and Hübner, Philipp and Platzner, Marco and Rinner, Bernhard}}, booktitle = {{12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}}, keywords = {{embedded systems, image sensors, power aware computing, wireless sensor networks, Zynq-based VSN node prototype, computational self-awareness, design approach, platform levels, power consumption, visual sensor networks, visual sensor nodes, Cameras, Hardware, Middleware, Multicore processing, Operating systems, Runtime, Reconfigurable platforms, distributed embedded systems, performance-resource trade-off, self-awareness, visual sensor nodes}}, pages = {{1--8}}, title = {{{Computational self-awareness as design approach for visual sensor nodes}}}, doi = {{10.1109/ReCoSoC.2017.8016147}}, year = {{2017}}, } @inproceedings{14893, author = {{Ghribi, Ines and Abdallah, Riadh Ben and Khalgui, Mohamed and Platzner, Marco}}, booktitle = {{Communications in Computer and Information Science}}, isbn = {{9783319625683}}, issn = {{1865-0929}}, publisher = {{Springer }}, title = {{{I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems}}}, doi = {{10.1007/978-3-319-62569-0_8}}, year = {{2017}}, } @article{222, abstract = {{Virtual field programmable gate arrays (FPGA) are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA, along with an analysis of the area and delay overheads involved.}}, author = {{Wiersema, Tobias and Bockhorn, Arne and Platzner, Marco}}, journal = {{Computers & Electrical Engineering}}, pages = {{112----122}}, publisher = {{Elsevier}}, title = {{{An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip}}}, doi = {{10.1016/j.compeleceng.2016.04.005}}, year = {{2016}}, } @inproceedings{5812, author = {{Boschmann, Alexander and Agne, Andreas and Witschen, Linus and Thombansen, Georg and Kraus, Florian and Platzner, Marco}}, booktitle = {{2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)}}, isbn = {{9781467394062}}, publisher = {{IEEE}}, title = {{{FPGA-based acceleration of high density myoelectric signal processing}}}, doi = {{10.1109/reconfig.2015.7393312}}, year = {{2016}}, } @misc{10612, author = {{Cedric Mertens, Jan}}, publisher = {{Paderborn University}}, title = {{{Sprint Diagnostic with RTK-GPS \& IMU Sensor Fusion}}}, year = {{2016}}, } @misc{10616, author = {{Nassery, Abdul Sami}}, publisher = {{Paderborn University}}, title = {{{Implementation of Bilinear Pairings on Reconfigurable Hardware}}}, year = {{2016}}, } @misc{10617, author = {{Amin, Omair}}, publisher = {{Paderborn University}}, title = {{{Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method}}}, year = {{2016}}, } @inproceedings{10622, author = {{Anwer, Jahanzeb and Platzner, Marco}}, booktitle = {{Euromicro Conference on Digital System Design (DSD)}}, title = {{{Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs}}}, doi = {{10.1109/DSD.2016.35}}, year = {{2016}}, }